Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.46 95.60 88.91 96.68 50.00 94.10 97.35 96.58


Total test records in report: 1480
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T1327 /workspace/coverage/default/23.random_length_in_trans.801506264 Apr 28 02:13:27 PM PDT 24 Apr 28 02:13:36 PM PDT 24 8538665548 ps
T1328 /workspace/coverage/default/33.usbdev_fifo_rst.1272475324 Apr 28 02:14:19 PM PDT 24 Apr 28 02:14:22 PM PDT 24 208678830 ps
T1329 /workspace/coverage/default/26.usbdev_stall_trans.963865229 Apr 28 02:13:43 PM PDT 24 Apr 28 02:13:52 PM PDT 24 8396333006 ps
T1330 /workspace/coverage/default/36.usbdev_random_length_out_trans.1946902477 Apr 28 02:14:29 PM PDT 24 Apr 28 02:14:39 PM PDT 24 8388062310 ps
T1331 /workspace/coverage/default/39.usbdev_av_buffer.3324967219 Apr 28 02:14:41 PM PDT 24 Apr 28 02:14:49 PM PDT 24 8375224177 ps
T1332 /workspace/coverage/default/38.usbdev_in_iso.2679457203 Apr 28 02:14:43 PM PDT 24 Apr 28 02:14:52 PM PDT 24 8390712253 ps
T1333 /workspace/coverage/default/1.usbdev_in_iso.1244125120 Apr 28 02:11:05 PM PDT 24 Apr 28 02:11:14 PM PDT 24 8394335927 ps
T1334 /workspace/coverage/default/39.min_length_in_transaction.779702747 Apr 28 02:14:48 PM PDT 24 Apr 28 02:14:56 PM PDT 24 8384191240 ps
T1335 /workspace/coverage/default/22.usbdev_pkt_received.3569734352 Apr 28 02:13:24 PM PDT 24 Apr 28 02:13:33 PM PDT 24 8463760858 ps
T1336 /workspace/coverage/default/20.usbdev_phy_pins_sense.950222431 Apr 28 02:13:13 PM PDT 24 Apr 28 02:13:15 PM PDT 24 95186192 ps
T1337 /workspace/coverage/default/36.usbdev_pkt_received.2809788915 Apr 28 02:14:31 PM PDT 24 Apr 28 02:14:39 PM PDT 24 8466381589 ps
T1338 /workspace/coverage/default/36.usbdev_phy_pins_sense.2867991135 Apr 28 02:14:30 PM PDT 24 Apr 28 02:14:32 PM PDT 24 73987331 ps
T1339 /workspace/coverage/default/48.usbdev_in_iso.790319040 Apr 28 02:15:33 PM PDT 24 Apr 28 02:15:42 PM PDT 24 8431287541 ps
T1340 /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.60134412 Apr 28 02:14:41 PM PDT 24 Apr 28 02:14:50 PM PDT 24 8370573147 ps
T1341 /workspace/coverage/default/37.usbdev_pending_in_trans.1367140308 Apr 28 02:14:37 PM PDT 24 Apr 28 02:14:45 PM PDT 24 8409231685 ps
T1342 /workspace/coverage/default/3.max_length_in_transaction.2961625479 Apr 28 02:11:22 PM PDT 24 Apr 28 02:11:30 PM PDT 24 8472170772 ps
T1343 /workspace/coverage/default/39.usbdev_phy_pins_sense.3742093972 Apr 28 02:14:44 PM PDT 24 Apr 28 02:14:45 PM PDT 24 45045887 ps
T1344 /workspace/coverage/default/2.usbdev_in_iso.234085501 Apr 28 02:11:14 PM PDT 24 Apr 28 02:11:24 PM PDT 24 8419700717 ps
T1345 /workspace/coverage/default/15.usbdev_setup_stage.2464577199 Apr 28 02:12:45 PM PDT 24 Apr 28 02:12:53 PM PDT 24 8397033181 ps
T1346 /workspace/coverage/default/32.usbdev_in_trans.2896209812 Apr 28 02:14:12 PM PDT 24 Apr 28 02:14:22 PM PDT 24 8464493428 ps
T1347 /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.606289581 Apr 28 02:14:02 PM PDT 24 Apr 28 02:14:12 PM PDT 24 8368364084 ps
T1348 /workspace/coverage/default/45.usbdev_out_stall.423557963 Apr 28 02:15:06 PM PDT 24 Apr 28 02:15:15 PM PDT 24 8417311015 ps
T1349 /workspace/coverage/default/14.usbdev_av_buffer.719224384 Apr 28 02:12:36 PM PDT 24 Apr 28 02:12:45 PM PDT 24 8409269424 ps
T1350 /workspace/coverage/default/36.usbdev_in_stall.3662983259 Apr 28 02:14:33 PM PDT 24 Apr 28 02:14:43 PM PDT 24 8396338050 ps
T1351 /workspace/coverage/default/20.usbdev_stall_trans.3440198649 Apr 28 02:13:12 PM PDT 24 Apr 28 02:13:22 PM PDT 24 8420309631 ps
T1352 /workspace/coverage/default/9.usbdev_pkt_buffer.4234946213 Apr 28 02:12:02 PM PDT 24 Apr 28 02:13:16 PM PDT 24 33019574948 ps
T1353 /workspace/coverage/default/7.random_length_in_trans.3984427569 Apr 28 02:11:52 PM PDT 24 Apr 28 02:12:01 PM PDT 24 8396073183 ps
T1354 /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3492903326 Apr 28 02:14:19 PM PDT 24 Apr 28 02:14:29 PM PDT 24 8369813100 ps
T1355 /workspace/coverage/default/18.usbdev_out_stall.4168589439 Apr 28 02:13:02 PM PDT 24 Apr 28 02:13:11 PM PDT 24 8399529725 ps
T1356 /workspace/coverage/default/4.usbdev_setup_trans_ignored.1897988921 Apr 28 02:11:24 PM PDT 24 Apr 28 02:11:32 PM PDT 24 8371050452 ps
T1357 /workspace/coverage/default/19.usbdev_pkt_sent.62341580 Apr 28 02:13:11 PM PDT 24 Apr 28 02:13:20 PM PDT 24 8400519075 ps
T1358 /workspace/coverage/default/16.usbdev_setup_stage.3013118095 Apr 28 02:12:51 PM PDT 24 Apr 28 02:13:00 PM PDT 24 8373317139 ps
T1359 /workspace/coverage/default/26.usbdev_nak_trans.2593951925 Apr 28 02:13:46 PM PDT 24 Apr 28 02:13:55 PM PDT 24 8429128064 ps
T1360 /workspace/coverage/default/37.usbdev_in_trans.3729120640 Apr 28 02:14:37 PM PDT 24 Apr 28 02:14:46 PM PDT 24 8443488412 ps
T1361 /workspace/coverage/default/15.usbdev_in_iso.3211616872 Apr 28 02:12:43 PM PDT 24 Apr 28 02:12:53 PM PDT 24 8425240858 ps
T1362 /workspace/coverage/default/44.usbdev_smoke.1684550337 Apr 28 02:15:05 PM PDT 24 Apr 28 02:15:14 PM PDT 24 8450423209 ps
T1363 /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1334798072 Apr 28 02:13:21 PM PDT 24 Apr 28 02:13:29 PM PDT 24 8422740419 ps
T1364 /workspace/coverage/default/48.usbdev_pkt_sent.1873111885 Apr 28 02:15:23 PM PDT 24 Apr 28 02:15:34 PM PDT 24 8433089041 ps
T1365 /workspace/coverage/default/47.usbdev_pkt_received.2622871987 Apr 28 02:15:12 PM PDT 24 Apr 28 02:15:22 PM PDT 24 8426743954 ps
T1366 /workspace/coverage/default/22.min_length_in_transaction.91621553 Apr 28 02:13:22 PM PDT 24 Apr 28 02:13:31 PM PDT 24 8381298168 ps
T1367 /workspace/coverage/default/7.usbdev_setup_stage.1187005166 Apr 28 02:11:52 PM PDT 24 Apr 28 02:12:00 PM PDT 24 8381853490 ps
T1368 /workspace/coverage/default/32.usbdev_setup_trans_ignored.2858711060 Apr 28 02:14:14 PM PDT 24 Apr 28 02:14:24 PM PDT 24 8364149636 ps
T1369 /workspace/coverage/default/47.usbdev_nak_trans.954860971 Apr 28 02:15:13 PM PDT 24 Apr 28 02:15:22 PM PDT 24 8428383858 ps
T1370 /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1401929677 Apr 28 02:13:14 PM PDT 24 Apr 28 02:13:23 PM PDT 24 8379139559 ps
T1371 /workspace/coverage/default/32.usbdev_in_iso.3069393104 Apr 28 02:14:14 PM PDT 24 Apr 28 02:14:24 PM PDT 24 8451562471 ps
T1372 /workspace/coverage/default/13.usbdev_pkt_sent.3064827032 Apr 28 02:12:29 PM PDT 24 Apr 28 02:12:38 PM PDT 24 8446149795 ps
T1373 /workspace/coverage/default/8.usbdev_in_trans.4130948760 Apr 28 02:11:55 PM PDT 24 Apr 28 02:12:03 PM PDT 24 8380468270 ps
T1374 /workspace/coverage/default/25.usbdev_pending_in_trans.1890745871 Apr 28 02:13:44 PM PDT 24 Apr 28 02:13:55 PM PDT 24 8391173033 ps
T1375 /workspace/coverage/default/36.usbdev_stall_trans.3568376233 Apr 28 02:14:30 PM PDT 24 Apr 28 02:14:39 PM PDT 24 8412062660 ps
T1376 /workspace/coverage/default/30.min_length_in_transaction.1453973667 Apr 28 02:14:02 PM PDT 24 Apr 28 02:14:10 PM PDT 24 8379016039 ps
T1377 /workspace/coverage/default/32.usbdev_fifo_rst.3252873618 Apr 28 02:14:13 PM PDT 24 Apr 28 02:14:16 PM PDT 24 79905999 ps
T1378 /workspace/coverage/default/10.usbdev_pkt_sent.2229223012 Apr 28 02:12:06 PM PDT 24 Apr 28 02:12:14 PM PDT 24 8445889272 ps
T1379 /workspace/coverage/default/44.usbdev_pending_in_trans.367476657 Apr 28 02:15:03 PM PDT 24 Apr 28 02:15:12 PM PDT 24 8407758624 ps
T1380 /workspace/coverage/default/7.usbdev_setup_trans_ignored.584159279 Apr 28 02:11:47 PM PDT 24 Apr 28 02:11:56 PM PDT 24 8372468384 ps
T1381 /workspace/coverage/default/27.usbdev_pkt_sent.4214435100 Apr 28 02:13:47 PM PDT 24 Apr 28 02:13:56 PM PDT 24 8450523123 ps
T55 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3187249794 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 78552918 ps
T1382 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3655681605 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:27 PM PDT 24 109303649 ps
T64 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1871091401 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:29 PM PDT 24 1480137523 ps
T65 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3938828993 Apr 28 12:58:46 PM PDT 24 Apr 28 12:58:47 PM PDT 24 80024388 ps
T66 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1473230329 Apr 28 12:58:43 PM PDT 24 Apr 28 12:58:44 PM PDT 24 50011542 ps
T56 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3116453167 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:25 PM PDT 24 865899633 ps
T67 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4016071309 Apr 28 12:58:33 PM PDT 24 Apr 28 12:58:34 PM PDT 24 41513898 ps
T68 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1197171680 Apr 28 12:58:37 PM PDT 24 Apr 28 12:58:38 PM PDT 24 29949236 ps
T57 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.745936438 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:26 PM PDT 24 570208638 ps
T69 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2430213462 Apr 28 12:59:03 PM PDT 24 Apr 28 12:59:06 PM PDT 24 26698682 ps
T92 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2580946875 Apr 28 12:58:25 PM PDT 24 Apr 28 12:58:27 PM PDT 24 284104330 ps
T61 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.899457553 Apr 28 12:58:15 PM PDT 24 Apr 28 12:58:19 PM PDT 24 74202727 ps
T270 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4198682778 Apr 28 12:58:39 PM PDT 24 Apr 28 12:58:40 PM PDT 24 53181019 ps
T271 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.586908786 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:24 PM PDT 24 38758425 ps
T93 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3296739562 Apr 28 12:58:13 PM PDT 24 Apr 28 12:58:19 PM PDT 24 465706231 ps
T94 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4014145795 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:17 PM PDT 24 62318748 ps
T244 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2698895084 Apr 28 12:58:10 PM PDT 24 Apr 28 12:58:12 PM PDT 24 110203962 ps
T95 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1068375746 Apr 28 12:58:45 PM PDT 24 Apr 28 12:58:46 PM PDT 24 47604026 ps
T96 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2211581823 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:26 PM PDT 24 39279497 ps
T97 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1804170420 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:15 PM PDT 24 117119492 ps
T230 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4058723856 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:20 PM PDT 24 55085392 ps
T98 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3223408500 Apr 28 12:58:15 PM PDT 24 Apr 28 12:58:19 PM PDT 24 95873310 ps
T268 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.944013342 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 36370667 ps
T202 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1415514255 Apr 28 12:58:28 PM PDT 24 Apr 28 12:58:31 PM PDT 24 324171537 ps
T272 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2877660173 Apr 28 12:58:34 PM PDT 24 Apr 28 12:58:35 PM PDT 24 36532644 ps
T265 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1629011429 Apr 28 12:58:49 PM PDT 24 Apr 28 12:58:50 PM PDT 24 34678597 ps
T269 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3943733075 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 46835812 ps
T277 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.228202915 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:29 PM PDT 24 62895598 ps
T201 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.777669314 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:43 PM PDT 24 82067822 ps
T234 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2465021035 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:27 PM PDT 24 773136207 ps
T203 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.925865394 Apr 28 12:58:23 PM PDT 24 Apr 28 12:58:27 PM PDT 24 754582741 ps
T1383 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.454360404 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:19 PM PDT 24 37010870 ps
T273 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1368476495 Apr 28 12:58:44 PM PDT 24 Apr 28 12:58:45 PM PDT 24 70003290 ps
T206 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1573985252 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:26 PM PDT 24 127350988 ps
T274 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1283963381 Apr 28 12:58:42 PM PDT 24 Apr 28 12:58:43 PM PDT 24 23424474 ps
T275 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3783099718 Apr 28 12:58:47 PM PDT 24 Apr 28 12:58:49 PM PDT 24 40752115 ps
T266 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.739179707 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:42 PM PDT 24 70038660 ps
T253 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1811847112 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:32 PM PDT 24 75277331 ps
T207 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2958288763 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:30 PM PDT 24 53765470 ps
T278 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2329076197 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:23 PM PDT 24 27771395 ps
T254 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.4156457276 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:29 PM PDT 24 61630065 ps
T255 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2114455528 Apr 28 12:58:28 PM PDT 24 Apr 28 12:58:31 PM PDT 24 137797696 ps
T256 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.30036109 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 79165767 ps
T233 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3982900929 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 308065232 ps
T276 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4053799563 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:41 PM PDT 24 42772953 ps
T257 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.25518700 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:21 PM PDT 24 51321633 ps
T208 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3328722666 Apr 28 12:58:15 PM PDT 24 Apr 28 12:58:19 PM PDT 24 129511654 ps
T232 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4018403380 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:27 PM PDT 24 530859088 ps
T204 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1971219159 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:25 PM PDT 24 135308386 ps
T267 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2520124737 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:16 PM PDT 24 75535290 ps
T227 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3890537425 Apr 28 12:58:33 PM PDT 24 Apr 28 12:58:35 PM PDT 24 67377269 ps
T209 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2792882475 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:22 PM PDT 24 249984944 ps
T245 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3290175928 Apr 28 12:58:33 PM PDT 24 Apr 28 12:58:34 PM PDT 24 118901435 ps
T225 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3868449959 Apr 28 12:58:25 PM PDT 24 Apr 28 12:58:28 PM PDT 24 201653376 ps
T1384 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1206980802 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:43 PM PDT 24 33889596 ps
T1385 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2228253954 Apr 28 12:58:43 PM PDT 24 Apr 28 12:58:46 PM PDT 24 166405016 ps
T264 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.208633681 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:15 PM PDT 24 54822567 ps
T246 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2652783374 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:21 PM PDT 24 198261026 ps
T1386 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1116283935 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:43 PM PDT 24 255012187 ps
T1387 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2671977164 Apr 28 12:58:39 PM PDT 24 Apr 28 12:58:42 PM PDT 24 549175295 ps
T279 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4017207581 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 57146083 ps
T1388 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3022459777 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:21 PM PDT 24 30567680 ps
T1389 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.961536822 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:30 PM PDT 24 56192194 ps
T226 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.133128022 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:44 PM PDT 24 111414412 ps
T247 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.37874707 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:23 PM PDT 24 41130314 ps
T248 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4135156057 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:22 PM PDT 24 44120442 ps
T229 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2327179222 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:25 PM PDT 24 141516155 ps
T261 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2845208798 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:26 PM PDT 24 140901746 ps
T205 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3069335540 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:22 PM PDT 24 154746740 ps
T1390 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3961760387 Apr 28 12:58:34 PM PDT 24 Apr 28 12:58:35 PM PDT 24 32819897 ps
T249 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1825582466 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:25 PM PDT 24 420302174 ps
T1391 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2459142183 Apr 28 12:58:25 PM PDT 24 Apr 28 12:58:29 PM PDT 24 435171698 ps
T262 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3019851932 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:27 PM PDT 24 157976788 ps
T1392 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1141175137 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:23 PM PDT 24 100720884 ps
T1393 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4270412802 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:30 PM PDT 24 57985723 ps
T1394 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2843176182 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:42 PM PDT 24 63530268 ps
T62 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3472016149 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:23 PM PDT 24 95208236 ps
T1395 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.152564289 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:29 PM PDT 24 32321200 ps
T63 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.484036747 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:24 PM PDT 24 64062869 ps
T263 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1039535454 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:21 PM PDT 24 218645960 ps
T228 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1356352552 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:45 PM PDT 24 108326057 ps
T1396 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3134155143 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:31 PM PDT 24 35769137 ps
T250 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3695565591 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:24 PM PDT 24 46537447 ps
T1397 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.326454612 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:32 PM PDT 24 85667898 ps
T251 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2480948046 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:22 PM PDT 24 349899229 ps
T1398 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2404432123 Apr 28 12:58:25 PM PDT 24 Apr 28 12:58:27 PM PDT 24 144831929 ps
T1399 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2582945978 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:33 PM PDT 24 175199334 ps
T280 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.927031957 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:44 PM PDT 24 286146549 ps
T252 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2137353863 Apr 28 12:58:17 PM PDT 24 Apr 28 12:58:23 PM PDT 24 375281144 ps
T1400 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3360144570 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:25 PM PDT 24 55536215 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.282658663 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:24 PM PDT 24 109389829 ps
T1401 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3416097520 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:19 PM PDT 24 59650631 ps
T1402 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3931522785 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:32 PM PDT 24 135314261 ps
T1403 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1868755696 Apr 28 12:58:23 PM PDT 24 Apr 28 12:58:26 PM PDT 24 66057746 ps
T1404 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2955834231 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:42 PM PDT 24 36873812 ps
T281 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1311301484 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:35 PM PDT 24 627850092 ps
T1405 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2661801039 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:41 PM PDT 24 31059934 ps
T1406 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1741362176 Apr 28 12:58:28 PM PDT 24 Apr 28 12:58:30 PM PDT 24 34440925 ps
T1407 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2615808449 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:29 PM PDT 24 462458679 ps
T1408 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1964773807 Apr 28 12:58:32 PM PDT 24 Apr 28 12:58:35 PM PDT 24 280215661 ps
T1409 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2992717335 Apr 28 12:58:43 PM PDT 24 Apr 28 12:58:44 PM PDT 24 55422985 ps
T1410 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2433846216 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:19 PM PDT 24 38849923 ps
T1411 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2341042682 Apr 28 12:58:25 PM PDT 24 Apr 28 12:58:27 PM PDT 24 192211596 ps
T284 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2964604532 Apr 28 12:58:25 PM PDT 24 Apr 28 12:58:31 PM PDT 24 833810530 ps
T1412 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1106589147 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:28 PM PDT 24 132671001 ps
T282 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.788223697 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:24 PM PDT 24 369595543 ps
T1413 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2728391637 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:17 PM PDT 24 271944981 ps
T1414 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1008468323 Apr 28 12:58:32 PM PDT 24 Apr 28 12:58:36 PM PDT 24 1005829687 ps
T1415 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2300887093 Apr 28 12:58:28 PM PDT 24 Apr 28 12:58:30 PM PDT 24 127002632 ps
T1416 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1624071587 Apr 28 12:58:14 PM PDT 24 Apr 28 12:58:19 PM PDT 24 247111192 ps
T1417 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.323253813 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:25 PM PDT 24 96026082 ps
T1418 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2367073673 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:22 PM PDT 24 365930689 ps
T1419 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.559700579 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:14 PM PDT 24 87437469 ps
T1420 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.498533052 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:29 PM PDT 24 34042962 ps
T1421 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.175293671 Apr 28 12:58:47 PM PDT 24 Apr 28 12:58:48 PM PDT 24 30769941 ps
T1422 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3738397333 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:25 PM PDT 24 90418768 ps
T1423 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3646062035 Apr 28 12:58:21 PM PDT 24 Apr 28 12:58:26 PM PDT 24 489142403 ps
T1424 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3700358182 Apr 28 12:58:43 PM PDT 24 Apr 28 12:58:45 PM PDT 24 40240930 ps
T1425 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1275278264 Apr 28 12:58:38 PM PDT 24 Apr 28 12:58:40 PM PDT 24 61636518 ps
T1426 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3906218753 Apr 28 12:58:15 PM PDT 24 Apr 28 12:58:20 PM PDT 24 117177042 ps
T1427 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2123735014 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:38 PM PDT 24 174904986 ps
T1428 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3420676839 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:42 PM PDT 24 48328652 ps
T1429 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3138565902 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:15 PM PDT 24 233019911 ps
T1430 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3258305024 Apr 28 12:58:22 PM PDT 24 Apr 28 12:58:24 PM PDT 24 48743987 ps
T1431 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3235804411 Apr 28 12:58:44 PM PDT 24 Apr 28 12:58:45 PM PDT 24 25576527 ps
T1432 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3770416009 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:19 PM PDT 24 48332708 ps
T1433 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.184849390 Apr 28 12:58:31 PM PDT 24 Apr 28 12:58:33 PM PDT 24 267984452 ps
T1434 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1366169678 Apr 28 12:58:42 PM PDT 24 Apr 28 12:58:43 PM PDT 24 99523139 ps
T1435 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4085875620 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:29 PM PDT 24 80949242 ps
T1436 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3717406470 Apr 28 12:58:42 PM PDT 24 Apr 28 12:58:43 PM PDT 24 41987521 ps
T1437 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2625486204 Apr 28 12:58:12 PM PDT 24 Apr 28 12:58:15 PM PDT 24 208975895 ps
T1438 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1674849306 Apr 28 12:58:31 PM PDT 24 Apr 28 12:58:36 PM PDT 24 864135248 ps
T1439 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3927716188 Apr 28 12:58:15 PM PDT 24 Apr 28 12:58:21 PM PDT 24 339078782 ps
T1440 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1685097807 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:30 PM PDT 24 202788148 ps
T1441 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1322285205 Apr 28 12:58:26 PM PDT 24 Apr 28 12:58:29 PM PDT 24 92393899 ps
T1442 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3832878705 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:45 PM PDT 24 271372293 ps
T1443 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3536228729 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:23 PM PDT 24 311586325 ps
T1444 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1414930728 Apr 28 12:58:13 PM PDT 24 Apr 28 12:58:19 PM PDT 24 727899137 ps
T1445 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3488149497 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:22 PM PDT 24 636043703 ps
T1446 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4075096747 Apr 28 12:58:28 PM PDT 24 Apr 28 12:58:30 PM PDT 24 36937737 ps
T1447 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1362142814 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:33 PM PDT 24 153262377 ps
T1448 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4215079477 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:37 PM PDT 24 34533490 ps
T1449 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2177729964 Apr 28 12:58:42 PM PDT 24 Apr 28 12:58:43 PM PDT 24 63018751 ps
T1450 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4017518501 Apr 28 12:58:44 PM PDT 24 Apr 28 12:58:46 PM PDT 24 27036556 ps
T1451 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4068167744 Apr 28 12:58:27 PM PDT 24 Apr 28 12:58:30 PM PDT 24 154898393 ps
T1452 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3238581567 Apr 28 12:58:55 PM PDT 24 Apr 28 12:58:56 PM PDT 24 33086956 ps
T1453 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.130906278 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:22 PM PDT 24 137025438 ps
T1454 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2359467773 Apr 28 12:58:16 PM PDT 24 Apr 28 12:58:20 PM PDT 24 160288622 ps
T1455 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3799322225 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:26 PM PDT 24 53740492 ps
T1456 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2930551835 Apr 28 12:58:28 PM PDT 24 Apr 28 12:58:30 PM PDT 24 125302767 ps
T1457 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2348489858 Apr 28 12:58:29 PM PDT 24 Apr 28 12:58:31 PM PDT 24 59452995 ps
T1458 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.651677909 Apr 28 12:58:23 PM PDT 24 Apr 28 12:58:26 PM PDT 24 140294268 ps
T1459 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3878876053 Apr 28 12:58:29 PM PDT 24 Apr 28 12:58:34 PM PDT 24 730987558 ps
T1460 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.885526810 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:22 PM PDT 24 98998454 ps
T1461 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3486470108 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:43 PM PDT 24 51617611 ps
T1462 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2530245519 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:42 PM PDT 24 28633742 ps
T1463 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1288486269 Apr 28 12:58:35 PM PDT 24 Apr 28 12:58:36 PM PDT 24 61415262 ps
T1464 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4293824813 Apr 28 12:58:43 PM PDT 24 Apr 28 12:58:45 PM PDT 24 32477460 ps
T283 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4029307540 Apr 28 12:58:10 PM PDT 24 Apr 28 12:58:14 PM PDT 24 374708215 ps
T1465 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2906121570 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:33 PM PDT 24 318192493 ps
T1466 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.129607995 Apr 28 12:58:19 PM PDT 24 Apr 28 12:58:22 PM PDT 24 95339551 ps
T1467 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.449368583 Apr 28 12:58:37 PM PDT 24 Apr 28 12:58:38 PM PDT 24 36021805 ps
T1468 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.193983691 Apr 28 12:58:33 PM PDT 24 Apr 28 12:58:40 PM PDT 24 38955459 ps
T1469 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1797552873 Apr 28 12:58:40 PM PDT 24 Apr 28 12:58:41 PM PDT 24 29508529 ps
T1470 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.163668524 Apr 28 12:58:30 PM PDT 24 Apr 28 12:58:33 PM PDT 24 185347748 ps
T1471 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3264090464 Apr 28 12:58:46 PM PDT 24 Apr 28 12:58:47 PM PDT 24 36475613 ps
T1472 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1413474693 Apr 28 12:58:36 PM PDT 24 Apr 28 12:58:40 PM PDT 24 480866201 ps
T1473 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.146051132 Apr 28 12:58:20 PM PDT 24 Apr 28 12:58:23 PM PDT 24 77285742 ps
T1474 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3544279268 Apr 28 12:58:37 PM PDT 24 Apr 28 12:58:39 PM PDT 24 91821373 ps
T1475 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2789797307 Apr 28 12:58:35 PM PDT 24 Apr 28 12:58:37 PM PDT 24 69961700 ps
T1476 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1876349925 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:25 PM PDT 24 39246568 ps
T1477 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2703413950 Apr 28 12:58:24 PM PDT 24 Apr 28 12:58:28 PM PDT 24 134925199 ps
T1478 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3458868151 Apr 28 12:58:35 PM PDT 24 Apr 28 12:58:36 PM PDT 24 40220896 ps
T1479 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3892097546 Apr 28 12:58:31 PM PDT 24 Apr 28 12:58:33 PM PDT 24 49547516 ps
T1480 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1827783801 Apr 28 12:58:18 PM PDT 24 Apr 28 12:58:21 PM PDT 24 124942464 ps

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1189710277
Short name T12
Test name
Test status
Simulation time 25747460374 ps
CPU time 49.49 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 204352 kb
Host smart-8628a1c2-266d-49a7-b141-4974626e5447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11897
10277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1189710277
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4016071309
Short name T67
Test name
Test status
Simulation time 41513898 ps
CPU time 0.65 seconds
Started Apr 28 12:58:33 PM PDT 24
Finished Apr 28 12:58:34 PM PDT 24
Peak memory 203304 kb
Host smart-305c39ac-db0e-458c-add2-07cc8209cbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016071309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4016071309
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.745936438
Short name T57
Test name
Test status
Simulation time 570208638 ps
CPU time 4.36 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 203924 kb
Host smart-b13d9659-9ee6-4242-9af6-f87648f96c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=745936438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.745936438
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1263033983
Short name T23
Test name
Test status
Simulation time 8432956665 ps
CPU time 9.65 seconds
Started Apr 28 02:12:08 PM PDT 24
Finished Apr 28 02:12:18 PM PDT 24
Peak memory 204132 kb
Host smart-8c311538-262e-405f-b7b4-8265142412a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12630
33983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1263033983
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1702014437
Short name T1
Test name
Test status
Simulation time 38928543 ps
CPU time 0.65 seconds
Started Apr 28 02:11:07 PM PDT 24
Finished Apr 28 02:11:09 PM PDT 24
Peak memory 204036 kb
Host smart-e8580800-7272-44dc-89e4-01b260c901f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17020
14437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1702014437
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3938828993
Short name T65
Test name
Test status
Simulation time 80024388 ps
CPU time 0.69 seconds
Started Apr 28 12:58:46 PM PDT 24
Finished Apr 28 12:58:47 PM PDT 24
Peak memory 203088 kb
Host smart-6b4b8052-3a8c-43ba-8301-343735973c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3938828993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3938828993
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2406816425
Short name T37
Test name
Test status
Simulation time 8407364635 ps
CPU time 10.3 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:48 PM PDT 24
Peak memory 204104 kb
Host smart-ad7a74cc-606b-435e-a022-dd2ea9d32262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068
16425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2406816425
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3187249794
Short name T55
Test name
Test status
Simulation time 78552918 ps
CPU time 1.18 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 212252 kb
Host smart-43280d1a-a90f-4ce2-ab8e-cdd70d7b0ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187249794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3187249794
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.769158120
Short name T4
Test name
Test status
Simulation time 8363772189 ps
CPU time 10.12 seconds
Started Apr 28 02:13:46 PM PDT 24
Finished Apr 28 02:13:57 PM PDT 24
Peak memory 204148 kb
Host smart-ffa5d456-f7ff-44f5-8b5c-0fd50c9cc86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76915
8120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.769158120
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2023600738
Short name T322
Test name
Test status
Simulation time 8367666617 ps
CPU time 8.16 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204124 kb
Host smart-02466ed7-55e7-436d-be01-2319ed48f96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236
00738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2023600738
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3153540687
Short name T39
Test name
Test status
Simulation time 8409698407 ps
CPU time 7.84 seconds
Started Apr 28 02:12:30 PM PDT 24
Finished Apr 28 02:12:38 PM PDT 24
Peak memory 204124 kb
Host smart-0112ad14-24aa-48f7-8f63-0d66806ffd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31535
40687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3153540687
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2606896670
Short name T58
Test name
Test status
Simulation time 543377898 ps
CPU time 1.47 seconds
Started Apr 28 02:11:31 PM PDT 24
Finished Apr 28 02:11:33 PM PDT 24
Peak memory 221412 kb
Host smart-1616357a-ee1b-4c4a-a3e7-b7a8c4cbbb90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2606896670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2606896670
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1197171680
Short name T68
Test name
Test status
Simulation time 29949236 ps
CPU time 0.65 seconds
Started Apr 28 12:58:37 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203228 kb
Host smart-d271cd10-bacf-4997-9083-6ead354614de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1197171680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1197171680
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4020591852
Short name T52
Test name
Test status
Simulation time 71197741 ps
CPU time 1.67 seconds
Started Apr 28 02:14:03 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204140 kb
Host smart-fd40afaa-5f3d-40d5-8871-2b699578cd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40205
91852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4020591852
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.586908786
Short name T271
Test name
Test status
Simulation time 38758425 ps
CPU time 0.66 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:24 PM PDT 24
Peak memory 203260 kb
Host smart-37c2c372-8b40-4a76-b63b-cb4bba76a73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=586908786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.586908786
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.4131310986
Short name T40
Test name
Test status
Simulation time 8388078333 ps
CPU time 8.9 seconds
Started Apr 28 02:12:16 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204092 kb
Host smart-2bc55cfe-7763-4f24-86d9-91e1f294c764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41313
10986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.4131310986
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.899457553
Short name T61
Test name
Test status
Simulation time 74202727 ps
CPU time 0.83 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203616 kb
Host smart-218c91e6-7952-4edb-a7b2-ff69404f19d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=899457553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.899457553
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1356352552
Short name T228
Test name
Test status
Simulation time 108326057 ps
CPU time 2.79 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:45 PM PDT 24
Peak memory 204088 kb
Host smart-0d917e0e-e194-455b-94d0-7ad279f3b090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1356352552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1356352552
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1741362176
Short name T1406
Test name
Test status
Simulation time 34440925 ps
CPU time 0.66 seconds
Started Apr 28 12:58:28 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 203208 kb
Host smart-0078c5d8-3160-4467-a5e8-9eb4f411e84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1741362176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1741362176
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1311301484
Short name T281
Test name
Test status
Simulation time 627850092 ps
CPU time 4.57 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:35 PM PDT 24
Peak memory 203396 kb
Host smart-a416a73a-aeaf-44c4-8376-77bc7c38b2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1311301484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1311301484
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.472276940
Short name T81
Test name
Test status
Simulation time 8386340634 ps
CPU time 9.45 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:58 PM PDT 24
Peak memory 204100 kb
Host smart-55602d17-d6c3-45d5-9943-d79cbd7ccc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47227
6940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.472276940
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3296739562
Short name T93
Test name
Test status
Simulation time 465706231 ps
CPU time 4.19 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203840 kb
Host smart-5060c5ba-5b16-4639-a9f4-7bd234adf054
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3296739562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3296739562
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3023882164
Short name T11
Test name
Test status
Simulation time 5103208331 ps
CPU time 133.67 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:13:10 PM PDT 24
Peak memory 204368 kb
Host smart-58fdbed3-f35c-4c2e-81bb-78adf495256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
82164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3023882164
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2298812104
Short name T90
Test name
Test status
Simulation time 15855828353 ps
CPU time 28.7 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:40 PM PDT 24
Peak memory 204360 kb
Host smart-7cfc9051-52b2-4565-a211-d4ab08691156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22988
12104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2298812104
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.25518700
Short name T257
Test name
Test status
Simulation time 51321633 ps
CPU time 0.85 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 203768 kb
Host smart-0dce1bb1-af75-4354-8670-21a613bef8c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=25518700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.25518700
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3982900929
Short name T233
Test name
Test status
Simulation time 308065232 ps
CPU time 2.43 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203992 kb
Host smart-1e813a8c-5e24-4de0-b596-62ddea9d8476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3982900929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3982900929
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1413474693
Short name T1472
Test name
Test status
Simulation time 480866201 ps
CPU time 3.04 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:40 PM PDT 24
Peak memory 203968 kb
Host smart-a3304d70-2541-4a1e-b42d-56d2c0ef4969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1413474693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1413474693
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3776937513
Short name T43
Test name
Test status
Simulation time 88476079 ps
CPU time 0.76 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:36 PM PDT 24
Peak memory 203892 kb
Host smart-ed05fdc6-b448-4f9f-8c1a-1c410c132079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37769
37513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3776937513
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.4133163532
Short name T79
Test name
Test status
Simulation time 8463765596 ps
CPU time 8.16 seconds
Started Apr 28 02:10:59 PM PDT 24
Finished Apr 28 02:11:07 PM PDT 24
Peak memory 204068 kb
Host smart-a91a9e16-7876-4b7e-8b14-3f423adef925
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4133163532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.4133163532
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3635022619
Short name T186
Test name
Test status
Simulation time 8401249640 ps
CPU time 7.32 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 204108 kb
Host smart-f879385f-6b22-4fe7-86e6-9bbd50a3fb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36350
22619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3635022619
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_smoke.4242546616
Short name T516
Test name
Test status
Simulation time 8426368073 ps
CPU time 10.09 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:11:01 PM PDT 24
Peak memory 204076 kb
Host smart-d0802bf4-9b58-4161-82f0-a288cade1533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42425
46616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.4242546616
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3649711636
Short name T179
Test name
Test status
Simulation time 8373103682 ps
CPU time 8.43 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:35 PM PDT 24
Peak memory 204152 kb
Host smart-9b48df50-800a-424b-b693-e7337122631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36497
11636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3649711636
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2128984232
Short name T176
Test name
Test status
Simulation time 8423599294 ps
CPU time 8.35 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:36 PM PDT 24
Peak memory 204100 kb
Host smart-82c8c8d3-56cd-44b0-b900-1a5a4b2e5461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21289
84232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2128984232
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1838690941
Short name T19
Test name
Test status
Simulation time 8383649193 ps
CPU time 8.07 seconds
Started Apr 28 02:12:49 PM PDT 24
Finished Apr 28 02:12:58 PM PDT 24
Peak memory 204104 kb
Host smart-6244a3ff-6e36-492d-aff6-8c19bd088756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18386
90941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1838690941
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.809933774
Short name T1110
Test name
Test status
Simulation time 8404764621 ps
CPU time 8.24 seconds
Started Apr 28 02:13:11 PM PDT 24
Finished Apr 28 02:13:20 PM PDT 24
Peak memory 204100 kb
Host smart-1983c432-3f58-4e39-b28e-d302494d1974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80993
3774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.809933774
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2494008795
Short name T765
Test name
Test status
Simulation time 8411367059 ps
CPU time 7.56 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:20 PM PDT 24
Peak memory 204032 kb
Host smart-106b9d55-2030-46ff-be93-4ea87a7d568e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24940
08795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2494008795
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1423819930
Short name T86
Test name
Test status
Simulation time 8376402506 ps
CPU time 7.69 seconds
Started Apr 28 02:13:30 PM PDT 24
Finished Apr 28 02:13:38 PM PDT 24
Peak memory 204112 kb
Host smart-d5b4edda-cd59-44b4-bdf1-53b945f661ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14238
19930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1423819930
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1227295244
Short name T170
Test name
Test status
Simulation time 8404200644 ps
CPU time 7.63 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204056 kb
Host smart-d703e460-c9da-4e86-a464-ee06cbc8c448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12272
95244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1227295244
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2407603460
Short name T615
Test name
Test status
Simulation time 8440112918 ps
CPU time 8.06 seconds
Started Apr 28 02:14:12 PM PDT 24
Finished Apr 28 02:14:21 PM PDT 24
Peak memory 204128 kb
Host smart-d945ef7d-4971-474b-93db-526da96ad33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24076
03460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2407603460
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2106038495
Short name T237
Test name
Test status
Simulation time 8402811046 ps
CPU time 8.23 seconds
Started Apr 28 02:12:09 PM PDT 24
Finished Apr 28 02:12:18 PM PDT 24
Peak memory 204100 kb
Host smart-dbfa4662-6dda-4f50-a35a-c961a45b9d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21060
38495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2106038495
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1624071587
Short name T1416
Test name
Test status
Simulation time 247111192 ps
CPU time 2.79 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 212268 kb
Host smart-7add6fef-4ec4-40ac-bbb2-5d010e222c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1624071587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1624071587
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3367561767
Short name T1151
Test name
Test status
Simulation time 8393304234 ps
CPU time 9.52 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:37 PM PDT 24
Peak memory 204108 kb
Host smart-26cddf46-a719-4d7c-9734-0942be996dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33675
61767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3367561767
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3069335540
Short name T205
Test name
Test status
Simulation time 154746740 ps
CPU time 2.23 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 204012 kb
Host smart-4c61d884-4733-4ca6-b014-a32d1ef51842
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3069335540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3069335540
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1105682440
Short name T862
Test name
Test status
Simulation time 8410517771 ps
CPU time 10.34 seconds
Started Apr 28 02:11:00 PM PDT 24
Finished Apr 28 02:11:10 PM PDT 24
Peak memory 204144 kb
Host smart-bb2c0cb0-0028-40e0-8923-556151099625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11056
82440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1105682440
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3964700012
Short name T1000
Test name
Test status
Simulation time 8365876622 ps
CPU time 8.68 seconds
Started Apr 28 02:10:59 PM PDT 24
Finished Apr 28 02:11:08 PM PDT 24
Peak memory 204104 kb
Host smart-e02d2aad-1ae2-4d8c-9e05-28f82c876691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39647
00012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3964700012
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.776503346
Short name T112
Test name
Test status
Simulation time 8436421350 ps
CPU time 7.57 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:03 PM PDT 24
Peak memory 204108 kb
Host smart-659a4e79-47c0-4117-bbad-3c0133ed50e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77650
3346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.776503346
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3876809645
Short name T195
Test name
Test status
Simulation time 8368991104 ps
CPU time 7.55 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:13 PM PDT 24
Peak memory 204076 kb
Host smart-8111610a-3a8b-4c98-baaa-0e04c085a945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38768
09645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3876809645
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3997399589
Short name T701
Test name
Test status
Simulation time 8434495794 ps
CPU time 7.93 seconds
Started Apr 28 02:11:01 PM PDT 24
Finished Apr 28 02:11:09 PM PDT 24
Peak memory 204124 kb
Host smart-87e9cb6e-bf1e-4b62-85f4-57b74e683bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39973
99589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3997399589
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.605314677
Short name T101
Test name
Test status
Simulation time 8425635751 ps
CPU time 8.73 seconds
Started Apr 28 02:11:03 PM PDT 24
Finished Apr 28 02:11:12 PM PDT 24
Peak memory 204116 kb
Host smart-03a10f5e-1615-4126-b41d-dd5b15cc96d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60531
4677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.605314677
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4082289793
Short name T169
Test name
Test status
Simulation time 8441472120 ps
CPU time 9.56 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:15 PM PDT 24
Peak memory 204088 kb
Host smart-74c9fc5c-605e-4613-aebd-886004d65c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40822
89793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4082289793
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1756093072
Short name T692
Test name
Test status
Simulation time 8414055714 ps
CPU time 8.71 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:11 PM PDT 24
Peak memory 204108 kb
Host smart-d1f5d9be-88be-490f-a62e-9a019c072fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
93072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1756093072
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3013133230
Short name T29
Test name
Test status
Simulation time 8389413946 ps
CPU time 7.56 seconds
Started Apr 28 02:11:07 PM PDT 24
Finished Apr 28 02:11:16 PM PDT 24
Peak memory 204160 kb
Host smart-cc86fd04-96c2-4964-8ee5-8da551c98d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
33230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3013133230
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.558304477
Short name T1319
Test name
Test status
Simulation time 8421032112 ps
CPU time 7.65 seconds
Started Apr 28 02:12:07 PM PDT 24
Finished Apr 28 02:12:15 PM PDT 24
Peak memory 204104 kb
Host smart-2258b318-89e6-42f6-8e77-7043d4e2fe38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55830
4477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.558304477
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3068753068
Short name T1193
Test name
Test status
Simulation time 8370575089 ps
CPU time 8.71 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:37 PM PDT 24
Peak memory 204120 kb
Host smart-d3e1c84f-6d85-4cd3-b6e2-6c5391d6f655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
53068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3068753068
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3225698913
Short name T1211
Test name
Test status
Simulation time 8397607823 ps
CPU time 8.95 seconds
Started Apr 28 02:12:15 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204092 kb
Host smart-3f5bb06e-07e7-440e-976c-b5533a299b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32256
98913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3225698913
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.239903320
Short name T241
Test name
Test status
Simulation time 23972689915 ps
CPU time 42.13 seconds
Started Apr 28 02:12:29 PM PDT 24
Finished Apr 28 02:13:12 PM PDT 24
Peak memory 204448 kb
Host smart-ca27ab07-36b7-489e-8f5b-dbdabd961bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
3320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.239903320
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.387411867
Short name T72
Test name
Test status
Simulation time 8465776341 ps
CPU time 7.83 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:43 PM PDT 24
Peak memory 204072 kb
Host smart-d5352468-f503-4d5d-ba3d-e9545eedc84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38741
1867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.387411867
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2714186551
Short name T843
Test name
Test status
Simulation time 8365104138 ps
CPU time 9.35 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204140 kb
Host smart-2c6e219f-0208-4a44-914d-dab1e816ceb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27141
86551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2714186551
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1710876495
Short name T36
Test name
Test status
Simulation time 8457777042 ps
CPU time 7.48 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:55 PM PDT 24
Peak memory 204092 kb
Host smart-1c218823-3161-410c-9a23-e28b35056cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17108
76495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1710876495
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3684557986
Short name T100
Test name
Test status
Simulation time 8433060053 ps
CPU time 8.06 seconds
Started Apr 28 02:12:50 PM PDT 24
Finished Apr 28 02:12:59 PM PDT 24
Peak memory 204036 kb
Host smart-808d4c85-ebe8-4533-b856-211e09b0c0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36845
57986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3684557986
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3540892285
Short name T138
Test name
Test status
Simulation time 8526754816 ps
CPU time 9.54 seconds
Started Apr 28 02:12:58 PM PDT 24
Finished Apr 28 02:13:08 PM PDT 24
Peak memory 204000 kb
Host smart-5610ff44-2f73-477c-b9c0-bf58ce9e36be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35408
92285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3540892285
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4223083673
Short name T110
Test name
Test status
Simulation time 8508728626 ps
CPU time 7.56 seconds
Started Apr 28 02:12:58 PM PDT 24
Finished Apr 28 02:13:07 PM PDT 24
Peak memory 204080 kb
Host smart-65b47612-396c-41a8-9937-b787d509ee77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42230
83673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4223083673
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.911341700
Short name T1107
Test name
Test status
Simulation time 8446626331 ps
CPU time 7.91 seconds
Started Apr 28 02:13:06 PM PDT 24
Finished Apr 28 02:13:15 PM PDT 24
Peak memory 204036 kb
Host smart-3d13ed7c-4d03-4d05-bb2f-07cf8f6f58fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91134
1700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.911341700
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2994420335
Short name T102
Test name
Test status
Simulation time 8393349126 ps
CPU time 9.13 seconds
Started Apr 28 02:13:06 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204072 kb
Host smart-8086b6bf-e3da-4e0a-b015-51fe0f587ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29944
20335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2994420335
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.470149861
Short name T26
Test name
Test status
Simulation time 8409529134 ps
CPU time 10 seconds
Started Apr 28 02:11:10 PM PDT 24
Finished Apr 28 02:11:21 PM PDT 24
Peak memory 204156 kb
Host smart-8967a3f0-146a-4548-8412-2b9b128d970c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47014
9861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.470149861
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2958616146
Short name T105
Test name
Test status
Simulation time 8434918632 ps
CPU time 8.79 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:44 PM PDT 24
Peak memory 203852 kb
Host smart-a76dfabd-239f-4c81-a7fa-dda07024bc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29586
16146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2958616146
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.128579149
Short name T1115
Test name
Test status
Simulation time 8449291788 ps
CPU time 8.84 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:10 PM PDT 24
Peak memory 204100 kb
Host smart-ce1f2214-56f5-471d-b51f-e4c0d03fba38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12857
9149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.128579149
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2262812889
Short name T118
Test name
Test status
Simulation time 8406924861 ps
CPU time 8.39 seconds
Started Apr 28 02:14:59 PM PDT 24
Finished Apr 28 02:15:08 PM PDT 24
Peak memory 204084 kb
Host smart-8b072af1-af60-4724-89a5-b2c29d03a760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22628
12889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2262812889
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1825582466
Short name T249
Test name
Test status
Simulation time 420302174 ps
CPU time 3.66 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 203712 kb
Host smart-5545d246-8445-48a0-bf9a-ff9a0a06d6ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1825582466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1825582466
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2480948046
Short name T251
Test name
Test status
Simulation time 349899229 ps
CPU time 3.85 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 203792 kb
Host smart-aa4d45f8-e574-4387-a4b0-b05a3d0a76f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2480948046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2480948046
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.484036747
Short name T63
Test name
Test status
Simulation time 64062869 ps
CPU time 0.8 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:24 PM PDT 24
Peak memory 203628 kb
Host smart-a946d554-8390-49f4-acb1-547aad1e5b93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=484036747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.484036747
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1804170420
Short name T97
Test name
Test status
Simulation time 117119492 ps
CPU time 1.7 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 212220 kb
Host smart-2ae95b0a-4c56-49a4-b0b6-75006e86c7cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804170420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1804170420
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.454360404
Short name T1383
Test name
Test status
Simulation time 37010870 ps
CPU time 0.66 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203248 kb
Host smart-9faab50c-542c-48ea-8893-fed92d956427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=454360404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.454360404
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2359467773
Short name T1454
Test name
Test status
Simulation time 160288622 ps
CPU time 2.33 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 212176 kb
Host smart-e8a537b7-7d37-451e-b31d-7315b4d462b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2359467773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2359467773
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2728391637
Short name T1413
Test name
Test status
Simulation time 271944981 ps
CPU time 2.54 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 203764 kb
Host smart-e7ffa5d4-cf0d-493f-9f10-3c8bdab23756
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2728391637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2728391637
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3138565902
Short name T1429
Test name
Test status
Simulation time 233019911 ps
CPU time 1.82 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 203960 kb
Host smart-99e757bc-b38d-4318-b2db-0ab37ebafb73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3138565902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3138565902
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3328722666
Short name T208
Test name
Test status
Simulation time 129511654 ps
CPU time 1.61 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203936 kb
Host smart-bd634cfd-59dc-4dbf-a494-98ed31b11ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3328722666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3328722666
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3927716188
Short name T1439
Test name
Test status
Simulation time 339078782 ps
CPU time 3.56 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 203736 kb
Host smart-eb38a072-645a-4c21-8353-cefed374a719
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3927716188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3927716188
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3488149497
Short name T1445
Test name
Test status
Simulation time 636043703 ps
CPU time 4.42 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 203940 kb
Host smart-a5afd8c9-8e6f-4f72-8caa-62c9981df004
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3488149497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3488149497
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4058723856
Short name T230
Test name
Test status
Simulation time 55085392 ps
CPU time 0.89 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 203596 kb
Host smart-6195c437-1da0-4864-8640-19106bae52a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4058723856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4058723856
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.885526810
Short name T1460
Test name
Test status
Simulation time 98998454 ps
CPU time 1.31 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 212224 kb
Host smart-97351d3e-ba36-4021-af85-de9ca76fbb37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885526810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.885526810
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.559700579
Short name T1419
Test name
Test status
Simulation time 87437469 ps
CPU time 0.83 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:14 PM PDT 24
Peak memory 203584 kb
Host smart-e8e8df7a-4471-49e2-be7b-949346ab8b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=559700579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.559700579
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2520124737
Short name T267
Test name
Test status
Simulation time 75535290 ps
CPU time 0.69 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:16 PM PDT 24
Peak memory 203288 kb
Host smart-4056b7ed-ee64-479d-8415-b28f649620bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2520124737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2520124737
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2698895084
Short name T244
Test name
Test status
Simulation time 110203962 ps
CPU time 1.41 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:12 PM PDT 24
Peak memory 204008 kb
Host smart-d5555fe6-5161-4f6b-af65-4b20b45c0a30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2698895084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2698895084
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3646062035
Short name T1423
Test name
Test status
Simulation time 489142403 ps
CPU time 4.45 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 203876 kb
Host smart-64a56ebd-7cbf-49f1-b969-df98136d0fc3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3646062035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3646062035
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.130906278
Short name T1453
Test name
Test status
Simulation time 137025438 ps
CPU time 1.62 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 203888 kb
Host smart-6163452a-a425-4376-8ab6-6edc91683868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=130906278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.130906278
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1116283935
Short name T1386
Test name
Test status
Simulation time 255012187 ps
CPU time 2.25 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 212052 kb
Host smart-88e3d025-889a-4d38-8548-0aba2b7e1ab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116283935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1116283935
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.4156457276
Short name T254
Test name
Test status
Simulation time 61630065 ps
CPU time 0.97 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203888 kb
Host smart-103323f5-13d1-43fc-b3de-d8f0ff050a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4156457276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.4156457276
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4053799563
Short name T276
Test name
Test status
Simulation time 42772953 ps
CPU time 0.64 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:41 PM PDT 24
Peak memory 203312 kb
Host smart-05386b4f-c87c-4670-a943-16a657cf49a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4053799563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4053799563
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4270412802
Short name T1393
Test name
Test status
Simulation time 57985723 ps
CPU time 1.06 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 203948 kb
Host smart-00d88e0c-f734-4ca8-8d26-da5c4ed01f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270412802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4270412802
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1685097807
Short name T1440
Test name
Test status
Simulation time 202788148 ps
CPU time 2.53 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 204028 kb
Host smart-476cd20b-15ea-41ac-9bf9-19177e5f89ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1685097807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1685097807
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2582945978
Short name T1399
Test name
Test status
Simulation time 175199334 ps
CPU time 1.95 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:33 PM PDT 24
Peak memory 214352 kb
Host smart-fb13a07a-6e7e-4fa1-ad72-3649200432d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582945978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2582945978
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3420676839
Short name T1428
Test name
Test status
Simulation time 48328652 ps
CPU time 0.78 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:42 PM PDT 24
Peak memory 203588 kb
Host smart-c92d2e9c-2e26-4be2-95fb-4a9bb2035e40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3420676839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3420676839
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2955834231
Short name T1404
Test name
Test status
Simulation time 36873812 ps
CPU time 0.67 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:42 PM PDT 24
Peak memory 203116 kb
Host smart-070c77a4-4edf-432a-958a-046d816893d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2955834231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2955834231
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3931522785
Short name T1402
Test name
Test status
Simulation time 135314261 ps
CPU time 1.1 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:32 PM PDT 24
Peak memory 203832 kb
Host smart-72b634f0-5935-4652-92c2-13cfecd00b83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3931522785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3931522785
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2930551835
Short name T1456
Test name
Test status
Simulation time 125302767 ps
CPU time 1.31 seconds
Started Apr 28 12:58:28 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 204088 kb
Host smart-1457f9d1-98d5-4058-8956-097f27e36a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930551835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2930551835
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3878876053
Short name T1459
Test name
Test status
Simulation time 730987558 ps
CPU time 4.43 seconds
Started Apr 28 12:58:29 PM PDT 24
Finished Apr 28 12:58:34 PM PDT 24
Peak memory 203940 kb
Host smart-82db350f-9d07-4887-8029-e4c18e14d9ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3878876053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3878876053
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.961536822
Short name T1389
Test name
Test status
Simulation time 56192194 ps
CPU time 1.42 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 214784 kb
Host smart-27d48694-2c9d-43a9-8c79-806220bd6e6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961536822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.961536822
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4085875620
Short name T1435
Test name
Test status
Simulation time 80949242 ps
CPU time 0.91 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203892 kb
Host smart-41732c12-9088-48a0-b80c-dbafb90f9ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4085875620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4085875620
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2530245519
Short name T1462
Test name
Test status
Simulation time 28633742 ps
CPU time 0.73 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:42 PM PDT 24
Peak memory 203288 kb
Host smart-5648be04-ecd2-4ac2-8b3a-08bdbdd27231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2530245519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2530245519
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3892097546
Short name T1479
Test name
Test status
Simulation time 49547516 ps
CPU time 1 seconds
Started Apr 28 12:58:31 PM PDT 24
Finished Apr 28 12:58:33 PM PDT 24
Peak memory 204020 kb
Host smart-05474619-6b66-4b80-9657-1af5c3cb7096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3892097546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3892097546
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2958288763
Short name T207
Test name
Test status
Simulation time 53765470 ps
CPU time 1.41 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 203992 kb
Host smart-fe1f489b-df8c-42e1-82b7-472777af743a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2958288763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2958288763
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.163668524
Short name T1470
Test name
Test status
Simulation time 185347748 ps
CPU time 2.44 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:33 PM PDT 24
Peak memory 203884 kb
Host smart-6a4ad1e6-cea3-4d85-ae43-6da9f3808bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=163668524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.163668524
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.777669314
Short name T201
Test name
Test status
Simulation time 82067822 ps
CPU time 1.93 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 212184 kb
Host smart-64588b8e-f2a8-42d1-a735-2bd958260097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777669314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.777669314
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3290175928
Short name T245
Test name
Test status
Simulation time 118901435 ps
CPU time 1.02 seconds
Started Apr 28 12:58:33 PM PDT 24
Finished Apr 28 12:58:34 PM PDT 24
Peak memory 203884 kb
Host smart-d85d7904-9543-4381-a721-28f0edccb1c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3290175928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3290175928
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.184849390
Short name T1433
Test name
Test status
Simulation time 267984452 ps
CPU time 1.81 seconds
Started Apr 28 12:58:31 PM PDT 24
Finished Apr 28 12:58:33 PM PDT 24
Peak memory 203996 kb
Host smart-d9bef83f-b3f9-4c0e-af4c-f85514273261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=184849390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.184849390
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1008468323
Short name T1414
Test name
Test status
Simulation time 1005829687 ps
CPU time 3.55 seconds
Started Apr 28 12:58:32 PM PDT 24
Finished Apr 28 12:58:36 PM PDT 24
Peak memory 204000 kb
Host smart-f1ed5247-e416-48c8-8bb4-74c8273c881d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1008468323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1008468323
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1362142814
Short name T1447
Test name
Test status
Simulation time 153262377 ps
CPU time 1.83 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:33 PM PDT 24
Peak memory 212092 kb
Host smart-88841bbf-97f3-4285-93e1-73ab24961c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362142814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1362142814
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.193983691
Short name T1468
Test name
Test status
Simulation time 38955459 ps
CPU time 0.92 seconds
Started Apr 28 12:58:33 PM PDT 24
Finished Apr 28 12:58:40 PM PDT 24
Peak memory 203860 kb
Host smart-25974453-6749-4e77-8687-801eda318979
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=193983691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.193983691
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.498533052
Short name T1420
Test name
Test status
Simulation time 34042962 ps
CPU time 0.67 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203280 kb
Host smart-6c903298-5cf5-413d-ad19-17e8bb3ad33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498533052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.498533052
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2580946875
Short name T92
Test name
Test status
Simulation time 284104330 ps
CPU time 1.19 seconds
Started Apr 28 12:58:25 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 203952 kb
Host smart-5434e39c-982f-4c1b-a9b6-5bf52b0d7579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2580946875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2580946875
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4068167744
Short name T1451
Test name
Test status
Simulation time 154898393 ps
CPU time 1.81 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 203964 kb
Host smart-97c487e8-78df-4760-8d70-51cc137280d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4068167744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4068167744
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1674849306
Short name T1438
Test name
Test status
Simulation time 864135248 ps
CPU time 4.63 seconds
Started Apr 28 12:58:31 PM PDT 24
Finished Apr 28 12:58:36 PM PDT 24
Peak memory 203756 kb
Host smart-d6e20698-7267-40ba-9b2f-113b315c5647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1674849306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1674849306
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1322285205
Short name T1441
Test name
Test status
Simulation time 92393899 ps
CPU time 2.02 seconds
Started Apr 28 12:58:26 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 215348 kb
Host smart-fef6f58c-85dd-42f6-a5ed-21fe51ecbbf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322285205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1322285205
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4075096747
Short name T1446
Test name
Test status
Simulation time 36937737 ps
CPU time 0.88 seconds
Started Apr 28 12:58:28 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 203944 kb
Host smart-1c8726f2-bb1b-422e-be28-2a2e7fb20f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4075096747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4075096747
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.228202915
Short name T277
Test name
Test status
Simulation time 62895598 ps
CPU time 0.73 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203164 kb
Host smart-0b8c96c5-809b-4899-8d24-6e383ff9ff72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=228202915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.228202915
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1811847112
Short name T253
Test name
Test status
Simulation time 75277331 ps
CPU time 1.34 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:32 PM PDT 24
Peak memory 203848 kb
Host smart-fc581cab-ca7a-4f2c-baa9-566a3e630d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811847112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1811847112
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.133128022
Short name T226
Test name
Test status
Simulation time 111414412 ps
CPU time 2.92 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:44 PM PDT 24
Peak memory 204072 kb
Host smart-b0d16938-6983-404f-8a79-0ca481729a16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=133128022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.133128022
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2964604532
Short name T284
Test name
Test status
Simulation time 833810530 ps
CPU time 5.26 seconds
Started Apr 28 12:58:25 PM PDT 24
Finished Apr 28 12:58:31 PM PDT 24
Peak memory 203880 kb
Host smart-92e3363b-8826-4cbf-b9f5-fc87e17ed681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2964604532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2964604532
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3890537425
Short name T227
Test name
Test status
Simulation time 67377269 ps
CPU time 1.73 seconds
Started Apr 28 12:58:33 PM PDT 24
Finished Apr 28 12:58:35 PM PDT 24
Peak memory 212200 kb
Host smart-5f86e40c-0dc4-47fe-9e15-a1d010633179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890537425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3890537425
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2843176182
Short name T1394
Test name
Test status
Simulation time 63530268 ps
CPU time 1.04 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:42 PM PDT 24
Peak memory 203916 kb
Host smart-2ae3a784-350f-4602-95e9-3faa54fdfc81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2843176182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2843176182
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.739179707
Short name T266
Test name
Test status
Simulation time 70038660 ps
CPU time 0.69 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:42 PM PDT 24
Peak memory 203296 kb
Host smart-cf5e1d77-8747-4554-9fcf-c78a53b8cb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=739179707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.739179707
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.30036109
Short name T256
Test name
Test status
Simulation time 79165767 ps
CPU time 1.1 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203952 kb
Host smart-7c6e4b0c-a94a-40f3-9e49-96cb35ffd320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=30036109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.30036109
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1964773807
Short name T1408
Test name
Test status
Simulation time 280215661 ps
CPU time 2.83 seconds
Started Apr 28 12:58:32 PM PDT 24
Finished Apr 28 12:58:35 PM PDT 24
Peak memory 212228 kb
Host smart-e6d102c4-71bb-46bf-83d5-1bba5d9f498e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1964773807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1964773807
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1275278264
Short name T1425
Test name
Test status
Simulation time 61636518 ps
CPU time 1.14 seconds
Started Apr 28 12:58:38 PM PDT 24
Finished Apr 28 12:58:40 PM PDT 24
Peak memory 213652 kb
Host smart-d43e74fd-5a26-4e79-9427-6eaeaad7e7c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275278264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1275278264
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3544279268
Short name T1474
Test name
Test status
Simulation time 91821373 ps
CPU time 0.93 seconds
Started Apr 28 12:58:37 PM PDT 24
Finished Apr 28 12:58:39 PM PDT 24
Peak memory 203748 kb
Host smart-355b295a-ee8a-4b95-85eb-0a9e437aa4b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3544279268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3544279268
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.152564289
Short name T1395
Test name
Test status
Simulation time 32321200 ps
CPU time 0.69 seconds
Started Apr 28 12:58:27 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203232 kb
Host smart-5dc5d8e0-73a4-4904-936b-301ab7ba87bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=152564289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.152564289
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1288486269
Short name T1463
Test name
Test status
Simulation time 61415262 ps
CPU time 0.97 seconds
Started Apr 28 12:58:35 PM PDT 24
Finished Apr 28 12:58:36 PM PDT 24
Peak memory 203952 kb
Host smart-805d47b3-8ab2-4a6c-b848-7796347ef82a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1288486269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1288486269
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2348489858
Short name T1457
Test name
Test status
Simulation time 59452995 ps
CPU time 1.63 seconds
Started Apr 28 12:58:29 PM PDT 24
Finished Apr 28 12:58:31 PM PDT 24
Peak memory 203944 kb
Host smart-dc6ec246-1143-4127-8a1e-822bf9c5dc46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2348489858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2348489858
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.927031957
Short name T280
Test name
Test status
Simulation time 286146549 ps
CPU time 2.7 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:44 PM PDT 24
Peak memory 204012 kb
Host smart-ff93aca3-6d83-4438-9402-0d9b9e5742d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=927031957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.927031957
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2906121570
Short name T1465
Test name
Test status
Simulation time 318192493 ps
CPU time 2.02 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:33 PM PDT 24
Peak memory 212056 kb
Host smart-cf732bad-8f44-40ba-9621-49985d287f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906121570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2906121570
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2789797307
Short name T1475
Test name
Test status
Simulation time 69961700 ps
CPU time 0.96 seconds
Started Apr 28 12:58:35 PM PDT 24
Finished Apr 28 12:58:37 PM PDT 24
Peak memory 203888 kb
Host smart-46a78096-ef36-4ab6-906b-0694c7a1db28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2789797307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2789797307
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3458868151
Short name T1478
Test name
Test status
Simulation time 40220896 ps
CPU time 0.71 seconds
Started Apr 28 12:58:35 PM PDT 24
Finished Apr 28 12:58:36 PM PDT 24
Peak memory 203316 kb
Host smart-ecfda8b2-72c1-4fad-92fe-a4a65fa788c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3458868151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3458868151
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2123735014
Short name T1427
Test name
Test status
Simulation time 174904986 ps
CPU time 1.55 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 204048 kb
Host smart-d17cdbd6-ee7a-487c-9710-24879da3fb12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2123735014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2123735014
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3832878705
Short name T1442
Test name
Test status
Simulation time 271372293 ps
CPU time 3.13 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:45 PM PDT 24
Peak memory 204012 kb
Host smart-94075e6e-75a5-4371-99c3-68214af8d9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3832878705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3832878705
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1068375746
Short name T95
Test name
Test status
Simulation time 47604026 ps
CPU time 0.77 seconds
Started Apr 28 12:58:45 PM PDT 24
Finished Apr 28 12:58:46 PM PDT 24
Peak memory 203748 kb
Host smart-9ac3acc2-d7a5-4931-968a-bff37f06b0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1068375746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1068375746
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1366169678
Short name T1434
Test name
Test status
Simulation time 99523139 ps
CPU time 0.71 seconds
Started Apr 28 12:58:42 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 203288 kb
Host smart-02d8152e-9fca-45d2-81a2-182720dcf9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1366169678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1366169678
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2228253954
Short name T1385
Test name
Test status
Simulation time 166405016 ps
CPU time 1.48 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:58:46 PM PDT 24
Peak memory 203824 kb
Host smart-5f422846-5327-4005-b610-30704ee2f8b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2228253954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2228253954
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3486470108
Short name T1461
Test name
Test status
Simulation time 51617611 ps
CPU time 1.59 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 203980 kb
Host smart-932b55d0-5332-4e2e-ab3d-d3ad68748403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3486470108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3486470108
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2671977164
Short name T1387
Test name
Test status
Simulation time 549175295 ps
CPU time 2.8 seconds
Started Apr 28 12:58:39 PM PDT 24
Finished Apr 28 12:58:42 PM PDT 24
Peak memory 203912 kb
Host smart-1873571a-8e44-4f0a-b9a2-529be1ee76e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2671977164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2671977164
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2625486204
Short name T1437
Test name
Test status
Simulation time 208975895 ps
CPU time 2.31 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 203900 kb
Host smart-9b9ee434-5e0b-41be-906d-3723bed97385
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2625486204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2625486204
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3416097520
Short name T1401
Test name
Test status
Simulation time 59650631 ps
CPU time 0.88 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203732 kb
Host smart-322e77e5-fc69-40c0-b15b-11fb430c8da8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3416097520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3416097520
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3906218753
Short name T1426
Test name
Test status
Simulation time 117177042 ps
CPU time 2.46 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:20 PM PDT 24
Peak memory 212224 kb
Host smart-cb667e05-7ebe-4ee7-9b74-636ec85efbd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906218753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3906218753
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.208633681
Short name T264
Test name
Test status
Simulation time 54822567 ps
CPU time 0.84 seconds
Started Apr 28 12:58:12 PM PDT 24
Finished Apr 28 12:58:15 PM PDT 24
Peak memory 203632 kb
Host smart-0ff810f9-7020-4a90-afaa-9b8e40aac76f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=208633681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.208633681
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3022459777
Short name T1388
Test name
Test status
Simulation time 30567680 ps
CPU time 0.67 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 203172 kb
Host smart-6b6bc3bc-b4f7-4779-9645-828bbf27128c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3022459777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3022459777
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2652783374
Short name T246
Test name
Test status
Simulation time 198261026 ps
CPU time 2.37 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 212204 kb
Host smart-787b62c2-fe59-42a8-9d88-e38b43dd5292
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2652783374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2652783374
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1414930728
Short name T1444
Test name
Test status
Simulation time 727899137 ps
CPU time 4.49 seconds
Started Apr 28 12:58:13 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203904 kb
Host smart-fd5436bc-daab-49ac-9d4c-f9a7c393b771
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1414930728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1414930728
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1039535454
Short name T263
Test name
Test status
Simulation time 218645960 ps
CPU time 1.72 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 203936 kb
Host smart-d13ddab0-5467-4469-a47c-5c2f6b9f3f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1039535454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1039535454
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.282658663
Short name T231
Test name
Test status
Simulation time 109389829 ps
CPU time 3.25 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:24 PM PDT 24
Peak memory 212220 kb
Host smart-aaceddbd-1eb9-48d3-916c-e5275b543ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282658663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.282658663
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4029307540
Short name T283
Test name
Test status
Simulation time 374708215 ps
CPU time 3.93 seconds
Started Apr 28 12:58:10 PM PDT 24
Finished Apr 28 12:58:14 PM PDT 24
Peak memory 203880 kb
Host smart-4dfeb9d2-b2e5-43cc-81bc-3e2bff691d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4029307540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4029307540
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3961760387
Short name T1390
Test name
Test status
Simulation time 32819897 ps
CPU time 0.67 seconds
Started Apr 28 12:58:34 PM PDT 24
Finished Apr 28 12:58:35 PM PDT 24
Peak memory 203248 kb
Host smart-eea86742-61db-4dda-83a3-8da8c0a67717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3961760387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3961760387
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2661801039
Short name T1405
Test name
Test status
Simulation time 31059934 ps
CPU time 0.65 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:41 PM PDT 24
Peak memory 203212 kb
Host smart-28cf1ed3-61c8-4aa1-8f24-7df0af944a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661801039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2661801039
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.944013342
Short name T268
Test name
Test status
Simulation time 36370667 ps
CPU time 0.68 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203108 kb
Host smart-8796acee-d2da-4b54-96b9-74aad406a41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=944013342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.944013342
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3235804411
Short name T1431
Test name
Test status
Simulation time 25576527 ps
CPU time 0.67 seconds
Started Apr 28 12:58:44 PM PDT 24
Finished Apr 28 12:58:45 PM PDT 24
Peak memory 203020 kb
Host smart-b938cd7b-e663-4390-897a-8b05f1426883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235804411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3235804411
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2877660173
Short name T272
Test name
Test status
Simulation time 36532644 ps
CPU time 0.67 seconds
Started Apr 28 12:58:34 PM PDT 24
Finished Apr 28 12:58:35 PM PDT 24
Peak memory 203272 kb
Host smart-2be2e859-0947-4ed8-b206-7302ecc1587a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2877660173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2877660173
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4215079477
Short name T1448
Test name
Test status
Simulation time 34533490 ps
CPU time 0.65 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:37 PM PDT 24
Peak memory 203244 kb
Host smart-aa1d5af8-b459-454c-b4cf-c9b4cf2d10d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4215079477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4215079477
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3134155143
Short name T1396
Test name
Test status
Simulation time 35769137 ps
CPU time 0.67 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:31 PM PDT 24
Peak memory 203320 kb
Host smart-14a3eae8-18b0-40fa-a341-9da962313e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3134155143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3134155143
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4017207581
Short name T279
Test name
Test status
Simulation time 57146083 ps
CPU time 0.68 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203332 kb
Host smart-f7e3d7b0-08a7-4a52-8e97-7c9bd4db07a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4017207581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4017207581
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2177729964
Short name T1449
Test name
Test status
Simulation time 63018751 ps
CPU time 0.7 seconds
Started Apr 28 12:58:42 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 203180 kb
Host smart-edfd95f8-6716-4c12-bee0-6fb038c8bc95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2177729964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2177729964
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3700358182
Short name T1424
Test name
Test status
Simulation time 40240930 ps
CPU time 0.68 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:58:45 PM PDT 24
Peak memory 203112 kb
Host smart-7312ff06-558a-41b2-b120-b4dfc368cd4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700358182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3700358182
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2137353863
Short name T252
Test name
Test status
Simulation time 375281144 ps
CPU time 3.65 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 203932 kb
Host smart-3b74b670-2a88-49fb-ae28-cdd7f1b64381
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2137353863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2137353863
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2615808449
Short name T1407
Test name
Test status
Simulation time 462458679 ps
CPU time 6.95 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203912 kb
Host smart-f3001584-c764-4c7e-b7f7-a767c0d28c92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2615808449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2615808449
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.129607995
Short name T1466
Test name
Test status
Simulation time 95339551 ps
CPU time 1.25 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 212120 kb
Host smart-4a71136c-17f4-4dfd-8d35-856f6af5ea11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129607995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.129607995
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2211581823
Short name T96
Test name
Test status
Simulation time 39279497 ps
CPU time 0.93 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 203836 kb
Host smart-5f4efb77-85bf-41e3-bc3e-53f697163275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2211581823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2211581823
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3770416009
Short name T1432
Test name
Test status
Simulation time 48332708 ps
CPU time 0.65 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203216 kb
Host smart-6b8ed7ce-8ef0-4ba4-8b54-4d7c91282c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3770416009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3770416009
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4135156057
Short name T248
Test name
Test status
Simulation time 44120442 ps
CPU time 1.33 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 212052 kb
Host smart-b054cc44-5176-4af8-8fd5-0eb50da8c2bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4135156057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4135156057
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3655681605
Short name T1382
Test name
Test status
Simulation time 109303649 ps
CPU time 2.34 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 203936 kb
Host smart-3d072c46-3575-4d20-9e00-b5df25f658ae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3655681605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3655681605
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3223408500
Short name T98
Test name
Test status
Simulation time 95873310 ps
CPU time 1.09 seconds
Started Apr 28 12:58:15 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 204032 kb
Host smart-746c64ac-26c7-4e9b-855c-ae98ab4fcfa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3223408500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3223408500
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2792882475
Short name T209
Test name
Test status
Simulation time 249984944 ps
CPU time 2.67 seconds
Started Apr 28 12:58:17 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 203908 kb
Host smart-0dbba3c1-034d-4071-86a7-24018d3de5af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2792882475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2792882475
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3116453167
Short name T56
Test name
Test status
Simulation time 865899633 ps
CPU time 4.91 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 203912 kb
Host smart-fee17ce2-a712-4c40-a6ea-928bf03d2572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3116453167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3116453167
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4198682778
Short name T270
Test name
Test status
Simulation time 53181019 ps
CPU time 0.69 seconds
Started Apr 28 12:58:39 PM PDT 24
Finished Apr 28 12:58:40 PM PDT 24
Peak memory 203324 kb
Host smart-cc98abef-70c7-48bb-aa3c-4b26cfd7fbba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4198682778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4198682778
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3717406470
Short name T1436
Test name
Test status
Simulation time 41987521 ps
CPU time 0.65 seconds
Started Apr 28 12:58:42 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 203184 kb
Host smart-25a25c13-65ea-4812-91b4-638bf80d817a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3717406470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3717406470
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1206980802
Short name T1384
Test name
Test status
Simulation time 33889596 ps
CPU time 0.67 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 203196 kb
Host smart-146c7e61-1928-460c-9cc0-31925b595079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1206980802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1206980802
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1473230329
Short name T66
Test name
Test status
Simulation time 50011542 ps
CPU time 0.68 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:58:44 PM PDT 24
Peak memory 203184 kb
Host smart-d3c3abbb-02b6-4779-9ee5-64209790dabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1473230329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1473230329
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3238581567
Short name T1452
Test name
Test status
Simulation time 33086956 ps
CPU time 0.63 seconds
Started Apr 28 12:58:55 PM PDT 24
Finished Apr 28 12:58:56 PM PDT 24
Peak memory 203292 kb
Host smart-29857e20-04bf-47ad-a08e-382eaaa71862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3238581567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3238581567
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1368476495
Short name T273
Test name
Test status
Simulation time 70003290 ps
CPU time 0.72 seconds
Started Apr 28 12:58:44 PM PDT 24
Finished Apr 28 12:58:45 PM PDT 24
Peak memory 203300 kb
Host smart-35f44453-9e89-4064-a9fe-22b1b673497d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1368476495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1368476495
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4293824813
Short name T1464
Test name
Test status
Simulation time 32477460 ps
CPU time 0.65 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:58:45 PM PDT 24
Peak memory 203288 kb
Host smart-389f2cde-0ea5-4e2c-96b9-c2a63d897908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4293824813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4293824813
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3783099718
Short name T275
Test name
Test status
Simulation time 40752115 ps
CPU time 0.67 seconds
Started Apr 28 12:58:47 PM PDT 24
Finished Apr 28 12:58:49 PM PDT 24
Peak memory 203292 kb
Host smart-1b6d3f2b-bbec-4d6b-b628-47bf45f09650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783099718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3783099718
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2430213462
Short name T69
Test name
Test status
Simulation time 26698682 ps
CPU time 0.69 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:06 PM PDT 24
Peak memory 203108 kb
Host smart-b9fef68c-44a8-41ee-bb74-debb8b0ce5a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430213462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2430213462
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2992717335
Short name T1409
Test name
Test status
Simulation time 55422985 ps
CPU time 0.68 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:58:44 PM PDT 24
Peak memory 203272 kb
Host smart-1199cda2-0850-49fc-8ca3-7d3597f2c6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2992717335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2992717335
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2367073673
Short name T1418
Test name
Test status
Simulation time 365930689 ps
CPU time 3.58 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:22 PM PDT 24
Peak memory 203672 kb
Host smart-6bd93bcd-5810-4449-8570-dc6f287936e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2367073673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2367073673
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1871091401
Short name T64
Test name
Test status
Simulation time 1480137523 ps
CPU time 8.37 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203904 kb
Host smart-75dedd50-00cb-4593-9cad-fd4518155361
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1871091401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1871091401
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3472016149
Short name T62
Test name
Test status
Simulation time 95208236 ps
CPU time 0.93 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 203564 kb
Host smart-c7dac824-7bad-4769-ad23-9d0be897940d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3472016149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3472016149
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1971219159
Short name T204
Test name
Test status
Simulation time 135308386 ps
CPU time 2.45 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 212176 kb
Host smart-fc52596c-51c7-4877-af09-089accc3bd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971219159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1971219159
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4014145795
Short name T94
Test name
Test status
Simulation time 62318748 ps
CPU time 0.93 seconds
Started Apr 28 12:58:14 PM PDT 24
Finished Apr 28 12:58:17 PM PDT 24
Peak memory 203960 kb
Host smart-fe2e8f4f-f86a-4131-8b08-79e7a5e1bccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4014145795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.4014145795
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2433846216
Short name T1410
Test name
Test status
Simulation time 38849923 ps
CPU time 0.66 seconds
Started Apr 28 12:58:16 PM PDT 24
Finished Apr 28 12:58:19 PM PDT 24
Peak memory 203264 kb
Host smart-8eb089f6-c628-4e5d-8c92-341f74d1f787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2433846216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2433846216
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.323253813
Short name T1417
Test name
Test status
Simulation time 96026082 ps
CPU time 1.47 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 204016 kb
Host smart-eb753cf6-ca1f-46c1-b412-ac847ed79d1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=323253813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.323253813
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2459142183
Short name T1391
Test name
Test status
Simulation time 435171698 ps
CPU time 2.69 seconds
Started Apr 28 12:58:25 PM PDT 24
Finished Apr 28 12:58:29 PM PDT 24
Peak memory 203792 kb
Host smart-24c4417a-1ab6-4b8e-8f85-a8433949a04a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2459142183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2459142183
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1827783801
Short name T1480
Test name
Test status
Simulation time 124942464 ps
CPU time 1.5 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:21 PM PDT 24
Peak memory 203908 kb
Host smart-75997710-c549-4874-bd3b-d0fccbb343a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1827783801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1827783801
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3868449959
Short name T225
Test name
Test status
Simulation time 201653376 ps
CPU time 2.51 seconds
Started Apr 28 12:58:25 PM PDT 24
Finished Apr 28 12:58:28 PM PDT 24
Peak memory 203892 kb
Host smart-014831ee-c322-47b9-a1cd-0ce09d2c0a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3868449959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3868449959
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2465021035
Short name T234
Test name
Test status
Simulation time 773136207 ps
CPU time 2.86 seconds
Started Apr 28 12:58:18 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 203968 kb
Host smart-83a76d20-6276-495f-8038-8b47c3421515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2465021035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2465021035
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4017518501
Short name T1450
Test name
Test status
Simulation time 27036556 ps
CPU time 0.62 seconds
Started Apr 28 12:58:44 PM PDT 24
Finished Apr 28 12:58:46 PM PDT 24
Peak memory 203136 kb
Host smart-a298cc42-177c-4fe3-a068-53b01ae260bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4017518501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.4017518501
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.449368583
Short name T1467
Test name
Test status
Simulation time 36021805 ps
CPU time 0.67 seconds
Started Apr 28 12:58:37 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203096 kb
Host smart-7990b668-0519-486e-a147-9b5886ca3838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=449368583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.449368583
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3264090464
Short name T1471
Test name
Test status
Simulation time 36475613 ps
CPU time 0.72 seconds
Started Apr 28 12:58:46 PM PDT 24
Finished Apr 28 12:58:47 PM PDT 24
Peak memory 203208 kb
Host smart-0da86124-09d2-4ab0-94cf-578b1464f4e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3264090464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3264090464
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1797552873
Short name T1469
Test name
Test status
Simulation time 29508529 ps
CPU time 0.64 seconds
Started Apr 28 12:58:40 PM PDT 24
Finished Apr 28 12:58:41 PM PDT 24
Peak memory 203224 kb
Host smart-bd9f2f99-acc8-46cc-8ecb-deffe2d0f85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1797552873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1797552873
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1629011429
Short name T265
Test name
Test status
Simulation time 34678597 ps
CPU time 0.64 seconds
Started Apr 28 12:58:49 PM PDT 24
Finished Apr 28 12:58:50 PM PDT 24
Peak memory 203184 kb
Host smart-b8f29962-9355-4ee1-b149-2a440bb9d1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1629011429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1629011429
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3943733075
Short name T269
Test name
Test status
Simulation time 46835812 ps
CPU time 0.7 seconds
Started Apr 28 12:58:36 PM PDT 24
Finished Apr 28 12:58:38 PM PDT 24
Peak memory 203244 kb
Host smart-7bb5e91a-51a2-4f15-9d76-8b19bbd1f9e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3943733075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3943733075
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1283963381
Short name T274
Test name
Test status
Simulation time 23424474 ps
CPU time 0.61 seconds
Started Apr 28 12:58:42 PM PDT 24
Finished Apr 28 12:58:43 PM PDT 24
Peak memory 203240 kb
Host smart-35bfbc3f-7a3f-4aba-8cda-3b2d6a27f4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1283963381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1283963381
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.175293671
Short name T1421
Test name
Test status
Simulation time 30769941 ps
CPU time 0.63 seconds
Started Apr 28 12:58:47 PM PDT 24
Finished Apr 28 12:58:48 PM PDT 24
Peak memory 203188 kb
Host smart-cd5a457c-0579-4775-a037-bf3fa7ff72c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=175293671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.175293671
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3019851932
Short name T262
Test name
Test status
Simulation time 157976788 ps
CPU time 1.95 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 212116 kb
Host smart-95c358f7-a1f0-4791-882e-adfa469f7593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019851932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.3019851932
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3799322225
Short name T1455
Test name
Test status
Simulation time 53740492 ps
CPU time 0.86 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 203640 kb
Host smart-1be79b13-bc6f-444e-a008-c7144cc96039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3799322225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3799322225
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2329076197
Short name T278
Test name
Test status
Simulation time 27771395 ps
CPU time 0.65 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 203292 kb
Host smart-8814405c-3418-4bec-a2c7-020853e6c996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2329076197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2329076197
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2300887093
Short name T1415
Test name
Test status
Simulation time 127002632 ps
CPU time 1.48 seconds
Started Apr 28 12:58:28 PM PDT 24
Finished Apr 28 12:58:30 PM PDT 24
Peak memory 203960 kb
Host smart-e26fe012-e44a-4d60-9ae8-d7a6da85c876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2300887093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2300887093
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1868755696
Short name T1403
Test name
Test status
Simulation time 66057746 ps
CPU time 1.94 seconds
Started Apr 28 12:58:23 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 204012 kb
Host smart-29e08214-017c-4016-9bea-e401a5fd4a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1868755696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1868755696
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3536228729
Short name T1443
Test name
Test status
Simulation time 311586325 ps
CPU time 2.4 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 203944 kb
Host smart-135faddf-03a2-4f69-9909-47e6c4670f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3536228729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3536228729
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2404432123
Short name T1398
Test name
Test status
Simulation time 144831929 ps
CPU time 1.38 seconds
Started Apr 28 12:58:25 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 213672 kb
Host smart-562f6f91-1b58-426b-83a2-be3e124e0826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404432123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2404432123
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3695565591
Short name T250
Test name
Test status
Simulation time 46537447 ps
CPU time 0.91 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:24 PM PDT 24
Peak memory 203932 kb
Host smart-4a4925fe-3446-41fb-9c89-0463251bb12f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3695565591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3695565591
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.651677909
Short name T1458
Test name
Test status
Simulation time 140294268 ps
CPU time 1.57 seconds
Started Apr 28 12:58:23 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 203836 kb
Host smart-9ec6ddb3-3d39-46fb-9fb4-ebcdf5279d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=651677909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.651677909
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1573985252
Short name T206
Test name
Test status
Simulation time 127350988 ps
CPU time 1.57 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 204032 kb
Host smart-01488c88-c092-431e-aa6c-1f529680df80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1573985252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1573985252
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1415514255
Short name T202
Test name
Test status
Simulation time 324171537 ps
CPU time 2.44 seconds
Started Apr 28 12:58:28 PM PDT 24
Finished Apr 28 12:58:31 PM PDT 24
Peak memory 203812 kb
Host smart-51d8d9a7-8a0a-4938-bd62-ffda9d3638db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1415514255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1415514255
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3738397333
Short name T1422
Test name
Test status
Simulation time 90418768 ps
CPU time 2.37 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 212208 kb
Host smart-9d310181-4805-440c-bdbe-c759d01192bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738397333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3738397333
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.37874707
Short name T247
Test name
Test status
Simulation time 41130314 ps
CPU time 0.83 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 203740 kb
Host smart-03e6d13a-d023-470a-99c8-b18a1580e93e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=37874707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.37874707
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3258305024
Short name T1430
Test name
Test status
Simulation time 48743987 ps
CPU time 0.66 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:24 PM PDT 24
Peak memory 203308 kb
Host smart-24b5aa93-d68f-49ae-9241-6dd4a1518c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3258305024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3258305024
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1141175137
Short name T1392
Test name
Test status
Simulation time 100720884 ps
CPU time 1.61 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 204012 kb
Host smart-c20e65cb-75df-4946-8395-a4f5167682a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1141175137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1141175137
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1106589147
Short name T1412
Test name
Test status
Simulation time 132671001 ps
CPU time 1.45 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:28 PM PDT 24
Peak memory 203844 kb
Host smart-9d633785-715d-451e-ae11-608e3e748c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1106589147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1106589147
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.788223697
Short name T282
Test name
Test status
Simulation time 369595543 ps
CPU time 2.51 seconds
Started Apr 28 12:58:21 PM PDT 24
Finished Apr 28 12:58:24 PM PDT 24
Peak memory 203888 kb
Host smart-e9f57141-9393-4ab4-a550-2523da57c576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=788223697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.788223697
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2327179222
Short name T229
Test name
Test status
Simulation time 141516155 ps
CPU time 1.73 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 214512 kb
Host smart-628d5861-72bc-40f2-b849-3ef9c98edd51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327179222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2327179222
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3360144570
Short name T1400
Test name
Test status
Simulation time 55536215 ps
CPU time 0.89 seconds
Started Apr 28 12:58:19 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 203840 kb
Host smart-11b3e51e-3b44-43d8-ae27-795ac7058348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3360144570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3360144570
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1876349925
Short name T1476
Test name
Test status
Simulation time 39246568 ps
CPU time 0.67 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:25 PM PDT 24
Peak memory 203308 kb
Host smart-d858cd44-b709-4687-ac1a-47177597e5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1876349925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1876349925
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2845208798
Short name T261
Test name
Test status
Simulation time 140901746 ps
CPU time 1.28 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:26 PM PDT 24
Peak memory 203944 kb
Host smart-3928110f-c3d7-41d6-a2c6-f7bd9e05f53d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2845208798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2845208798
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.146051132
Short name T1473
Test name
Test status
Simulation time 77285742 ps
CPU time 2.24 seconds
Started Apr 28 12:58:20 PM PDT 24
Finished Apr 28 12:58:23 PM PDT 24
Peak memory 203888 kb
Host smart-a2419415-0eb5-49f0-9ab0-8cff3bbe33e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=146051132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.146051132
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4018403380
Short name T232
Test name
Test status
Simulation time 530859088 ps
CPU time 4.05 seconds
Started Apr 28 12:58:22 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 203992 kb
Host smart-e65513ba-92fe-45c6-90be-1116cacd93b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4018403380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4018403380
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2341042682
Short name T1411
Test name
Test status
Simulation time 192211596 ps
CPU time 1.4 seconds
Started Apr 28 12:58:25 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 212164 kb
Host smart-bb0a0df7-2a63-455b-ac53-e5b202f3fc82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341042682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2341042682
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.326454612
Short name T1397
Test name
Test status
Simulation time 85667898 ps
CPU time 0.98 seconds
Started Apr 28 12:58:30 PM PDT 24
Finished Apr 28 12:58:32 PM PDT 24
Peak memory 203960 kb
Host smart-210f6ac3-0550-4a06-9d3b-d5aaa637c6b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=326454612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.326454612
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2114455528
Short name T255
Test name
Test status
Simulation time 137797696 ps
CPU time 1.55 seconds
Started Apr 28 12:58:28 PM PDT 24
Finished Apr 28 12:58:31 PM PDT 24
Peak memory 203972 kb
Host smart-5d7f5a80-25bd-4885-8e81-d4675d01ef4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2114455528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2114455528
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2703413950
Short name T1477
Test name
Test status
Simulation time 134925199 ps
CPU time 2.74 seconds
Started Apr 28 12:58:24 PM PDT 24
Finished Apr 28 12:58:28 PM PDT 24
Peak memory 203932 kb
Host smart-1f7b914e-67ed-43ff-82a9-b90dae813342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2703413950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2703413950
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.925865394
Short name T203
Test name
Test status
Simulation time 754582741 ps
CPU time 3.25 seconds
Started Apr 28 12:58:23 PM PDT 24
Finished Apr 28 12:58:27 PM PDT 24
Peak memory 203888 kb
Host smart-902ba7cf-d293-4a3b-bfef-e396171c3bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=925865394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.925865394
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.3188520807
Short name T665
Test name
Test status
Simulation time 8379761342 ps
CPU time 8.39 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:11 PM PDT 24
Peak memory 204108 kb
Host smart-c95e6ad9-4ae7-4526-82b6-cd560e20164a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3188520807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.3188520807
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.1289986198
Short name T747
Test name
Test status
Simulation time 8405577097 ps
CPU time 9.41 seconds
Started Apr 28 02:11:03 PM PDT 24
Finished Apr 28 02:11:13 PM PDT 24
Peak memory 204112 kb
Host smart-7ee611e3-68e0-46c0-8cf1-99d4a2e9d3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899
86198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.1289986198
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4108421630
Short name T1061
Test name
Test status
Simulation time 8419884496 ps
CPU time 7.65 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:03 PM PDT 24
Peak memory 204040 kb
Host smart-fef3f9a5-6bd7-45ac-864b-04a4b3ab6691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084
21630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4108421630
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.3221564090
Short name T1029
Test name
Test status
Simulation time 8438439613 ps
CPU time 10.49 seconds
Started Apr 28 02:10:52 PM PDT 24
Finished Apr 28 02:11:03 PM PDT 24
Peak memory 204080 kb
Host smart-ef6d8342-8aa5-4211-ba46-3d3230b485e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32215
64090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3221564090
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2563897095
Short name T1022
Test name
Test status
Simulation time 76797186 ps
CPU time 2.01 seconds
Started Apr 28 02:10:56 PM PDT 24
Finished Apr 28 02:10:59 PM PDT 24
Peak memory 204200 kb
Host smart-b44e87ef-6bd5-4569-b86b-7a38e5b99273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
97095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2563897095
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1616361990
Short name T452
Test name
Test status
Simulation time 8438062612 ps
CPU time 7.36 seconds
Started Apr 28 02:10:56 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 204108 kb
Host smart-f6abf8cc-94bd-4c3e-9816-bc03667f3b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
61990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1616361990
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.941410928
Short name T374
Test name
Test status
Simulation time 8441028200 ps
CPU time 7.45 seconds
Started Apr 28 02:10:58 PM PDT 24
Finished Apr 28 02:11:06 PM PDT 24
Peak memory 204160 kb
Host smart-01d44b32-6379-4236-9979-086ca269ab90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94141
0928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.941410928
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3385802244
Short name T896
Test name
Test status
Simulation time 8365210028 ps
CPU time 7.75 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:03 PM PDT 24
Peak memory 204112 kb
Host smart-b16f7c20-6407-4509-93ea-d1d5553f8f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33858
02244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3385802244
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4184569411
Short name T833
Test name
Test status
Simulation time 8413713585 ps
CPU time 7.78 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 204068 kb
Host smart-de5b9a11-88d6-4600-8921-bf5902180fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
69411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4184569411
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2497768389
Short name T416
Test name
Test status
Simulation time 8404281248 ps
CPU time 9.06 seconds
Started Apr 28 02:10:57 PM PDT 24
Finished Apr 28 02:11:07 PM PDT 24
Peak memory 204160 kb
Host smart-7c6d012b-b43e-4893-b483-578ac4435366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24977
68389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2497768389
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1572006003
Short name T1003
Test name
Test status
Simulation time 8374888834 ps
CPU time 8.79 seconds
Started Apr 28 02:10:54 PM PDT 24
Finished Apr 28 02:11:03 PM PDT 24
Peak memory 204028 kb
Host smart-b2e3bdb9-9c30-465c-93f7-a1bc56300b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15720
06003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1572006003
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.544799432
Short name T784
Test name
Test status
Simulation time 35137370 ps
CPU time 0.62 seconds
Started Apr 28 02:10:59 PM PDT 24
Finished Apr 28 02:11:00 PM PDT 24
Peak memory 203888 kb
Host smart-2e423d82-d6f8-4d8f-b3f7-d5a7f3ca1541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54479
9432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.544799432
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3526131559
Short name T1217
Test name
Test status
Simulation time 18408753244 ps
CPU time 36.2 seconds
Started Apr 28 02:10:54 PM PDT 24
Finished Apr 28 02:11:31 PM PDT 24
Peak memory 204400 kb
Host smart-cc790ddd-b5da-437f-97d7-627e66642ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35261
31559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3526131559
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.308215488
Short name T1069
Test name
Test status
Simulation time 8415436407 ps
CPU time 8.44 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:05 PM PDT 24
Peak memory 204116 kb
Host smart-34a2ff5b-f49d-4a15-86c1-65ea25d8cf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.308215488
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2457125107
Short name T1204
Test name
Test status
Simulation time 8421217493 ps
CPU time 7.97 seconds
Started Apr 28 02:10:56 PM PDT 24
Finished Apr 28 02:11:05 PM PDT 24
Peak memory 204108 kb
Host smart-f6dde044-271e-4a56-ad12-342567b3a970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24571
25107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2457125107
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3224377434
Short name T894
Test name
Test status
Simulation time 8391917277 ps
CPU time 7.18 seconds
Started Apr 28 02:10:54 PM PDT 24
Finished Apr 28 02:11:02 PM PDT 24
Peak memory 204136 kb
Host smart-a9254503-9452-498a-969b-5ddc956562f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32243
77434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3224377434
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2898629311
Short name T70
Test name
Test status
Simulation time 276703008 ps
CPU time 1.11 seconds
Started Apr 28 02:11:03 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 221444 kb
Host smart-60732041-0a2f-4338-95ea-04312266b6d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2898629311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2898629311
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3338057559
Short name T794
Test name
Test status
Simulation time 8376544498 ps
CPU time 8.56 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:05 PM PDT 24
Peak memory 204152 kb
Host smart-1d69bae8-d77f-4ccb-9ea7-268f93aab60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33380
57559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3338057559
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2032600318
Short name T818
Test name
Test status
Simulation time 8380030694 ps
CPU time 7.39 seconds
Started Apr 28 02:10:54 PM PDT 24
Finished Apr 28 02:11:02 PM PDT 24
Peak memory 204056 kb
Host smart-92d0910d-fb39-443b-935b-13359d43a074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
00318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2032600318
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.245997030
Short name T1152
Test name
Test status
Simulation time 8390080313 ps
CPU time 9.42 seconds
Started Apr 28 02:10:54 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 204164 kb
Host smart-70f8cad0-7115-4f51-9e92-b4245902a38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24599
7030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.245997030
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3258972267
Short name T824
Test name
Test status
Simulation time 8387543551 ps
CPU time 7.87 seconds
Started Apr 28 02:10:54 PM PDT 24
Finished Apr 28 02:11:03 PM PDT 24
Peak memory 204092 kb
Host smart-714cf0d1-8004-449d-b5fa-f1e33c214262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
72267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3258972267
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1157463635
Short name T46
Test name
Test status
Simulation time 8462240670 ps
CPU time 8.05 seconds
Started Apr 28 02:11:06 PM PDT 24
Finished Apr 28 02:11:15 PM PDT 24
Peak memory 203992 kb
Host smart-b802b714-a333-4dbb-b525-f1c11eb64cf0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1157463635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1157463635
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3282143334
Short name T740
Test name
Test status
Simulation time 8398744248 ps
CPU time 8.84 seconds
Started Apr 28 02:11:08 PM PDT 24
Finished Apr 28 02:11:18 PM PDT 24
Peak memory 204120 kb
Host smart-c3a85e14-c21c-4eed-a10f-cde95e7156a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3282143334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3282143334
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.2767161186
Short name T319
Test name
Test status
Simulation time 8419618979 ps
CPU time 7.7 seconds
Started Apr 28 02:11:06 PM PDT 24
Finished Apr 28 02:11:15 PM PDT 24
Peak memory 204028 kb
Host smart-efccbe95-ec2a-4770-b51a-27fe9041d35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27671
61186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.2767161186
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2682534519
Short name T1244
Test name
Test status
Simulation time 8378567288 ps
CPU time 10.51 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:13 PM PDT 24
Peak memory 204060 kb
Host smart-f2085eeb-fe79-410e-bc5b-3cc9e036644d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
34519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2682534519
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.70351696
Short name T705
Test name
Test status
Simulation time 8443835315 ps
CPU time 8.77 seconds
Started Apr 28 02:11:00 PM PDT 24
Finished Apr 28 02:11:10 PM PDT 24
Peak memory 204060 kb
Host smart-9dc820aa-f159-4a4f-9ebe-85442fc6ddc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70351
696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.70351696
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1512686832
Short name T1145
Test name
Test status
Simulation time 140639314 ps
CPU time 1.64 seconds
Started Apr 28 02:11:00 PM PDT 24
Finished Apr 28 02:11:02 PM PDT 24
Peak memory 204236 kb
Host smart-28503954-b2b3-4acd-a35c-04133dc89c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15126
86832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1512686832
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1244125120
Short name T1333
Test name
Test status
Simulation time 8394335927 ps
CPU time 7.59 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:14 PM PDT 24
Peak memory 204100 kb
Host smart-9c44d1e3-4bc0-4ec0-818c-c1883f3529ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
25120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1244125120
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1032010953
Short name T1075
Test name
Test status
Simulation time 8425377277 ps
CPU time 7.96 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:10 PM PDT 24
Peak memory 204140 kb
Host smart-a414a29c-82f9-4d1b-8226-49d4081208b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
10953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1032010953
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3804340346
Short name T310
Test name
Test status
Simulation time 8366990255 ps
CPU time 7.53 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:10 PM PDT 24
Peak memory 204156 kb
Host smart-78f3e5ea-3618-4285-9201-d5bedf91bbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38043
40346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3804340346
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3276733972
Short name T907
Test name
Test status
Simulation time 8411201370 ps
CPU time 8.94 seconds
Started Apr 28 02:11:00 PM PDT 24
Finished Apr 28 02:11:09 PM PDT 24
Peak memory 204052 kb
Host smart-6939005d-e9ed-4e27-b899-d5ee9cf98886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32767
33972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3276733972
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3861624591
Short name T661
Test name
Test status
Simulation time 8387741802 ps
CPU time 8.16 seconds
Started Apr 28 02:11:00 PM PDT 24
Finished Apr 28 02:11:09 PM PDT 24
Peak memory 204084 kb
Host smart-3daca8ea-8f30-4144-9424-4e3539f8d6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38616
24591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3861624591
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.91095811
Short name T572
Test name
Test status
Simulation time 8371815754 ps
CPU time 8.09 seconds
Started Apr 28 02:11:06 PM PDT 24
Finished Apr 28 02:11:15 PM PDT 24
Peak memory 203968 kb
Host smart-afea067e-d413-4491-9657-224c96e4df42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91095
811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.91095811
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.211810154
Short name T695
Test name
Test status
Simulation time 21526615125 ps
CPU time 44.87 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:47 PM PDT 24
Peak memory 204404 kb
Host smart-26eff71d-4f6f-4522-90c5-550f58820d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21181
0154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.211810154
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.662038033
Short name T996
Test name
Test status
Simulation time 8402567508 ps
CPU time 7.85 seconds
Started Apr 28 02:11:02 PM PDT 24
Finished Apr 28 02:11:11 PM PDT 24
Peak memory 204160 kb
Host smart-1eaa644b-973e-46b2-b715-5a706f962497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66203
8033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.662038033
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.254626345
Short name T1203
Test name
Test status
Simulation time 8387384921 ps
CPU time 7.56 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:13 PM PDT 24
Peak memory 204120 kb
Host smart-c04359e0-0416-4e72-86ac-c636d55e5ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25462
6345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.254626345
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4255913319
Short name T59
Test name
Test status
Simulation time 170212351 ps
CPU time 1.01 seconds
Started Apr 28 02:11:08 PM PDT 24
Finished Apr 28 02:11:09 PM PDT 24
Peak memory 220440 kb
Host smart-5fe2b522-9b6d-4131-bf2b-6930c816f14a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4255913319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4255913319
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.531892623
Short name T528
Test name
Test status
Simulation time 8436284554 ps
CPU time 7.61 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:14 PM PDT 24
Peak memory 204140 kb
Host smart-d3bcc7d4-e0b1-4f1e-bf07-82fe146fb162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53189
2623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.531892623
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1289969836
Short name T350
Test name
Test status
Simulation time 8435283795 ps
CPU time 7.94 seconds
Started Apr 28 02:11:01 PM PDT 24
Finished Apr 28 02:11:09 PM PDT 24
Peak memory 204080 kb
Host smart-2fe745d1-f47b-47e8-a3f4-9aa7de04f38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899
69836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1289969836
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4056659683
Short name T999
Test name
Test status
Simulation time 8389234916 ps
CPU time 8.54 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:14 PM PDT 24
Peak memory 204084 kb
Host smart-8f26c45a-c384-4be4-83d1-44760983e74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40566
59683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4056659683
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1039718819
Short name T777
Test name
Test status
Simulation time 8408694155 ps
CPU time 8.06 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:14 PM PDT 24
Peak memory 204124 kb
Host smart-bb6f3da5-b6fd-401e-8a55-ece21d55342d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10397
18819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1039718819
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.959043030
Short name T337
Test name
Test status
Simulation time 8477825272 ps
CPU time 8.89 seconds
Started Apr 28 02:12:12 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204084 kb
Host smart-358ef0d9-ecd4-4175-9518-52a2ac95092b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=959043030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.959043030
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2758373249
Short name T622
Test name
Test status
Simulation time 8381371596 ps
CPU time 10.24 seconds
Started Apr 28 02:12:15 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204008 kb
Host smart-fb8a9e85-d7fb-4f0b-baef-6faaa582be45
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2758373249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2758373249
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2804773552
Short name T927
Test name
Test status
Simulation time 8445890924 ps
CPU time 7.69 seconds
Started Apr 28 02:12:11 PM PDT 24
Finished Apr 28 02:12:19 PM PDT 24
Peak memory 204108 kb
Host smart-26b95fec-6831-4bd2-b23a-b2f2500a2d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28047
73552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2804773552
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.427536593
Short name T947
Test name
Test status
Simulation time 8386498979 ps
CPU time 7.77 seconds
Started Apr 28 02:12:08 PM PDT 24
Finished Apr 28 02:12:16 PM PDT 24
Peak memory 204120 kb
Host smart-562ce046-7302-49de-a775-fb0e4614272f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42753
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.427536593
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.1489704132
Short name T466
Test name
Test status
Simulation time 8377812751 ps
CPU time 7.56 seconds
Started Apr 28 02:12:06 PM PDT 24
Finished Apr 28 02:12:13 PM PDT 24
Peak memory 204108 kb
Host smart-afccba66-ac9c-4f2e-b677-591a2e17136f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14897
04132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1489704132
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3060570739
Short name T686
Test name
Test status
Simulation time 188537681 ps
CPU time 1.6 seconds
Started Apr 28 02:12:08 PM PDT 24
Finished Apr 28 02:12:10 PM PDT 24
Peak memory 204224 kb
Host smart-fb765b83-c942-4954-8dc2-230a0951b6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30605
70739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3060570739
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1992168135
Short name T737
Test name
Test status
Simulation time 8403855165 ps
CPU time 7.3 seconds
Started Apr 28 02:12:11 PM PDT 24
Finished Apr 28 02:12:19 PM PDT 24
Peak memory 204080 kb
Host smart-ce760f39-5c5a-4892-8307-074d95e7761f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19921
68135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1992168135
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2963525296
Short name T1195
Test name
Test status
Simulation time 8381853735 ps
CPU time 8.14 seconds
Started Apr 28 02:12:12 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204120 kb
Host smart-620fb7d9-28c6-48da-bcdf-2ac6c8f505e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29635
25296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2963525296
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3583304494
Short name T1318
Test name
Test status
Simulation time 8406187624 ps
CPU time 9.34 seconds
Started Apr 28 02:12:07 PM PDT 24
Finished Apr 28 02:12:16 PM PDT 24
Peak memory 204100 kb
Host smart-4ea01142-d54a-4f06-bcff-2a2b64240219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35833
04494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3583304494
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3847720393
Short name T326
Test name
Test status
Simulation time 8418415338 ps
CPU time 7.74 seconds
Started Apr 28 02:12:07 PM PDT 24
Finished Apr 28 02:12:15 PM PDT 24
Peak memory 204092 kb
Host smart-92f06021-2754-498a-9b3a-296d7fba9283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38477
20393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3847720393
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.531641837
Short name T1210
Test name
Test status
Simulation time 8366359036 ps
CPU time 7.86 seconds
Started Apr 28 02:12:05 PM PDT 24
Finished Apr 28 02:12:13 PM PDT 24
Peak memory 204152 kb
Host smart-bfd2dbe8-f83a-4721-b310-8963fa507b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53164
1837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.531641837
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.268907664
Short name T353
Test name
Test status
Simulation time 8390146848 ps
CPU time 9.39 seconds
Started Apr 28 02:12:14 PM PDT 24
Finished Apr 28 02:12:23 PM PDT 24
Peak memory 204056 kb
Host smart-c8d2e4d6-6582-4e7a-925b-77424b75221a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26890
7664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.268907664
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2942777477
Short name T31
Test name
Test status
Simulation time 8397625217 ps
CPU time 7.76 seconds
Started Apr 28 02:12:08 PM PDT 24
Finished Apr 28 02:12:16 PM PDT 24
Peak memory 204128 kb
Host smart-49c63fcb-beae-405e-b788-2e4de17f8d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
77477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2942777477
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2149346749
Short name T1047
Test name
Test status
Simulation time 8375776212 ps
CPU time 9.37 seconds
Started Apr 28 02:12:11 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204052 kb
Host smart-8cf03c5b-6484-4e58-975f-1299c8f313fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
46749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2149346749
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.173343992
Short name T1048
Test name
Test status
Simulation time 8373549205 ps
CPU time 10.06 seconds
Started Apr 28 02:12:10 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204148 kb
Host smart-6baa519f-b363-44ba-8b8d-4873469aa429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17334
3992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.173343992
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3134668183
Short name T385
Test name
Test status
Simulation time 45430344 ps
CPU time 0.66 seconds
Started Apr 28 02:12:13 PM PDT 24
Finished Apr 28 02:12:14 PM PDT 24
Peak memory 203956 kb
Host smart-d9a897d5-310e-4db8-aa0a-43663dd30a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31346
68183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3134668183
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3872914640
Short name T1108
Test name
Test status
Simulation time 17190990125 ps
CPU time 33.37 seconds
Started Apr 28 02:12:09 PM PDT 24
Finished Apr 28 02:12:42 PM PDT 24
Peak memory 204404 kb
Host smart-496ba911-5d7a-4ce3-b90e-f6a0929ced79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38729
14640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3872914640
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.293252243
Short name T427
Test name
Test status
Simulation time 8411209770 ps
CPU time 7.85 seconds
Started Apr 28 02:12:08 PM PDT 24
Finished Apr 28 02:12:16 PM PDT 24
Peak memory 204096 kb
Host smart-833a93f4-cebb-409f-babf-a644ddfb730d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29325
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.293252243
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2229223012
Short name T1378
Test name
Test status
Simulation time 8445889272 ps
CPU time 8.08 seconds
Started Apr 28 02:12:06 PM PDT 24
Finished Apr 28 02:12:14 PM PDT 24
Peak memory 204052 kb
Host smart-1e3a6ce2-33cb-42e7-a4e7-24b1c64c5d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
23012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2229223012
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1061992359
Short name T1212
Test name
Test status
Simulation time 8386567241 ps
CPU time 8.56 seconds
Started Apr 28 02:12:06 PM PDT 24
Finished Apr 28 02:12:15 PM PDT 24
Peak memory 204032 kb
Host smart-dee45632-eaef-401b-b029-b7e502cdcc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10619
92359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1061992359
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2032638263
Short name T844
Test name
Test status
Simulation time 8409489606 ps
CPU time 7.84 seconds
Started Apr 28 02:12:10 PM PDT 24
Finished Apr 28 02:12:19 PM PDT 24
Peak memory 204124 kb
Host smart-c7a0fb96-df86-4af4-86f2-c327e99883dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
38263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2032638263
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.312206614
Short name T803
Test name
Test status
Simulation time 8372548527 ps
CPU time 8.75 seconds
Started Apr 28 02:12:11 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204120 kb
Host smart-8f5fd377-7b80-4815-af8e-36f04c0e702e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31220
6614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.312206614
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3483092376
Short name T300
Test name
Test status
Simulation time 8453749388 ps
CPU time 8.52 seconds
Started Apr 28 02:12:12 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204112 kb
Host smart-6c9ad927-9f67-4cd2-9026-4f8393b6678a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34830
92376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3483092376
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.2949009709
Short name T882
Test name
Test status
Simulation time 8474818854 ps
CPU time 8.65 seconds
Started Apr 28 02:12:20 PM PDT 24
Finished Apr 28 02:12:29 PM PDT 24
Peak memory 204036 kb
Host smart-a9c7df11-deaa-44c8-900d-8fb3225aaef5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2949009709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.2949009709
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.2203922933
Short name T546
Test name
Test status
Simulation time 8380272508 ps
CPU time 7.58 seconds
Started Apr 28 02:12:20 PM PDT 24
Finished Apr 28 02:12:28 PM PDT 24
Peak memory 204120 kb
Host smart-0b6fff76-0e4a-45e0-9e38-c8e2a0f93b8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2203922933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.2203922933
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.80896800
Short name T873
Test name
Test status
Simulation time 8441120995 ps
CPU time 8.51 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:36 PM PDT 24
Peak memory 204028 kb
Host smart-212275c3-ab54-476c-a7e1-e3042ed6758e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80896
800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.80896800
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3500465510
Short name T1008
Test name
Test status
Simulation time 8388583593 ps
CPU time 8.76 seconds
Started Apr 28 02:12:14 PM PDT 24
Finished Apr 28 02:12:23 PM PDT 24
Peak memory 204040 kb
Host smart-f1bcce6d-7787-41af-8910-e8d83c5b86d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004
65510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3500465510
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3510729459
Short name T694
Test name
Test status
Simulation time 8380039196 ps
CPU time 8.03 seconds
Started Apr 28 02:12:11 PM PDT 24
Finished Apr 28 02:12:20 PM PDT 24
Peak memory 204104 kb
Host smart-0b3020f6-9134-4211-ab02-973e9fb75d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35107
29459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3510729459
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3158572115
Short name T486
Test name
Test status
Simulation time 75852404 ps
CPU time 2 seconds
Started Apr 28 02:12:18 PM PDT 24
Finished Apr 28 02:12:20 PM PDT 24
Peak memory 204144 kb
Host smart-6bfc909b-7318-46d2-ba82-82e2b67fe095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
72115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3158572115
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1043171370
Short name T50
Test name
Test status
Simulation time 8388311108 ps
CPU time 7.84 seconds
Started Apr 28 02:12:23 PM PDT 24
Finished Apr 28 02:12:31 PM PDT 24
Peak memory 204120 kb
Host smart-db14d351-1f41-4d40-92f6-377ee9e794a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1043171370
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1009347831
Short name T218
Test name
Test status
Simulation time 8424904815 ps
CPU time 8.46 seconds
Started Apr 28 02:12:16 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204128 kb
Host smart-83c4983b-9ed2-43a0-b4c6-70c016842eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
47831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1009347831
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2096140710
Short name T1104
Test name
Test status
Simulation time 8407678473 ps
CPU time 7.32 seconds
Started Apr 28 02:12:16 PM PDT 24
Finished Apr 28 02:12:24 PM PDT 24
Peak memory 204140 kb
Host smart-f01b4b4c-9d78-4a96-ac57-d7ee27b13239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20961
40710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2096140710
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1892561688
Short name T545
Test name
Test status
Simulation time 8401633756 ps
CPU time 8.8 seconds
Started Apr 28 02:12:15 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204148 kb
Host smart-208ba7c7-2a0e-4bfc-b50c-1c3b7543fbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925
61688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1892561688
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2872483507
Short name T961
Test name
Test status
Simulation time 8377486418 ps
CPU time 8.47 seconds
Started Apr 28 02:12:17 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204100 kb
Host smart-b06f6a4d-b513-41ba-9ae5-f355261c1af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28724
83507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2872483507
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2267981806
Short name T523
Test name
Test status
Simulation time 8366598686 ps
CPU time 10.5 seconds
Started Apr 28 02:12:28 PM PDT 24
Finished Apr 28 02:12:39 PM PDT 24
Peak memory 204028 kb
Host smart-39f4746f-5fdb-4323-b0f6-3d20df90a011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22679
81806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2267981806
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1693853776
Short name T605
Test name
Test status
Simulation time 39652218 ps
CPU time 0.68 seconds
Started Apr 28 02:12:25 PM PDT 24
Finished Apr 28 02:12:27 PM PDT 24
Peak memory 204008 kb
Host smart-e67ecc82-2827-4322-b1cc-0b335b83a42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16938
53776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1693853776
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4193503959
Short name T563
Test name
Test status
Simulation time 15384699098 ps
CPU time 28.49 seconds
Started Apr 28 02:12:15 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 204320 kb
Host smart-428d3df6-43a7-49a1-9321-20aeabc45cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41935
03959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4193503959
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.356460160
Short name T1112
Test name
Test status
Simulation time 8429848387 ps
CPU time 7.79 seconds
Started Apr 28 02:12:16 PM PDT 24
Finished Apr 28 02:12:24 PM PDT 24
Peak memory 204108 kb
Host smart-17542321-933e-43e5-ad3a-3ca7b27ba0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35646
0160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.356460160
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3107308250
Short name T596
Test name
Test status
Simulation time 8393882843 ps
CPU time 8.51 seconds
Started Apr 28 02:12:16 PM PDT 24
Finished Apr 28 02:12:25 PM PDT 24
Peak memory 204008 kb
Host smart-972a6a18-9cca-4363-9a17-33b83f00cef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31073
08250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3107308250
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.75808773
Short name T929
Test name
Test status
Simulation time 8385310293 ps
CPU time 7.45 seconds
Started Apr 28 02:12:20 PM PDT 24
Finished Apr 28 02:12:28 PM PDT 24
Peak memory 204132 kb
Host smart-2770a865-be74-444c-a3cf-f5cc3304e48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75808
773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.75808773
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3114577833
Short name T981
Test name
Test status
Simulation time 8375342002 ps
CPU time 9.11 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:37 PM PDT 24
Peak memory 204032 kb
Host smart-c61aee1c-3800-45c0-81a1-d1d9d2ed9b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31145
77833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3114577833
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1418116044
Short name T383
Test name
Test status
Simulation time 8375376277 ps
CPU time 7.62 seconds
Started Apr 28 02:12:23 PM PDT 24
Finished Apr 28 02:12:31 PM PDT 24
Peak memory 204068 kb
Host smart-df12d33f-7ba4-4fdd-945a-33ebe188d87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14181
16044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1418116044
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2879328241
Short name T951
Test name
Test status
Simulation time 8460815425 ps
CPU time 7.99 seconds
Started Apr 28 02:12:13 PM PDT 24
Finished Apr 28 02:12:21 PM PDT 24
Peak memory 204116 kb
Host smart-d7aa75d8-7795-4b5b-bb98-e20db9d94236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
28241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2879328241
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2533228997
Short name T670
Test name
Test status
Simulation time 8405531987 ps
CPU time 7.79 seconds
Started Apr 28 02:12:21 PM PDT 24
Finished Apr 28 02:12:29 PM PDT 24
Peak memory 204132 kb
Host smart-d297b3d2-c993-476e-95f5-02cf6e1ff737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25332
28997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2533228997
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2704041624
Short name T417
Test name
Test status
Simulation time 8387975574 ps
CPU time 9.67 seconds
Started Apr 28 02:12:21 PM PDT 24
Finished Apr 28 02:12:32 PM PDT 24
Peak memory 204092 kb
Host smart-656698c3-89d8-41ff-936b-8755063f2a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27040
41624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2704041624
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.9410921
Short name T502
Test name
Test status
Simulation time 8482293185 ps
CPU time 7.72 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:35 PM PDT 24
Peak memory 204104 kb
Host smart-276559b6-2bfe-40da-a249-f1b1978a0e98
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=9410921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.9410921
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.2474366110
Short name T910
Test name
Test status
Simulation time 8384547642 ps
CPU time 10.09 seconds
Started Apr 28 02:12:24 PM PDT 24
Finished Apr 28 02:12:34 PM PDT 24
Peak memory 204104 kb
Host smart-6f37992e-ce27-4cdb-b002-4ac2463649ef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2474366110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2474366110
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.817985974
Short name T1221
Test name
Test status
Simulation time 8482743572 ps
CPU time 8.1 seconds
Started Apr 28 02:12:28 PM PDT 24
Finished Apr 28 02:12:37 PM PDT 24
Peak memory 204028 kb
Host smart-3cbafea4-67d0-4593-89fb-1966d121f248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81798
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.817985974
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.554460873
Short name T600
Test name
Test status
Simulation time 8379213158 ps
CPU time 7.82 seconds
Started Apr 28 02:12:22 PM PDT 24
Finished Apr 28 02:12:31 PM PDT 24
Peak memory 204124 kb
Host smart-0587ab7b-0152-4a23-b40b-496c053b7be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55446
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.554460873
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.383729635
Short name T977
Test name
Test status
Simulation time 8404217345 ps
CPU time 8.83 seconds
Started Apr 28 02:12:24 PM PDT 24
Finished Apr 28 02:12:33 PM PDT 24
Peak memory 204032 kb
Host smart-eb71e196-46aa-41ae-9cbe-099f6b6b7eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38372
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.383729635
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.277565673
Short name T1240
Test name
Test status
Simulation time 142625306 ps
CPU time 1.6 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:28 PM PDT 24
Peak memory 204208 kb
Host smart-b5de1d8d-e029-4110-adb7-cf19bd58acd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27756
5673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.277565673
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2630032544
Short name T148
Test name
Test status
Simulation time 8439311692 ps
CPU time 7.44 seconds
Started Apr 28 02:12:28 PM PDT 24
Finished Apr 28 02:12:36 PM PDT 24
Peak memory 204112 kb
Host smart-4cd839c0-1184-4aaa-bcd3-c23ede049de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26300
32544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2630032544
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4193877814
Short name T802
Test name
Test status
Simulation time 8383389941 ps
CPU time 7.46 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:34 PM PDT 24
Peak memory 204120 kb
Host smart-9e5239a9-775e-4812-a104-b95c4411151e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
77814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4193877814
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3084515415
Short name T21
Test name
Test status
Simulation time 8440244216 ps
CPU time 7.9 seconds
Started Apr 28 02:12:24 PM PDT 24
Finished Apr 28 02:12:32 PM PDT 24
Peak memory 204036 kb
Host smart-39b023df-faaa-4db7-82f5-0f7f84c2db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30845
15415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3084515415
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.107489123
Short name T328
Test name
Test status
Simulation time 8440007233 ps
CPU time 8.62 seconds
Started Apr 28 02:12:21 PM PDT 24
Finished Apr 28 02:12:30 PM PDT 24
Peak memory 204136 kb
Host smart-8c5219aa-6beb-41f5-a9ef-ceda3b133034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10748
9123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.107489123
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2389874531
Short name T1200
Test name
Test status
Simulation time 8457505700 ps
CPU time 7.89 seconds
Started Apr 28 02:12:21 PM PDT 24
Finished Apr 28 02:12:29 PM PDT 24
Peak memory 204084 kb
Host smart-9bebcb59-5bb1-4a58-bee4-d996cef2291e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
74531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2389874531
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.33165636
Short name T915
Test name
Test status
Simulation time 8434187464 ps
CPU time 7.89 seconds
Started Apr 28 02:12:20 PM PDT 24
Finished Apr 28 02:12:28 PM PDT 24
Peak memory 203984 kb
Host smart-a1d7c07f-6255-4bf7-8a03-a8703fea08a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.33165636
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3633580963
Short name T950
Test name
Test status
Simulation time 8412247841 ps
CPU time 8.74 seconds
Started Apr 28 02:12:21 PM PDT 24
Finished Apr 28 02:12:30 PM PDT 24
Peak memory 204128 kb
Host smart-a3577e2a-c1f0-49d2-92ab-a09abdc8d481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36335
80963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3633580963
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.197725858
Short name T211
Test name
Test status
Simulation time 8382437632 ps
CPU time 8.26 seconds
Started Apr 28 02:12:23 PM PDT 24
Finished Apr 28 02:12:32 PM PDT 24
Peak memory 204116 kb
Host smart-fd54a6ea-b49d-4a36-a915-2ae7cc8475e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
5858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.197725858
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2871194697
Short name T583
Test name
Test status
Simulation time 8372741678 ps
CPU time 7.78 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:36 PM PDT 24
Peak memory 204132 kb
Host smart-df4056c2-4105-4315-981c-3304f9a354dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711
94697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2871194697
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3374715393
Short name T823
Test name
Test status
Simulation time 80991413 ps
CPU time 0.69 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:29 PM PDT 24
Peak memory 203904 kb
Host smart-5c9ff070-98b9-4b38-8af0-5b66ab6db6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33747
15393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3374715393
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.957204099
Short name T989
Test name
Test status
Simulation time 8416598638 ps
CPU time 7.69 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:34 PM PDT 24
Peak memory 204096 kb
Host smart-ddd942e3-657a-4b2b-b0cd-2f6c81c443cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95720
4099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.957204099
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3205647276
Short name T458
Test name
Test status
Simulation time 8405066074 ps
CPU time 8.3 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:34 PM PDT 24
Peak memory 204120 kb
Host smart-2e2deb91-d090-4a51-aa41-dcad47405096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32056
47276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3205647276
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1308288321
Short name T362
Test name
Test status
Simulation time 8397881686 ps
CPU time 7.58 seconds
Started Apr 28 02:12:25 PM PDT 24
Finished Apr 28 02:12:33 PM PDT 24
Peak memory 203996 kb
Host smart-4a4e1c73-135a-4502-8a83-edb82dbee0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13082
88321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1308288321
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2624717476
Short name T959
Test name
Test status
Simulation time 8372225856 ps
CPU time 7.32 seconds
Started Apr 28 02:12:27 PM PDT 24
Finished Apr 28 02:12:35 PM PDT 24
Peak memory 204112 kb
Host smart-922ac4c4-b3eb-4e7c-9b67-fbf74b7fc9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26247
17476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2624717476
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2439152190
Short name T1249
Test name
Test status
Simulation time 8370034961 ps
CPU time 8.32 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:35 PM PDT 24
Peak memory 204132 kb
Host smart-77a9a52f-6f6e-422c-9b0f-3a94abed7fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
52190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2439152190
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.562996254
Short name T77
Test name
Test status
Simulation time 8460291790 ps
CPU time 10.16 seconds
Started Apr 28 02:12:22 PM PDT 24
Finished Apr 28 02:12:32 PM PDT 24
Peak memory 204104 kb
Host smart-f1d0ed8b-98a2-45de-84a2-a6968e20f347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56299
6254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.562996254
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3461226952
Short name T1042
Test name
Test status
Simulation time 8407608896 ps
CPU time 9.75 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:36 PM PDT 24
Peak memory 204068 kb
Host smart-c831c2ee-28b1-4326-aed5-aead452428b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34612
26952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3461226952
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2528505465
Short name T403
Test name
Test status
Simulation time 8407789739 ps
CPU time 8.78 seconds
Started Apr 28 02:12:28 PM PDT 24
Finished Apr 28 02:12:37 PM PDT 24
Peak memory 204112 kb
Host smart-57112e49-91b1-4fc7-9c9a-d614b069b06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
05465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2528505465
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.3371229374
Short name T1157
Test name
Test status
Simulation time 8529973214 ps
CPU time 8.32 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 204128 kb
Host smart-cb9d4791-963b-4ef3-812e-fe45ee900188
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3371229374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.3371229374
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.2994412443
Short name T581
Test name
Test status
Simulation time 8380113541 ps
CPU time 8.68 seconds
Started Apr 28 02:12:37 PM PDT 24
Finished Apr 28 02:12:46 PM PDT 24
Peak memory 204120 kb
Host smart-9f9b1585-6663-43db-b994-c7b1b817a205
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2994412443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.2994412443
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2194332058
Short name T941
Test name
Test status
Simulation time 8452562433 ps
CPU time 8.45 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:44 PM PDT 24
Peak memory 204112 kb
Host smart-11e50792-b592-415e-a0d0-e7bfbde977d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943
32058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2194332058
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2275191996
Short name T1228
Test name
Test status
Simulation time 8411878126 ps
CPU time 8.49 seconds
Started Apr 28 02:12:24 PM PDT 24
Finished Apr 28 02:12:33 PM PDT 24
Peak memory 204116 kb
Host smart-95fc550d-acbe-47ac-b312-ea82cfa219b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751
91996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2275191996
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.3516182507
Short name T804
Test name
Test status
Simulation time 8379158298 ps
CPU time 7.65 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:34 PM PDT 24
Peak memory 204112 kb
Host smart-65aaddbb-07ee-4294-87e3-035861ef3101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
82507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3516182507
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1788144309
Short name T1170
Test name
Test status
Simulation time 209116371 ps
CPU time 2.24 seconds
Started Apr 28 02:12:26 PM PDT 24
Finished Apr 28 02:12:29 PM PDT 24
Peak memory 204236 kb
Host smart-d6f4e18e-9616-4a88-932f-008c7967d71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17881
44309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1788144309
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2586094141
Short name T880
Test name
Test status
Simulation time 8397755000 ps
CPU time 8.9 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:41 PM PDT 24
Peak memory 204104 kb
Host smart-0a8eeb10-2260-4fd1-b491-b2a36e3a47af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25860
94141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2586094141
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1529752397
Short name T1314
Test name
Test status
Simulation time 8422869402 ps
CPU time 8.43 seconds
Started Apr 28 02:12:30 PM PDT 24
Finished Apr 28 02:12:38 PM PDT 24
Peak memory 204124 kb
Host smart-40dcc2de-bf4a-426d-bf4e-bec59373107c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15297
52397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1529752397
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1199145393
Short name T1156
Test name
Test status
Simulation time 8404947070 ps
CPU time 7.51 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:39 PM PDT 24
Peak memory 204108 kb
Host smart-9eedc713-e9b3-4ad7-aa72-5e60112c010d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11991
45393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1199145393
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.701425334
Short name T905
Test name
Test status
Simulation time 8435335744 ps
CPU time 9.01 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:41 PM PDT 24
Peak memory 204032 kb
Host smart-79ddb90a-385f-4a82-9ca0-afc3c6633b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70142
5334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.701425334
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1310041186
Short name T821
Test name
Test status
Simulation time 8402501836 ps
CPU time 7.68 seconds
Started Apr 28 02:12:33 PM PDT 24
Finished Apr 28 02:12:41 PM PDT 24
Peak memory 204112 kb
Host smart-94a41234-67e4-466b-9eb4-2f5e461fcacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13100
41186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1310041186
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1359936752
Short name T497
Test name
Test status
Simulation time 8392578249 ps
CPU time 8.67 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:40 PM PDT 24
Peak memory 204148 kb
Host smart-5ac85320-3ffb-438e-923e-f34f78ceb5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13599
36752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1359936752
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3282303781
Short name T30
Test name
Test status
Simulation time 8376749877 ps
CPU time 7.31 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:39 PM PDT 24
Peak memory 204096 kb
Host smart-257042e8-49aa-4acf-a602-2044410f736c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32823
03781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3282303781
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2840185022
Short name T1322
Test name
Test status
Simulation time 8376486557 ps
CPU time 8.39 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:40 PM PDT 24
Peak memory 204092 kb
Host smart-14a1d36a-21c0-476b-a93e-d85ea1070bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
85022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2840185022
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.381577044
Short name T1010
Test name
Test status
Simulation time 8372160055 ps
CPU time 7.65 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:12:39 PM PDT 24
Peak memory 204000 kb
Host smart-9b293e13-a603-4f4c-bc17-c092d16d5341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157
7044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.381577044
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4222859568
Short name T766
Test name
Test status
Simulation time 52240305 ps
CPU time 0.68 seconds
Started Apr 28 02:12:32 PM PDT 24
Finished Apr 28 02:12:33 PM PDT 24
Peak memory 203904 kb
Host smart-c0844eda-4ef7-4c0b-a00f-1fd6a0b7c7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
59568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4222859568
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1506651358
Short name T1248
Test name
Test status
Simulation time 23797635793 ps
CPU time 42.9 seconds
Started Apr 28 02:12:31 PM PDT 24
Finished Apr 28 02:13:14 PM PDT 24
Peak memory 204448 kb
Host smart-3749a7ea-965d-4909-9752-449c8e46a800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
51358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1506651358
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1527629208
Short name T724
Test name
Test status
Simulation time 8408225150 ps
CPU time 7.32 seconds
Started Apr 28 02:12:29 PM PDT 24
Finished Apr 28 02:12:37 PM PDT 24
Peak memory 204108 kb
Host smart-376a42cc-7a66-43f7-9212-dce0ff2307f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
29208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1527629208
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3064827032
Short name T1372
Test name
Test status
Simulation time 8446149795 ps
CPU time 7.99 seconds
Started Apr 28 02:12:29 PM PDT 24
Finished Apr 28 02:12:38 PM PDT 24
Peak memory 204164 kb
Host smart-f9b4bfab-a4aa-4a97-a02c-dfa7a839e758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
27032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3064827032
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.227535424
Short name T479
Test name
Test status
Simulation time 8409722553 ps
CPU time 7.48 seconds
Started Apr 28 02:12:32 PM PDT 24
Finished Apr 28 02:12:40 PM PDT 24
Peak memory 204116 kb
Host smart-54a506a9-ce7e-4ee0-b537-b95cc4c418ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22753
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.227535424
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3655354419
Short name T1153
Test name
Test status
Simulation time 8370678998 ps
CPU time 7.57 seconds
Started Apr 28 02:12:32 PM PDT 24
Finished Apr 28 02:12:40 PM PDT 24
Peak memory 204168 kb
Host smart-16b5bd0b-e865-4444-8f20-e36fdf93e8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36553
54419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3655354419
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4249028870
Short name T1172
Test name
Test status
Simulation time 8406587930 ps
CPU time 7.91 seconds
Started Apr 28 02:12:29 PM PDT 24
Finished Apr 28 02:12:38 PM PDT 24
Peak memory 204140 kb
Host smart-cc87460b-f464-4f1f-9758-9e76676ea51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42490
28870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4249028870
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1646547051
Short name T1263
Test name
Test status
Simulation time 8392661732 ps
CPU time 9.83 seconds
Started Apr 28 02:12:32 PM PDT 24
Finished Apr 28 02:12:42 PM PDT 24
Peak memory 204168 kb
Host smart-8da4d1f3-1557-4d4b-8be4-5dbdd71ffcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16465
47051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1646547051
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.305290113
Short name T1021
Test name
Test status
Simulation time 8412890358 ps
CPU time 8.09 seconds
Started Apr 28 02:12:30 PM PDT 24
Finished Apr 28 02:12:39 PM PDT 24
Peak memory 204080 kb
Host smart-55cbd24a-32d9-424c-9336-ff97f469e985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30529
0113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.305290113
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.3417341995
Short name T430
Test name
Test status
Simulation time 8468935489 ps
CPU time 9.81 seconds
Started Apr 28 02:12:41 PM PDT 24
Finished Apr 28 02:12:51 PM PDT 24
Peak memory 204128 kb
Host smart-fc1fffec-9bd6-4106-9225-4ac92342f659
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3417341995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.3417341995
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.4181529391
Short name T445
Test name
Test status
Simulation time 8396758043 ps
CPU time 9.79 seconds
Started Apr 28 02:12:39 PM PDT 24
Finished Apr 28 02:12:50 PM PDT 24
Peak memory 204136 kb
Host smart-241c07eb-f507-473c-9e3d-130ee8b55fe6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4181529391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.4181529391
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2027403232
Short name T713
Test name
Test status
Simulation time 8463023220 ps
CPU time 7.74 seconds
Started Apr 28 02:12:42 PM PDT 24
Finished Apr 28 02:12:50 PM PDT 24
Peak memory 204092 kb
Host smart-a9dcfc79-859d-4a8a-b6a8-a7e86d8d8a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
03232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2027403232
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.719224384
Short name T1349
Test name
Test status
Simulation time 8409269424 ps
CPU time 7.91 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 204128 kb
Host smart-d14171e7-b985-4331-a77e-790911074fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71922
4384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.719224384
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.1232913237
Short name T1235
Test name
Test status
Simulation time 8372475897 ps
CPU time 10.06 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:12:47 PM PDT 24
Peak memory 204076 kb
Host smart-ed6c001b-1429-4d1b-a841-f6c3ee1d31df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12329
13237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1232913237
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2453839270
Short name T507
Test name
Test status
Simulation time 208565666 ps
CPU time 1.87 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:12:39 PM PDT 24
Peak memory 204288 kb
Host smart-6c0fbb9b-20cf-4203-86da-54d5f8795646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24538
39270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2453839270
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.68135007
Short name T722
Test name
Test status
Simulation time 8453785747 ps
CPU time 7.97 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204080 kb
Host smart-f4dabd55-d552-4da9-af78-d00e8040591f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68135
007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.68135007
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1605854620
Short name T484
Test name
Test status
Simulation time 8372924129 ps
CPU time 7.96 seconds
Started Apr 28 02:12:39 PM PDT 24
Finished Apr 28 02:12:47 PM PDT 24
Peak memory 203968 kb
Host smart-143ac34e-90e7-4515-9084-1d53253d6762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16058
54620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1605854620
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2589527990
Short name T157
Test name
Test status
Simulation time 8430020723 ps
CPU time 8.47 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 204056 kb
Host smart-39e939d1-a7e2-4cf5-8142-7cc8b6c620f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25895
27990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2589527990
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3420568770
Short name T1086
Test name
Test status
Simulation time 8417935796 ps
CPU time 7.85 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:44 PM PDT 24
Peak memory 203996 kb
Host smart-e53616ce-c18e-47aa-860e-3080a06bf8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34205
68770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3420568770
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3245847278
Short name T810
Test name
Test status
Simulation time 8402388857 ps
CPU time 7.93 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:44 PM PDT 24
Peak memory 204160 kb
Host smart-0a63629d-1ede-40fd-897e-d593185a7c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32458
47278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3245847278
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1458535863
Short name T1142
Test name
Test status
Simulation time 8433782857 ps
CPU time 8.81 seconds
Started Apr 28 02:12:34 PM PDT 24
Finished Apr 28 02:12:44 PM PDT 24
Peak memory 204160 kb
Host smart-ff07be18-2b4b-453b-a536-70d803b1b1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14585
35863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1458535863
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1486078245
Short name T1071
Test name
Test status
Simulation time 8417846562 ps
CPU time 9.28 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:50 PM PDT 24
Peak memory 204084 kb
Host smart-088b25d1-4bd0-412c-bc61-0dd8a4b5a49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14860
78245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1486078245
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1462316921
Short name T536
Test name
Test status
Simulation time 8419752535 ps
CPU time 8.03 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 204176 kb
Host smart-24f5af9a-aa79-436b-9c36-2b787af31e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
16921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1462316921
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2977154034
Short name T490
Test name
Test status
Simulation time 8404487613 ps
CPU time 8.78 seconds
Started Apr 28 02:12:42 PM PDT 24
Finished Apr 28 02:12:52 PM PDT 24
Peak memory 204116 kb
Host smart-df2327b7-3757-410d-91c0-a511ee92ef25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29771
54034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2977154034
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4190850106
Short name T10
Test name
Test status
Simulation time 8378158817 ps
CPU time 8.18 seconds
Started Apr 28 02:12:43 PM PDT 24
Finished Apr 28 02:12:52 PM PDT 24
Peak memory 204112 kb
Host smart-591a4554-aedf-4120-b2dc-7090503c5b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41908
50106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4190850106
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1995535004
Short name T628
Test name
Test status
Simulation time 37500307 ps
CPU time 0.66 seconds
Started Apr 28 02:12:42 PM PDT 24
Finished Apr 28 02:12:43 PM PDT 24
Peak memory 204032 kb
Host smart-4a4dfdd8-b229-4178-9bb6-77d09d36d7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955
35004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1995535004
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3832559478
Short name T555
Test name
Test status
Simulation time 25637286101 ps
CPU time 52.84 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204420 kb
Host smart-44e9d0ce-1f64-470c-b602-7efc72eb98a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38325
59478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3832559478
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4161499520
Short name T768
Test name
Test status
Simulation time 8463424677 ps
CPU time 8.91 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:12:46 PM PDT 24
Peak memory 204112 kb
Host smart-ccb37b81-80c0-43a0-b65b-cf84a18ec8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41614
99520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4161499520
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1101544650
Short name T806
Test name
Test status
Simulation time 8398239200 ps
CPU time 8 seconds
Started Apr 28 02:12:35 PM PDT 24
Finished Apr 28 02:12:44 PM PDT 24
Peak memory 204112 kb
Host smart-bc724c87-4372-4b78-a81a-4ffa3985a804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11015
44650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1101544650
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2954911377
Short name T441
Test name
Test status
Simulation time 8378202778 ps
CPU time 8.18 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204140 kb
Host smart-444de7b1-e995-4e1d-9594-8958dbc8dc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
11377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2954911377
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3548376558
Short name T626
Test name
Test status
Simulation time 8369144774 ps
CPU time 7.84 seconds
Started Apr 28 02:12:41 PM PDT 24
Finished Apr 28 02:12:50 PM PDT 24
Peak memory 204104 kb
Host smart-6e20021c-9e64-4c15-8f5f-99c6aff9f1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35483
76558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3548376558
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3634581193
Short name T1127
Test name
Test status
Simulation time 8444682751 ps
CPU time 10.16 seconds
Started Apr 28 02:12:36 PM PDT 24
Finished Apr 28 02:12:47 PM PDT 24
Peak memory 204120 kb
Host smart-5c32796f-a11a-47aa-a600-d5130901ba37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36345
81193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3634581193
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2520654100
Short name T488
Test name
Test status
Simulation time 8388010922 ps
CPU time 10.2 seconds
Started Apr 28 02:12:41 PM PDT 24
Finished Apr 28 02:12:51 PM PDT 24
Peak memory 204084 kb
Host smart-50283c7e-9c64-4358-af83-421c31e66ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25206
54100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2520654100
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3326885530
Short name T750
Test name
Test status
Simulation time 8430964091 ps
CPU time 9.28 seconds
Started Apr 28 02:12:38 PM PDT 24
Finished Apr 28 02:12:47 PM PDT 24
Peak memory 204116 kb
Host smart-9cfe7848-37ad-4d0d-bc22-cfba66d3560a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
85530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3326885530
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.3812831897
Short name T995
Test name
Test status
Simulation time 8477799068 ps
CPU time 8.39 seconds
Started Apr 28 02:12:46 PM PDT 24
Finished Apr 28 02:12:55 PM PDT 24
Peak memory 204064 kb
Host smart-2abaa508-d2b0-4aab-a26e-bcf757c11e63
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3812831897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.3812831897
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.517040397
Short name T963
Test name
Test status
Simulation time 8379525549 ps
CPU time 7.54 seconds
Started Apr 28 02:12:44 PM PDT 24
Finished Apr 28 02:12:53 PM PDT 24
Peak memory 204128 kb
Host smart-746e3c65-7772-459c-bf3b-38e1dc50bd15
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=517040397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.517040397
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.517588471
Short name T459
Test name
Test status
Simulation time 8415279312 ps
CPU time 7.8 seconds
Started Apr 28 02:12:48 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204072 kb
Host smart-57ae1ec8-0748-4ae7-a717-4af1e077e5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51758
8471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.517588471
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2384966050
Short name T754
Test name
Test status
Simulation time 8386813688 ps
CPU time 9.63 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204084 kb
Host smart-830ccd99-c253-4a11-9ae9-b3796d722d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
66050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2384966050
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.3898234904
Short name T1312
Test name
Test status
Simulation time 8399082130 ps
CPU time 8.12 seconds
Started Apr 28 02:13:00 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 204060 kb
Host smart-55b78012-b39e-4f33-9794-3e721ce283b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38982
34904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3898234904
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.410702005
Short name T637
Test name
Test status
Simulation time 121356498 ps
CPU time 1.5 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204208 kb
Host smart-23438770-90e5-4baf-9129-2d88e5833adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
2005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.410702005
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3211616872
Short name T1361
Test name
Test status
Simulation time 8425240858 ps
CPU time 8.82 seconds
Started Apr 28 02:12:43 PM PDT 24
Finished Apr 28 02:12:53 PM PDT 24
Peak memory 204072 kb
Host smart-473d0338-8ac9-4f3a-8f97-3bdf4f8799ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
16872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3211616872
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4131403519
Short name T1148
Test name
Test status
Simulation time 8506695928 ps
CPU time 8.13 seconds
Started Apr 28 02:12:39 PM PDT 24
Finished Apr 28 02:12:48 PM PDT 24
Peak memory 204080 kb
Host smart-6198209b-d4a3-43a4-887c-c97552fc319f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
03519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4131403519
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.99208461
Short name T597
Test name
Test status
Simulation time 8444119603 ps
CPU time 7.47 seconds
Started Apr 28 02:12:41 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204148 kb
Host smart-4e764ca8-dd86-429e-94c2-8e579836be8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99208
461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.99208461
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2237123320
Short name T1093
Test name
Test status
Simulation time 8371521437 ps
CPU time 7.87 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204128 kb
Host smart-2afd9aa4-f56e-47d7-ba0e-1666bbf93caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
23320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2237123320
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2653779009
Short name T130
Test name
Test status
Simulation time 8445967450 ps
CPU time 7.8 seconds
Started Apr 28 02:12:43 PM PDT 24
Finished Apr 28 02:12:51 PM PDT 24
Peak memory 204128 kb
Host smart-f6b53c41-b3e8-4076-980a-c8fdfe157125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26537
79009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2653779009
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1618246738
Short name T1316
Test name
Test status
Simulation time 8393904032 ps
CPU time 7.37 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:48 PM PDT 24
Peak memory 204152 kb
Host smart-68d96bf4-b124-4c12-9083-74a55bb03b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16182
46738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1618246738
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2249840010
Short name T681
Test name
Test status
Simulation time 8423962007 ps
CPU time 7.7 seconds
Started Apr 28 02:12:43 PM PDT 24
Finished Apr 28 02:12:51 PM PDT 24
Peak memory 204112 kb
Host smart-9afb323f-3e11-4003-94fd-74a684d74526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22498
40010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2249840010
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2590269567
Short name T158
Test name
Test status
Simulation time 8369036180 ps
CPU time 7.71 seconds
Started Apr 28 02:12:46 PM PDT 24
Finished Apr 28 02:12:54 PM PDT 24
Peak memory 204108 kb
Host smart-3c06a697-44d8-4abd-b883-4bc20c4f3051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25902
69567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2590269567
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.844915311
Short name T691
Test name
Test status
Simulation time 8444035997 ps
CPU time 7.9 seconds
Started Apr 28 02:12:45 PM PDT 24
Finished Apr 28 02:12:54 PM PDT 24
Peak memory 204120 kb
Host smart-fe3821f0-98e4-4753-bba8-550626b969fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84491
5311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.844915311
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.561486066
Short name T548
Test name
Test status
Simulation time 65334505 ps
CPU time 0.66 seconds
Started Apr 28 02:12:44 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 203968 kb
Host smart-4598f737-2fdf-438a-ba11-c58f918d4c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56148
6066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.561486066
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2538047070
Short name T222
Test name
Test status
Simulation time 30370327043 ps
CPU time 58.48 seconds
Started Apr 28 02:12:42 PM PDT 24
Finished Apr 28 02:13:41 PM PDT 24
Peak memory 204412 kb
Host smart-8a1c068e-757b-4d59-970a-5466af92c0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
47070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2538047070
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2681658189
Short name T409
Test name
Test status
Simulation time 8375433914 ps
CPU time 7.66 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:48 PM PDT 24
Peak memory 204096 kb
Host smart-29679720-ff8b-4809-b25f-5fb87c0e04eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26816
58189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2681658189
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3260094035
Short name T515
Test name
Test status
Simulation time 8442187615 ps
CPU time 8.43 seconds
Started Apr 28 02:12:44 PM PDT 24
Finished Apr 28 02:12:53 PM PDT 24
Peak memory 204056 kb
Host smart-fcc7503b-86d3-459f-9cb1-390c99047e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32600
94035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3260094035
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1577458356
Short name T991
Test name
Test status
Simulation time 8404828021 ps
CPU time 7.54 seconds
Started Apr 28 02:12:45 PM PDT 24
Finished Apr 28 02:12:53 PM PDT 24
Peak memory 204132 kb
Host smart-ba97d2cc-7a00-43bb-9655-b29f7d8b1b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
58356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1577458356
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2464577199
Short name T1345
Test name
Test status
Simulation time 8397033181 ps
CPU time 7.56 seconds
Started Apr 28 02:12:45 PM PDT 24
Finished Apr 28 02:12:53 PM PDT 24
Peak memory 204084 kb
Host smart-780abb44-809a-48eb-af4d-635391be525c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24645
77199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2464577199
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1935615536
Short name T964
Test name
Test status
Simulation time 8366982996 ps
CPU time 7.68 seconds
Started Apr 28 02:12:46 PM PDT 24
Finished Apr 28 02:12:54 PM PDT 24
Peak memory 204060 kb
Host smart-98d244b8-2082-4b26-98fc-0b3c36b77ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19356
15536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1935615536
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3262541606
Short name T870
Test name
Test status
Simulation time 8474160963 ps
CPU time 8.55 seconds
Started Apr 28 02:12:40 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204084 kb
Host smart-f57ea441-6035-467a-a6d8-9405aa873f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625
41606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3262541606
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1983973263
Short name T898
Test name
Test status
Simulation time 8406656328 ps
CPU time 7.98 seconds
Started Apr 28 02:12:49 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204076 kb
Host smart-a4f0d8f0-68f2-46f4-b1f1-ce93de76d51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
73263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1983973263
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.491863510
Short name T338
Test name
Test status
Simulation time 8396107159 ps
CPU time 9.5 seconds
Started Apr 28 02:12:48 PM PDT 24
Finished Apr 28 02:12:58 PM PDT 24
Peak memory 204084 kb
Host smart-e312a654-da3e-4cf2-ae7f-fde854042d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49186
3510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.491863510
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.2403216877
Short name T805
Test name
Test status
Simulation time 8466497904 ps
CPU time 7.66 seconds
Started Apr 28 02:12:55 PM PDT 24
Finished Apr 28 02:13:03 PM PDT 24
Peak memory 204120 kb
Host smart-46f56579-596e-472c-b026-8ecf3ff4cc0d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2403216877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.2403216877
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.965718225
Short name T793
Test name
Test status
Simulation time 8379881102 ps
CPU time 7.83 seconds
Started Apr 28 02:12:56 PM PDT 24
Finished Apr 28 02:13:04 PM PDT 24
Peak memory 204120 kb
Host smart-811f58de-9cdf-467e-bc3d-e05deff044b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=965718225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.965718225
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.3706943013
Short name T786
Test name
Test status
Simulation time 8411414668 ps
CPU time 9.15 seconds
Started Apr 28 02:12:53 PM PDT 24
Finished Apr 28 02:13:03 PM PDT 24
Peak memory 204112 kb
Host smart-d9686dea-43a9-49bf-8264-c53b1c74be4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
43013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.3706943013
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.490592904
Short name T640
Test name
Test status
Simulation time 8369361728 ps
CPU time 7.53 seconds
Started Apr 28 02:12:48 PM PDT 24
Finished Apr 28 02:12:55 PM PDT 24
Peak memory 204040 kb
Host smart-50b59924-fbde-4516-834e-34d052f4b630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49059
2904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.490592904
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.3951244119
Short name T975
Test name
Test status
Simulation time 8397031570 ps
CPU time 8.4 seconds
Started Apr 28 02:12:43 PM PDT 24
Finished Apr 28 02:12:52 PM PDT 24
Peak memory 204112 kb
Host smart-d87e5e47-6323-4df6-b5e4-bd0add1b667e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39512
44119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3951244119
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.264996297
Short name T496
Test name
Test status
Simulation time 101020207 ps
CPU time 1.13 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:49 PM PDT 24
Peak memory 204208 kb
Host smart-64053070-2541-44ff-9d5a-71917bd56e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26499
6297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.264996297
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3940042155
Short name T639
Test name
Test status
Simulation time 8411181246 ps
CPU time 8.36 seconds
Started Apr 28 02:12:56 PM PDT 24
Finished Apr 28 02:13:05 PM PDT 24
Peak memory 204096 kb
Host smart-920aa9e3-f44a-4a6a-8bab-8687eedf70c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
42155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3940042155
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3074403971
Short name T192
Test name
Test status
Simulation time 8366308852 ps
CPU time 7.99 seconds
Started Apr 28 02:12:53 PM PDT 24
Finished Apr 28 02:13:02 PM PDT 24
Peak memory 204040 kb
Host smart-2fc400d1-712c-478a-ae65-a37cf86937f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30744
03971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3074403971
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.677293318
Short name T744
Test name
Test status
Simulation time 8423408589 ps
CPU time 8.31 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:56 PM PDT 24
Peak memory 204136 kb
Host smart-d89304aa-81b1-475a-9d19-b48a02cbc30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67729
3318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.677293318
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1939613569
Short name T595
Test name
Test status
Simulation time 8376015970 ps
CPU time 8.62 seconds
Started Apr 28 02:12:48 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204028 kb
Host smart-9f562453-b350-4167-b52b-65e51035e6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
13569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1939613569
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2169615166
Short name T302
Test name
Test status
Simulation time 8406546328 ps
CPU time 8.95 seconds
Started Apr 28 02:12:49 PM PDT 24
Finished Apr 28 02:12:59 PM PDT 24
Peak memory 204052 kb
Host smart-9af6ca7e-17fb-4cac-aa81-ac4ab07e1da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21696
15166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2169615166
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2315781105
Short name T1233
Test name
Test status
Simulation time 8416946571 ps
CPU time 8.08 seconds
Started Apr 28 02:12:49 PM PDT 24
Finished Apr 28 02:12:58 PM PDT 24
Peak memory 204024 kb
Host smart-3b5325bb-0215-409e-84c7-bbce3fa04221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23157
81105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2315781105
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1131992146
Short name T717
Test name
Test status
Simulation time 8384766860 ps
CPU time 8.12 seconds
Started Apr 28 02:12:48 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204080 kb
Host smart-371aebd1-d317-4f00-96e8-4117e8a1953e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319
92146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1131992146
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3614915940
Short name T1118
Test name
Test status
Simulation time 32220711 ps
CPU time 0.67 seconds
Started Apr 28 02:12:55 PM PDT 24
Finished Apr 28 02:12:56 PM PDT 24
Peak memory 204028 kb
Host smart-974d5555-9904-4c30-9e6a-37365823f18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
15940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3614915940
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1306680758
Short name T858
Test name
Test status
Simulation time 17467983219 ps
CPU time 35.32 seconds
Started Apr 28 02:12:50 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204388 kb
Host smart-a0c4e71c-3012-4708-843b-c0f1072aa3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13066
80758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1306680758
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3671622452
Short name T968
Test name
Test status
Simulation time 8392145432 ps
CPU time 9.09 seconds
Started Apr 28 02:12:51 PM PDT 24
Finished Apr 28 02:13:00 PM PDT 24
Peak memory 204160 kb
Host smart-c6767877-e573-4668-af57-1adf12a89abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36716
22452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3671622452
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1940917467
Short name T1096
Test name
Test status
Simulation time 8411684635 ps
CPU time 7.97 seconds
Started Apr 28 02:12:48 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204108 kb
Host smart-63205e0b-6887-4a46-9870-13064621d9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
17467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1940917467
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2815610558
Short name T296
Test name
Test status
Simulation time 8381534266 ps
CPU time 7.99 seconds
Started Apr 28 02:12:50 PM PDT 24
Finished Apr 28 02:12:58 PM PDT 24
Peak memory 204084 kb
Host smart-af420c16-24e5-4175-a712-fc0951fa3241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
10558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2815610558
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3013118095
Short name T1358
Test name
Test status
Simulation time 8373317139 ps
CPU time 8.47 seconds
Started Apr 28 02:12:51 PM PDT 24
Finished Apr 28 02:13:00 PM PDT 24
Peak memory 204084 kb
Host smart-6d94289b-eed4-4344-9585-5c0cf7b13100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
18095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3013118095
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3711504412
Short name T704
Test name
Test status
Simulation time 8374679796 ps
CPU time 7.56 seconds
Started Apr 28 02:12:49 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204148 kb
Host smart-759ace67-0907-42ca-87fd-fcf14dcb3f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
04412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3711504412
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.417218532
Short name T756
Test name
Test status
Simulation time 8454963803 ps
CPU time 8.54 seconds
Started Apr 28 02:12:47 PM PDT 24
Finished Apr 28 02:12:56 PM PDT 24
Peak memory 204128 kb
Host smart-2cd9f802-8afb-4e00-b33f-92fd38f2ed92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
8532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.417218532
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1948447976
Short name T1076
Test name
Test status
Simulation time 8371993762 ps
CPU time 10.74 seconds
Started Apr 28 02:12:51 PM PDT 24
Finished Apr 28 02:13:02 PM PDT 24
Peak memory 204000 kb
Host smart-86a19894-8348-4dbc-a8c4-34632927a5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19484
47976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1948447976
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2095025238
Short name T530
Test name
Test status
Simulation time 8396572042 ps
CPU time 8.41 seconds
Started Apr 28 02:12:51 PM PDT 24
Finished Apr 28 02:13:00 PM PDT 24
Peak memory 204084 kb
Host smart-6ee40960-3049-4ac2-90f5-c835d1a95350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
25238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2095025238
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2385490608
Short name T33
Test name
Test status
Simulation time 8466819323 ps
CPU time 7.78 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204116 kb
Host smart-b026241c-8553-4123-85ef-731a5007ae29
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2385490608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2385490608
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1640460880
Short name T447
Test name
Test status
Simulation time 8379151895 ps
CPU time 9.69 seconds
Started Apr 28 02:13:00 PM PDT 24
Finished Apr 28 02:13:10 PM PDT 24
Peak memory 204164 kb
Host smart-1072a696-46ca-4933-9c7e-aa151e83542d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1640460880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1640460880
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3536995785
Short name T970
Test name
Test status
Simulation time 8390428368 ps
CPU time 7.74 seconds
Started Apr 28 02:12:58 PM PDT 24
Finished Apr 28 02:13:06 PM PDT 24
Peak memory 204148 kb
Host smart-f55b8f90-4992-4059-9d94-2249a88f5629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35369
95785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3536995785
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3293230766
Short name T943
Test name
Test status
Simulation time 8387159356 ps
CPU time 7.89 seconds
Started Apr 28 02:12:54 PM PDT 24
Finished Apr 28 02:13:02 PM PDT 24
Peak memory 204160 kb
Host smart-f5c241c9-629c-446b-ab8d-65834676f438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32932
30766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3293230766
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.753289871
Short name T911
Test name
Test status
Simulation time 8386678082 ps
CPU time 7.62 seconds
Started Apr 28 02:12:53 PM PDT 24
Finished Apr 28 02:13:01 PM PDT 24
Peak memory 204132 kb
Host smart-276dee09-e921-4e86-a541-3cdd2e14896b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75328
9871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.753289871
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3990455761
Short name T1025
Test name
Test status
Simulation time 243642064 ps
CPU time 1.87 seconds
Started Apr 28 02:12:55 PM PDT 24
Finished Apr 28 02:12:57 PM PDT 24
Peak memory 204276 kb
Host smart-41ed0589-89d3-4135-9105-3f936f77faa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39904
55761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3990455761
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2308626392
Short name T190
Test name
Test status
Simulation time 8376154010 ps
CPU time 8.69 seconds
Started Apr 28 02:12:59 PM PDT 24
Finished Apr 28 02:13:08 PM PDT 24
Peak memory 204056 kb
Host smart-d44bfe68-514c-4ea8-91df-42d14da1c291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
26392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2308626392
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1973574046
Short name T1147
Test name
Test status
Simulation time 8463720017 ps
CPU time 7.95 seconds
Started Apr 28 02:12:57 PM PDT 24
Finished Apr 28 02:13:06 PM PDT 24
Peak memory 203552 kb
Host smart-f1710177-740c-4455-8df6-2a5890f14e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19735
74046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1973574046
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2091634620
Short name T571
Test name
Test status
Simulation time 8522488644 ps
CPU time 10.63 seconds
Started Apr 28 02:12:54 PM PDT 24
Finished Apr 28 02:13:05 PM PDT 24
Peak memory 204132 kb
Host smart-311c8e18-1bab-4e5b-bd31-0dc59ec0c3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20916
34620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2091634620
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.172435981
Short name T783
Test name
Test status
Simulation time 8371766279 ps
CPU time 7.37 seconds
Started Apr 28 02:12:54 PM PDT 24
Finished Apr 28 02:13:02 PM PDT 24
Peak memory 204096 kb
Host smart-1aa2b2f2-10f6-4788-9899-817cb6ae25e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
5981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.172435981
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.4254264904
Short name T856
Test name
Test status
Simulation time 8414673160 ps
CPU time 8.57 seconds
Started Apr 28 02:12:58 PM PDT 24
Finished Apr 28 02:13:07 PM PDT 24
Peak memory 204084 kb
Host smart-5061eb2b-efad-4d97-9fa3-1ab7b6c9171f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42542
64904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.4254264904
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2921228434
Short name T1165
Test name
Test status
Simulation time 8401801475 ps
CPU time 7.96 seconds
Started Apr 28 02:12:53 PM PDT 24
Finished Apr 28 02:13:02 PM PDT 24
Peak memory 204140 kb
Host smart-19673d56-6cc7-4ed0-aaff-5789266ee482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29212
28434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2921228434
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2771207380
Short name T1301
Test name
Test status
Simulation time 8401909279 ps
CPU time 7.86 seconds
Started Apr 28 02:13:01 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 204028 kb
Host smart-5e8ed993-a6f1-424b-a548-44067eb016c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27712
07380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2771207380
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1647782886
Short name T575
Test name
Test status
Simulation time 90449526 ps
CPU time 0.72 seconds
Started Apr 28 02:12:59 PM PDT 24
Finished Apr 28 02:13:00 PM PDT 24
Peak memory 204028 kb
Host smart-aba24958-020d-4b1b-aad8-3cff8e6a29f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16477
82886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1647782886
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.4212360510
Short name T224
Test name
Test status
Simulation time 27259228777 ps
CPU time 49.4 seconds
Started Apr 28 02:12:53 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204372 kb
Host smart-d5186499-56be-4510-b249-95321714a0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
60510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.4212360510
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2621712315
Short name T592
Test name
Test status
Simulation time 8403344657 ps
CPU time 7.43 seconds
Started Apr 28 02:12:52 PM PDT 24
Finished Apr 28 02:13:00 PM PDT 24
Peak memory 204136 kb
Host smart-791504b0-864f-434d-aee3-7b0b4a1f8d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26217
12315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2621712315
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.4029915697
Short name T711
Test name
Test status
Simulation time 8424210658 ps
CPU time 8.2 seconds
Started Apr 28 02:12:54 PM PDT 24
Finished Apr 28 02:13:03 PM PDT 24
Peak memory 204096 kb
Host smart-477a9a36-684b-4da7-958b-b96a869e6a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40299
15697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.4029915697
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2255888758
Short name T828
Test name
Test status
Simulation time 8384769735 ps
CPU time 7.72 seconds
Started Apr 28 02:12:59 PM PDT 24
Finished Apr 28 02:13:07 PM PDT 24
Peak memory 204132 kb
Host smart-c2a4a6be-a23d-4910-81dc-5d79db409776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22558
88758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2255888758
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3755969220
Short name T160
Test name
Test status
Simulation time 8382737747 ps
CPU time 7.5 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204092 kb
Host smart-69f0ec78-7eae-4b83-be3d-09e6632b5252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
69220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3755969220
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2052913749
Short name T363
Test name
Test status
Simulation time 8394206732 ps
CPU time 7.6 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:10 PM PDT 24
Peak memory 204092 kb
Host smart-299e2de3-f9bc-42cd-875b-ec46c40c770a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20529
13749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2052913749
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3229631459
Short name T983
Test name
Test status
Simulation time 8412788372 ps
CPU time 9.38 seconds
Started Apr 28 02:12:57 PM PDT 24
Finished Apr 28 02:13:06 PM PDT 24
Peak memory 204032 kb
Host smart-1c1c08fb-bd14-49de-a5e0-b40a657f515e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
31459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3229631459
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4181229164
Short name T2
Test name
Test status
Simulation time 8403635888 ps
CPU time 9.04 seconds
Started Apr 28 02:12:58 PM PDT 24
Finished Apr 28 02:13:07 PM PDT 24
Peak memory 204140 kb
Host smart-f4bd8508-f431-4fe1-a73a-3241966568a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41812
29164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.4181229164
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1946892799
Short name T638
Test name
Test status
Simulation time 8397478070 ps
CPU time 7.73 seconds
Started Apr 28 02:13:00 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 204148 kb
Host smart-f33fa9d3-a186-46b9-8e17-2b205de61fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19468
92799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1946892799
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2496062452
Short name T1116
Test name
Test status
Simulation time 8463318517 ps
CPU time 7.71 seconds
Started Apr 28 02:13:03 PM PDT 24
Finished Apr 28 02:13:12 PM PDT 24
Peak memory 204136 kb
Host smart-8babe42c-5757-4371-b7a2-4f5f854ff1de
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2496062452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2496062452
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.1317580682
Short name T684
Test name
Test status
Simulation time 8376530269 ps
CPU time 7.64 seconds
Started Apr 28 02:13:04 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204120 kb
Host smart-cd55ea67-ecbb-4e62-bfa0-65b51331da26
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1317580682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.1317580682
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.2259881538
Short name T1023
Test name
Test status
Simulation time 8440357157 ps
CPU time 7.84 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204092 kb
Host smart-5ee79101-a484-4f6e-a719-989c39d0db6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
81538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.2259881538
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2653556443
Short name T236
Test name
Test status
Simulation time 8440083959 ps
CPU time 8.26 seconds
Started Apr 28 02:13:00 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 204128 kb
Host smart-b85aeda8-9f09-4c28-91dd-cbbf8583d5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26535
56443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2653556443
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.1636218221
Short name T1114
Test name
Test status
Simulation time 8377097842 ps
CPU time 7.79 seconds
Started Apr 28 02:13:00 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 203988 kb
Host smart-869bac10-0ca3-4929-b7ab-393c6748846d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16362
18221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1636218221
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2827779051
Short name T495
Test name
Test status
Simulation time 183295050 ps
CPU time 2 seconds
Started Apr 28 02:12:58 PM PDT 24
Finished Apr 28 02:13:01 PM PDT 24
Peak memory 204204 kb
Host smart-bb306816-ab0e-4f0d-bee2-0b783a26544a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
79051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2827779051
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2626902367
Short name T916
Test name
Test status
Simulation time 8467500869 ps
CPU time 10.62 seconds
Started Apr 28 02:13:05 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204084 kb
Host smart-85946bc5-a552-4777-b2fc-6952c48e1ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26269
02367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2626902367
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2332079528
Short name T980
Test name
Test status
Simulation time 8373787668 ps
CPU time 7.19 seconds
Started Apr 28 02:13:05 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204136 kb
Host smart-e431e5b6-a86e-45f2-a47b-138ad0068094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23320
79528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2332079528
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2659113736
Short name T478
Test name
Test status
Simulation time 8475863020 ps
CPU time 8.09 seconds
Started Apr 28 02:12:59 PM PDT 24
Finished Apr 28 02:13:08 PM PDT 24
Peak memory 204064 kb
Host smart-fad16cda-2024-4304-a9c6-33674e2cca98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
13736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2659113736
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1776567626
Short name T454
Test name
Test status
Simulation time 8441076448 ps
CPU time 9.19 seconds
Started Apr 28 02:12:59 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 204112 kb
Host smart-ba608c86-06af-4e36-ad37-58964a752481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17765
67626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1776567626
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1267828787
Short name T298
Test name
Test status
Simulation time 8380542297 ps
CPU time 7.69 seconds
Started Apr 28 02:13:05 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204112 kb
Host smart-23c453e4-a9d0-4e46-a5f2-3b1d81698fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12678
28787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1267828787
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4168589439
Short name T1355
Test name
Test status
Simulation time 8399529725 ps
CPU time 8.26 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204120 kb
Host smart-5afbf0dd-c319-4243-9798-4e2aaec12594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41685
89439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4168589439
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3498069105
Short name T834
Test name
Test status
Simulation time 8386445017 ps
CPU time 8.19 seconds
Started Apr 28 02:13:02 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204132 kb
Host smart-adc0914f-2b4a-4cc6-8175-a93b00905178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980
69105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3498069105
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3616833127
Short name T1267
Test name
Test status
Simulation time 8407810216 ps
CPU time 8.4 seconds
Started Apr 28 02:13:03 PM PDT 24
Finished Apr 28 02:13:12 PM PDT 24
Peak memory 204108 kb
Host smart-e628d91e-1a7a-43df-9b61-5a07ca5403b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168
33127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3616833127
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.404746158
Short name T733
Test name
Test status
Simulation time 8369914519 ps
CPU time 8.26 seconds
Started Apr 28 02:13:06 PM PDT 24
Finished Apr 28 02:13:15 PM PDT 24
Peak memory 203972 kb
Host smart-1c134e66-10d8-42ce-8dbe-468254e8910c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40474
6158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.404746158
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3999402560
Short name T1051
Test name
Test status
Simulation time 47458246 ps
CPU time 0.64 seconds
Started Apr 28 02:13:05 PM PDT 24
Finished Apr 28 02:13:06 PM PDT 24
Peak memory 204016 kb
Host smart-2b95c1f7-43fa-4559-b402-b88215faf9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39994
02560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3999402560
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1805197721
Short name T933
Test name
Test status
Simulation time 22480967876 ps
CPU time 47.04 seconds
Started Apr 28 02:13:06 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 204248 kb
Host smart-182ec2e4-5d59-4c4e-ac73-287242964c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18051
97721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1805197721
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2186416813
Short name T1273
Test name
Test status
Simulation time 8381176783 ps
CPU time 7.83 seconds
Started Apr 28 02:13:04 PM PDT 24
Finished Apr 28 02:13:12 PM PDT 24
Peak memory 203988 kb
Host smart-b6857605-2f33-4372-b575-9f1618f0917a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
16813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2186416813
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.84810777
Short name T593
Test name
Test status
Simulation time 8478929874 ps
CPU time 8.28 seconds
Started Apr 28 02:13:04 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204108 kb
Host smart-c775275f-393d-4a11-9083-11c1e62009f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84810
777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.84810777
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.291661803
Short name T412
Test name
Test status
Simulation time 8420854147 ps
CPU time 7.7 seconds
Started Apr 28 02:13:03 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204036 kb
Host smart-b2d87ecb-a0a6-4fcb-a321-a5fd53f449af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
1803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.291661803
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.188391936
Short name T48
Test name
Test status
Simulation time 8373044030 ps
CPU time 7.8 seconds
Started Apr 28 02:13:04 PM PDT 24
Finished Apr 28 02:13:12 PM PDT 24
Peak memory 204108 kb
Host smart-ffc9c5f4-0506-4c99-9e5c-34c41f872742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
1936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.188391936
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3200611020
Short name T1161
Test name
Test status
Simulation time 8373771499 ps
CPU time 7.89 seconds
Started Apr 28 02:13:03 PM PDT 24
Finished Apr 28 02:13:11 PM PDT 24
Peak memory 204128 kb
Host smart-bd0db38b-9a21-43df-b153-c3dbd1171b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32006
11020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3200611020
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3484584775
Short name T156
Test name
Test status
Simulation time 8482452466 ps
CPU time 7.97 seconds
Started Apr 28 02:13:00 PM PDT 24
Finished Apr 28 02:13:09 PM PDT 24
Peak memory 204088 kb
Host smart-b78ec11a-1b21-4cff-ac1b-6a51f48000ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34845
84775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3484584775
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1829080267
Short name T474
Test name
Test status
Simulation time 8390219908 ps
CPU time 8.26 seconds
Started Apr 28 02:13:04 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204104 kb
Host smart-654678c5-f6c4-4e5e-8fac-69b6c9060115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18290
80267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1829080267
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2642813161
Short name T654
Test name
Test status
Simulation time 8409669220 ps
CPU time 8.65 seconds
Started Apr 28 02:13:04 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204032 kb
Host smart-bab95d11-7ce1-4133-9581-8f9e9cdc41ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26428
13161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2642813161
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.657309983
Short name T1167
Test name
Test status
Simulation time 8493057716 ps
CPU time 7.91 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:21 PM PDT 24
Peak memory 204124 kb
Host smart-3568283f-8478-4a03-be73-2df9cd53c189
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=657309983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.657309983
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1236338045
Short name T341
Test name
Test status
Simulation time 8381004483 ps
CPU time 7.6 seconds
Started Apr 28 02:13:11 PM PDT 24
Finished Apr 28 02:13:19 PM PDT 24
Peak memory 203996 kb
Host smart-2c859018-e67b-45a5-96d5-ffc405722ac3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1236338045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1236338045
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.826893087
Short name T503
Test name
Test status
Simulation time 8424208524 ps
CPU time 7.89 seconds
Started Apr 28 02:13:10 PM PDT 24
Finished Apr 28 02:13:18 PM PDT 24
Peak memory 204136 kb
Host smart-e8cdf080-fe22-46f9-9227-a789aa7f6a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82689
3087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.826893087
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.4244066375
Short name T697
Test name
Test status
Simulation time 8385065273 ps
CPU time 8.3 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:17 PM PDT 24
Peak memory 204084 kb
Host smart-07855174-6cc1-450c-86a6-b1bd98d95dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42440
66375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.4244066375
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.3696867356
Short name T1247
Test name
Test status
Simulation time 8404979705 ps
CPU time 7.94 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 203484 kb
Host smart-590bae99-9607-4691-8a92-c62b7745f05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36968
67356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3696867356
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3832651926
Short name T702
Test name
Test status
Simulation time 109557226 ps
CPU time 1.27 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:10 PM PDT 24
Peak memory 204208 kb
Host smart-c9d347d7-086e-4f38-8ea8-d4b9f92a4285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
51926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3832651926
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1367972935
Short name T144
Test name
Test status
Simulation time 8408334691 ps
CPU time 8.57 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:21 PM PDT 24
Peak memory 204032 kb
Host smart-8f50cf09-ec0b-477a-a0e7-201de59c8b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13679
72935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1367972935
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.237389934
Short name T565
Test name
Test status
Simulation time 8391641293 ps
CPU time 10.05 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204108 kb
Host smart-3ccdf72a-f323-4453-a4df-0be048fe7056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23738
9934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.237389934
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2067506006
Short name T150
Test name
Test status
Simulation time 8375766099 ps
CPU time 7.81 seconds
Started Apr 28 02:13:11 PM PDT 24
Finished Apr 28 02:13:19 PM PDT 24
Peak memory 204140 kb
Host smart-51eab1b3-d733-4fca-b0f0-416d43061827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675
06006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2067506006
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4254323277
Short name T671
Test name
Test status
Simulation time 8431960701 ps
CPU time 7.89 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204108 kb
Host smart-4245094e-ad2c-4f14-bb6c-a699c2162037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
23277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4254323277
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3886723934
Short name T291
Test name
Test status
Simulation time 8377060947 ps
CPU time 7.41 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204128 kb
Host smart-97b27088-4ff3-40eb-bc32-d3bf893bc9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38867
23934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3886723934
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.25232891
Short name T1097
Test name
Test status
Simulation time 8410126512 ps
CPU time 8.08 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:20 PM PDT 24
Peak memory 204032 kb
Host smart-149ecf8e-f871-42e3-85f1-17bfbcd3b82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25232
891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.25232891
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3587496592
Short name T721
Test name
Test status
Simulation time 8474206380 ps
CPU time 8.65 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:18 PM PDT 24
Peak memory 204096 kb
Host smart-eb54cf24-11dd-48e3-8472-59c2aecb2006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
96592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3587496592
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.644813396
Short name T952
Test name
Test status
Simulation time 8385202107 ps
CPU time 7.66 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204116 kb
Host smart-6e38472e-7ed7-4eed-a4b3-3565f3ff0222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64481
3396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.644813396
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1629903702
Short name T330
Test name
Test status
Simulation time 38307102 ps
CPU time 0.72 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:13 PM PDT 24
Peak memory 204016 kb
Host smart-cf4ffd2c-e8f2-4f6c-a7ac-853a9d5d69a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16299
03702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1629903702
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.148122304
Short name T240
Test name
Test status
Simulation time 14084579269 ps
CPU time 23.44 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 203736 kb
Host smart-1edd25b7-f794-4ddf-a876-a78795925c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14812
2304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.148122304
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3915654427
Short name T219
Test name
Test status
Simulation time 8508074835 ps
CPU time 9.46 seconds
Started Apr 28 02:13:07 PM PDT 24
Finished Apr 28 02:13:17 PM PDT 24
Peak memory 204108 kb
Host smart-90804206-9d2a-4e7d-90c0-b37ed8e7dd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
54427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3915654427
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.62341580
Short name T1357
Test name
Test status
Simulation time 8400519075 ps
CPU time 8.1 seconds
Started Apr 28 02:13:11 PM PDT 24
Finished Apr 28 02:13:20 PM PDT 24
Peak memory 204032 kb
Host smart-c1612cd5-d3b7-43cb-8f26-5f363de098ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62341
580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.62341580
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.131973183
Short name T345
Test name
Test status
Simulation time 8413928365 ps
CPU time 7.95 seconds
Started Apr 28 02:13:08 PM PDT 24
Finished Apr 28 02:13:17 PM PDT 24
Peak memory 204136 kb
Host smart-ee8a5aeb-aa86-4186-8c3b-9296f0e34f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
3183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.131973183
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1491834015
Short name T769
Test name
Test status
Simulation time 8376285754 ps
CPU time 8.32 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 203528 kb
Host smart-b38d49b6-107b-48eb-8b31-990df9d0449f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14918
34015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1491834015
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3907987918
Short name T761
Test name
Test status
Simulation time 8369175030 ps
CPU time 7.48 seconds
Started Apr 28 02:13:11 PM PDT 24
Finished Apr 28 02:13:19 PM PDT 24
Peak memory 204136 kb
Host smart-9ab5d0bf-a364-459c-b1bb-abb707bac381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
87918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3907987918
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2511386802
Short name T958
Test name
Test status
Simulation time 8438992289 ps
CPU time 9.44 seconds
Started Apr 28 02:13:10 PM PDT 24
Finished Apr 28 02:13:19 PM PDT 24
Peak memory 204000 kb
Host smart-ae82155d-90f2-48ee-b7c6-091b7b31a4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25113
86802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2511386802
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2139454650
Short name T1236
Test name
Test status
Simulation time 8393615482 ps
CPU time 7.39 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:21 PM PDT 24
Peak memory 203564 kb
Host smart-22bb01ca-0885-43ef-821a-236e13b818eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394
54650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2139454650
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1007508532
Short name T1202
Test name
Test status
Simulation time 8370756279 ps
CPU time 8.72 seconds
Started Apr 28 02:13:10 PM PDT 24
Finished Apr 28 02:13:19 PM PDT 24
Peak memory 204092 kb
Host smart-4325b4ce-df1a-4f74-b03c-afa1ee1e7c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10075
08532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1007508532
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.3832585286
Short name T613
Test name
Test status
Simulation time 8462351170 ps
CPU time 8.1 seconds
Started Apr 28 02:11:18 PM PDT 24
Finished Apr 28 02:11:27 PM PDT 24
Peak memory 204068 kb
Host smart-29e47648-4204-49d7-b7d6-750529fa6702
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3832585286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.3832585286
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1955051294
Short name T334
Test name
Test status
Simulation time 8392094897 ps
CPU time 7.3 seconds
Started Apr 28 02:11:16 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204120 kb
Host smart-41d1a6a7-4c5b-49d7-9302-be972f12b702
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1955051294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1955051294
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.2501280789
Short name T414
Test name
Test status
Simulation time 8397826290 ps
CPU time 8.3 seconds
Started Apr 28 02:11:15 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204100 kb
Host smart-b5e9fc84-82b9-4870-9176-2a6e38003c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25012
80789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.2501280789
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4127822615
Short name T508
Test name
Test status
Simulation time 8378246253 ps
CPU time 7.56 seconds
Started Apr 28 02:11:08 PM PDT 24
Finished Apr 28 02:11:16 PM PDT 24
Peak memory 204120 kb
Host smart-9f6f1396-a38b-4430-8a5b-07c05afe5be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41278
22615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4127822615
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.3081132942
Short name T404
Test name
Test status
Simulation time 8374155434 ps
CPU time 7.37 seconds
Started Apr 28 02:11:04 PM PDT 24
Finished Apr 28 02:11:13 PM PDT 24
Peak memory 204076 kb
Host smart-3cbbf575-db33-4b6d-8be5-4aad3b7612e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30811
32942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3081132942
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.740808952
Short name T736
Test name
Test status
Simulation time 57000006 ps
CPU time 1.33 seconds
Started Apr 28 02:11:04 PM PDT 24
Finished Apr 28 02:11:07 PM PDT 24
Peak memory 204176 kb
Host smart-227f425a-ff17-471d-9adb-eeab6dde74e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74080
8952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.740808952
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.234085501
Short name T1344
Test name
Test status
Simulation time 8419700717 ps
CPU time 9.07 seconds
Started Apr 28 02:11:14 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204004 kb
Host smart-c65a08bf-917f-4e7d-a30f-ba983f102472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
5501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.234085501
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3787528558
Short name T1315
Test name
Test status
Simulation time 8365173264 ps
CPU time 7.56 seconds
Started Apr 28 02:11:09 PM PDT 24
Finished Apr 28 02:11:17 PM PDT 24
Peak memory 204076 kb
Host smart-168b8f01-6078-476d-9d9c-c98167dff18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
28558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3787528558
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.82020777
Short name T336
Test name
Test status
Simulation time 8433142536 ps
CPU time 7.95 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:14 PM PDT 24
Peak memory 204100 kb
Host smart-43461f2e-5926-4fa8-9b68-c45f6c0b7284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82020
777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.82020777
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1426709671
Short name T400
Test name
Test status
Simulation time 8418116630 ps
CPU time 9.01 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:21 PM PDT 24
Peak memory 204136 kb
Host smart-9c5ed522-5982-4e9f-bd59-541a76aed6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14267
09671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1426709671
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.447737751
Short name T1011
Test name
Test status
Simulation time 8369204035 ps
CPU time 8.61 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 204120 kb
Host smart-1ac66aa5-315f-41b1-abda-d187d3d8b9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44773
7751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.447737751
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.818163435
Short name T108
Test name
Test status
Simulation time 8461045210 ps
CPU time 7.86 seconds
Started Apr 28 02:11:12 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 204036 kb
Host smart-25bc3b9a-e9f9-4ccb-afd4-6975395ce97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81816
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.818163435
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3915994582
Short name T1102
Test name
Test status
Simulation time 8395402958 ps
CPU time 7.66 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:19 PM PDT 24
Peak memory 204096 kb
Host smart-7bd1d1c5-17da-4da4-85f0-1fd63596508f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159
94582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3915994582
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3566066139
Short name T899
Test name
Test status
Simulation time 8395156185 ps
CPU time 9.16 seconds
Started Apr 28 02:11:09 PM PDT 24
Finished Apr 28 02:11:19 PM PDT 24
Peak memory 204128 kb
Host smart-f8572117-9e85-481f-baab-ef2264c7bd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35660
66139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3566066139
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3347073908
Short name T1258
Test name
Test status
Simulation time 8374625789 ps
CPU time 9.15 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:21 PM PDT 24
Peak memory 204108 kb
Host smart-f3e8136c-7d43-4b49-b17c-b3ba7d4c7c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33470
73908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3347073908
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.455682235
Short name T1251
Test name
Test status
Simulation time 40146294 ps
CPU time 0.66 seconds
Started Apr 28 02:11:08 PM PDT 24
Finished Apr 28 02:11:10 PM PDT 24
Peak memory 203872 kb
Host smart-40e8bacf-516d-4b31-a544-7f8b5314785a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45568
2235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.455682235
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1324823973
Short name T1297
Test name
Test status
Simulation time 8386780103 ps
CPU time 9.74 seconds
Started Apr 28 02:11:10 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 204096 kb
Host smart-ff2458ba-7cd8-496c-b98e-633722e32298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248
23973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1324823973
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1376492134
Short name T514
Test name
Test status
Simulation time 8453596489 ps
CPU time 7.57 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:19 PM PDT 24
Peak memory 204056 kb
Host smart-72c4912e-2469-45ba-b05e-8d3698f69215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
92134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1376492134
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1629832195
Short name T648
Test name
Test status
Simulation time 8416736843 ps
CPU time 8.02 seconds
Started Apr 28 02:11:10 PM PDT 24
Finished Apr 28 02:11:18 PM PDT 24
Peak memory 204144 kb
Host smart-2c0e198d-2459-4d7b-b938-64d991f67ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
32195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1629832195
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2676271639
Short name T71
Test name
Test status
Simulation time 299314598 ps
CPU time 1.13 seconds
Started Apr 28 02:11:16 PM PDT 24
Finished Apr 28 02:11:18 PM PDT 24
Peak memory 220304 kb
Host smart-4e6e9fc1-3752-4fcf-95c0-e1a3f1c28d41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2676271639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2676271639
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2233000641
Short name T1230
Test name
Test status
Simulation time 8446535829 ps
CPU time 10.3 seconds
Started Apr 28 02:11:13 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204040 kb
Host smart-f12580e0-d768-4978-a192-b6552c65f257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
00641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2233000641
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3471154511
Short name T432
Test name
Test status
Simulation time 8374139341 ps
CPU time 8.17 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 204092 kb
Host smart-09112648-c89d-4e7d-a054-2041be9193fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34711
54511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3471154511
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3228782482
Short name T1103
Test name
Test status
Simulation time 8427800115 ps
CPU time 9.58 seconds
Started Apr 28 02:11:05 PM PDT 24
Finished Apr 28 02:11:16 PM PDT 24
Peak memory 204108 kb
Host smart-7d655ab0-a074-4f96-8149-8633e6f5fac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
82482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3228782482
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1652802761
Short name T901
Test name
Test status
Simulation time 8407877297 ps
CPU time 8.24 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 204100 kb
Host smart-f194037e-1543-4ff8-a423-b3329917e706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
02761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1652802761
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1761218434
Short name T518
Test name
Test status
Simulation time 8396903339 ps
CPU time 8.47 seconds
Started Apr 28 02:11:11 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 204124 kb
Host smart-02c7c77c-85b0-40c2-b2a6-b8dbe69084b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17612
18434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1761218434
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.1291755235
Short name T602
Test name
Test status
Simulation time 8469970753 ps
CPU time 7.67 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:27 PM PDT 24
Peak memory 204120 kb
Host smart-f5ecbcf4-daff-4b14-9b83-59a94515894b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1291755235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.1291755235
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.3369925774
Short name T930
Test name
Test status
Simulation time 8408093205 ps
CPU time 8.3 seconds
Started Apr 28 02:13:20 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204160 kb
Host smart-d3d028ba-1884-460c-8236-dc1ec05c6afc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3369925774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.3369925774
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.4143377034
Short name T906
Test name
Test status
Simulation time 8377460421 ps
CPU time 8.92 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:28 PM PDT 24
Peak memory 204108 kb
Host smart-4ef72762-bb4e-48d5-b52e-39d5d2172bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433
77034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.4143377034
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.4230740251
Short name T1032
Test name
Test status
Simulation time 8377361093 ps
CPU time 7.68 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204104 kb
Host smart-97d41811-ae71-46ae-a986-5e37cf43e3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
40251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.4230740251
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.2159276921
Short name T618
Test name
Test status
Simulation time 8376695591 ps
CPU time 8.17 seconds
Started Apr 28 02:13:15 PM PDT 24
Finished Apr 28 02:13:23 PM PDT 24
Peak memory 204060 kb
Host smart-49cbaf77-eaf1-472b-9219-6e03b21ada2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21592
76921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2159276921
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3427687619
Short name T212
Test name
Test status
Simulation time 60900236 ps
CPU time 1.55 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204276 kb
Host smart-127f8426-3e6b-4104-b3e3-6cdd1fba1ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34276
87619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3427687619
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3517181385
Short name T574
Test name
Test status
Simulation time 8433626501 ps
CPU time 7.9 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204068 kb
Host smart-82e1c3cf-b8f6-4a0e-8603-1fd1faf41278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35171
81385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3517181385
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3831382141
Short name T1073
Test name
Test status
Simulation time 8369021060 ps
CPU time 8.25 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204104 kb
Host smart-79ff49a5-8afe-4b9c-ac38-d368539ed5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38313
82141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3831382141
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.66760174
Short name T133
Test name
Test status
Simulation time 8404300110 ps
CPU time 8.54 seconds
Started Apr 28 02:13:17 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204116 kb
Host smart-d14e5b90-21cc-4f0d-a405-17548c88203b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66760
174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.66760174
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.683107651
Short name T388
Test name
Test status
Simulation time 8417812505 ps
CPU time 8.98 seconds
Started Apr 28 02:13:15 PM PDT 24
Finished Apr 28 02:13:24 PM PDT 24
Peak memory 204104 kb
Host smart-bb97db7f-7b01-4e74-aea6-4b2a6e75bbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68310
7651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.683107651
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.61132498
Short name T1043
Test name
Test status
Simulation time 8370544390 ps
CPU time 7.57 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:21 PM PDT 24
Peak memory 204048 kb
Host smart-f92db848-e9f6-47dd-8b11-5edde5b2ecb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61132
498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.61132498
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3931052338
Short name T124
Test name
Test status
Simulation time 8431262007 ps
CPU time 7.84 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204128 kb
Host smart-d0654ba9-ec07-45fe-ab78-01f981a14ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39310
52338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3931052338
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1919950188
Short name T339
Test name
Test status
Simulation time 8406082677 ps
CPU time 7.8 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:21 PM PDT 24
Peak memory 204164 kb
Host smart-d4678516-70e0-4ffd-bebb-d5c1c3c26464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19199
50188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1919950188
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2417493937
Short name T534
Test name
Test status
Simulation time 8396938663 ps
CPU time 7.98 seconds
Started Apr 28 02:13:17 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204168 kb
Host smart-fa9f738d-5307-44ad-b474-670b1fae5d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24174
93937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2417493937
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3019331491
Short name T185
Test name
Test status
Simulation time 8410723745 ps
CPU time 7.98 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204128 kb
Host smart-b811bd90-86ba-4f6d-a8d6-940ac8217699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30193
31491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3019331491
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1401929677
Short name T1370
Test name
Test status
Simulation time 8379139559 ps
CPU time 8.11 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:23 PM PDT 24
Peak memory 204084 kb
Host smart-db604d83-1df2-4849-94b5-de7488a22559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
29677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1401929677
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.950222431
Short name T1336
Test name
Test status
Simulation time 95186192 ps
CPU time 0.75 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:15 PM PDT 24
Peak memory 204048 kb
Host smart-0c3fd009-034c-4603-86b0-3fa1dd756f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95022
2431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.950222431
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2713495671
Short name T1015
Test name
Test status
Simulation time 13918757949 ps
CPU time 23.32 seconds
Started Apr 28 02:13:13 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 204444 kb
Host smart-76b71b33-dd8a-4157-943a-c3928bd2276b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27134
95671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2713495671
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.931667548
Short name T489
Test name
Test status
Simulation time 8380215322 ps
CPU time 8.16 seconds
Started Apr 28 02:13:15 PM PDT 24
Finished Apr 28 02:13:23 PM PDT 24
Peak memory 203984 kb
Host smart-6b589637-2582-4854-808a-8d13cdc61afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93166
7548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.931667548
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1323681454
Short name T957
Test name
Test status
Simulation time 8511021672 ps
CPU time 7.56 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204056 kb
Host smart-ce03a70c-63db-42ca-9d35-db519c54b5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236
81454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1323681454
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3470446158
Short name T985
Test name
Test status
Simulation time 8399577778 ps
CPU time 7.7 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204132 kb
Host smart-597c1574-192a-48bf-9d4c-1ffe6abd93f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
46158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3470446158
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2521261673
Short name T501
Test name
Test status
Simulation time 8414012535 ps
CPU time 8.13 seconds
Started Apr 28 02:13:16 PM PDT 24
Finished Apr 28 02:13:24 PM PDT 24
Peak memory 204100 kb
Host smart-edecd23b-f47b-4298-a344-92271b8da979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25212
61673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2521261673
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2184221887
Short name T476
Test name
Test status
Simulation time 8369432972 ps
CPU time 10.33 seconds
Started Apr 28 02:13:15 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204136 kb
Host smart-518002b6-ea7c-4a93-8ba8-719130a1b68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21842
21887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2184221887
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4102702550
Short name T913
Test name
Test status
Simulation time 8393486798 ps
CPU time 9.53 seconds
Started Apr 28 02:13:14 PM PDT 24
Finished Apr 28 02:13:24 PM PDT 24
Peak memory 204132 kb
Host smart-f1cab3ce-8f5e-41c0-9656-7097e19b2751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41027
02550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4102702550
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3440198649
Short name T1351
Test name
Test status
Simulation time 8420309631 ps
CPU time 8.49 seconds
Started Apr 28 02:13:12 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204100 kb
Host smart-72704ff8-3093-43cc-b303-a859fc64e2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34401
98649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3440198649
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.934195844
Short name T1296
Test name
Test status
Simulation time 8485121677 ps
CPU time 7.63 seconds
Started Apr 28 02:13:23 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 204128 kb
Host smart-6dc2d48e-0db8-4e27-a612-cf2e825c5b0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=934195844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.934195844
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.3246445697
Short name T816
Test name
Test status
Simulation time 8379382867 ps
CPU time 7.67 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:32 PM PDT 24
Peak memory 204136 kb
Host smart-28a6da7a-172f-4899-b3ca-f82edd2e7f66
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3246445697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3246445697
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3348115407
Short name T428
Test name
Test status
Simulation time 8409740663 ps
CPU time 10.05 seconds
Started Apr 28 02:13:17 PM PDT 24
Finished Apr 28 02:13:28 PM PDT 24
Peak memory 204156 kb
Host smart-a7ce08de-fee6-48de-a934-e47128ff22ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33481
15407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3348115407
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2124377634
Short name T469
Test name
Test status
Simulation time 8381689805 ps
CPU time 7.64 seconds
Started Apr 28 02:13:20 PM PDT 24
Finished Apr 28 02:13:28 PM PDT 24
Peak memory 204068 kb
Host smart-512a3a11-52e8-467a-b6d2-d73fcc6bd9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21243
77634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2124377634
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.4070736177
Short name T389
Test name
Test status
Simulation time 8399692688 ps
CPU time 7.82 seconds
Started Apr 28 02:13:18 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204072 kb
Host smart-f1d7c62a-c56b-4fd4-ab27-f6991fdb7572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40707
36177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.4070736177
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1763430823
Short name T822
Test name
Test status
Simulation time 170401149 ps
CPU time 1.5 seconds
Started Apr 28 02:13:20 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 204228 kb
Host smart-6cd749b1-76d8-43f6-966c-56f715f153c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
30823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1763430823
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2608227286
Short name T1302
Test name
Test status
Simulation time 8435775854 ps
CPU time 9.29 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204136 kb
Host smart-3dabd00c-1f0f-4863-809c-22a840f422d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26082
27286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2608227286
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3079362090
Short name T194
Test name
Test status
Simulation time 8379000534 ps
CPU time 8.95 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 204068 kb
Host smart-c236d32e-c6a4-4c19-9da9-7881db4cae89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
62090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3079362090
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2786359173
Short name T384
Test name
Test status
Simulation time 8410580661 ps
CPU time 8.19 seconds
Started Apr 28 02:13:17 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204100 kb
Host smart-3f8ebdde-37d2-41ed-8ed5-ccff314626b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27863
59173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2786359173
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2467279433
Short name T408
Test name
Test status
Simulation time 8463706935 ps
CPU time 9.72 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204092 kb
Host smart-541acead-2be1-42e7-b56d-1bc0656cd582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24672
79433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2467279433
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3632617032
Short name T1232
Test name
Test status
Simulation time 8392493405 ps
CPU time 7.94 seconds
Started Apr 28 02:13:20 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204096 kb
Host smart-419f0319-47c9-4c7f-8b77-4f117d1843a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36326
17032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3632617032
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3200712547
Short name T122
Test name
Test status
Simulation time 8430109674 ps
CPU time 8.07 seconds
Started Apr 28 02:13:17 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204120 kb
Host smart-7ea4f082-3d12-4e00-92c3-7d60a4aeed11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32007
12547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3200712547
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2374464327
Short name T450
Test name
Test status
Simulation time 8404065938 ps
CPU time 7.49 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:27 PM PDT 24
Peak memory 204104 kb
Host smart-7346ee75-3ded-4065-a014-b3250b0700b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
64327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2374464327
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2724035212
Short name T288
Test name
Test status
Simulation time 8415223336 ps
CPU time 8.21 seconds
Started Apr 28 02:13:21 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204168 kb
Host smart-64701122-7cb1-4c47-a349-c424d69d1919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27240
35212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2724035212
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2540267806
Short name T415
Test name
Test status
Simulation time 8419982243 ps
CPU time 8.69 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204096 kb
Host smart-a134b6e9-f3ec-4040-b403-88c66bf2eaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
67806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2540267806
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.4013218411
Short name T393
Test name
Test status
Simulation time 8403656294 ps
CPU time 7.52 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204088 kb
Host smart-c5efa949-1f85-4c2e-8281-439970007479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40132
18411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.4013218411
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1879638476
Short name T487
Test name
Test status
Simulation time 48790210 ps
CPU time 0.69 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:21 PM PDT 24
Peak memory 203868 kb
Host smart-fcb8cc61-691e-46e5-9b37-2b9987b13280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
38476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1879638476
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2073549746
Short name T89
Test name
Test status
Simulation time 29797892301 ps
CPU time 61.63 seconds
Started Apr 28 02:13:21 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204452 kb
Host smart-d0681515-39e5-4782-a75c-fa71a083f753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
49746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2073549746
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1714702887
Short name T1014
Test name
Test status
Simulation time 8445749125 ps
CPU time 8.94 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204104 kb
Host smart-bb8fa608-e3cf-4ed1-92b9-b64454e64e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17147
02887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1714702887
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2830633902
Short name T1089
Test name
Test status
Simulation time 8435013652 ps
CPU time 8.38 seconds
Started Apr 28 02:13:20 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204048 kb
Host smart-31cbeb1c-6c58-49a7-ac5d-99b11b494278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306
33902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2830633902
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1113589237
Short name T1219
Test name
Test status
Simulation time 8411106462 ps
CPU time 8.4 seconds
Started Apr 28 02:13:21 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204132 kb
Host smart-c4f87865-da1e-4020-91ec-6ad4e63ba2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
89237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1113589237
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.182694419
Short name T569
Test name
Test status
Simulation time 8396051451 ps
CPU time 7.81 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:27 PM PDT 24
Peak memory 204116 kb
Host smart-2e0304ca-1c56-4390-877e-4b3ddf422801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18269
4419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.182694419
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.4076234336
Short name T421
Test name
Test status
Simulation time 8371661546 ps
CPU time 7.7 seconds
Started Apr 28 02:13:19 PM PDT 24
Finished Apr 28 02:13:27 PM PDT 24
Peak memory 204112 kb
Host smart-ddfbc254-6086-4994-bb4a-f51a17740ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40762
34336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.4076234336
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2445065634
Short name T1040
Test name
Test status
Simulation time 8441417782 ps
CPU time 8.92 seconds
Started Apr 28 02:13:16 PM PDT 24
Finished Apr 28 02:13:25 PM PDT 24
Peak memory 204104 kb
Host smart-b049524b-c382-4cea-ba7d-022f5a9eb85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24450
65634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2445065634
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1334798072
Short name T1363
Test name
Test status
Simulation time 8422740419 ps
CPU time 7.91 seconds
Started Apr 28 02:13:21 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204000 kb
Host smart-7e10d32d-2fbb-4b71-900d-a4cf59862f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13347
98072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1334798072
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2897866112
Short name T519
Test name
Test status
Simulation time 8391705624 ps
CPU time 9.61 seconds
Started Apr 28 02:13:17 PM PDT 24
Finished Apr 28 02:13:28 PM PDT 24
Peak memory 204088 kb
Host smart-c1c2a4c3-e67c-488a-b578-5afe672da83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28978
66112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2897866112
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.2244111195
Short name T370
Test name
Test status
Simulation time 8474519204 ps
CPU time 9.81 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204140 kb
Host smart-7cfb2580-f9ed-4912-b465-33756b4fe733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2244111195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.2244111195
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.91621553
Short name T1366
Test name
Test status
Simulation time 8381298168 ps
CPU time 8.44 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 204076 kb
Host smart-067f86b6-9126-4f47-a1f5-0af0e2333847
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=91621553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.91621553
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.3160950983
Short name T1313
Test name
Test status
Simulation time 8403053781 ps
CPU time 7.6 seconds
Started Apr 28 02:13:23 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 204160 kb
Host smart-dc19fcbe-23d3-480a-89ef-6788d3b164d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31609
50983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.3160950983
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3690462871
Short name T1143
Test name
Test status
Simulation time 8373338899 ps
CPU time 8.26 seconds
Started Apr 28 02:13:25 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204152 kb
Host smart-0b32be0e-5925-4af4-b1b7-81455db37b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904
62871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3690462871
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.354418730
Short name T331
Test name
Test status
Simulation time 8379337054 ps
CPU time 7.84 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204048 kb
Host smart-8b49fc01-b694-484a-961c-2800a3e359bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35441
8730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.354418730
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1564781311
Short name T343
Test name
Test status
Simulation time 298240559 ps
CPU time 2.39 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:26 PM PDT 24
Peak memory 204252 kb
Host smart-f87bc5e9-c0a5-48b8-a291-67b4c8a59a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
81311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1564781311
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1538258505
Short name T1234
Test name
Test status
Simulation time 8504174708 ps
CPU time 8.96 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204112 kb
Host smart-806fc1f8-43a0-4265-bfa1-e34092b8c4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15382
58505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1538258505
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2028102825
Short name T1013
Test name
Test status
Simulation time 8375720864 ps
CPU time 7.72 seconds
Started Apr 28 02:13:25 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204148 kb
Host smart-a3e5da93-dc0d-4d75-bbc7-c09f107cc141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20281
02825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2028102825
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3759249
Short name T1091
Test name
Test status
Simulation time 8466359323 ps
CPU time 8.6 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204004 kb
Host smart-f64eea06-99d6-4c23-934d-40dc4679fbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37592
49 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3759249
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2840151908
Short name T354
Test name
Test status
Simulation time 8448930224 ps
CPU time 7.58 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:30 PM PDT 24
Peak memory 204040 kb
Host smart-c31c3cea-4eee-4d9a-8d2c-f6ab1e0f62b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
51908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2840151908
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3507010657
Short name T1081
Test name
Test status
Simulation time 8380340766 ps
CPU time 7.95 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 203996 kb
Host smart-c591521d-5291-479a-869d-ba0366be51f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35070
10657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3507010657
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3492393069
Short name T109
Test name
Test status
Simulation time 8395893078 ps
CPU time 8.81 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204100 kb
Host smart-3f0d81f3-83eb-4886-8911-87c00b162897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34923
93069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3492393069
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.494199874
Short name T1144
Test name
Test status
Simulation time 8410985115 ps
CPU time 10.39 seconds
Started Apr 28 02:13:22 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204084 kb
Host smart-7525d81d-5a29-42b2-8d2b-dd19989392a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49419
9874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.494199874
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3201858723
Short name T734
Test name
Test status
Simulation time 8387948354 ps
CPU time 9.23 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204116 kb
Host smart-4763380e-43d3-481b-8123-92b8d3706597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
58723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3201858723
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.570761531
Short name T163
Test name
Test status
Simulation time 8394155615 ps
CPU time 7.76 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204144 kb
Host smart-ca4dd6f2-ef13-4320-91b1-fa5416dce04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57076
1531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.570761531
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2262728515
Short name T1054
Test name
Test status
Simulation time 8374088014 ps
CPU time 7.48 seconds
Started Apr 28 02:13:23 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 204132 kb
Host smart-96afc64c-6f49-4dc7-b0ca-968d6ac53178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22627
28515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2262728515
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.596822832
Short name T982
Test name
Test status
Simulation time 31235023 ps
CPU time 0.64 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:25 PM PDT 24
Peak memory 203984 kb
Host smart-eaa672b9-838c-4f09-8f12-a260e71b52f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59682
2832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.596822832
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.114357981
Short name T259
Test name
Test status
Simulation time 29927327434 ps
CPU time 62.14 seconds
Started Apr 28 02:13:23 PM PDT 24
Finished Apr 28 02:14:25 PM PDT 24
Peak memory 204376 kb
Host smart-d74a07af-19fb-4a36-ab01-d1bf15e89bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.114357981
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3569734352
Short name T1335
Test name
Test status
Simulation time 8463760858 ps
CPU time 7.94 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204112 kb
Host smart-fcf6d83e-71af-4a27-b723-7798d0120d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35697
34352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3569734352
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3640554461
Short name T1124
Test name
Test status
Simulation time 8492559689 ps
CPU time 8.22 seconds
Started Apr 28 02:13:32 PM PDT 24
Finished Apr 28 02:13:41 PM PDT 24
Peak memory 204068 kb
Host smart-93070a71-5054-4d7f-8f91-71c738f300f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405
54461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3640554461
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3048575595
Short name T1209
Test name
Test status
Simulation time 8376231107 ps
CPU time 7.52 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204032 kb
Host smart-b9689593-429c-4777-badb-d95616f5c31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30485
75595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3048575595
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1958423479
Short name T1229
Test name
Test status
Simulation time 8384107653 ps
CPU time 9.23 seconds
Started Apr 28 02:13:31 PM PDT 24
Finished Apr 28 02:13:41 PM PDT 24
Peak memory 204080 kb
Host smart-53c5faed-b892-459d-a46a-06cc3a8abc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19584
23479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1958423479
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3531886459
Short name T861
Test name
Test status
Simulation time 8383422193 ps
CPU time 8.3 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204120 kb
Host smart-02911566-de21-425e-8f4d-0d48d9583c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35318
86459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3531886459
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2210082522
Short name T562
Test name
Test status
Simulation time 8470733967 ps
CPU time 7.52 seconds
Started Apr 28 02:13:26 PM PDT 24
Finished Apr 28 02:13:33 PM PDT 24
Peak memory 204080 kb
Host smart-1bdd443a-2e0a-4c3e-b719-52c105f3fd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22100
82522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2210082522
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2765693688
Short name T707
Test name
Test status
Simulation time 8406469124 ps
CPU time 8.83 seconds
Started Apr 28 02:13:24 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204092 kb
Host smart-0926fd44-78e8-4c06-9bc6-87307dd55fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27656
93688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2765693688
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3780381786
Short name T468
Test name
Test status
Simulation time 8388251873 ps
CPU time 8.77 seconds
Started Apr 28 02:13:23 PM PDT 24
Finished Apr 28 02:13:32 PM PDT 24
Peak memory 204152 kb
Host smart-464bedab-82b2-4777-9924-2e57f3744e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37803
81786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3780381786
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1897221074
Short name T984
Test name
Test status
Simulation time 8462324430 ps
CPU time 8.09 seconds
Started Apr 28 02:13:29 PM PDT 24
Finished Apr 28 02:13:38 PM PDT 24
Peak memory 204084 kb
Host smart-614043e4-cb6a-4918-920e-d3e84a5fef28
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1897221074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1897221074
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.4207543976
Short name T1155
Test name
Test status
Simulation time 8418604758 ps
CPU time 8.03 seconds
Started Apr 28 02:13:30 PM PDT 24
Finished Apr 28 02:13:39 PM PDT 24
Peak memory 204120 kb
Host smart-10f25ee0-97e8-4a55-b8ae-4ce39b0a9c3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4207543976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.4207543976
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.801506264
Short name T1327
Test name
Test status
Simulation time 8538665548 ps
CPU time 8.23 seconds
Started Apr 28 02:13:27 PM PDT 24
Finished Apr 28 02:13:36 PM PDT 24
Peak memory 204068 kb
Host smart-373fb126-f554-4364-88a9-ced3e3ad2b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80150
6264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.801506264
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.658383839
Short name T367
Test name
Test status
Simulation time 8378018214 ps
CPU time 8.11 seconds
Started Apr 28 02:13:28 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 204076 kb
Host smart-c1302c1f-4eac-4e60-9373-47fcd457cdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65838
3839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.658383839
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.1092981586
Short name T1160
Test name
Test status
Simulation time 8412961062 ps
CPU time 7.45 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204072 kb
Host smart-e6c64558-f82c-4060-b027-95a16a5c6c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
81586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1092981586
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3575979094
Short name T1085
Test name
Test status
Simulation time 82876227 ps
CPU time 1.91 seconds
Started Apr 28 02:13:27 PM PDT 24
Finished Apr 28 02:13:29 PM PDT 24
Peak memory 204192 kb
Host smart-cacc36c3-4881-4171-9564-61d940bcee18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
79094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3575979094
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2365474957
Short name T380
Test name
Test status
Simulation time 8443586048 ps
CPU time 7.81 seconds
Started Apr 28 02:13:27 PM PDT 24
Finished Apr 28 02:13:36 PM PDT 24
Peak memory 204112 kb
Host smart-dce50ca5-41ee-4ddc-ae66-b34ef3a9e8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23654
74957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2365474957
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3063700073
Short name T191
Test name
Test status
Simulation time 8370797763 ps
CPU time 8.61 seconds
Started Apr 28 02:13:27 PM PDT 24
Finished Apr 28 02:13:36 PM PDT 24
Peak memory 204092 kb
Host smart-6de675ab-9375-4511-b85a-6a39cef0a3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30637
00073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3063700073
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2842291006
Short name T1206
Test name
Test status
Simulation time 8435584760 ps
CPU time 9.32 seconds
Started Apr 28 02:13:29 PM PDT 24
Finished Apr 28 02:13:39 PM PDT 24
Peak memory 204148 kb
Host smart-1a7f15c2-8828-4132-aff3-31770c1c6021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28422
91006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2842291006
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.291780707
Short name T366
Test name
Test status
Simulation time 8432651774 ps
CPU time 8.07 seconds
Started Apr 28 02:13:27 PM PDT 24
Finished Apr 28 02:13:36 PM PDT 24
Peak memory 204120 kb
Host smart-1c333bcf-2b72-4a10-95cc-3304bda0f520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29178
0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.291780707
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2453107780
Short name T842
Test name
Test status
Simulation time 8388444896 ps
CPU time 7.68 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204112 kb
Host smart-f9588dff-24a0-4977-8a35-2d908483b1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24531
07780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2453107780
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1692985285
Short name T956
Test name
Test status
Simulation time 8377047724 ps
CPU time 8.06 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 203820 kb
Host smart-56016eb1-457f-4ea4-8eef-08ad5379a856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
85285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1692985285
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4282088606
Short name T1286
Test name
Test status
Simulation time 8411337535 ps
CPU time 8.65 seconds
Started Apr 28 02:13:28 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 204112 kb
Host smart-c2195099-ed14-424d-a5ad-e46874b71c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42820
88606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4282088606
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1248644880
Short name T183
Test name
Test status
Simulation time 8378155391 ps
CPU time 7.97 seconds
Started Apr 28 02:13:28 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 204072 kb
Host smart-929119f2-57e6-4318-bcaa-46dc8796e261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12486
44880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1248644880
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2873820911
Short name T8
Test name
Test status
Simulation time 8393319349 ps
CPU time 7.64 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204100 kb
Host smart-71c011f3-06b5-4d32-af2e-2f57ca393a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28738
20911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2873820911
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3996386427
Short name T35
Test name
Test status
Simulation time 36492828 ps
CPU time 0.66 seconds
Started Apr 28 02:13:30 PM PDT 24
Finished Apr 28 02:13:31 PM PDT 24
Peak memory 203992 kb
Host smart-bcddd3b5-bafb-44dd-87b1-058d7efe9da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
86427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3996386427
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.239319662
Short name T220
Test name
Test status
Simulation time 27781922330 ps
CPU time 56.17 seconds
Started Apr 28 02:13:30 PM PDT 24
Finished Apr 28 02:14:27 PM PDT 24
Peak memory 204404 kb
Host smart-0e6d3d6c-7bff-41ef-8b14-fd8cd4a12eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
9662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.239319662
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1791558191
Short name T289
Test name
Test status
Simulation time 8372700913 ps
CPU time 7.59 seconds
Started Apr 28 02:13:32 PM PDT 24
Finished Apr 28 02:13:40 PM PDT 24
Peak memory 204068 kb
Host smart-65771355-333d-40f7-86f5-e3eef528c987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17915
58191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1791558191
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2285962623
Short name T1141
Test name
Test status
Simulation time 8408013030 ps
CPU time 8.23 seconds
Started Apr 28 02:13:26 PM PDT 24
Finished Apr 28 02:13:35 PM PDT 24
Peak memory 204056 kb
Host smart-d5865352-320f-4ae7-b426-7e23ea3bd69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22859
62623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2285962623
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.367748601
Short name T313
Test name
Test status
Simulation time 8443302214 ps
CPU time 8.61 seconds
Started Apr 28 02:13:27 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 204092 kb
Host smart-9a00d903-c0b8-42b2-9c5c-5bbe1b3d2cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36774
8601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.367748601
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.167661848
Short name T314
Test name
Test status
Simulation time 8389636480 ps
CPU time 9.98 seconds
Started Apr 28 02:13:26 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 204148 kb
Host smart-d877725c-ff01-47ae-9e2f-d89036d8280c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.167661848
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2295319163
Short name T764
Test name
Test status
Simulation time 8449217353 ps
CPU time 8.54 seconds
Started Apr 28 02:13:30 PM PDT 24
Finished Apr 28 02:13:39 PM PDT 24
Peak memory 204124 kb
Host smart-a6f48a7a-9e6d-4729-b5bc-2a702abe6b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22953
19163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2295319163
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3064843801
Short name T790
Test name
Test status
Simulation time 8406036783 ps
CPU time 7.69 seconds
Started Apr 28 02:13:26 PM PDT 24
Finished Apr 28 02:13:34 PM PDT 24
Peak memory 204128 kb
Host smart-98282b0e-d7d6-4c6a-80e9-f5985b298124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
43801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3064843801
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.4136774947
Short name T650
Test name
Test status
Simulation time 8373973555 ps
CPU time 7.59 seconds
Started Apr 28 02:13:32 PM PDT 24
Finished Apr 28 02:13:41 PM PDT 24
Peak memory 204032 kb
Host smart-b50204cd-efc3-45c6-94a8-88e1fd65239c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41367
74947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.4136774947
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.4064926814
Short name T939
Test name
Test status
Simulation time 8462481549 ps
CPU time 7.87 seconds
Started Apr 28 02:13:37 PM PDT 24
Finished Apr 28 02:13:46 PM PDT 24
Peak memory 204120 kb
Host smart-da36de3d-9c42-4861-98f0-6834a049d716
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4064926814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.4064926814
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3985235049
Short name T1059
Test name
Test status
Simulation time 8396123780 ps
CPU time 8.16 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:45 PM PDT 24
Peak memory 204108 kb
Host smart-ade82bcc-634b-4b51-85b1-c5020add718f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3985235049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3985235049
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.1988580248
Short name T782
Test name
Test status
Simulation time 8426029185 ps
CPU time 7.39 seconds
Started Apr 28 02:13:39 PM PDT 24
Finished Apr 28 02:13:47 PM PDT 24
Peak memory 204124 kb
Host smart-651a3486-2615-421b-8f53-ad65de67afe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885
80248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.1988580248
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3182682021
Short name T1019
Test name
Test status
Simulation time 8384883376 ps
CPU time 8.23 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204108 kb
Host smart-e9b381cd-93aa-41db-b0bc-791b0d683369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826
82021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3182682021
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.894099684
Short name T512
Test name
Test status
Simulation time 8372375083 ps
CPU time 9.47 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:46 PM PDT 24
Peak memory 203736 kb
Host smart-1e470a70-7dee-4877-a1a9-aaea12d8e173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89409
9684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.894099684
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1655985713
Short name T392
Test name
Test status
Simulation time 74756096 ps
CPU time 1.37 seconds
Started Apr 28 02:13:35 PM PDT 24
Finished Apr 28 02:13:37 PM PDT 24
Peak memory 203612 kb
Host smart-c492d7e2-d9b0-47cb-ac58-88e95f81c830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
85713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1655985713
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2875606742
Short name T398
Test name
Test status
Simulation time 8431140020 ps
CPU time 7.39 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:44 PM PDT 24
Peak memory 204084 kb
Host smart-a54fb396-fc6e-451b-8167-b934f776a153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28756
06742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2875606742
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1064079558
Short name T189
Test name
Test status
Simulation time 8392656776 ps
CPU time 7.6 seconds
Started Apr 28 02:13:31 PM PDT 24
Finished Apr 28 02:13:39 PM PDT 24
Peak memory 204116 kb
Host smart-84ff3b50-a644-446e-b787-1529affb92f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10640
79558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1064079558
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3295385610
Short name T1261
Test name
Test status
Simulation time 8415215698 ps
CPU time 8.52 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204104 kb
Host smart-6b57652f-e763-4db3-90b9-1bf5d0ec59ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
85610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3295385610
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2024720153
Short name T825
Test name
Test status
Simulation time 8421318880 ps
CPU time 8.62 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:44 PM PDT 24
Peak memory 204132 kb
Host smart-81a56441-7e66-482b-ac78-968d9f8ef859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
20153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2024720153
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3106267681
Short name T351
Test name
Test status
Simulation time 8365194807 ps
CPU time 7.26 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:42 PM PDT 24
Peak memory 204080 kb
Host smart-ae70fb92-c8e8-41da-8e13-bbb19398ad2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
67681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3106267681
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2281628476
Short name T125
Test name
Test status
Simulation time 8445447065 ps
CPU time 9.08 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204108 kb
Host smart-b6cc9a13-bc81-4a40-a29c-9b9abc352d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22816
28476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2281628476
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.256885501
Short name T1305
Test name
Test status
Simulation time 8389682740 ps
CPU time 9.6 seconds
Started Apr 28 02:13:32 PM PDT 24
Finished Apr 28 02:13:42 PM PDT 24
Peak memory 204088 kb
Host smart-08d8cc6c-1a87-4e64-8cb1-fc03d3974a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688
5501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.256885501
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2002991231
Short name T390
Test name
Test status
Simulation time 8419191883 ps
CPU time 8.63 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204100 kb
Host smart-41fba0ea-6598-4da8-9b43-648558096a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20029
91231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2002991231
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1748569135
Short name T787
Test name
Test status
Simulation time 8383043753 ps
CPU time 8.26 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204108 kb
Host smart-7978140d-1ca4-4fa4-b3e7-e6e355936ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17485
69135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1748569135
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3619305431
Short name T1326
Test name
Test status
Simulation time 8394233717 ps
CPU time 7.57 seconds
Started Apr 28 02:13:35 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204112 kb
Host smart-291ede5f-3be6-4f4a-96ba-d1d29d09175f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193
05431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3619305431
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1438413587
Short name T242
Test name
Test status
Simulation time 21110043497 ps
CPU time 42.19 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204424 kb
Host smart-d686a9d2-e16d-4e23-99e8-ddb9c462dc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14384
13587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1438413587
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3269221094
Short name T627
Test name
Test status
Simulation time 8418642391 ps
CPU time 8.19 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204000 kb
Host smart-3652d062-77dd-4095-95b2-3152e1a81247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
21094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3269221094
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3275485391
Short name T136
Test name
Test status
Simulation time 8416766970 ps
CPU time 7.96 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204092 kb
Host smart-e79da018-37fd-4427-9536-e5367223b1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
85391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3275485391
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2289898194
Short name T1123
Test name
Test status
Simulation time 8372147354 ps
CPU time 8.03 seconds
Started Apr 28 02:13:34 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204136 kb
Host smart-791f3ba6-9959-497a-b91f-37f855e7711c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22898
98194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2289898194
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.476804818
Short name T552
Test name
Test status
Simulation time 8394351809 ps
CPU time 8.08 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:43 PM PDT 24
Peak memory 204160 kb
Host smart-d3363d05-2c40-45dc-9333-af8ee81e1b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47680
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.476804818
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2880419680
Short name T601
Test name
Test status
Simulation time 8377537654 ps
CPU time 7.76 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:42 PM PDT 24
Peak memory 204120 kb
Host smart-f6929025-ea15-44e7-9460-c290a254133c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28804
19680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2880419680
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1458461364
Short name T742
Test name
Test status
Simulation time 8433810274 ps
CPU time 8.94 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:45 PM PDT 24
Peak memory 203848 kb
Host smart-76da47c8-1c9f-4abb-93f9-bb5f03dfe199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
61364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1458461364
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2344366712
Short name T875
Test name
Test status
Simulation time 8375590469 ps
CPU time 7.58 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:44 PM PDT 24
Peak memory 204104 kb
Host smart-4b25313d-3d92-4de7-966b-be84695b992f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23443
66712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2344366712
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2140386487
Short name T800
Test name
Test status
Simulation time 8380919504 ps
CPU time 7.74 seconds
Started Apr 28 02:13:33 PM PDT 24
Finished Apr 28 02:13:42 PM PDT 24
Peak memory 204140 kb
Host smart-6973bd13-ba55-46a4-b3d0-939120771925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21403
86487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2140386487
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.384837815
Short name T715
Test name
Test status
Simulation time 8467563072 ps
CPU time 9.71 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:53 PM PDT 24
Peak memory 204128 kb
Host smart-545290dd-a613-4569-89e9-0d8b0fe6e3df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=384837815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.384837815
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.772241093
Short name T776
Test name
Test status
Simulation time 8381440678 ps
CPU time 10.38 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 204056 kb
Host smart-0ba5f6e5-b070-4e90-b226-639d8277d696
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=772241093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.772241093
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.534963598
Short name T1050
Test name
Test status
Simulation time 8468462848 ps
CPU time 8.16 seconds
Started Apr 28 02:13:45 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 204092 kb
Host smart-300dd37c-dcb1-4ed9-a6ac-7fc03531b08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53496
3598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.534963598
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3420603387
Short name T329
Test name
Test status
Simulation time 8410465942 ps
CPU time 8.17 seconds
Started Apr 28 02:13:39 PM PDT 24
Finished Apr 28 02:13:48 PM PDT 24
Peak memory 204136 kb
Host smart-ed28b00f-4ffa-4a78-9282-cefdb3f07c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34206
03387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3420603387
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.3713886450
Short name T1321
Test name
Test status
Simulation time 8380030868 ps
CPU time 7.54 seconds
Started Apr 28 02:13:37 PM PDT 24
Finished Apr 28 02:13:45 PM PDT 24
Peak memory 204140 kb
Host smart-1f172a69-9073-4213-ab6e-ec51ae2f3506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
86450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3713886450
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.119723931
Short name T753
Test name
Test status
Simulation time 221714104 ps
CPU time 2.2 seconds
Started Apr 28 02:13:37 PM PDT 24
Finished Apr 28 02:13:40 PM PDT 24
Peak memory 204148 kb
Host smart-1e60c0b8-8bc8-49ca-b346-55e32cf29741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11972
3931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.119723931
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.442758462
Short name T682
Test name
Test status
Simulation time 8446716238 ps
CPU time 8.19 seconds
Started Apr 28 02:13:49 PM PDT 24
Finished Apr 28 02:13:58 PM PDT 24
Peak memory 204076 kb
Host smart-34d65ed2-7c65-4ccc-a1d0-b6f074b5ccb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44275
8462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.442758462
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2246897764
Short name T568
Test name
Test status
Simulation time 8425473805 ps
CPU time 8.27 seconds
Started Apr 28 02:13:37 PM PDT 24
Finished Apr 28 02:13:46 PM PDT 24
Peak memory 204136 kb
Host smart-6e4de3c5-5a5b-4bfa-8a4c-a3bc32dfee45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
97764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2246897764
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1876091056
Short name T1260
Test name
Test status
Simulation time 8505918623 ps
CPU time 8.4 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:45 PM PDT 24
Peak memory 204088 kb
Host smart-265f1ac8-3a7f-4851-bec1-57e2853613ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18760
91056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1876091056
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.461307492
Short name T795
Test name
Test status
Simulation time 8372655339 ps
CPU time 8.31 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:45 PM PDT 24
Peak memory 204088 kb
Host smart-302ac34d-bfe9-416a-993b-40f544998a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46130
7492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.461307492
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.88723765
Short name T113
Test name
Test status
Simulation time 8443807969 ps
CPU time 10.32 seconds
Started Apr 28 02:13:39 PM PDT 24
Finished Apr 28 02:13:49 PM PDT 24
Peak memory 204116 kb
Host smart-21eff484-0e59-4063-8e73-9b07a5bedf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88723
765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.88723765
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1577971479
Short name T15
Test name
Test status
Simulation time 8451665409 ps
CPU time 8.25 seconds
Started Apr 28 02:13:37 PM PDT 24
Finished Apr 28 02:13:46 PM PDT 24
Peak memory 204032 kb
Host smart-34fd9ba9-333b-40f8-8b26-7b6292f31398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15779
71479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1577971479
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1972554090
Short name T419
Test name
Test status
Simulation time 8401732552 ps
CPU time 8.51 seconds
Started Apr 28 02:13:38 PM PDT 24
Finished Apr 28 02:13:47 PM PDT 24
Peak memory 204100 kb
Host smart-607b7034-04b7-4d92-8790-a44bc9629fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
54090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1972554090
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1890745871
Short name T1374
Test name
Test status
Simulation time 8391173033 ps
CPU time 10.02 seconds
Started Apr 28 02:13:44 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 204020 kb
Host smart-f49a5de4-78c3-4086-9483-de435981895f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18907
45871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1890745871
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1783993878
Short name T1185
Test name
Test status
Simulation time 8381397457 ps
CPU time 7.69 seconds
Started Apr 28 02:13:44 PM PDT 24
Finished Apr 28 02:13:52 PM PDT 24
Peak memory 204152 kb
Host smart-7bef30a6-0160-490c-be92-ab1ab0b86585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17839
93878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1783993878
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.300758940
Short name T610
Test name
Test status
Simulation time 73571687 ps
CPU time 0.7 seconds
Started Apr 28 02:13:45 PM PDT 24
Finished Apr 28 02:13:46 PM PDT 24
Peak memory 203968 kb
Host smart-725785b4-2ba6-4dc7-8443-714e9525fb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30075
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.300758940
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3022605365
Short name T238
Test name
Test status
Simulation time 19663309515 ps
CPU time 43.62 seconds
Started Apr 28 02:13:39 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204368 kb
Host smart-30678791-bded-48c9-951d-c7119ec4ac74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226
05365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3022605365
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2924134383
Short name T481
Test name
Test status
Simulation time 8406192198 ps
CPU time 8.18 seconds
Started Apr 28 02:13:38 PM PDT 24
Finished Apr 28 02:13:47 PM PDT 24
Peak memory 204044 kb
Host smart-0bc6bf62-3054-4572-bf36-1beeeb083d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29241
34383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2924134383
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2156879051
Short name T667
Test name
Test status
Simulation time 8427820103 ps
CPU time 7.88 seconds
Started Apr 28 02:13:37 PM PDT 24
Finished Apr 28 02:13:46 PM PDT 24
Peak memory 204140 kb
Host smart-a22c3fcc-6584-4e55-bdd2-b395b0290614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
79051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2156879051
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.798584024
Short name T812
Test name
Test status
Simulation time 8394436021 ps
CPU time 8.23 seconds
Started Apr 28 02:13:38 PM PDT 24
Finished Apr 28 02:13:47 PM PDT 24
Peak memory 204004 kb
Host smart-6537c831-3e60-49c5-9ce5-ce36842b81bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79858
4024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.798584024
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3863557337
Short name T167
Test name
Test status
Simulation time 8393445489 ps
CPU time 9.73 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 204028 kb
Host smart-844e66dd-af01-4202-b17a-9749fb72d3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38635
57337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3863557337
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.4216442958
Short name T1311
Test name
Test status
Simulation time 8370366351 ps
CPU time 8.11 seconds
Started Apr 28 02:13:45 PM PDT 24
Finished Apr 28 02:13:53 PM PDT 24
Peak memory 204112 kb
Host smart-ab072f8c-9dfe-4521-8ebe-73071e4db1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42164
42958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.4216442958
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.472703803
Short name T544
Test name
Test status
Simulation time 8462152011 ps
CPU time 8.56 seconds
Started Apr 28 02:13:36 PM PDT 24
Finished Apr 28 02:13:45 PM PDT 24
Peak memory 204140 kb
Host smart-522562cd-6b7a-4eb9-8c4d-4051cfab8c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47270
3803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.472703803
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.725016068
Short name T867
Test name
Test status
Simulation time 8381043806 ps
CPU time 7.47 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:51 PM PDT 24
Peak memory 204132 kb
Host smart-dbb5864a-706a-4b09-b46a-a13bb4702edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72501
6068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.725016068
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2626089202
Short name T1129
Test name
Test status
Simulation time 8401863517 ps
CPU time 7.87 seconds
Started Apr 28 02:13:44 PM PDT 24
Finished Apr 28 02:13:52 PM PDT 24
Peak memory 204104 kb
Host smart-453bd762-189d-4d5f-a9b4-5f02cc77dc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
89202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2626089202
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.884421569
Short name T1300
Test name
Test status
Simulation time 8468364298 ps
CPU time 10.27 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204084 kb
Host smart-d1fa5b10-d141-4633-9dc3-5ac0f056be19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=884421569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.884421569
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2024474691
Short name T874
Test name
Test status
Simulation time 8375071450 ps
CPU time 9.81 seconds
Started Apr 28 02:13:49 PM PDT 24
Finished Apr 28 02:14:00 PM PDT 24
Peak memory 204120 kb
Host smart-559002c1-f2ea-49c5-b2b1-7c204d36b6e6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2024474691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2024474691
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.1725662467
Short name T542
Test name
Test status
Simulation time 8448893474 ps
CPU time 7.32 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:56 PM PDT 24
Peak memory 204080 kb
Host smart-66d3a614-74ec-4dee-8dbb-7876344506ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
62467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.1725662467
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1305198670
Short name T646
Test name
Test status
Simulation time 8378979638 ps
CPU time 8.64 seconds
Started Apr 28 02:13:42 PM PDT 24
Finished Apr 28 02:13:51 PM PDT 24
Peak memory 204148 kb
Host smart-f2845ae4-2036-4119-b395-1f16555a4fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13051
98670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1305198670
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.2185566834
Short name T521
Test name
Test status
Simulation time 8380794801 ps
CPU time 9.82 seconds
Started Apr 28 02:13:45 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 204160 kb
Host smart-22bd4002-5632-47df-b8fd-cc983a0fe0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21855
66834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2185566834
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2762193735
Short name T462
Test name
Test status
Simulation time 52648196 ps
CPU time 1.15 seconds
Started Apr 28 02:13:42 PM PDT 24
Finished Apr 28 02:13:44 PM PDT 24
Peak memory 204240 kb
Host smart-038c6fbd-f929-4885-b18f-bee630a7fa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27621
93735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2762193735
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2087355975
Short name T444
Test name
Test status
Simulation time 8386886350 ps
CPU time 8.31 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204136 kb
Host smart-33141dae-3282-4e28-934b-7dd593a53c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20873
55975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2087355975
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1567367962
Short name T517
Test name
Test status
Simulation time 8384752501 ps
CPU time 7.86 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204100 kb
Host smart-cbee1b60-ad2d-4a54-998f-bb9138074109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
67962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1567367962
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3677422126
Short name T892
Test name
Test status
Simulation time 8459054966 ps
CPU time 8.27 seconds
Started Apr 28 02:13:44 PM PDT 24
Finished Apr 28 02:13:53 PM PDT 24
Peak memory 204164 kb
Host smart-755adfb1-91e7-46ed-9783-d5c2bbd10d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36774
22126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3677422126
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1986553314
Short name T1320
Test name
Test status
Simulation time 8447562329 ps
CPU time 7.74 seconds
Started Apr 28 02:13:41 PM PDT 24
Finished Apr 28 02:13:50 PM PDT 24
Peak memory 204116 kb
Host smart-fd445272-11cb-4c3c-865f-9d96b7d73598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19865
53314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1986553314
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1503171086
Short name T807
Test name
Test status
Simulation time 8371850897 ps
CPU time 8.24 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:52 PM PDT 24
Peak memory 204144 kb
Host smart-47d46a64-93a5-41ba-8f12-b585624c7353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15031
71086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1503171086
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2593951925
Short name T1359
Test name
Test status
Simulation time 8429128064 ps
CPU time 7.95 seconds
Started Apr 28 02:13:46 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 204120 kb
Host smart-bb886634-b1c4-4ba3-93d6-ff8cc0678329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939
51925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2593951925
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2844183331
Short name T1205
Test name
Test status
Simulation time 8432548525 ps
CPU time 8.27 seconds
Started Apr 28 02:13:46 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 203996 kb
Host smart-0ff8e66b-c413-4291-a662-7dc3ca4fbc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28441
83331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2844183331
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.27490851
Short name T509
Test name
Test status
Simulation time 8390398155 ps
CPU time 7.98 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204072 kb
Host smart-448091ca-95a0-4fb8-98b9-710de32af331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.27490851
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2605235227
Short name T859
Test name
Test status
Simulation time 8396050043 ps
CPU time 7.94 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:57 PM PDT 24
Peak memory 204104 kb
Host smart-9a2da92d-3499-4998-a2e1-28716eb8b928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26052
35227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2605235227
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2918557452
Short name T934
Test name
Test status
Simulation time 8374366195 ps
CPU time 7.51 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:56 PM PDT 24
Peak memory 204140 kb
Host smart-e241d68e-0da9-485b-ad54-ba314391932e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29185
57452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2918557452
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.752028733
Short name T1171
Test name
Test status
Simulation time 57065080 ps
CPU time 0.68 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:49 PM PDT 24
Peak memory 203988 kb
Host smart-260363df-e84c-43b2-acfd-6f180fdebd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75202
8733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.752028733
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.385046026
Short name T13
Test name
Test status
Simulation time 14872850605 ps
CPU time 27.22 seconds
Started Apr 28 02:13:47 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204404 kb
Host smart-9332daa2-8072-4bb0-8a35-07a942d56fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38504
6026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.385046026
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2024899171
Short name T866
Test name
Test status
Simulation time 8384327243 ps
CPU time 9.73 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 203996 kb
Host smart-fb7a48d8-6a3a-41d9-93ff-b2ae39fbe581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20248
99171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2024899171
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1933247078
Short name T1283
Test name
Test status
Simulation time 8401462281 ps
CPU time 7.61 seconds
Started Apr 28 02:13:44 PM PDT 24
Finished Apr 28 02:13:52 PM PDT 24
Peak memory 204120 kb
Host smart-52cab978-a7e5-4140-aa31-1bb43008f517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19332
47078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1933247078
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3156612407
Short name T1188
Test name
Test status
Simulation time 8388463385 ps
CPU time 8.36 seconds
Started Apr 28 02:13:47 PM PDT 24
Finished Apr 28 02:13:56 PM PDT 24
Peak memory 204112 kb
Host smart-d061be06-d44b-4a9a-a498-0a4294b4e58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566
12407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3156612407
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1852392806
Short name T171
Test name
Test status
Simulation time 8387531891 ps
CPU time 9.13 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:57 PM PDT 24
Peak memory 204132 kb
Host smart-d77c07c4-a90e-450f-9a7d-aaae09bf9120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18523
92806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1852392806
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1398869248
Short name T1098
Test name
Test status
Simulation time 8369413196 ps
CPU time 8.35 seconds
Started Apr 28 02:13:49 PM PDT 24
Finished Apr 28 02:13:58 PM PDT 24
Peak memory 204080 kb
Host smart-f69beb33-c4b8-46be-b63e-370585857944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13988
69248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1398869248
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4285488621
Short name T492
Test name
Test status
Simulation time 8474497260 ps
CPU time 9.5 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:53 PM PDT 24
Peak memory 204124 kb
Host smart-d56364ce-de94-4774-83ab-a27c8b789d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
88621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4285488621
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.287033429
Short name T876
Test name
Test status
Simulation time 8422738498 ps
CPU time 8.25 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:52 PM PDT 24
Peak memory 204088 kb
Host smart-5eec9740-eeef-4049-80a4-be73a2717a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28703
3429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.287033429
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.963865229
Short name T1329
Test name
Test status
Simulation time 8396333006 ps
CPU time 8.46 seconds
Started Apr 28 02:13:43 PM PDT 24
Finished Apr 28 02:13:52 PM PDT 24
Peak memory 204120 kb
Host smart-8d28d518-ee5f-4dee-b959-ef51d43f2320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96386
5229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.963865229
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.1172955226
Short name T935
Test name
Test status
Simulation time 8470839813 ps
CPU time 8 seconds
Started Apr 28 02:13:54 PM PDT 24
Finished Apr 28 02:14:03 PM PDT 24
Peak memory 203992 kb
Host smart-6b6b2555-4b98-41b5-bba3-2f6ac34b68fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1172955226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.1172955226
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.774580441
Short name T1292
Test name
Test status
Simulation time 8377440163 ps
CPU time 7.66 seconds
Started Apr 28 02:13:53 PM PDT 24
Finished Apr 28 02:14:01 PM PDT 24
Peak memory 204120 kb
Host smart-575e2456-c885-4f22-ab7b-8178c33eb922
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=774580441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.774580441
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.2271306329
Short name T1083
Test name
Test status
Simulation time 8422990704 ps
CPU time 7.76 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204028 kb
Host smart-76640295-5495-444f-a1ef-f5adbe99ab41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
06329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.2271306329
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2925865181
Short name T1066
Test name
Test status
Simulation time 8387041453 ps
CPU time 8.07 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:56 PM PDT 24
Peak memory 203996 kb
Host smart-58903aad-99bc-41ea-a7e4-1935a416076e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29258
65181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2925865181
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.4122419640
Short name T1291
Test name
Test status
Simulation time 8378279537 ps
CPU time 7.71 seconds
Started Apr 28 02:13:46 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 204060 kb
Host smart-cc82276b-548c-467d-ac6b-d9f37d36bced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41224
19640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.4122419640
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4140156608
Short name T1045
Test name
Test status
Simulation time 64169890 ps
CPU time 1.26 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204136 kb
Host smart-d4157880-b506-420e-909c-7ed08df9f6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
56608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4140156608
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1174382368
Short name T609
Test name
Test status
Simulation time 8420744414 ps
CPU time 7.91 seconds
Started Apr 28 02:13:51 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204068 kb
Host smart-45b1c33d-b2c7-457e-9764-bc6791ef4b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11743
82368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1174382368
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3907206396
Short name T872
Test name
Test status
Simulation time 8388101887 ps
CPU time 8.32 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204084 kb
Host smart-a0189d04-19bf-40d1-be87-88d3a1097c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
06396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3907206396
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2144468805
Short name T1214
Test name
Test status
Simulation time 8497660678 ps
CPU time 8.66 seconds
Started Apr 28 02:13:49 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204164 kb
Host smart-e35ed2c2-1f2f-4c99-9bf8-b0911b1cb99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21444
68805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2144468805
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1645902669
Short name T456
Test name
Test status
Simulation time 8416882023 ps
CPU time 9.13 seconds
Started Apr 28 02:13:47 PM PDT 24
Finished Apr 28 02:13:57 PM PDT 24
Peak memory 204164 kb
Host smart-e8d7ffe2-b0ee-45e4-b08d-ee4aae4e6a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
02669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1645902669
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.803120906
Short name T987
Test name
Test status
Simulation time 8369472204 ps
CPU time 8.02 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204076 kb
Host smart-16df8193-d011-42f6-a5ea-21709042ccfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80312
0906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.803120906
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2905994484
Short name T127
Test name
Test status
Simulation time 8418512365 ps
CPU time 7.76 seconds
Started Apr 28 02:13:49 PM PDT 24
Finished Apr 28 02:13:57 PM PDT 24
Peak memory 204068 kb
Host smart-9f4979d0-a996-49d2-9da4-138879d8a0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29059
94484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2905994484
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3052840497
Short name T3
Test name
Test status
Simulation time 8411303720 ps
CPU time 8.68 seconds
Started Apr 28 02:13:51 PM PDT 24
Finished Apr 28 02:14:00 PM PDT 24
Peak memory 204040 kb
Host smart-b8ae0e15-ae07-405e-98d6-70a4bf6c031d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30528
40497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3052840497
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2489076773
Short name T32
Test name
Test status
Simulation time 8409053059 ps
CPU time 7.76 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:13:58 PM PDT 24
Peak memory 204148 kb
Host smart-67a81f42-5608-414b-ac27-9d11c5bc5575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890
76773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2489076773
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1353797867
Short name T1146
Test name
Test status
Simulation time 8403084134 ps
CPU time 7.96 seconds
Started Apr 28 02:13:53 PM PDT 24
Finished Apr 28 02:14:02 PM PDT 24
Peak memory 204124 kb
Host smart-27690852-ce30-4d98-8786-7f7d4088d6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
97867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1353797867
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4264258731
Short name T854
Test name
Test status
Simulation time 8406085444 ps
CPU time 9.26 seconds
Started Apr 28 02:13:46 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 204096 kb
Host smart-93818666-52f3-470a-9f6e-e61f9d9025c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
58731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4264258731
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3309553279
Short name T706
Test name
Test status
Simulation time 36027595 ps
CPU time 0.63 seconds
Started Apr 28 02:13:53 PM PDT 24
Finished Apr 28 02:13:54 PM PDT 24
Peak memory 203932 kb
Host smart-59d0adb0-4fdc-445a-b34b-c29caa97b389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095
53279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3309553279
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2025396673
Short name T658
Test name
Test status
Simulation time 27198190362 ps
CPU time 52.32 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204332 kb
Host smart-20883809-1962-4469-a03d-7dbc04c59979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253
96673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2025396673
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.4214435100
Short name T1381
Test name
Test status
Simulation time 8450523123 ps
CPU time 8.46 seconds
Started Apr 28 02:13:47 PM PDT 24
Finished Apr 28 02:13:56 PM PDT 24
Peak memory 204140 kb
Host smart-d6bbb5c5-879d-44b0-beb6-e511c52d2373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144
35100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.4214435100
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2309206437
Short name T477
Test name
Test status
Simulation time 8402862048 ps
CPU time 8.31 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:14:05 PM PDT 24
Peak memory 204076 kb
Host smart-8845bcc9-e70c-4973-894c-6d79c17635e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23092
06437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2309206437
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2743363994
Short name T649
Test name
Test status
Simulation time 8375618132 ps
CPU time 8.2 seconds
Started Apr 28 02:13:55 PM PDT 24
Finished Apr 28 02:14:04 PM PDT 24
Peak memory 204028 kb
Host smart-3ccaf0b1-1228-4d75-ad24-18aa804c27af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
63994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2743363994
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2900115111
Short name T498
Test name
Test status
Simulation time 8362257347 ps
CPU time 8.28 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:13:58 PM PDT 24
Peak memory 204160 kb
Host smart-f527686e-81a7-400f-a5d0-50311a03511b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29001
15111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2900115111
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3169914506
Short name T1038
Test name
Test status
Simulation time 8491998909 ps
CPU time 7.47 seconds
Started Apr 28 02:13:45 PM PDT 24
Finished Apr 28 02:13:53 PM PDT 24
Peak memory 204060 kb
Host smart-15ceea44-0fa7-4ac1-b246-e64d03fa0abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31699
14506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3169914506
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1677226497
Short name T299
Test name
Test status
Simulation time 8425679386 ps
CPU time 8.05 seconds
Started Apr 28 02:13:48 PM PDT 24
Finished Apr 28 02:13:56 PM PDT 24
Peak memory 204068 kb
Host smart-9828b583-dfc3-4359-a7d7-e957c24e90cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16772
26497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1677226497
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1888550137
Short name T1164
Test name
Test status
Simulation time 8376625614 ps
CPU time 8.16 seconds
Started Apr 28 02:13:51 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204032 kb
Host smart-cadd3662-6dbd-4e87-a1cd-bb6740fd7a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
50137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1888550137
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2375363513
Short name T917
Test name
Test status
Simulation time 8460651865 ps
CPU time 7.44 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:14:04 PM PDT 24
Peak memory 204140 kb
Host smart-9b130eb9-df03-4d94-ad5b-c3a5885e75a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2375363513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2375363513
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.436082798
Short name T921
Test name
Test status
Simulation time 8378577166 ps
CPU time 7.96 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204004 kb
Host smart-1f1310f2-6f82-48b3-9b42-a26b6e15641d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=436082798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.436082798
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.3774055625
Short name T547
Test name
Test status
Simulation time 8384245612 ps
CPU time 7.79 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204148 kb
Host smart-7842f8cd-bee8-4b29-9ec9-d4664cf2b96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37740
55625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.3774055625
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.195307084
Short name T397
Test name
Test status
Simulation time 8374620730 ps
CPU time 8.41 seconds
Started Apr 28 02:13:52 PM PDT 24
Finished Apr 28 02:14:01 PM PDT 24
Peak memory 204112 kb
Host smart-7491747c-c9db-4d33-999c-2370f8e0148e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19530
7084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.195307084
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.3346761818
Short name T944
Test name
Test status
Simulation time 8375541561 ps
CPU time 8.31 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 203572 kb
Host smart-d3d1ff09-2e4f-411c-b77e-43968cd948fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33467
61818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3346761818
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.620324476
Short name T54
Test name
Test status
Simulation time 73866066 ps
CPU time 1.8 seconds
Started Apr 28 02:13:53 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 204288 kb
Host smart-311fe6a1-992f-4906-b811-f64f3ec8f810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62032
4476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.620324476
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2330633667
Short name T154
Test name
Test status
Simulation time 8403394549 ps
CPU time 8 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204112 kb
Host smart-e385617b-02f8-4864-9a5f-d7e2d5888d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23306
33667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2330633667
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.570905505
Short name T1049
Test name
Test status
Simulation time 8372893745 ps
CPU time 8.27 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:08 PM PDT 24
Peak memory 203984 kb
Host smart-686f8f14-7b74-44dd-b49d-6486d7eb7035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57090
5505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.570905505
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2881208203
Short name T510
Test name
Test status
Simulation time 8439673214 ps
CPU time 7.87 seconds
Started Apr 28 02:13:52 PM PDT 24
Finished Apr 28 02:14:01 PM PDT 24
Peak memory 204148 kb
Host smart-a616edf2-aa45-4df5-8e12-cb975020c40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28812
08203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2881208203
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3860281919
Short name T1295
Test name
Test status
Simulation time 8416712945 ps
CPU time 8.21 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204028 kb
Host smart-3a7d291a-888a-499a-84fc-6ef6a1917ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
81919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3860281919
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1458774230
Short name T779
Test name
Test status
Simulation time 8397630518 ps
CPU time 7.8 seconds
Started Apr 28 02:13:54 PM PDT 24
Finished Apr 28 02:14:02 PM PDT 24
Peak memory 204140 kb
Host smart-db2ca9c0-824a-4545-a1a9-98b4e03ed9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587
74230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1458774230
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1845335216
Short name T1280
Test name
Test status
Simulation time 8416456152 ps
CPU time 8.93 seconds
Started Apr 28 02:13:53 PM PDT 24
Finished Apr 28 02:14:03 PM PDT 24
Peak memory 204148 kb
Host smart-ae466d76-2589-45f4-bb90-b752f99d2903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
35216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1845335216
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3015441302
Short name T840
Test name
Test status
Simulation time 8402321390 ps
CPU time 8.29 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204040 kb
Host smart-dbc5ae96-75e2-4057-829d-6d5a7e1f0227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30154
41302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3015441302
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1114486705
Short name T751
Test name
Test status
Simulation time 8416024491 ps
CPU time 10.18 seconds
Started Apr 28 02:13:50 PM PDT 24
Finished Apr 28 02:14:01 PM PDT 24
Peak memory 204136 kb
Host smart-2d50f67d-23be-41bc-a888-dfbd2dfd96da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
86705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1114486705
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2390941253
Short name T436
Test name
Test status
Simulation time 8368816854 ps
CPU time 7.88 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204096 kb
Host smart-76741c94-558a-4f86-b033-e8b2d237140c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
41253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2390941253
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3438001807
Short name T1039
Test name
Test status
Simulation time 77370661 ps
CPU time 0.71 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 203952 kb
Host smart-e38bd8be-3df9-467f-abef-41b188a6409f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34380
01807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3438001807
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4164266962
Short name T900
Test name
Test status
Simulation time 22440694599 ps
CPU time 47.19 seconds
Started Apr 28 02:13:54 PM PDT 24
Finished Apr 28 02:14:42 PM PDT 24
Peak memory 204264 kb
Host smart-138d6ca7-be25-415a-9a84-a448000fb253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41642
66962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4164266962
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2544156249
Short name T16
Test name
Test status
Simulation time 8413547873 ps
CPU time 7.82 seconds
Started Apr 28 02:13:55 PM PDT 24
Finished Apr 28 02:14:03 PM PDT 24
Peak memory 204124 kb
Host smart-92a6b1a6-b48a-47bf-abf6-f0cef8c409c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25441
56249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2544156249
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2359526195
Short name T726
Test name
Test status
Simulation time 8397281126 ps
CPU time 7.67 seconds
Started Apr 28 02:13:54 PM PDT 24
Finished Apr 28 02:14:02 PM PDT 24
Peak memory 204108 kb
Host smart-22b9d4d9-86b8-4f06-9963-f588dcf88853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23595
26195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2359526195
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2356023028
Short name T1016
Test name
Test status
Simulation time 8404134289 ps
CPU time 8.14 seconds
Started Apr 28 02:13:52 PM PDT 24
Finished Apr 28 02:14:00 PM PDT 24
Peak memory 204116 kb
Host smart-bbf1d164-7a08-467e-a2d0-657f21a2bf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
23028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2356023028
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3257843086
Short name T159
Test name
Test status
Simulation time 8388036379 ps
CPU time 8.28 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:14:05 PM PDT 24
Peak memory 204120 kb
Host smart-d4c8e29d-4cd3-48b7-9d0d-383473929b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32578
43086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3257843086
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2507096976
Short name T630
Test name
Test status
Simulation time 8368019063 ps
CPU time 8.09 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204112 kb
Host smart-fc185406-633e-4200-a388-776909c64720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25070
96976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2507096976
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1663924971
Short name T149
Test name
Test status
Simulation time 8437446839 ps
CPU time 9.28 seconds
Started Apr 28 02:13:52 PM PDT 24
Finished Apr 28 02:14:02 PM PDT 24
Peak memory 204004 kb
Host smart-b2b91422-4015-4178-a935-74121e79b0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
24971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1663924971
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.442708703
Short name T443
Test name
Test status
Simulation time 8375262260 ps
CPU time 8.17 seconds
Started Apr 28 02:14:01 PM PDT 24
Finished Apr 28 02:14:10 PM PDT 24
Peak memory 204112 kb
Host smart-bcc580e3-f587-4673-beb6-2ed3d3afdb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44270
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.442708703
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1982210013
Short name T687
Test name
Test status
Simulation time 8406753615 ps
CPU time 9.56 seconds
Started Apr 28 02:13:54 PM PDT 24
Finished Apr 28 02:14:04 PM PDT 24
Peak memory 204076 kb
Host smart-b83a2724-3fc4-4d9b-97b4-c386e857b3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
10013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1982210013
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.4004030024
Short name T716
Test name
Test status
Simulation time 8500459359 ps
CPU time 9.16 seconds
Started Apr 28 02:14:02 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 204080 kb
Host smart-d20c0394-91ff-4699-b360-93856a9e5cc7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4004030024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.4004030024
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.107135207
Short name T1272
Test name
Test status
Simulation time 8395394329 ps
CPU time 7.7 seconds
Started Apr 28 02:14:03 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 204140 kb
Host smart-ae4a30bf-3947-45f8-880e-e813271d614c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=107135207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.107135207
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.4223432268
Short name T683
Test name
Test status
Simulation time 8392886385 ps
CPU time 7.44 seconds
Started Apr 28 02:14:04 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 204136 kb
Host smart-7db096aa-9acd-40de-8928-f42c2a20082a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42234
32268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.4223432268
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2804340197
Short name T590
Test name
Test status
Simulation time 8385334335 ps
CPU time 8.06 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204124 kb
Host smart-1070c462-2927-4e7d-8dd8-858983940612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043
40197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2804340197
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.98496813
Short name T971
Test name
Test status
Simulation time 8375665303 ps
CPU time 8.82 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204060 kb
Host smart-16e318e7-93d5-43f9-89fa-fc04de9a58b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98496
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.98496813
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2243725791
Short name T746
Test name
Test status
Simulation time 97181611 ps
CPU time 1.1 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204176 kb
Host smart-64c1f2bc-cc94-458b-9fab-121ee0119726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
25791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2243725791
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3979194532
Short name T739
Test name
Test status
Simulation time 8441158687 ps
CPU time 7.52 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204084 kb
Host smart-4b4464d1-3518-4d81-afcd-4aba201278e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
94532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3979194532
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1610765635
Short name T74
Test name
Test status
Simulation time 8370940170 ps
CPU time 7.62 seconds
Started Apr 28 02:13:55 PM PDT 24
Finished Apr 28 02:14:04 PM PDT 24
Peak memory 204116 kb
Host smart-ef6a8092-d2fa-4e3d-ac90-d95269236c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16107
65635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1610765635
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3874973325
Short name T826
Test name
Test status
Simulation time 8401657540 ps
CPU time 9.84 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:11 PM PDT 24
Peak memory 204080 kb
Host smart-6bedf847-84c5-44c7-8598-5b85e20e6c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
73325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3874973325
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1580509708
Short name T293
Test name
Test status
Simulation time 8424197839 ps
CPU time 7.8 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 203996 kb
Host smart-cf36914f-9d2b-446f-8b3e-8740c3fb1996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15805
09708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1580509708
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2414109612
Short name T589
Test name
Test status
Simulation time 8386551005 ps
CPU time 7.56 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204000 kb
Host smart-1ea5142a-f2e8-4654-a387-a65f376e1026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24141
09612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2414109612
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.4154020472
Short name T460
Test name
Test status
Simulation time 8388227661 ps
CPU time 8.04 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204092 kb
Host smart-ccbfac67-3f3b-467b-ab1a-2e21c88ad77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540
20472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.4154020472
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.366405823
Short name T235
Test name
Test status
Simulation time 8375624147 ps
CPU time 7.48 seconds
Started Apr 28 02:13:59 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204096 kb
Host smart-fda4c7d7-b533-4197-93cf-8b63a55eb124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36640
5823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.366405823
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.4116080165
Short name T1198
Test name
Test status
Simulation time 8407419935 ps
CPU time 9.08 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204116 kb
Host smart-356556c0-5132-4e69-9add-5c09d841d2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41160
80165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.4116080165
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1606832564
Short name T1254
Test name
Test status
Simulation time 8369326506 ps
CPU time 7.79 seconds
Started Apr 28 02:13:59 PM PDT 24
Finished Apr 28 02:14:08 PM PDT 24
Peak memory 204128 kb
Host smart-96a06f68-34c2-409e-b922-b15ab9a7032c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16068
32564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1606832564
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2735033289
Short name T1053
Test name
Test status
Simulation time 39183928 ps
CPU time 0.63 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:13:59 PM PDT 24
Peak memory 204012 kb
Host smart-9efce02c-2f6d-4242-9548-f7a4c2a1600f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27350
33289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2735033289
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1332730164
Short name T1290
Test name
Test status
Simulation time 17602246996 ps
CPU time 32.41 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204392 kb
Host smart-3dcb17c7-5ffb-42ef-b93f-8ed6a52dbe1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13327
30164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1332730164
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3215433383
Short name T775
Test name
Test status
Simulation time 8434242193 ps
CPU time 7.75 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 204108 kb
Host smart-666c8834-50a2-44c0-a525-ed9e4f9b0d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
33383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3215433383
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1454336234
Short name T147
Test name
Test status
Simulation time 8400519025 ps
CPU time 9.85 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:11 PM PDT 24
Peak memory 204080 kb
Host smart-5e1ba199-fd3c-4b15-bbed-d90c8cec4680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14543
36234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1454336234
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1891612931
Short name T438
Test name
Test status
Simulation time 8433440811 ps
CPU time 7.56 seconds
Started Apr 28 02:13:58 PM PDT 24
Finished Apr 28 02:14:07 PM PDT 24
Peak memory 203996 kb
Host smart-3016f72a-b4cd-47a4-b991-b49b1082cf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
12931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1891612931
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2641342861
Short name T774
Test name
Test status
Simulation time 8379175142 ps
CPU time 8.41 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204132 kb
Host smart-eb803ad2-329e-4190-a52b-1a23e4d4ec49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
42861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2641342861
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.872481478
Short name T832
Test name
Test status
Simulation time 8372588769 ps
CPU time 8.4 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:09 PM PDT 24
Peak memory 204116 kb
Host smart-71c6050f-4d17-4d4b-b83a-c983e988f171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87248
1478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.872481478
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1536356667
Short name T87
Test name
Test status
Simulation time 8460787769 ps
CPU time 10.28 seconds
Started Apr 28 02:14:00 PM PDT 24
Finished Apr 28 02:14:11 PM PDT 24
Peak memory 204136 kb
Host smart-dfeab8f2-c198-4dc4-abab-d580ba789e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15363
56667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1536356667
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1135403134
Short name T1186
Test name
Test status
Simulation time 8417004162 ps
CPU time 8.21 seconds
Started Apr 28 02:13:57 PM PDT 24
Finished Apr 28 02:14:06 PM PDT 24
Peak memory 204068 kb
Host smart-6b57f1df-f5ee-40f4-baa6-e238a6bbbd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11354
03134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1135403134
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2015095492
Short name T526
Test name
Test status
Simulation time 8401531574 ps
CPU time 7.96 seconds
Started Apr 28 02:13:56 PM PDT 24
Finished Apr 28 02:14:05 PM PDT 24
Peak memory 203980 kb
Host smart-3d6bcffe-33f7-42c4-9b1a-c249a17c738c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150
95492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2015095492
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.2961625479
Short name T1342
Test name
Test status
Simulation time 8472170772 ps
CPU time 7.92 seconds
Started Apr 28 02:11:22 PM PDT 24
Finished Apr 28 02:11:30 PM PDT 24
Peak memory 204052 kb
Host smart-11d896b5-f367-45ba-9c05-2d7a8e2cb496
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2961625479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.2961625479
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2755347745
Short name T781
Test name
Test status
Simulation time 8388547595 ps
CPU time 7.67 seconds
Started Apr 28 02:11:21 PM PDT 24
Finished Apr 28 02:11:29 PM PDT 24
Peak memory 204124 kb
Host smart-6ad6883d-1cd2-43e4-8620-c5cb5cbb9b37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2755347745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2755347745
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.1003790440
Short name T1026
Test name
Test status
Simulation time 8427151686 ps
CPU time 8.05 seconds
Started Apr 28 02:11:20 PM PDT 24
Finished Apr 28 02:11:28 PM PDT 24
Peak memory 204160 kb
Host smart-94f64f3c-af0d-420f-b86c-0fe91bd21862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10037
90440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.1003790440
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3633470214
Short name T1190
Test name
Test status
Simulation time 8398168124 ps
CPU time 7.88 seconds
Started Apr 28 02:11:17 PM PDT 24
Finished Apr 28 02:11:25 PM PDT 24
Peak memory 204140 kb
Host smart-0522a7b8-7b3f-4724-a350-9a6e2a759eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36334
70214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3633470214
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.60871795
Short name T657
Test name
Test status
Simulation time 8374482160 ps
CPU time 7.86 seconds
Started Apr 28 02:11:16 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204072 kb
Host smart-21f90572-bc34-4b8e-97db-0cccc47a6b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60871
795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.60871795
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.432042566
Short name T838
Test name
Test status
Simulation time 151812867 ps
CPU time 1.36 seconds
Started Apr 28 02:11:14 PM PDT 24
Finished Apr 28 02:11:16 PM PDT 24
Peak memory 204204 kb
Host smart-bcf6a3cf-751a-45db-ab95-7812b8958161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43204
2566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.432042566
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.99284273
Short name T925
Test name
Test status
Simulation time 8455762672 ps
CPU time 8.84 seconds
Started Apr 28 02:11:23 PM PDT 24
Finished Apr 28 02:11:33 PM PDT 24
Peak memory 204116 kb
Host smart-0d80a8d6-0107-4351-8d9a-f2712563909f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99284
273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.99284273
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.26082205
Short name T193
Test name
Test status
Simulation time 8364850171 ps
CPU time 9.02 seconds
Started Apr 28 02:11:20 PM PDT 24
Finished Apr 28 02:11:30 PM PDT 24
Peak memory 204072 kb
Host smart-4f4a5963-bd0f-4b03-919e-4a219d6b40e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26082
205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.26082205
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.89164061
Short name T1276
Test name
Test status
Simulation time 8423423349 ps
CPU time 8.03 seconds
Started Apr 28 02:11:17 PM PDT 24
Finished Apr 28 02:11:26 PM PDT 24
Peak memory 204056 kb
Host smart-b392089d-1c66-46c5-b3aa-d9b0639c84e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89164
061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.89164061
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2076965288
Short name T473
Test name
Test status
Simulation time 8451470477 ps
CPU time 7.62 seconds
Started Apr 28 02:11:16 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204140 kb
Host smart-6ae552d3-20c7-47a4-8545-ece4b04d4301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20769
65288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2076965288
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2945384289
Short name T1192
Test name
Test status
Simulation time 8392175039 ps
CPU time 8.5 seconds
Started Apr 28 02:11:15 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204064 kb
Host smart-15a25195-8979-419c-86d0-3ad3e256bb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
84289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2945384289
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3417118930
Short name T126
Test name
Test status
Simulation time 8425173901 ps
CPU time 9.81 seconds
Started Apr 28 02:11:15 PM PDT 24
Finished Apr 28 02:11:25 PM PDT 24
Peak memory 203972 kb
Host smart-c7e44bb9-256f-4822-870a-be0534f43c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
18930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3417118930
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3506274666
Short name T643
Test name
Test status
Simulation time 8401013209 ps
CPU time 8.48 seconds
Started Apr 28 02:11:15 PM PDT 24
Finished Apr 28 02:11:24 PM PDT 24
Peak memory 204124 kb
Host smart-60fb1b37-d7e2-490d-a168-cdd5532bc078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35062
74666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3506274666
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.4173448126
Short name T1281
Test name
Test status
Simulation time 8375210210 ps
CPU time 8.9 seconds
Started Apr 28 02:11:14 PM PDT 24
Finished Apr 28 02:11:23 PM PDT 24
Peak memory 204084 kb
Host smart-d44e532d-579c-4963-8f3e-acd17c682e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
48126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.4173448126
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.402989391
Short name T1298
Test name
Test status
Simulation time 8407384041 ps
CPU time 7.71 seconds
Started Apr 28 02:11:19 PM PDT 24
Finished Apr 28 02:11:28 PM PDT 24
Peak memory 204100 kb
Host smart-6fc71d67-7261-4cc9-a760-a008fa922e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298
9391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.402989391
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2513370499
Short name T9
Test name
Test status
Simulation time 8442105355 ps
CPU time 7.83 seconds
Started Apr 28 02:11:22 PM PDT 24
Finished Apr 28 02:11:30 PM PDT 24
Peak memory 204112 kb
Host smart-11c90bf8-2705-4f46-a45e-db57e4db5022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25133
70499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2513370499
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.32345794
Short name T1173
Test name
Test status
Simulation time 41436634 ps
CPU time 0.64 seconds
Started Apr 28 02:11:22 PM PDT 24
Finished Apr 28 02:11:23 PM PDT 24
Peak memory 203920 kb
Host smart-1884b592-2358-4195-b5c9-03c4f6f75a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32345
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.32345794
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1000088115
Short name T891
Test name
Test status
Simulation time 20830128795 ps
CPU time 36.62 seconds
Started Apr 28 02:11:17 PM PDT 24
Finished Apr 28 02:11:54 PM PDT 24
Peak memory 204388 kb
Host smart-6f3157c4-e043-4dd3-b0be-e00e2ffec222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10000
88115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1000088115
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1612982835
Short name T449
Test name
Test status
Simulation time 8403903548 ps
CPU time 9.35 seconds
Started Apr 28 02:11:18 PM PDT 24
Finished Apr 28 02:11:28 PM PDT 24
Peak memory 204096 kb
Host smart-1fe1a58a-6eb3-4604-9608-051b2b9efb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129
82835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1612982835
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3903040344
Short name T321
Test name
Test status
Simulation time 8389197398 ps
CPU time 8.68 seconds
Started Apr 28 02:11:16 PM PDT 24
Finished Apr 28 02:11:25 PM PDT 24
Peak memory 204116 kb
Host smart-24b846b4-6852-46b8-92b9-8068fbab9687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
40344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3903040344
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3166899849
Short name T619
Test name
Test status
Simulation time 8398927367 ps
CPU time 7.98 seconds
Started Apr 28 02:11:17 PM PDT 24
Finished Apr 28 02:11:25 PM PDT 24
Peak memory 204100 kb
Host smart-7c53e1d9-fe6b-4bff-b18d-c30e72f732a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
99849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3166899849
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.598191861
Short name T60
Test name
Test status
Simulation time 409502397 ps
CPU time 1.24 seconds
Started Apr 28 02:11:19 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 221368 kb
Host smart-d34486aa-d8a4-429d-ab17-d03f40bcec42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=598191861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.598191861
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2240749881
Short name T1266
Test name
Test status
Simulation time 8377147637 ps
CPU time 7.62 seconds
Started Apr 28 02:11:20 PM PDT 24
Finished Apr 28 02:11:28 PM PDT 24
Peak memory 204064 kb
Host smart-bf312abf-4b59-4037-9def-7f22f9eac0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
49881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2240749881
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.498150050
Short name T442
Test name
Test status
Simulation time 8416497475 ps
CPU time 8.22 seconds
Started Apr 28 02:11:22 PM PDT 24
Finished Apr 28 02:11:31 PM PDT 24
Peak memory 204028 kb
Host smart-b5085809-bc38-4e3f-9381-3d73fdff062e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49815
0050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.498150050
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.936394390
Short name T161
Test name
Test status
Simulation time 8459344464 ps
CPU time 8.06 seconds
Started Apr 28 02:11:17 PM PDT 24
Finished Apr 28 02:11:25 PM PDT 24
Peak memory 204136 kb
Host smart-6e0f46de-d330-4828-8fec-5e7499c9f5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93639
4390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.936394390
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1829450865
Short name T869
Test name
Test status
Simulation time 8405620001 ps
CPU time 7.48 seconds
Started Apr 28 02:11:19 PM PDT 24
Finished Apr 28 02:11:27 PM PDT 24
Peak memory 204128 kb
Host smart-f3f3f1dd-fb45-4d1a-a373-9d063c33422c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
50865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1829450865
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3607371801
Short name T1052
Test name
Test status
Simulation time 8405599035 ps
CPU time 9.89 seconds
Started Apr 28 02:11:23 PM PDT 24
Finished Apr 28 02:11:33 PM PDT 24
Peak memory 204116 kb
Host smart-fb96fc84-a434-4a87-8191-af301488c84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
71801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3607371801
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2659553778
Short name T1242
Test name
Test status
Simulation time 8517347081 ps
CPU time 9.18 seconds
Started Apr 28 02:14:03 PM PDT 24
Finished Apr 28 02:14:13 PM PDT 24
Peak memory 204104 kb
Host smart-a813f74f-f4be-436d-ab49-053d5e3df30b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2659553778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2659553778
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.1453973667
Short name T1376
Test name
Test status
Simulation time 8379016039 ps
CPU time 7.52 seconds
Started Apr 28 02:14:02 PM PDT 24
Finished Apr 28 02:14:10 PM PDT 24
Peak memory 204104 kb
Host smart-3cfd5603-c08e-4118-b92c-e4cf93ff7b67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1453973667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.1453973667
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3157530960
Short name T38
Test name
Test status
Simulation time 8442094960 ps
CPU time 7.71 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:14 PM PDT 24
Peak memory 204164 kb
Host smart-b0ca2813-03a2-42d5-aa97-44ee1efc3a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31575
30960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3157530960
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.101454788
Short name T304
Test name
Test status
Simulation time 8382649389 ps
CPU time 8.05 seconds
Started Apr 28 02:14:05 PM PDT 24
Finished Apr 28 02:14:14 PM PDT 24
Peak memory 204164 kb
Host smart-2d346aee-d626-44bc-9b50-61a0af935a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
4788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.101454788
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.2987253795
Short name T612
Test name
Test status
Simulation time 8381659297 ps
CPU time 9.38 seconds
Started Apr 28 02:14:04 PM PDT 24
Finished Apr 28 02:14:14 PM PDT 24
Peak memory 204076 kb
Host smart-be553d04-aefd-4503-975e-216997c10111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29872
53795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2987253795
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3319732969
Short name T698
Test name
Test status
Simulation time 8425606374 ps
CPU time 7.61 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204036 kb
Host smart-0269aa6b-d45e-4489-a0fa-3408af73fe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
32969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3319732969
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2518503276
Short name T727
Test name
Test status
Simulation time 8370473552 ps
CPU time 8.66 seconds
Started Apr 28 02:14:03 PM PDT 24
Finished Apr 28 02:14:13 PM PDT 24
Peak memory 204020 kb
Host smart-e4002147-47a2-4cb4-815c-2e301f5989a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25185
03276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2518503276
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.809313407
Short name T378
Test name
Test status
Simulation time 8429521233 ps
CPU time 7.68 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:14 PM PDT 24
Peak memory 204116 kb
Host smart-b472c0a0-7691-447c-83d2-e2a3970b831e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80931
3407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.809313407
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2183279569
Short name T1036
Test name
Test status
Simulation time 8415131111 ps
CPU time 8.85 seconds
Started Apr 28 02:14:05 PM PDT 24
Finished Apr 28 02:14:14 PM PDT 24
Peak memory 204144 kb
Host smart-64b42eee-b9cc-4c70-911b-9cddba5f58bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
79569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2183279569
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1172026554
Short name T813
Test name
Test status
Simulation time 8376610104 ps
CPU time 8.82 seconds
Started Apr 28 02:14:02 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 204132 kb
Host smart-9623c9ab-7451-44b2-92b0-245aa0f88d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720
26554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1172026554
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2799703998
Short name T128
Test name
Test status
Simulation time 8392473494 ps
CPU time 8.19 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204120 kb
Host smart-c6a27375-5949-4cfe-a66a-e377eae11596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27997
03998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2799703998
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3501540193
Short name T376
Test name
Test status
Simulation time 8406797363 ps
CPU time 7.99 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204112 kb
Host smart-d2fc64ec-6b83-4878-8c1b-bccfabedf92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
40193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3501540193
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1091070832
Short name T1304
Test name
Test status
Simulation time 8381824079 ps
CPU time 7.45 seconds
Started Apr 28 02:14:05 PM PDT 24
Finished Apr 28 02:14:14 PM PDT 24
Peak memory 204148 kb
Host smart-04ff8411-e1e8-4fc6-bddf-fca50bb544bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10910
70832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1091070832
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2066689787
Short name T174
Test name
Test status
Simulation time 8397306132 ps
CPU time 7.35 seconds
Started Apr 28 02:14:08 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204024 kb
Host smart-316ddee4-23bd-4e6e-9aaf-9e7bc208cf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
89787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2066689787
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.606289581
Short name T1347
Test name
Test status
Simulation time 8368364084 ps
CPU time 8.69 seconds
Started Apr 28 02:14:02 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 204088 kb
Host smart-930e120d-0708-4e1c-98a6-5fbc916d0e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60628
9581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.606289581
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2706297976
Short name T967
Test name
Test status
Simulation time 57506297 ps
CPU time 0.66 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:16 PM PDT 24
Peak memory 203908 kb
Host smart-095eff50-c6f4-4305-84c5-6b8b83aa41ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
97976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2706297976
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3512313490
Short name T659
Test name
Test status
Simulation time 25075918598 ps
CPU time 54.35 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204392 kb
Host smart-ffdecb37-69b6-43fe-85e9-db37e56a3a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35123
13490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3512313490
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3384830939
Short name T1027
Test name
Test status
Simulation time 8394171206 ps
CPU time 7.95 seconds
Started Apr 28 02:14:05 PM PDT 24
Finished Apr 28 02:14:13 PM PDT 24
Peak memory 204168 kb
Host smart-207e170b-ab5d-4c98-b296-c80610306ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33848
30939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3384830939
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1841861352
Short name T1168
Test name
Test status
Simulation time 8467891520 ps
CPU time 8.44 seconds
Started Apr 28 02:14:03 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 204100 kb
Host smart-9a5b1eaa-6595-4fb5-bfbb-12fb5ac0bd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
61352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1841861352
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3680835437
Short name T946
Test name
Test status
Simulation time 8374449249 ps
CPU time 8.6 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204032 kb
Host smart-01c4837b-c7a3-47f3-860b-f0d5a0c3c649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36808
35437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3680835437
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2320479781
Short name T437
Test name
Test status
Simulation time 8454402306 ps
CPU time 7.76 seconds
Started Apr 28 02:14:03 PM PDT 24
Finished Apr 28 02:14:11 PM PDT 24
Peak memory 204112 kb
Host smart-e279534b-6e3c-474a-acd5-19c69ffb474e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23204
79781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2320479781
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1720097337
Short name T347
Test name
Test status
Simulation time 8380139055 ps
CPU time 8.09 seconds
Started Apr 28 02:14:02 PM PDT 24
Finished Apr 28 02:14:11 PM PDT 24
Peak memory 204108 kb
Host smart-193720f2-bef5-49d6-b557-94d61c480d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17200
97337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1720097337
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.589869890
Short name T773
Test name
Test status
Simulation time 8432288473 ps
CPU time 8.44 seconds
Started Apr 28 02:14:05 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204164 kb
Host smart-393aa614-533b-41fd-b29a-89fa1cfb817f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58986
9890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.589869890
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.534819531
Short name T730
Test name
Test status
Simulation time 8387040469 ps
CPU time 9.87 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:17 PM PDT 24
Peak memory 204112 kb
Host smart-19d8b7eb-6ea9-4c8a-8077-92d9c03ccd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53481
9531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.534819531
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.4292546970
Short name T379
Test name
Test status
Simulation time 8418996566 ps
CPU time 7.39 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204032 kb
Host smart-bcfb6b8e-835f-4389-bb7d-3ce9b885089b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925
46970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.4292546970
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.22516135
Short name T1294
Test name
Test status
Simulation time 8483883798 ps
CPU time 7.89 seconds
Started Apr 28 02:14:08 PM PDT 24
Finished Apr 28 02:14:16 PM PDT 24
Peak memory 204048 kb
Host smart-f2769706-eeaa-4a52-ab88-b4f7927f9c1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=22516135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.22516135
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.1229563805
Short name T371
Test name
Test status
Simulation time 8396935608 ps
CPU time 7.63 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204128 kb
Host smart-1fea6dbe-a51c-4013-9341-b3fdb72ec04d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1229563805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.1229563805
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.398674331
Short name T932
Test name
Test status
Simulation time 8394182740 ps
CPU time 8.2 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204116 kb
Host smart-ed8c0614-8d63-4f37-b20d-77988006d395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39867
4331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.398674331
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3469327421
Short name T718
Test name
Test status
Simulation time 8378455429 ps
CPU time 9.7 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:20 PM PDT 24
Peak memory 204148 kb
Host smart-f01733b8-84f2-44c0-bd7c-81f77530fa31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34693
27421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3469327421
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.1425280157
Short name T373
Test name
Test status
Simulation time 8388971065 ps
CPU time 7.41 seconds
Started Apr 28 02:14:07 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204096 kb
Host smart-48c82782-442c-4b16-9a1e-fb0b5ce17070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14252
80157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1425280157
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3207826704
Short name T780
Test name
Test status
Simulation time 241059767 ps
CPU time 1.87 seconds
Started Apr 28 02:14:08 PM PDT 24
Finished Apr 28 02:14:11 PM PDT 24
Peak memory 204236 kb
Host smart-fbc3b822-df2d-470c-b1ba-10a26482a1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32078
26704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3207826704
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4111725964
Short name T749
Test name
Test status
Simulation time 8471707105 ps
CPU time 8.15 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:19 PM PDT 24
Peak memory 204036 kb
Host smart-24619e01-9cc1-4c18-a3c9-da72b8a20cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
25964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4111725964
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.517633892
Short name T1079
Test name
Test status
Simulation time 8371866638 ps
CPU time 8 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204112 kb
Host smart-90b09997-a112-46ef-bac4-669a29a62ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51763
3892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.517633892
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.467900013
Short name T132
Test name
Test status
Simulation time 8421004270 ps
CPU time 7.92 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:19 PM PDT 24
Peak memory 204068 kb
Host smart-b57b9203-bc69-4a88-ade7-dbd940c9ddd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46790
0013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.467900013
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1737971725
Short name T614
Test name
Test status
Simulation time 8417006515 ps
CPU time 8.68 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204100 kb
Host smart-3d44c242-cfed-4d58-ac4e-ff168f184655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17379
71725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1737971725
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.187557991
Short name T320
Test name
Test status
Simulation time 8367819710 ps
CPU time 7.73 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204060 kb
Host smart-30ecd312-cddd-4511-afee-a5aef194b41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18755
7991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.187557991
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.987894221
Short name T117
Test name
Test status
Simulation time 8446422375 ps
CPU time 8.08 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:19 PM PDT 24
Peak memory 204056 kb
Host smart-4dd7e6af-bb0e-46bc-89f2-77598d818403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98789
4221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.987894221
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2408327423
Short name T1179
Test name
Test status
Simulation time 8388691005 ps
CPU time 9.38 seconds
Started Apr 28 02:14:08 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204112 kb
Host smart-d4758583-8cb6-4d47-9443-6e14a97720a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
27423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2408327423
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3318468925
Short name T1163
Test name
Test status
Simulation time 8402720474 ps
CPU time 8.35 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:14:22 PM PDT 24
Peak memory 204108 kb
Host smart-31a8e673-521f-47c9-8bc0-45b6e40bceb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33184
68925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3318468925
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.421618099
Short name T1196
Test name
Test status
Simulation time 8382270655 ps
CPU time 9.07 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:20 PM PDT 24
Peak memory 204132 kb
Host smart-8e3ff0a7-f582-40fb-8583-994bf2cb9543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42161
8099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.421618099
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1738850819
Short name T402
Test name
Test status
Simulation time 8367369832 ps
CPU time 9.7 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204088 kb
Host smart-eda6ba51-a329-45b0-8e64-2316ff78d933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17388
50819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1738850819
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.265592399
Short name T644
Test name
Test status
Simulation time 31948343 ps
CPU time 0.65 seconds
Started Apr 28 02:14:11 PM PDT 24
Finished Apr 28 02:14:12 PM PDT 24
Peak memory 203868 kb
Host smart-a8e8346f-24d6-4adb-a721-f2c9c6a9cebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26559
2399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.265592399
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1219607034
Short name T714
Test name
Test status
Simulation time 24344371131 ps
CPU time 47.18 seconds
Started Apr 28 02:14:12 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 204384 kb
Host smart-f8355778-9ee7-4923-a785-b0acca1b1a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12196
07034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1219607034
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4264980660
Short name T471
Test name
Test status
Simulation time 8386154610 ps
CPU time 7.43 seconds
Started Apr 28 02:14:11 PM PDT 24
Finished Apr 28 02:14:19 PM PDT 24
Peak memory 204112 kb
Host smart-b9b2d2b0-4969-4b00-95bb-0bb93b6ceadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42649
80660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4264980660
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3645400539
Short name T690
Test name
Test status
Simulation time 8469184521 ps
CPU time 7.54 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204172 kb
Host smart-5bbd9011-2b48-475e-813a-3efa4e23cabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
00539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3645400539
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.1552375765
Short name T937
Test name
Test status
Simulation time 8381324607 ps
CPU time 8.2 seconds
Started Apr 28 02:14:08 PM PDT 24
Finished Apr 28 02:14:17 PM PDT 24
Peak memory 204084 kb
Host smart-02b6624f-491a-4a10-b04e-9429da34e4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
75765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.1552375765
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3327701537
Short name T845
Test name
Test status
Simulation time 8408478419 ps
CPU time 8.13 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204132 kb
Host smart-e2a76710-e714-4aef-8060-5eaa5f8c8ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
01537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3327701537
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3995594951
Short name T625
Test name
Test status
Simulation time 8367815208 ps
CPU time 7.71 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204032 kb
Host smart-fb1b1cf3-63ae-4a8f-ac1c-053c2dbd04ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
94951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3995594951
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.231312326
Short name T908
Test name
Test status
Simulation time 8469287598 ps
CPU time 9.7 seconds
Started Apr 28 02:14:06 PM PDT 24
Finished Apr 28 02:14:16 PM PDT 24
Peak memory 204092 kb
Host smart-5ad466cd-c35c-4b0a-9962-4c4425778c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23131
2326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.231312326
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2919465983
Short name T1177
Test name
Test status
Simulation time 8404515605 ps
CPU time 10.09 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204068 kb
Host smart-5342fa27-20b8-441d-b332-1ba5794827f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29194
65983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2919465983
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1807742712
Short name T285
Test name
Test status
Simulation time 8378900609 ps
CPU time 7.61 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:17 PM PDT 24
Peak memory 204032 kb
Host smart-42a1167a-148a-438c-afb5-b351e3099d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18077
42712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1807742712
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.3820165403
Short name T564
Test name
Test status
Simulation time 8550010551 ps
CPU time 7.92 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204140 kb
Host smart-3348cea3-d4e1-4204-97bc-0136c8740369
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3820165403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.3820165403
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.120700721
Short name T1275
Test name
Test status
Simulation time 8383683915 ps
CPU time 7.72 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:28 PM PDT 24
Peak memory 204108 kb
Host smart-b7278311-48cb-4945-96d1-5b5e1f9adb45
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=120700721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.120700721
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.3987782026
Short name T1126
Test name
Test status
Simulation time 8403787123 ps
CPU time 9.99 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204164 kb
Host smart-f348afdf-3283-4f69-8784-38d9d859e8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
82026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.3987782026
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2981639078
Short name T357
Test name
Test status
Simulation time 8376871398 ps
CPU time 8.14 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:14:22 PM PDT 24
Peak memory 204060 kb
Host smart-2bd52431-ca98-4eb8-bfa4-0873e0b41a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29816
39078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2981639078
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.3885259824
Short name T1324
Test name
Test status
Simulation time 8437291787 ps
CPU time 8.19 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204128 kb
Host smart-852c631e-b055-4b58-948d-2fcc64e84784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
59824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3885259824
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3252873618
Short name T1377
Test name
Test status
Simulation time 79905999 ps
CPU time 1.94 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:14:16 PM PDT 24
Peak memory 204140 kb
Host smart-cdbbb81c-08c8-4cd8-82ff-b3b83ab5e5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32528
73618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3252873618
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3069393104
Short name T1371
Test name
Test status
Simulation time 8451562471 ps
CPU time 8.25 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204124 kb
Host smart-f6740386-f388-47c7-8a6e-465cb53489d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30693
93104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3069393104
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2938907811
Short name T187
Test name
Test status
Simulation time 8365764986 ps
CPU time 8.37 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204120 kb
Host smart-4d279379-87ea-45a5-bb93-aa283f178e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
07811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2938907811
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2896209812
Short name T1346
Test name
Test status
Simulation time 8464493428 ps
CPU time 9.05 seconds
Started Apr 28 02:14:12 PM PDT 24
Finished Apr 28 02:14:22 PM PDT 24
Peak memory 204084 kb
Host smart-3b2e2538-d7e6-428c-a347-6f01898d5c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28962
09812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2896209812
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3642299966
Short name T675
Test name
Test status
Simulation time 8423478604 ps
CPU time 9.22 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:20 PM PDT 24
Peak memory 204112 kb
Host smart-a744630c-be68-4b92-86bb-6dfb4f3d8bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
99966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3642299966
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3864179007
Short name T1101
Test name
Test status
Simulation time 8377505044 ps
CPU time 8.19 seconds
Started Apr 28 02:14:10 PM PDT 24
Finished Apr 28 02:14:18 PM PDT 24
Peak memory 204112 kb
Host smart-822323c7-c512-4e3d-a37e-d695e355e804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38641
79007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3864179007
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3948641105
Short name T1325
Test name
Test status
Simulation time 8430359320 ps
CPU time 7.66 seconds
Started Apr 28 02:14:09 PM PDT 24
Finished Apr 28 02:14:17 PM PDT 24
Peak memory 204120 kb
Host smart-db904f2c-0994-4a9d-b564-3da253b2ff8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39486
41105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3948641105
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3396422567
Short name T676
Test name
Test status
Simulation time 8397057734 ps
CPU time 7.43 seconds
Started Apr 28 02:14:16 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204136 kb
Host smart-bf201116-f5bf-48c1-867b-300f5e915982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33964
22567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3396422567
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.150464751
Short name T897
Test name
Test status
Simulation time 8431952944 ps
CPU time 7.67 seconds
Started Apr 28 02:14:16 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204112 kb
Host smart-b767a0c9-4b18-44fb-a15d-e2c695b28080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
4751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.150464751
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3492903326
Short name T1354
Test name
Test status
Simulation time 8369813100 ps
CPU time 9.34 seconds
Started Apr 28 02:14:19 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204156 kb
Host smart-cdd76e5e-3b02-4a2c-84e0-1e99d07d2446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
03326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3492903326
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3372391851
Short name T567
Test name
Test status
Simulation time 46607940 ps
CPU time 0.64 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:15 PM PDT 24
Peak memory 204024 kb
Host smart-d1dcf35b-fd2f-4039-9d20-09ac8fb6044f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33723
91851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3372391851
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1768464852
Short name T931
Test name
Test status
Simulation time 21954510969 ps
CPU time 41.03 seconds
Started Apr 28 02:14:16 PM PDT 24
Finished Apr 28 02:14:58 PM PDT 24
Peak memory 204408 kb
Host smart-e148d451-123e-4c1d-867c-34f24b6aade9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
64852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1768464852
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1813019053
Short name T888
Test name
Test status
Simulation time 8401730712 ps
CPU time 8.27 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204096 kb
Host smart-46996630-b5cd-4576-b8b4-c6474aa4aea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
19053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1813019053
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.728705240
Short name T815
Test name
Test status
Simulation time 8408201481 ps
CPU time 8 seconds
Started Apr 28 02:14:16 PM PDT 24
Finished Apr 28 02:14:25 PM PDT 24
Peak memory 204108 kb
Host smart-063bbcf8-258d-47be-99f4-59463bbddd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72870
5240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.728705240
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3272212783
Short name T864
Test name
Test status
Simulation time 8404041816 ps
CPU time 7.67 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204100 kb
Host smart-10b580bc-723f-488d-a187-e65bcf4afb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32722
12783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3272212783
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1850182638
Short name T709
Test name
Test status
Simulation time 8383343023 ps
CPU time 9.52 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:25 PM PDT 24
Peak memory 204068 kb
Host smart-04b1f949-600d-4575-a970-b04e29cfd714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
82638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1850182638
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2858711060
Short name T1368
Test name
Test status
Simulation time 8364149636 ps
CPU time 8.93 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204076 kb
Host smart-f03638cf-f082-4b2a-b8e6-d0350397a9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28587
11060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2858711060
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2836915018
Short name T146
Test name
Test status
Simulation time 8464425299 ps
CPU time 9.18 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204080 kb
Host smart-0c331e37-7b89-49c7-a2dc-98142d741114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
15018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2836915018
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1855504481
Short name T1191
Test name
Test status
Simulation time 8378190768 ps
CPU time 8.04 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204000 kb
Host smart-cb10c40d-e4f5-4abf-9378-f34319a16409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555
04481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1855504481
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.299158753
Short name T1062
Test name
Test status
Simulation time 8402026084 ps
CPU time 7.94 seconds
Started Apr 28 02:14:12 PM PDT 24
Finished Apr 28 02:14:21 PM PDT 24
Peak memory 204120 kb
Host smart-add9051e-4baf-4ce8-be65-6293ad5025a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
8753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.299158753
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3199525024
Short name T47
Test name
Test status
Simulation time 8462072692 ps
CPU time 7.71 seconds
Started Apr 28 02:14:23 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204152 kb
Host smart-f3fde053-0a10-4d45-a223-c869b4a4f2d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3199525024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3199525024
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.1746805659
Short name T689
Test name
Test status
Simulation time 8379270069 ps
CPU time 7.87 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204088 kb
Host smart-d068d997-b6b1-40e5-b23a-5e39d44c1260
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1746805659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.1746805659
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.488395987
Short name T1084
Test name
Test status
Simulation time 8459882770 ps
CPU time 9.16 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204076 kb
Host smart-bbfeb221-8d39-4fbc-bb19-5aba237e1cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48839
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.488395987
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3073001616
Short name T629
Test name
Test status
Simulation time 8373157797 ps
CPU time 7.36 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 204088 kb
Host smart-c1ac2594-ffd6-471a-9d72-549b9b35d794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30730
01616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3073001616
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.2705094309
Short name T886
Test name
Test status
Simulation time 8377201339 ps
CPU time 7.87 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204052 kb
Host smart-f7fd121f-f831-4361-8fd5-3a94b63406c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27050
94309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2705094309
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1272475324
Short name T1328
Test name
Test status
Simulation time 208678830 ps
CPU time 1.8 seconds
Started Apr 28 02:14:19 PM PDT 24
Finished Apr 28 02:14:22 PM PDT 24
Peak memory 204232 kb
Host smart-f2f93cd7-0e0f-47ad-a740-9436c98210be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
75324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1272475324
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2011791060
Short name T797
Test name
Test status
Simulation time 8458079599 ps
CPU time 7.58 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204104 kb
Host smart-0257a61d-0820-4b65-94a1-131b88d946d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
91060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2011791060
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.559409792
Short name T5
Test name
Test status
Simulation time 8367026702 ps
CPU time 7.44 seconds
Started Apr 28 02:14:19 PM PDT 24
Finished Apr 28 02:14:27 PM PDT 24
Peak memory 204080 kb
Host smart-c797d6d1-0f07-4ebe-bce5-61805ff32608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55940
9792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.559409792
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.633238567
Short name T653
Test name
Test status
Simulation time 8423784755 ps
CPU time 9.59 seconds
Started Apr 28 02:14:16 PM PDT 24
Finished Apr 28 02:14:26 PM PDT 24
Peak memory 204100 kb
Host smart-c38263ec-e200-4576-ab48-fb2b1a564243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63323
8567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.633238567
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3327127497
Short name T538
Test name
Test status
Simulation time 8414393592 ps
CPU time 10.19 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:26 PM PDT 24
Peak memory 204096 kb
Host smart-03540ee4-4713-4c07-b9cc-87214cc27bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33271
27497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3327127497
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.29891955
Short name T434
Test name
Test status
Simulation time 8384312403 ps
CPU time 7.81 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204080 kb
Host smart-d5990ffd-7532-492c-a0dc-d5b13f5fced4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.29891955
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3523422796
Short name T120
Test name
Test status
Simulation time 8408860039 ps
CPU time 10.03 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:26 PM PDT 24
Peak memory 204060 kb
Host smart-a7bd23ff-e779-4a90-a620-06ab5a427781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35234
22796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3523422796
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2293153756
Short name T1028
Test name
Test status
Simulation time 8384393535 ps
CPU time 7.93 seconds
Started Apr 28 02:14:14 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 203996 kb
Host smart-16977b79-d8ab-4ce1-83e4-e756af4d7d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22931
53756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2293153756
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2681757348
Short name T312
Test name
Test status
Simulation time 8379191730 ps
CPU time 8.32 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204096 kb
Host smart-a507b45e-0672-4247-83dc-360ba66de377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26817
57348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2681757348
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1398010491
Short name T685
Test name
Test status
Simulation time 8401278454 ps
CPU time 8.75 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204072 kb
Host smart-1844ec31-46a2-4de5-b31b-e236c3455dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13980
10491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1398010491
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3154213392
Short name T1246
Test name
Test status
Simulation time 8389063306 ps
CPU time 8.52 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204140 kb
Host smart-5cbea23d-d947-4b4c-ac58-e7b0450e9ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
13392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3154213392
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2084571467
Short name T1271
Test name
Test status
Simulation time 81913276 ps
CPU time 0.71 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:23 PM PDT 24
Peak memory 203956 kb
Host smart-42bcecf2-0fcc-4d38-a49b-fc5405bf932d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845
71467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2084571467
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3310377591
Short name T1270
Test name
Test status
Simulation time 29476434290 ps
CPU time 57.09 seconds
Started Apr 28 02:14:13 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204352 kb
Host smart-a3d00fed-ce72-41e7-b950-9fab9abfba9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33103
77591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3310377591
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3231877779
Short name T429
Test name
Test status
Simulation time 8380577515 ps
CPU time 9.63 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:26 PM PDT 24
Peak memory 204076 kb
Host smart-cb7b8307-7038-4720-b1df-b3a77d501621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318
77779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3231877779
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3096947306
Short name T315
Test name
Test status
Simulation time 8445191073 ps
CPU time 7.52 seconds
Started Apr 28 02:14:25 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204156 kb
Host smart-cb5b61af-bc96-4f36-8af5-a08f4e2bdc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
47306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3096947306
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3726134659
Short name T213
Test name
Test status
Simulation time 8374862502 ps
CPU time 7.67 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:35 PM PDT 24
Peak memory 204080 kb
Host smart-9ccf5456-522b-4216-8f3e-89101e684ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37261
34659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3726134659
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.557249695
Short name T165
Test name
Test status
Simulation time 8415528610 ps
CPU time 7.73 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204028 kb
Host smart-ac035d2b-6d87-49d4-b57a-d5fbc257ccea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55724
9695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.557249695
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3716190043
Short name T325
Test name
Test status
Simulation time 8376223282 ps
CPU time 7.59 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204120 kb
Host smart-823ce0f0-c880-41ea-8888-8ff16d4160d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161
90043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3716190043
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2458394565
Short name T860
Test name
Test status
Simulation time 8446656924 ps
CPU time 7.87 seconds
Started Apr 28 02:14:15 PM PDT 24
Finished Apr 28 02:14:24 PM PDT 24
Peak memory 204100 kb
Host smart-48d40194-5992-4810-bfee-712c21a64ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24583
94565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2458394565
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.481048371
Short name T666
Test name
Test status
Simulation time 8405040246 ps
CPU time 7.96 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204080 kb
Host smart-cb0a99e1-15ea-4056-81e9-cfc5ab309b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48104
8371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.481048371
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1472442559
Short name T1241
Test name
Test status
Simulation time 8395220576 ps
CPU time 7.84 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204068 kb
Host smart-6f562a7a-b972-40c1-b714-fabab43d9e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14724
42559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1472442559
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.351532249
Short name T814
Test name
Test status
Simulation time 8479593202 ps
CPU time 9.24 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204136 kb
Host smart-32b5283c-920b-4d87-9e1e-263b87278f99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=351532249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.351532249
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3531510002
Short name T969
Test name
Test status
Simulation time 8378831931 ps
CPU time 7.89 seconds
Started Apr 28 02:14:26 PM PDT 24
Finished Apr 28 02:14:34 PM PDT 24
Peak memory 204152 kb
Host smart-1f1b5d8d-d774-4e05-a779-1ea5b2e679f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3531510002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3531510002
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.2535333040
Short name T316
Test name
Test status
Simulation time 8459442114 ps
CPU time 8.11 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204136 kb
Host smart-978df12c-8efc-4c98-acaf-1a79cb25e506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
33040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.2535333040
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.418784132
Short name T83
Test name
Test status
Simulation time 8378401351 ps
CPU time 8.47 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204068 kb
Host smart-2e083877-7983-4be4-85f9-79fb363608ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41878
4132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.418784132
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.2008247581
Short name T1169
Test name
Test status
Simulation time 8390998652 ps
CPU time 8.17 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204140 kb
Host smart-46653a91-b92e-4bb7-94ef-0a737f2080be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082
47581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2008247581
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2357110556
Short name T360
Test name
Test status
Simulation time 272033318 ps
CPU time 2.46 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:25 PM PDT 24
Peak memory 204236 kb
Host smart-bc895229-68c1-4a72-be2b-836e38492936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23571
10556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2357110556
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.72884491
Short name T604
Test name
Test status
Simulation time 8411073051 ps
CPU time 8.05 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204092 kb
Host smart-6b262769-bb6c-4d69-87e1-7666a25cdc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72884
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.72884491
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3188844409
Short name T1158
Test name
Test status
Simulation time 8368035649 ps
CPU time 8.31 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204128 kb
Host smart-7573978e-82f3-45a2-b07b-3f2911205ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
44409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3188844409
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.266253073
Short name T871
Test name
Test status
Simulation time 8467692055 ps
CPU time 8.02 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204120 kb
Host smart-6eaa9f57-fdce-4593-af2c-41d26b0c36a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26625
3073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.266253073
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.683026125
Short name T406
Test name
Test status
Simulation time 8421206594 ps
CPU time 8.36 seconds
Started Apr 28 02:14:23 PM PDT 24
Finished Apr 28 02:14:32 PM PDT 24
Peak memory 204148 kb
Host smart-5c32e5ce-78f9-4eaf-866a-50563e0a8d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68302
6125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.683026125
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3194356496
Short name T611
Test name
Test status
Simulation time 8373344169 ps
CPU time 8.25 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204120 kb
Host smart-d1c888fd-9eb7-46e7-ace8-0c6f97828501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31943
56496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3194356496
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2094667142
Short name T115
Test name
Test status
Simulation time 8410827299 ps
CPU time 8.15 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204008 kb
Host smart-b445b490-a748-400b-b982-a02c705e63ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
67142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2094667142
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2626881316
Short name T506
Test name
Test status
Simulation time 8380126588 ps
CPU time 8.19 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204128 kb
Host smart-436e668d-1c31-4611-965d-01b870d25008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26268
81316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2626881316
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1691093553
Short name T1293
Test name
Test status
Simulation time 8399415873 ps
CPU time 10.29 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204112 kb
Host smart-80d263d7-13ec-4e79-816e-d45583b3f129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
93553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1691093553
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1491746861
Short name T771
Test name
Test status
Simulation time 8389335737 ps
CPU time 7.71 seconds
Started Apr 28 02:14:19 PM PDT 24
Finished Apr 28 02:14:27 PM PDT 24
Peak memory 204116 kb
Host smart-67eb2a84-b3b0-4605-8797-563b1d1f4d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14917
46861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1491746861
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3664338014
Short name T78
Test name
Test status
Simulation time 8372663464 ps
CPU time 9.28 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:34 PM PDT 24
Peak memory 204148 kb
Host smart-29cf1b1f-f3cf-4b7a-b3be-1165e64cb75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
38014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3664338014
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3347330703
Short name T34
Test name
Test status
Simulation time 88908407 ps
CPU time 0.72 seconds
Started Apr 28 02:14:26 PM PDT 24
Finished Apr 28 02:14:28 PM PDT 24
Peak memory 203976 kb
Host smart-604ef4e4-f5da-433b-bd3c-85516411fec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
30703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3347330703
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3464361610
Short name T91
Test name
Test status
Simulation time 24314885481 ps
CPU time 47.45 seconds
Started Apr 28 02:14:25 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204436 kb
Host smart-df01cb78-cdaa-4ecc-81b3-64623d4b50a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
61610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3464361610
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3867800048
Short name T669
Test name
Test status
Simulation time 8461807920 ps
CPU time 8.71 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:31 PM PDT 24
Peak memory 204108 kb
Host smart-1bd7b9d6-0147-4c45-a9e1-108c34d55576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678
00048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3867800048
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1536269562
Short name T141
Test name
Test status
Simulation time 8449981179 ps
CPU time 7.51 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204104 kb
Host smart-6b9a6b9a-6a1f-4e89-9508-f493c5165f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
69562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1536269562
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.78210497
Short name T1218
Test name
Test status
Simulation time 8377499420 ps
CPU time 7.87 seconds
Started Apr 28 02:14:20 PM PDT 24
Finished Apr 28 02:14:28 PM PDT 24
Peak memory 204068 kb
Host smart-483e5074-b4c4-4f2c-93e4-1b919f266c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78210
497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.78210497
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3667439794
Short name T162
Test name
Test status
Simulation time 8383099476 ps
CPU time 7.25 seconds
Started Apr 28 02:14:22 PM PDT 24
Finished Apr 28 02:14:29 PM PDT 24
Peak memory 204136 kb
Host smart-64655014-f122-4ae3-8df8-5f909626917f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
39794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3667439794
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1806716149
Short name T499
Test name
Test status
Simulation time 8370463919 ps
CPU time 7.91 seconds
Started Apr 28 02:14:25 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204136 kb
Host smart-da342bcd-9755-4569-b900-bff8b7533297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067
16149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1806716149
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2996482716
Short name T1174
Test name
Test status
Simulation time 8434390017 ps
CPU time 8.51 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:34 PM PDT 24
Peak memory 204156 kb
Host smart-11f760f6-d497-48df-ab84-bb7c5dd3150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29964
82716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2996482716
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2811957334
Short name T317
Test name
Test status
Simulation time 8402399462 ps
CPU time 8.85 seconds
Started Apr 28 02:14:21 PM PDT 24
Finished Apr 28 02:14:30 PM PDT 24
Peak memory 204112 kb
Host smart-c5fc44da-1762-4128-bef2-06602ea90166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
57334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2811957334
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1658106500
Short name T531
Test name
Test status
Simulation time 8373743489 ps
CPU time 7.69 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204008 kb
Host smart-c28cbf3c-4b24-4e2e-a7d7-3b41976014f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
06500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1658106500
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2503670149
Short name T1285
Test name
Test status
Simulation time 8465146503 ps
CPU time 7.57 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:14:37 PM PDT 24
Peak memory 204092 kb
Host smart-099c9575-a401-4cee-bbd1-00c276b02bb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2503670149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2503670149
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.478174147
Short name T992
Test name
Test status
Simulation time 8394384907 ps
CPU time 7.9 seconds
Started Apr 28 02:14:34 PM PDT 24
Finished Apr 28 02:14:42 PM PDT 24
Peak memory 204144 kb
Host smart-b7ad80ed-8b64-47af-9e74-702edcfac810
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=478174147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.478174147
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.2094492773
Short name T493
Test name
Test status
Simulation time 8410289821 ps
CPU time 8.7 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 203992 kb
Host smart-3355087c-c99d-4943-8a22-bf2f5ea9a03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20944
92773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.2094492773
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3232058058
Short name T847
Test name
Test status
Simulation time 8380841949 ps
CPU time 7.33 seconds
Started Apr 28 02:14:25 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204052 kb
Host smart-2c7a1aae-63cd-4635-81ed-c47e159e5653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
58058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3232058058
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.2388527962
Short name T17
Test name
Test status
Simulation time 8381214090 ps
CPU time 8.57 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204060 kb
Host smart-e5f5332e-72ae-4704-98f5-3dd93f7190f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
27962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2388527962
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.4188607874
Short name T217
Test name
Test status
Simulation time 129593432 ps
CPU time 1.28 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:25 PM PDT 24
Peak memory 204196 kb
Host smart-56135e86-bb2a-4470-a070-4e896065d265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
07874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.4188607874
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1382044324
Short name T728
Test name
Test status
Simulation time 8394954946 ps
CPU time 8.1 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 204068 kb
Host smart-dea25724-ddff-4c46-ba5f-bbd40573fbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13820
44324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1382044324
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2432117464
Short name T198
Test name
Test status
Simulation time 8362873716 ps
CPU time 7.82 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 204116 kb
Host smart-871b8feb-860b-45c9-bee8-84d1a53a4c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24321
17464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2432117464
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3911477503
Short name T633
Test name
Test status
Simulation time 8420038583 ps
CPU time 8 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:35 PM PDT 24
Peak memory 204008 kb
Host smart-b9ae72b8-e823-4250-bf6d-7d9a3e7647b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
77503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3911477503
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2684097402
Short name T297
Test name
Test status
Simulation time 8417897086 ps
CPU time 9 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:37 PM PDT 24
Peak memory 204032 kb
Host smart-25dfffbe-6e6e-43c3-8580-31e79b9d6f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26840
97402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2684097402
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2844052089
Short name T577
Test name
Test status
Simulation time 8372230972 ps
CPU time 10 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:35 PM PDT 24
Peak memory 204128 kb
Host smart-c7542c17-0c35-4c00-9079-4edd90319c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
52089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2844052089
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.427773508
Short name T1020
Test name
Test status
Simulation time 8422344348 ps
CPU time 8.78 seconds
Started Apr 28 02:14:23 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204108 kb
Host smart-28e67d6e-3dca-42a3-bcce-8305bf94117d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42777
3508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.427773508
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3681981399
Short name T1006
Test name
Test status
Simulation time 8442388283 ps
CPU time 8.45 seconds
Started Apr 28 02:14:25 PM PDT 24
Finished Apr 28 02:14:34 PM PDT 24
Peak memory 204108 kb
Host smart-7cf2e548-acdf-44b8-9bea-19823778a8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819
81399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3681981399
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1050836664
Short name T309
Test name
Test status
Simulation time 8418406399 ps
CPU time 9.33 seconds
Started Apr 28 02:14:28 PM PDT 24
Finished Apr 28 02:14:37 PM PDT 24
Peak memory 204112 kb
Host smart-2d689045-5f8b-4daf-9d80-85ff93356738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
36664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1050836664
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2590233392
Short name T808
Test name
Test status
Simulation time 8412726344 ps
CPU time 8.99 seconds
Started Apr 28 02:14:28 PM PDT 24
Finished Apr 28 02:14:38 PM PDT 24
Peak memory 204096 kb
Host smart-5b8d7770-505f-42d6-8f5f-f9028afbd607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25902
33392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2590233392
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.955768780
Short name T1058
Test name
Test status
Simulation time 8369102400 ps
CPU time 9.17 seconds
Started Apr 28 02:14:26 PM PDT 24
Finished Apr 28 02:14:35 PM PDT 24
Peak memory 204068 kb
Host smart-3604d0e6-808a-4a33-88e4-6b41b3172b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95576
8780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.955768780
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1674688482
Short name T44
Test name
Test status
Simulation time 208167000 ps
CPU time 0.8 seconds
Started Apr 28 02:14:34 PM PDT 24
Finished Apr 28 02:14:35 PM PDT 24
Peak memory 203988 kb
Host smart-b322d2cb-8ade-46d3-9814-ff73070e8e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16746
88482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1674688482
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.4023219423
Short name T1105
Test name
Test status
Simulation time 14406726679 ps
CPU time 27.68 seconds
Started Apr 28 02:14:23 PM PDT 24
Finished Apr 28 02:14:51 PM PDT 24
Peak memory 204428 kb
Host smart-77381d0e-db2f-4fb0-b0fd-2b1b4a60370f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232
19423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.4023219423
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2533515767
Short name T732
Test name
Test status
Simulation time 8403051905 ps
CPU time 7.67 seconds
Started Apr 28 02:14:24 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204112 kb
Host smart-738f223b-d48c-460c-b526-f23cb3b2991a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25335
15767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2533515767
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1324058686
Short name T457
Test name
Test status
Simulation time 8449075947 ps
CPU time 10.46 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 204124 kb
Host smart-7dc383f3-04b4-4390-811e-72dc47f9724a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13240
58686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1324058686
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2077982869
Short name T1067
Test name
Test status
Simulation time 8400032655 ps
CPU time 9.56 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 204136 kb
Host smart-c34b3dd4-1e53-455d-a050-a16665f8697b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20779
82869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2077982869
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.289913827
Short name T1056
Test name
Test status
Simulation time 8392175768 ps
CPU time 8.01 seconds
Started Apr 28 02:14:34 PM PDT 24
Finished Apr 28 02:14:42 PM PDT 24
Peak memory 204120 kb
Host smart-08202cc0-512d-449f-ba64-0405f70dafef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28991
3827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.289913827
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3649339923
Short name T308
Test name
Test status
Simulation time 8371105834 ps
CPU time 7.91 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:35 PM PDT 24
Peak memory 204128 kb
Host smart-2e3e891e-e9a4-4331-a938-090b949927ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
39923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3649339923
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.576914872
Short name T1070
Test name
Test status
Simulation time 8472311644 ps
CPU time 8.15 seconds
Started Apr 28 02:14:25 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204024 kb
Host smart-32a485a9-ee8e-4db1-88f7-7ae42f5f2ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57691
4872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.576914872
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3622218580
Short name T1289
Test name
Test status
Simulation time 8401189920 ps
CPU time 7.98 seconds
Started Apr 28 02:14:27 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204132 kb
Host smart-a28d6be9-8477-4a09-9a44-09b8e98950d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36222
18580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3622218580
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1109648028
Short name T1125
Test name
Test status
Simulation time 8410977089 ps
CPU time 9.56 seconds
Started Apr 28 02:14:26 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204116 kb
Host smart-fcd9ba4b-f7af-4889-b38b-220e82896807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11096
48028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1109648028
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3527459016
Short name T332
Test name
Test status
Simulation time 8477432504 ps
CPU time 10.57 seconds
Started Apr 28 02:14:42 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204084 kb
Host smart-97aa5b0e-90cc-4b03-a63d-5006740f87b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3527459016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3527459016
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.252753883
Short name T719
Test name
Test status
Simulation time 8376951187 ps
CPU time 7.72 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:44 PM PDT 24
Peak memory 204080 kb
Host smart-5d1491e8-ec0f-46f2-9e7d-82f3950ac900
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=252753883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.252753883
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.2619524255
Short name T1122
Test name
Test status
Simulation time 8420902601 ps
CPU time 7.69 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 204140 kb
Host smart-fe03931b-159e-4e25-9042-08260ee975ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26195
24255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.2619524255
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.295289014
Short name T520
Test name
Test status
Simulation time 8400377290 ps
CPU time 8.1 seconds
Started Apr 28 02:14:33 PM PDT 24
Finished Apr 28 02:14:41 PM PDT 24
Peak memory 204164 kb
Host smart-ba2917cc-67b0-407a-9edf-5df806c38eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29528
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.295289014
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.1894152315
Short name T85
Test name
Test status
Simulation time 8403333592 ps
CPU time 7.76 seconds
Started Apr 28 02:14:34 PM PDT 24
Finished Apr 28 02:14:43 PM PDT 24
Peak memory 204116 kb
Host smart-51c5d00b-5024-49db-be76-6f909299aa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18941
52315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1894152315
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4162747084
Short name T455
Test name
Test status
Simulation time 63470878 ps
CPU time 1.31 seconds
Started Apr 28 02:14:30 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 204220 kb
Host smart-e7c3a5f1-07f0-4cb0-bf0c-dbe8b9733323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627
47084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4162747084
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1633012879
Short name T140
Test name
Test status
Simulation time 8394466262 ps
CPU time 7.78 seconds
Started Apr 28 02:14:32 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 204120 kb
Host smart-9ce3729c-7bca-4418-a023-cce4882c07d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16330
12879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1633012879
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3662983259
Short name T1350
Test name
Test status
Simulation time 8396338050 ps
CPU time 9.49 seconds
Started Apr 28 02:14:33 PM PDT 24
Finished Apr 28 02:14:43 PM PDT 24
Peak memory 204124 kb
Host smart-479f39f1-c911-4939-a75b-06aae0ae643d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36629
83259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3662983259
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.35536863
Short name T883
Test name
Test status
Simulation time 8380088412 ps
CPU time 8.76 seconds
Started Apr 28 02:14:30 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 204064 kb
Host smart-dc085ed1-2eb8-4585-a7f6-08ecf14b3b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35536
863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.35536863
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1553825584
Short name T587
Test name
Test status
Simulation time 8409952404 ps
CPU time 8.94 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:41 PM PDT 24
Peak memory 204128 kb
Host smart-40e3f9e0-18bd-40b0-b93e-dadaa3269c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
25584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1553825584
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2398930192
Short name T674
Test name
Test status
Simulation time 8374876316 ps
CPU time 8.16 seconds
Started Apr 28 02:14:33 PM PDT 24
Finished Apr 28 02:14:41 PM PDT 24
Peak memory 204116 kb
Host smart-de8df232-6e1b-47e2-a2a7-d9e86f6c4063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23989
30192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2398930192
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.308068073
Short name T106
Test name
Test status
Simulation time 8414840128 ps
CPU time 9.62 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:46 PM PDT 24
Peak memory 204116 kb
Host smart-e7f4ba81-dcad-4463-b617-b07d6bf258b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
8073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.308068073
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3547248735
Short name T210
Test name
Test status
Simulation time 8407383382 ps
CPU time 7.93 seconds
Started Apr 28 02:14:28 PM PDT 24
Finished Apr 28 02:14:37 PM PDT 24
Peak memory 204132 kb
Host smart-185bfec6-4fd1-41d6-9a2b-6c71b2aae7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35472
48735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3547248735
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2955309333
Short name T543
Test name
Test status
Simulation time 8375721115 ps
CPU time 9.31 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:41 PM PDT 24
Peak memory 204156 kb
Host smart-4017b8e0-00c6-46aa-b0e1-7e9e49c20352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553
09333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2955309333
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1852200777
Short name T1181
Test name
Test status
Simulation time 8376647324 ps
CPU time 10.14 seconds
Started Apr 28 02:14:33 PM PDT 24
Finished Apr 28 02:14:44 PM PDT 24
Peak memory 204056 kb
Host smart-40894a85-8335-430f-bd1e-b07cc43df461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
00777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1852200777
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3244382655
Short name T295
Test name
Test status
Simulation time 8406920953 ps
CPU time 8.65 seconds
Started Apr 28 02:14:30 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 204040 kb
Host smart-c57cfab4-e857-4541-8e7f-8fb378da5a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32443
82655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3244382655
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2867991135
Short name T1338
Test name
Test status
Simulation time 73987331 ps
CPU time 0.72 seconds
Started Apr 28 02:14:30 PM PDT 24
Finished Apr 28 02:14:32 PM PDT 24
Peak memory 204008 kb
Host smart-851bc4c7-ad14-46d7-ab2d-95cbe690092f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28679
91135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2867991135
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2937527916
Short name T919
Test name
Test status
Simulation time 28389632553 ps
CPU time 53.68 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:15:24 PM PDT 24
Peak memory 204412 kb
Host smart-9b861df9-0be9-47ad-be02-dc9af6eb9624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
27916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2937527916
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2809788915
Short name T1337
Test name
Test status
Simulation time 8466381589 ps
CPU time 7.41 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 204056 kb
Host smart-743d6ed1-73f2-4a7f-8d91-aab031422ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
88915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2809788915
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3616662754
Short name T893
Test name
Test status
Simulation time 8449195143 ps
CPU time 7.38 seconds
Started Apr 28 02:14:33 PM PDT 24
Finished Apr 28 02:14:41 PM PDT 24
Peak memory 204124 kb
Host smart-364e136b-8d65-46d5-9b91-280ff5db6a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
62754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3616662754
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1946902477
Short name T1330
Test name
Test status
Simulation time 8388062310 ps
CPU time 9.09 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 203996 kb
Host smart-466923e6-5b0e-4a27-9361-3b58dd64cdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
02477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1946902477
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2843407500
Short name T1255
Test name
Test status
Simulation time 8369586718 ps
CPU time 8.58 seconds
Started Apr 28 02:14:30 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 204152 kb
Host smart-f9532506-c9f0-4c50-9aed-affe03683303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28434
07500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2843407500
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.26953085
Short name T573
Test name
Test status
Simulation time 8379172448 ps
CPU time 7.72 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:44 PM PDT 24
Peak memory 204112 kb
Host smart-e2e3ec6f-b7cf-4cad-88ab-9695af17bb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26953
085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.26953085
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2461478866
Short name T142
Test name
Test status
Simulation time 8412575270 ps
CPU time 9.93 seconds
Started Apr 28 02:14:31 PM PDT 24
Finished Apr 28 02:14:42 PM PDT 24
Peak memory 204160 kb
Host smart-cc0b8e6a-8e10-457b-80c5-7b6939be65da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24614
78866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2461478866
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.757879346
Short name T423
Test name
Test status
Simulation time 8398847768 ps
CPU time 7.53 seconds
Started Apr 28 02:14:29 PM PDT 24
Finished Apr 28 02:14:38 PM PDT 24
Peak memory 204104 kb
Host smart-8f4eb7cd-dd38-4393-9baa-b9b7a697d17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75787
9346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.757879346
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3568376233
Short name T1375
Test name
Test status
Simulation time 8412062660 ps
CPU time 7.9 seconds
Started Apr 28 02:14:30 PM PDT 24
Finished Apr 28 02:14:39 PM PDT 24
Peak memory 204152 kb
Host smart-4b6321b6-c122-4e15-b886-c00f6f481fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35683
76233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3568376233
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3133284873
Short name T778
Test name
Test status
Simulation time 8469005775 ps
CPU time 9.14 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204080 kb
Host smart-a2d7ec23-e896-4229-87b9-3600bec925b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3133284873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3133284873
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2949926392
Short name T594
Test name
Test status
Simulation time 8385808369 ps
CPU time 8.27 seconds
Started Apr 28 02:14:36 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204116 kb
Host smart-ad7f0d66-e020-47bb-b355-2adc510482d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2949926392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2949926392
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.1759053734
Short name T696
Test name
Test status
Simulation time 8454517032 ps
CPU time 9.06 seconds
Started Apr 28 02:14:38 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204160 kb
Host smart-1e76a436-6865-425c-9ec6-448266861a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17590
53734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.1759053734
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3217400544
Short name T1060
Test name
Test status
Simulation time 8415330071 ps
CPU time 8.49 seconds
Started Apr 28 02:14:33 PM PDT 24
Finished Apr 28 02:14:42 PM PDT 24
Peak memory 204068 kb
Host smart-736fbb58-fbb7-44b7-b8d7-e15597a47111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
00544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3217400544
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.2898249701
Short name T215
Test name
Test status
Simulation time 8378622119 ps
CPU time 7.79 seconds
Started Apr 28 02:14:42 PM PDT 24
Finished Apr 28 02:14:51 PM PDT 24
Peak memory 204072 kb
Host smart-07c0ee6d-6eca-4aea-a80c-b65b4cdfb22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982
49701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2898249701
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2359155343
Short name T1208
Test name
Test status
Simulation time 201140533 ps
CPU time 2.08 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:38 PM PDT 24
Peak memory 204148 kb
Host smart-80a33805-c963-4026-a993-708e036f7dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591
55343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2359155343
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1818681654
Short name T731
Test name
Test status
Simulation time 8366416015 ps
CPU time 8.77 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204092 kb
Host smart-84b35aaa-401a-478b-95af-e3d8206cfdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18186
81654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1818681654
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3729120640
Short name T1360
Test name
Test status
Simulation time 8443488412 ps
CPU time 7.94 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:46 PM PDT 24
Peak memory 203984 kb
Host smart-905c3633-262b-465d-ad20-d490abae5d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
20640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3729120640
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.580388167
Short name T1113
Test name
Test status
Simulation time 8466169029 ps
CPU time 7.8 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204120 kb
Host smart-31a4719e-e47f-4e6b-8eb4-7489e25f4e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58038
8167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.580388167
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1547508366
Short name T411
Test name
Test status
Simulation time 8374403395 ps
CPU time 9.18 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204116 kb
Host smart-03bf3226-4b34-4f05-bfac-73a790f4c58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
08366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1547508366
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1466374620
Short name T103
Test name
Test status
Simulation time 8421213095 ps
CPU time 9.08 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:46 PM PDT 24
Peak memory 204120 kb
Host smart-b62b16b5-e828-40d7-9edf-6d4a67d1067e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14663
74620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1466374620
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3577209977
Short name T647
Test name
Test status
Simulation time 8395041424 ps
CPU time 8.31 seconds
Started Apr 28 02:14:38 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204084 kb
Host smart-6877d070-e322-4f53-aa1d-833a1ff84b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
09977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3577209977
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1897281353
Short name T420
Test name
Test status
Simulation time 8418919124 ps
CPU time 7.97 seconds
Started Apr 28 02:14:36 PM PDT 24
Finished Apr 28 02:14:44 PM PDT 24
Peak memory 204148 kb
Host smart-597e004a-4036-48eb-8b34-450f411a2f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18972
81353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1897281353
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1367140308
Short name T1341
Test name
Test status
Simulation time 8409231685 ps
CPU time 7.46 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204128 kb
Host smart-e6bb11f1-be53-4fe8-85a4-d8a36a90dd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671
40308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1367140308
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3819357849
Short name T294
Test name
Test status
Simulation time 8372851131 ps
CPU time 9.71 seconds
Started Apr 28 02:14:34 PM PDT 24
Finished Apr 28 02:14:44 PM PDT 24
Peak memory 204096 kb
Host smart-cfd8436c-69a5-45d7-8a2c-61c4378b76b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
57849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3819357849
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1945565361
Short name T579
Test name
Test status
Simulation time 56159979 ps
CPU time 0.74 seconds
Started Apr 28 02:14:34 PM PDT 24
Finished Apr 28 02:14:36 PM PDT 24
Peak memory 204028 kb
Host smart-f1fa5e3e-fe34-423b-a650-cabc4d41d0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19455
65361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1945565361
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3459845802
Short name T480
Test name
Test status
Simulation time 26657882948 ps
CPU time 57.6 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 204280 kb
Host smart-8fbb1dcf-1f24-4736-8789-ffc821433c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34598
45802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3459845802
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.4034842040
Short name T560
Test name
Test status
Simulation time 8377631761 ps
CPU time 8.12 seconds
Started Apr 28 02:14:37 PM PDT 24
Finished Apr 28 02:14:46 PM PDT 24
Peak memory 204104 kb
Host smart-625b017b-ea4e-4d3f-a5bc-1c70ef808b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
42040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.4034842040
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2942052534
Short name T994
Test name
Test status
Simulation time 8386978731 ps
CPU time 7.89 seconds
Started Apr 28 02:14:40 PM PDT 24
Finished Apr 28 02:14:48 PM PDT 24
Peak memory 204088 kb
Host smart-b8c1e83c-b178-4f7a-8477-5c11bd202fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
52534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2942052534
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1753012548
Short name T84
Test name
Test status
Simulation time 8429895259 ps
CPU time 10.15 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:46 PM PDT 24
Peak memory 204108 kb
Host smart-50adbf9d-3794-41e6-bf83-356832d25755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
12548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1753012548
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2682548947
Short name T703
Test name
Test status
Simulation time 8380730481 ps
CPU time 7.65 seconds
Started Apr 28 02:14:36 PM PDT 24
Finished Apr 28 02:14:44 PM PDT 24
Peak memory 204148 kb
Host smart-ca545ddc-f287-444d-960c-d1f76eb0099a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
48947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2682548947
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1041458920
Short name T559
Test name
Test status
Simulation time 8398654699 ps
CPU time 7.66 seconds
Started Apr 28 02:14:35 PM PDT 24
Finished Apr 28 02:14:43 PM PDT 24
Peak memory 204116 kb
Host smart-a573e964-6bf9-42b9-843a-2f4ecd40f451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10414
58920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1041458920
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1243039935
Short name T827
Test name
Test status
Simulation time 8477886517 ps
CPU time 7.49 seconds
Started Apr 28 02:14:38 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204132 kb
Host smart-146210fb-ab67-4f58-a208-96ab565ef3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12430
39935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1243039935
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1051055451
Short name T131
Test name
Test status
Simulation time 8385770170 ps
CPU time 8.71 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:48 PM PDT 24
Peak memory 204028 kb
Host smart-d0d6119a-12d4-4cd2-9065-cfc660c17228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10510
55451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1051055451
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2147260105
Short name T1245
Test name
Test status
Simulation time 8402571750 ps
CPU time 8.14 seconds
Started Apr 28 02:14:36 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204100 kb
Host smart-fd3701d5-302e-4bc7-ae12-654228e7eba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21472
60105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2147260105
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.146062490
Short name T1194
Test name
Test status
Simulation time 8522425729 ps
CPU time 9.77 seconds
Started Apr 28 02:14:43 PM PDT 24
Finished Apr 28 02:14:53 PM PDT 24
Peak memory 204008 kb
Host smart-95555192-136d-40d3-9cb3-305ef5185597
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=146062490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.146062490
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.135291085
Short name T532
Test name
Test status
Simulation time 8380599576 ps
CPU time 10.69 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:55 PM PDT 24
Peak memory 204084 kb
Host smart-3561a68e-d374-431f-b342-7e8ed20439ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=135291085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.135291085
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.3313471488
Short name T918
Test name
Test status
Simulation time 8467889178 ps
CPU time 9.6 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:51 PM PDT 24
Peak memory 203628 kb
Host smart-e882236b-fd0f-40db-8297-c70354669e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
71488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.3313471488
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1025143931
Short name T533
Test name
Test status
Simulation time 8376349270 ps
CPU time 7.99 seconds
Started Apr 28 02:14:42 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204116 kb
Host smart-541fa682-a97c-4992-9ce6-dcaa0995dcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10251
43931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1025143931
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2739427128
Short name T1149
Test name
Test status
Simulation time 8392127368 ps
CPU time 7.74 seconds
Started Apr 28 02:14:38 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204112 kb
Host smart-f3e4a93c-c037-470f-9656-3949bc87dc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
27128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2739427128
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1577364336
Short name T475
Test name
Test status
Simulation time 134600738 ps
CPU time 1.69 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:42 PM PDT 24
Peak memory 204228 kb
Host smart-ccddcee8-c8f4-4767-95b3-3252199d2c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
64336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1577364336
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2679457203
Short name T1332
Test name
Test status
Simulation time 8390712253 ps
CPU time 8.29 seconds
Started Apr 28 02:14:43 PM PDT 24
Finished Apr 28 02:14:52 PM PDT 24
Peak memory 204088 kb
Host smart-4f1a7c5d-02d1-4930-ae89-27f95b19f6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794
57203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2679457203
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3784516023
Short name T182
Test name
Test status
Simulation time 8406843886 ps
CPU time 7.47 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204148 kb
Host smart-d452fd46-9dee-4e14-8e07-2025946e6031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37845
16023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3784516023
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.403167186
Short name T735
Test name
Test status
Simulation time 8487782232 ps
CPU time 8.29 seconds
Started Apr 28 02:14:40 PM PDT 24
Finished Apr 28 02:14:49 PM PDT 24
Peak memory 204104 kb
Host smart-2143486d-5782-4081-b522-08219d9f2a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
7186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.403167186
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3280449247
Short name T1265
Test name
Test status
Simulation time 8409555643 ps
CPU time 8.36 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 203648 kb
Host smart-14b9bf78-bf00-4c58-828a-641a76a5ae8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
49247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3280449247
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2064483082
Short name T340
Test name
Test status
Simulation time 8372235437 ps
CPU time 9.23 seconds
Started Apr 28 02:14:38 PM PDT 24
Finished Apr 28 02:14:49 PM PDT 24
Peak memory 204084 kb
Host smart-d095b20a-06d6-43af-86e6-0686d3d1e593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
83082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2064483082
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2298809774
Short name T978
Test name
Test status
Simulation time 8484061164 ps
CPU time 9.76 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:52 PM PDT 24
Peak memory 204156 kb
Host smart-b4b14202-2943-4c91-a91c-0f242056baa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22988
09774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2298809774
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1579898059
Short name T470
Test name
Test status
Simulation time 8390351622 ps
CPU time 8.27 seconds
Started Apr 28 02:14:43 PM PDT 24
Finished Apr 28 02:14:52 PM PDT 24
Peak memory 204104 kb
Host smart-6600b545-8b4b-4873-902f-0ea9fabc3051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15798
98059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1579898059
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.214349904
Short name T632
Test name
Test status
Simulation time 8381719741 ps
CPU time 8.83 seconds
Started Apr 28 02:14:45 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204112 kb
Host smart-b6c74c52-ad25-42fc-b7b3-35751c524e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
9904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.214349904
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3869528113
Short name T792
Test name
Test status
Simulation time 8390258932 ps
CPU time 7.62 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:47 PM PDT 24
Peak memory 204080 kb
Host smart-f87b2b6f-0e8b-415e-8601-380744053e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38695
28113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3869528113
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.60134412
Short name T1340
Test name
Test status
Simulation time 8370573147 ps
CPU time 8.33 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204156 kb
Host smart-668d69d3-2a08-4a4f-93e1-1ee65739d357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60134
412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.60134412
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.4056008904
Short name T1077
Test name
Test status
Simulation time 38310142 ps
CPU time 0.72 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:41 PM PDT 24
Peak memory 204000 kb
Host smart-874d02d2-2d65-4bfc-9c8c-3b432efc6eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
08904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.4056008904
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1932321260
Short name T260
Test name
Test status
Simulation time 16325756364 ps
CPU time 28.64 seconds
Started Apr 28 02:14:42 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204404 kb
Host smart-83884de1-6fe6-4cb1-8526-69dbd1c0192b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19323
21260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1932321260
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.924060223
Short name T912
Test name
Test status
Simulation time 8409944463 ps
CPU time 9.98 seconds
Started Apr 28 02:14:38 PM PDT 24
Finished Apr 28 02:14:48 PM PDT 24
Peak memory 204080 kb
Host smart-72e188fd-e796-413b-933f-f639cace5fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92406
0223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.924060223
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.37935161
Short name T541
Test name
Test status
Simulation time 8458537813 ps
CPU time 9.92 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204096 kb
Host smart-c80e6127-fddf-404e-b47c-cc17cf476d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37935
161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.37935161
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2453207698
Short name T82
Test name
Test status
Simulation time 8397956050 ps
CPU time 8.05 seconds
Started Apr 28 02:14:40 PM PDT 24
Finished Apr 28 02:14:49 PM PDT 24
Peak memory 204104 kb
Host smart-fa5588b0-a812-4eeb-8fba-1fd43478b55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24532
07698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2453207698
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3917934324
Short name T976
Test name
Test status
Simulation time 8376984187 ps
CPU time 7.87 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:49 PM PDT 24
Peak memory 204132 kb
Host smart-068737b4-5c4f-41c0-a287-1908073af448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39179
34324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3917934324
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2172253814
Short name T1224
Test name
Test status
Simulation time 8369108393 ps
CPU time 7.7 seconds
Started Apr 28 02:14:42 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204136 kb
Host smart-cb59b7cb-1828-4a3e-a2a8-614ad9fad6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
53814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2172253814
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2992965761
Short name T819
Test name
Test status
Simulation time 8454764318 ps
CPU time 8.12 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:48 PM PDT 24
Peak memory 204084 kb
Host smart-ebdd6e58-1938-4511-a2f6-07ea1728024a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929
65761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2992965761
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2315030751
Short name T1282
Test name
Test status
Simulation time 8381842203 ps
CPU time 10.1 seconds
Started Apr 28 02:14:39 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204168 kb
Host smart-23191ffd-b316-43f9-8979-8bc2261a8758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23150
30751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2315030751
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2877103917
Short name T80
Test name
Test status
Simulation time 8400307645 ps
CPU time 8.22 seconds
Started Apr 28 02:14:45 PM PDT 24
Finished Apr 28 02:14:53 PM PDT 24
Peak memory 204120 kb
Host smart-8ca668fe-68cc-42db-9597-09f39de21af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
03917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2877103917
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.3630335937
Short name T1287
Test name
Test status
Simulation time 8473010529 ps
CPU time 8.08 seconds
Started Apr 28 02:14:45 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204072 kb
Host smart-9878f161-7d60-4bae-921e-4684c7c79bc1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3630335937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.3630335937
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.779702747
Short name T1334
Test name
Test status
Simulation time 8384191240 ps
CPU time 7.32 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204120 kb
Host smart-80daef55-15e3-4f71-9f0c-d2dbb00bcf80
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=779702747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.779702747
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2404891893
Short name T1139
Test name
Test status
Simulation time 8400513853 ps
CPU time 9.99 seconds
Started Apr 28 02:14:46 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204096 kb
Host smart-4b30aaef-5179-48d1-b3d8-b221da336bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
91893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2404891893
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3324967219
Short name T1331
Test name
Test status
Simulation time 8375224177 ps
CPU time 7.88 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:49 PM PDT 24
Peak memory 204132 kb
Host smart-243002ef-c556-4527-bd8a-50da2a63deda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33249
67219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3324967219
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.3828365866
Short name T904
Test name
Test status
Simulation time 8402519789 ps
CPU time 9.1 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:51 PM PDT 24
Peak memory 204140 kb
Host smart-6c0e9d08-0639-4aff-b14f-f128f2fdb5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38283
65866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3828365866
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3134951689
Short name T1074
Test name
Test status
Simulation time 62818516 ps
CPU time 1.69 seconds
Started Apr 28 02:14:43 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204072 kb
Host smart-ac73b7d8-5955-4728-9715-376070eeb80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31349
51689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3134951689
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2191928221
Short name T1257
Test name
Test status
Simulation time 8436061649 ps
CPU time 8.29 seconds
Started Apr 28 02:14:50 PM PDT 24
Finished Apr 28 02:14:59 PM PDT 24
Peak memory 204052 kb
Host smart-9a838be4-6fc8-444b-8ab8-82a697d74000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21919
28221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2191928221
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2060869717
Short name T1277
Test name
Test status
Simulation time 8365982991 ps
CPU time 8.61 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:53 PM PDT 24
Peak memory 203968 kb
Host smart-fa9feb71-92b6-4904-9b50-309e7a8b8257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
69717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2060869717
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.4033259126
Short name T903
Test name
Test status
Simulation time 8460499426 ps
CPU time 7.75 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:52 PM PDT 24
Peak memory 204088 kb
Host smart-52d44b80-b0a3-4e4e-ab1a-f7e2b8032722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40332
59126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.4033259126
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2956552838
Short name T974
Test name
Test status
Simulation time 8421722051 ps
CPU time 8.25 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204028 kb
Host smart-0ed5d284-1630-4410-beaf-c6b19924cb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29565
52838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2956552838
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.461952889
Short name T955
Test name
Test status
Simulation time 8430680941 ps
CPU time 7.78 seconds
Started Apr 28 02:14:41 PM PDT 24
Finished Apr 28 02:14:50 PM PDT 24
Peak memory 204108 kb
Host smart-03273e4a-d774-4ef7-bfa9-f3fe044e3616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46195
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.461952889
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1759227713
Short name T123
Test name
Test status
Simulation time 8456904848 ps
CPU time 7.62 seconds
Started Apr 28 02:14:50 PM PDT 24
Finished Apr 28 02:14:59 PM PDT 24
Peak memory 204040 kb
Host smart-8a8e009d-773b-4990-af37-bd783155c96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17592
27713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1759227713
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1938336235
Short name T759
Test name
Test status
Simulation time 8399923402 ps
CPU time 9.74 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:59 PM PDT 24
Peak memory 204036 kb
Host smart-b13bca7a-e3f5-4197-b18b-954329404207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19383
36235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1938336235
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4020731756
Short name T820
Test name
Test status
Simulation time 8402908740 ps
CPU time 10.54 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204120 kb
Host smart-dc49d914-9e10-4f75-a15d-37e03440a4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40207
31756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4020731756
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1796340536
Short name T181
Test name
Test status
Simulation time 8400770654 ps
CPU time 7.79 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 203984 kb
Host smart-a6fae7f4-676a-40a1-8f12-67422cc03311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
40536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1796340536
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1128266631
Short name T1068
Test name
Test status
Simulation time 8388589993 ps
CPU time 8.15 seconds
Started Apr 28 02:14:45 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204136 kb
Host smart-6cc453e6-24c9-4f03-b289-0bdaa6db895b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11282
66631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1128266631
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3742093972
Short name T1343
Test name
Test status
Simulation time 45045887 ps
CPU time 0.66 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:45 PM PDT 24
Peak memory 204020 kb
Host smart-979337fc-c1e7-4850-aa74-21a210daee90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
93972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3742093972
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3165036303
Short name T88
Test name
Test status
Simulation time 28309426834 ps
CPU time 55.58 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 204400 kb
Host smart-40f9135b-f59f-4916-ab05-81129b23fa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31650
36303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3165036303
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.665983641
Short name T850
Test name
Test status
Simulation time 8401175757 ps
CPU time 10.35 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:58 PM PDT 24
Peak memory 204068 kb
Host smart-faed796a-31a1-43e5-8bb0-c1cb866a3c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66598
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.665983641
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.189089557
Short name T1237
Test name
Test status
Simulation time 8420242061 ps
CPU time 9.12 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204100 kb
Host smart-10850021-a71f-4840-b5cb-855310f0d3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18908
9557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.189089557
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2792377288
Short name T599
Test name
Test status
Simulation time 8400516965 ps
CPU time 9.9 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204000 kb
Host smart-0857cf0c-9705-41e4-8124-995caa37fa1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
77288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2792377288
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1034858707
Short name T635
Test name
Test status
Simulation time 8375595258 ps
CPU time 8.5 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204080 kb
Host smart-e675f428-eaf4-4651-81d9-92c87715b7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10348
58707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1034858707
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2839080851
Short name T395
Test name
Test status
Simulation time 8375221961 ps
CPU time 7.28 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:55 PM PDT 24
Peak memory 204068 kb
Host smart-532bdc19-d606-42d6-aeaa-a11576389fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
80851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2839080851
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.783111737
Short name T945
Test name
Test status
Simulation time 8399951460 ps
CPU time 8.11 seconds
Started Apr 28 02:14:42 PM PDT 24
Finished Apr 28 02:14:51 PM PDT 24
Peak memory 204072 kb
Host smart-cbb7fb5e-e416-4208-a4be-a073ff6f89e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78311
1737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.783111737
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.106655105
Short name T368
Test name
Test status
Simulation time 8400147654 ps
CPU time 8.87 seconds
Started Apr 28 02:14:46 PM PDT 24
Finished Apr 28 02:14:55 PM PDT 24
Peak memory 204084 kb
Host smart-bfb0e800-ad34-45c9-99f4-d50f18d4715d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.106655105
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.446995073
Short name T923
Test name
Test status
Simulation time 8375489475 ps
CPU time 7.81 seconds
Started Apr 28 02:14:46 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204108 kb
Host smart-8665cee2-05c0-4064-8afa-428b0e0264f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44699
5073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.446995073
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3814484143
Short name T1223
Test name
Test status
Simulation time 8520826893 ps
CPU time 10.35 seconds
Started Apr 28 02:11:32 PM PDT 24
Finished Apr 28 02:11:43 PM PDT 24
Peak memory 204036 kb
Host smart-fc939084-7a04-469c-a170-4405beccc663
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3814484143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3814484143
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.3364984038
Short name T464
Test name
Test status
Simulation time 8381225933 ps
CPU time 8.19 seconds
Started Apr 28 02:11:32 PM PDT 24
Finished Apr 28 02:11:41 PM PDT 24
Peak memory 204100 kb
Host smart-7c4fd514-2e47-44e2-a738-17a42244d3b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3364984038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.3364984038
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.576867442
Short name T461
Test name
Test status
Simulation time 8431434419 ps
CPU time 8.06 seconds
Started Apr 28 02:11:30 PM PDT 24
Finished Apr 28 02:11:39 PM PDT 24
Peak memory 204128 kb
Host smart-9c8e60b0-e993-4c86-adad-040c1ab0c944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57686
7442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.576867442
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.180529881
Short name T922
Test name
Test status
Simulation time 8381230988 ps
CPU time 8 seconds
Started Apr 28 02:11:23 PM PDT 24
Finished Apr 28 02:11:32 PM PDT 24
Peak memory 204116 kb
Host smart-0b08aceb-0c8c-43f9-922e-f0d90363927a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18052
9881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.180529881
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1356672377
Short name T346
Test name
Test status
Simulation time 8381229034 ps
CPU time 8.2 seconds
Started Apr 28 02:11:20 PM PDT 24
Finished Apr 28 02:11:29 PM PDT 24
Peak memory 204080 kb
Host smart-e43afb40-df45-4fb8-b99f-12f5357cf440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
72377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1356672377
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1341341914
Short name T53
Test name
Test status
Simulation time 318909179 ps
CPU time 2.12 seconds
Started Apr 28 02:11:21 PM PDT 24
Finished Apr 28 02:11:23 PM PDT 24
Peak memory 204152 kb
Host smart-ea571cb8-6d6d-4133-9cbc-f965c8759fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13413
41914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1341341914
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.693070938
Short name T884
Test name
Test status
Simulation time 8450776510 ps
CPU time 10.48 seconds
Started Apr 28 02:11:34 PM PDT 24
Finished Apr 28 02:11:45 PM PDT 24
Peak memory 204108 kb
Host smart-21b2dea3-3d34-4f1c-8f2b-09fdbf6de60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69307
0938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.693070938
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1624014771
Short name T184
Test name
Test status
Simulation time 8367326751 ps
CPU time 10.2 seconds
Started Apr 28 02:11:25 PM PDT 24
Finished Apr 28 02:11:35 PM PDT 24
Peak memory 204080 kb
Host smart-a3bd6665-fbbf-4be8-b6d2-00ff1a99445f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240
14771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1624014771
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.4109679629
Short name T623
Test name
Test status
Simulation time 8451101139 ps
CPU time 9.29 seconds
Started Apr 28 02:11:23 PM PDT 24
Finished Apr 28 02:11:33 PM PDT 24
Peak memory 204116 kb
Host smart-8fd57ec4-5267-423f-accb-9175d47901e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
79629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.4109679629
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.601956439
Short name T1166
Test name
Test status
Simulation time 8412738624 ps
CPU time 7.43 seconds
Started Apr 28 02:11:19 PM PDT 24
Finished Apr 28 02:11:27 PM PDT 24
Peak memory 204084 kb
Host smart-85a8d5cf-1b0f-4543-8f82-b618d2972730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60195
6439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.601956439
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1842877073
Short name T439
Test name
Test status
Simulation time 8370176591 ps
CPU time 8.41 seconds
Started Apr 28 02:11:20 PM PDT 24
Finished Apr 28 02:11:29 PM PDT 24
Peak memory 204036 kb
Host smart-01f038d7-1814-4a6d-b72b-9966a4c1edaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428
77073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1842877073
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2019309329
Short name T116
Test name
Test status
Simulation time 8453270543 ps
CPU time 8.63 seconds
Started Apr 28 02:11:28 PM PDT 24
Finished Apr 28 02:11:36 PM PDT 24
Peak memory 204140 kb
Host smart-b5f8922a-1ede-4670-946b-ba3f8596fa15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193
09329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2019309329
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2602866126
Short name T1279
Test name
Test status
Simulation time 8383152535 ps
CPU time 9.25 seconds
Started Apr 28 02:11:24 PM PDT 24
Finished Apr 28 02:11:34 PM PDT 24
Peak memory 204128 kb
Host smart-015a7f58-6ed9-4f3d-afd5-a9954ea25698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26028
66126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2602866126
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.4185284503
Short name T405
Test name
Test status
Simulation time 8396147081 ps
CPU time 9.09 seconds
Started Apr 28 02:11:27 PM PDT 24
Finished Apr 28 02:11:36 PM PDT 24
Peak memory 204076 kb
Host smart-e7ef5d55-aa3e-42bb-a76f-26483f125a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41852
84503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.4185284503
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2092700419
Short name T173
Test name
Test status
Simulation time 8395008267 ps
CPU time 7.75 seconds
Started Apr 28 02:11:27 PM PDT 24
Finished Apr 28 02:11:35 PM PDT 24
Peak memory 204120 kb
Host smart-07c31494-f49f-4fc7-a6db-f5c7a9854b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20927
00419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2092700419
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3715889508
Short name T1046
Test name
Test status
Simulation time 8372318018 ps
CPU time 7.55 seconds
Started Apr 28 02:11:26 PM PDT 24
Finished Apr 28 02:11:34 PM PDT 24
Peak memory 204064 kb
Host smart-8318b3a4-7370-4f05-a1a9-30148d6556e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37158
89508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3715889508
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2449019097
Short name T953
Test name
Test status
Simulation time 72230402 ps
CPU time 0.68 seconds
Started Apr 28 02:11:24 PM PDT 24
Finished Apr 28 02:11:25 PM PDT 24
Peak memory 204032 kb
Host smart-a0f4e2ed-9af4-40da-8ad8-6b6a87b6c269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
19097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2449019097
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3027050298
Short name T467
Test name
Test status
Simulation time 28686244951 ps
CPU time 52.98 seconds
Started Apr 28 02:11:27 PM PDT 24
Finished Apr 28 02:12:20 PM PDT 24
Peak memory 204324 kb
Host smart-d498aba7-2b61-4009-8ee2-c6d1b322369c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30270
50298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3027050298
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.763577801
Short name T1057
Test name
Test status
Simulation time 8406766062 ps
CPU time 8.9 seconds
Started Apr 28 02:11:28 PM PDT 24
Finished Apr 28 02:11:38 PM PDT 24
Peak memory 204036 kb
Host smart-de2b57ff-26ba-4343-808e-cdd75d699092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76357
7801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.763577801
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3691706128
Short name T369
Test name
Test status
Simulation time 8477778912 ps
CPU time 7.95 seconds
Started Apr 28 02:11:29 PM PDT 24
Finished Apr 28 02:11:37 PM PDT 24
Peak memory 204004 kb
Host smart-b0e5e0af-6124-4d94-afcd-c32dee6ee66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
06128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3691706128
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.534902920
Short name T1309
Test name
Test status
Simulation time 8392862872 ps
CPU time 7.44 seconds
Started Apr 28 02:11:27 PM PDT 24
Finished Apr 28 02:11:35 PM PDT 24
Peak memory 204140 kb
Host smart-378b093d-65e9-48a9-8ba2-39cf12cd08de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53490
2920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.534902920
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2820077826
Short name T1274
Test name
Test status
Simulation time 8381324551 ps
CPU time 8.14 seconds
Started Apr 28 02:11:24 PM PDT 24
Finished Apr 28 02:11:33 PM PDT 24
Peak memory 204116 kb
Host smart-6c8f0f17-dfdd-4e14-aa98-79509944a470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
77826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2820077826
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1897988921
Short name T1356
Test name
Test status
Simulation time 8371050452 ps
CPU time 7.53 seconds
Started Apr 28 02:11:24 PM PDT 24
Finished Apr 28 02:11:32 PM PDT 24
Peak memory 204132 kb
Host smart-71bf7599-5f68-417e-9381-02c76152ced3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18979
88921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1897988921
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1807558432
Short name T177
Test name
Test status
Simulation time 8433705497 ps
CPU time 7.6 seconds
Started Apr 28 02:11:19 PM PDT 24
Finished Apr 28 02:11:27 PM PDT 24
Peak memory 204144 kb
Host smart-ffe18e05-c121-4ae1-bca1-43a2739fa85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18075
58432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1807558432
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4277051819
Short name T879
Test name
Test status
Simulation time 8410007628 ps
CPU time 7.34 seconds
Started Apr 28 02:11:29 PM PDT 24
Finished Apr 28 02:11:37 PM PDT 24
Peak memory 204000 kb
Host smart-cf998009-38bf-411a-b5e8-5f70a7d0a7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
51819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4277051819
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.283546046
Short name T356
Test name
Test status
Simulation time 8382653946 ps
CPU time 9.89 seconds
Started Apr 28 02:11:26 PM PDT 24
Finished Apr 28 02:11:36 PM PDT 24
Peak memory 204080 kb
Host smart-021edaee-021b-4245-93f6-670111b7ff77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
6046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.283546046
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.4005938588
Short name T586
Test name
Test status
Simulation time 8464487803 ps
CPU time 8.99 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204116 kb
Host smart-3161ca56-998b-4f6b-a741-ee6c20484690
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4005938588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.4005938588
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.853875310
Short name T755
Test name
Test status
Simulation time 8385101148 ps
CPU time 9.64 seconds
Started Apr 28 02:14:52 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204096 kb
Host smart-14ab215b-5bf4-440e-ab61-dc09dea3597c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=853875310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.853875310
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.3755481607
Short name T758
Test name
Test status
Simulation time 8397033657 ps
CPU time 7.68 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 204140 kb
Host smart-888d72d3-a42c-492a-ba59-0070505ca5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554
81607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.3755481607
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1938691388
Short name T1268
Test name
Test status
Simulation time 8419389887 ps
CPU time 7.49 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:52 PM PDT 24
Peak memory 204108 kb
Host smart-c6da7aee-bdd9-405c-a75b-ad55cfabecc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19386
91388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1938691388
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.2040381041
Short name T796
Test name
Test status
Simulation time 8389981839 ps
CPU time 9.28 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:58 PM PDT 24
Peak memory 203988 kb
Host smart-3ff390e4-f12a-42ca-8286-075bb84a7b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20403
81041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2040381041
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.703939456
Short name T855
Test name
Test status
Simulation time 189596538 ps
CPU time 1.99 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:49 PM PDT 24
Peak memory 204252 kb
Host smart-654e4e06-43d3-4ba1-ac67-8353f89a7ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70393
9456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.703939456
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.37592659
Short name T1005
Test name
Test status
Simulation time 8416610316 ps
CPU time 7.84 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:05 PM PDT 24
Peak memory 204104 kb
Host smart-dc9821ea-6fa8-4f0e-b30b-0adc3e429d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37592
659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.37592659
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3976596693
Short name T743
Test name
Test status
Simulation time 8368815595 ps
CPU time 8.35 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204036 kb
Host smart-a1edc2a6-f35e-42d7-ab72-cee6a00c0626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
96693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3976596693
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1808574360
Short name T153
Test name
Test status
Simulation time 8388191009 ps
CPU time 7.63 seconds
Started Apr 28 02:14:45 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204100 kb
Host smart-243e7643-7f87-42e7-b48d-402f9e88518e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18085
74360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1808574360
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1723924223
Short name T1252
Test name
Test status
Simulation time 8418569143 ps
CPU time 8.29 seconds
Started Apr 28 02:14:46 PM PDT 24
Finished Apr 28 02:14:54 PM PDT 24
Peak memory 204124 kb
Host smart-aa6fda74-05e1-4ffd-818b-9a1fdbd9e9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17239
24223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1723924223
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.551178435
Short name T693
Test name
Test status
Simulation time 8379240345 ps
CPU time 7.9 seconds
Started Apr 28 02:14:44 PM PDT 24
Finished Apr 28 02:14:53 PM PDT 24
Peak memory 204068 kb
Host smart-34539c26-245f-4362-95ea-35c0e2419e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55117
8435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.551178435
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.4206701835
Short name T104
Test name
Test status
Simulation time 8467883565 ps
CPU time 8.28 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204104 kb
Host smart-5d1e803b-3e63-48c5-b43e-a88c135d82fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
01835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.4206701835
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.751596914
Short name T513
Test name
Test status
Simulation time 8406589234 ps
CPU time 8.74 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204088 kb
Host smart-221a6901-1e7d-448b-b926-c491de56df87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75159
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.751596914
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.237083851
Short name T767
Test name
Test status
Simulation time 8376271257 ps
CPU time 8.39 seconds
Started Apr 28 02:14:46 PM PDT 24
Finished Apr 28 02:14:55 PM PDT 24
Peak memory 204116 kb
Host smart-234507d8-8e8f-4d8e-b0cb-cdfe966b56c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
3851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.237083851
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2644840178
Short name T725
Test name
Test status
Simulation time 8409547111 ps
CPU time 8.19 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 203972 kb
Host smart-72ec0e1f-263b-4b3b-9f79-ed1adba6095b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448
40178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2644840178
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3747955054
Short name T940
Test name
Test status
Simulation time 8442310617 ps
CPU time 8.9 seconds
Started Apr 28 02:14:52 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204028 kb
Host smart-711f217c-609f-40b4-9b04-0514c108b212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37479
55054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3747955054
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2962761674
Short name T45
Test name
Test status
Simulation time 34375961 ps
CPU time 0.64 seconds
Started Apr 28 02:14:50 PM PDT 24
Finished Apr 28 02:14:51 PM PDT 24
Peak memory 203980 kb
Host smart-fe3b2c99-1ab4-47aa-bc18-affc4e05ae92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29627
61674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2962761674
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2383766165
Short name T223
Test name
Test status
Simulation time 16380598244 ps
CPU time 28.27 seconds
Started Apr 28 02:14:46 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204384 kb
Host smart-483845e5-a1f3-4b59-979b-714f782b693a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23837
66165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2383766165
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.450851714
Short name T431
Test name
Test status
Simulation time 8417801033 ps
CPU time 8.32 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204096 kb
Host smart-400a070d-e5d7-4421-a91e-c2b96a4b6562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45085
1714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.450851714
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1669206553
Short name T979
Test name
Test status
Simulation time 8489497064 ps
CPU time 8.63 seconds
Started Apr 28 02:14:47 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204124 kb
Host smart-19de1493-80c7-466b-b1cd-1d3a3ed51357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16692
06553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1669206553
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.219263067
Short name T216
Test name
Test status
Simulation time 8419353464 ps
CPU time 8.51 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204124 kb
Host smart-801273b0-4603-49fd-939b-0abedd91a552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21926
3067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.219263067
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2863976774
Short name T1031
Test name
Test status
Simulation time 8408822135 ps
CPU time 9.46 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204168 kb
Host smart-35366157-6153-495d-91f1-dfdcb2fbd8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28639
76774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2863976774
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2346587404
Short name T848
Test name
Test status
Simulation time 8376476303 ps
CPU time 10.68 seconds
Started Apr 28 02:14:58 PM PDT 24
Finished Apr 28 02:15:09 PM PDT 24
Peak memory 204032 kb
Host smart-885f198a-1dce-47be-b046-1159d3823a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
87404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2346587404
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2246938059
Short name T352
Test name
Test status
Simulation time 8478907426 ps
CPU time 7.97 seconds
Started Apr 28 02:14:49 PM PDT 24
Finished Apr 28 02:14:57 PM PDT 24
Peak memory 204100 kb
Host smart-8bd5f15c-db8d-431b-ba0c-0c00dce0261b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
38059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2246938059
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.4292045133
Short name T327
Test name
Test status
Simulation time 8379323568 ps
CPU time 7.65 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 204064 kb
Host smart-d2693c09-26ab-4fa4-bbc5-8b4ca076f21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42920
45133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.4292045133
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2466142837
Short name T849
Test name
Test status
Simulation time 8376589267 ps
CPU time 7.48 seconds
Started Apr 28 02:14:48 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204120 kb
Host smart-beef249b-7402-425c-bc3b-e6c9990eb56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24661
42837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2466142837
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3458395120
Short name T355
Test name
Test status
Simulation time 8459731005 ps
CPU time 7.89 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204120 kb
Host smart-0ec461f5-ce9a-4948-89fe-a0a4e1f283e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3458395120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3458395120
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3693220133
Short name T986
Test name
Test status
Simulation time 8392596237 ps
CPU time 8.98 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204140 kb
Host smart-c7564c45-6810-4525-acb2-2979564c2394
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3693220133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3693220133
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1258850656
Short name T1150
Test name
Test status
Simulation time 8396536158 ps
CPU time 7.45 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204152 kb
Host smart-4dbf5e95-f740-45e2-b8b9-29226376833c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12588
50656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1258850656
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1237834203
Short name T853
Test name
Test status
Simulation time 8378588824 ps
CPU time 8.42 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204124 kb
Host smart-9d30205a-fe42-4314-9908-ebcc66ec1040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
34203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1237834203
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3487849187
Short name T422
Test name
Test status
Simulation time 8395234022 ps
CPU time 9.56 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204076 kb
Host smart-a472fd33-723f-4880-8b21-eda124533483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34878
49187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3487849187
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.968245078
Short name T1175
Test name
Test status
Simulation time 136665783 ps
CPU time 1.63 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:14:53 PM PDT 24
Peak memory 204164 kb
Host smart-81a8db51-bd38-4396-91b6-c9967118326e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96824
5078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.968245078
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.607251135
Short name T349
Test name
Test status
Simulation time 8389192634 ps
CPU time 9.56 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204160 kb
Host smart-69d52a23-5c42-402a-ae98-ded224168865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60725
1135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.607251135
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1805007891
Short name T6
Test name
Test status
Simulation time 8367579190 ps
CPU time 7.99 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204100 kb
Host smart-d26f02ac-6e73-4d22-9be0-26342c39096b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18050
07891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1805007891
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1026775088
Short name T137
Test name
Test status
Simulation time 8394850862 ps
CPU time 7.27 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:14:59 PM PDT 24
Peak memory 204108 kb
Host smart-fac099fa-2b88-48c8-9171-d17f7be64475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
75088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1026775088
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1252954840
Short name T1136
Test name
Test status
Simulation time 8433542767 ps
CPU time 8.34 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 204096 kb
Host smart-a41b0f46-646d-4156-82ef-82bf0a4a3a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12529
54840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1252954840
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.569101480
Short name T1030
Test name
Test status
Simulation time 8380509467 ps
CPU time 10.44 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204084 kb
Host smart-715e56e4-b633-4683-aaa4-a40f2dadb7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56910
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.569101480
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3809305855
Short name T1121
Test name
Test status
Simulation time 8433731726 ps
CPU time 7.31 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204128 kb
Host smart-8d0feb1b-cb75-4511-904f-52f1cd78b0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38093
05855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3809305855
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3370265479
Short name T1306
Test name
Test status
Simulation time 8399576471 ps
CPU time 8.5 seconds
Started Apr 28 02:14:58 PM PDT 24
Finished Apr 28 02:15:07 PM PDT 24
Peak memory 204040 kb
Host smart-6d3b20c4-4f99-4812-8d34-15bfc5befe66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33702
65479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3370265479
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.446335353
Short name T410
Test name
Test status
Simulation time 8390325067 ps
CPU time 10.15 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204156 kb
Host smart-4e4023f4-7176-409d-9a05-218effd68420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44633
5353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.446335353
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2825141116
Short name T673
Test name
Test status
Simulation time 8398090937 ps
CPU time 7.47 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 204108 kb
Host smart-388f60db-7dd5-45e5-9d8f-bd90e695cf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28251
41116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2825141116
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1292514874
Short name T491
Test name
Test status
Simulation time 8395350325 ps
CPU time 8.09 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204112 kb
Host smart-08535c9f-9b50-4784-a44d-c577abba25ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12925
14874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1292514874
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2130968495
Short name T221
Test name
Test status
Simulation time 50465464 ps
CPU time 0.66 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:14:56 PM PDT 24
Peak memory 204016 kb
Host smart-bd357f10-c16b-4815-9351-0c8825d4c645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
68495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2130968495
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1934080082
Short name T588
Test name
Test status
Simulation time 8371457157 ps
CPU time 9.04 seconds
Started Apr 28 02:14:52 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204160 kb
Host smart-9c8225c9-1338-4285-bb87-b791b9598199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340
80082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1934080082
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3898623834
Short name T155
Test name
Test status
Simulation time 8458334096 ps
CPU time 9.27 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 203908 kb
Host smart-acf89937-f78b-4461-adbe-3846b171ed46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38986
23834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3898623834
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1949325975
Short name T993
Test name
Test status
Simulation time 8386688393 ps
CPU time 8.89 seconds
Started Apr 28 02:14:51 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204084 kb
Host smart-3e9f9e31-7b9b-4f69-8424-1b8365baa9fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
25975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1949325975
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1875534095
Short name T49
Test name
Test status
Simulation time 8375788394 ps
CPU time 7.72 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:05 PM PDT 24
Peak memory 204112 kb
Host smart-ab6f4bad-4dbf-4c32-9046-b93fb6ead3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18755
34095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1875534095
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3042668928
Short name T407
Test name
Test status
Simulation time 8372722502 ps
CPU time 8.28 seconds
Started Apr 28 02:14:55 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204076 kb
Host smart-acc1fe6c-bcff-4bfd-a902-329c08fab9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30426
68928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3042668928
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2641836500
Short name T139
Test name
Test status
Simulation time 8464906382 ps
CPU time 8.57 seconds
Started Apr 28 02:14:50 PM PDT 24
Finished Apr 28 02:15:00 PM PDT 24
Peak memory 204144 kb
Host smart-90593594-3b7d-425f-a0ee-9918f7597b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418
36500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2641836500
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1461290161
Short name T663
Test name
Test status
Simulation time 8406091589 ps
CPU time 7.69 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204168 kb
Host smart-7415a891-eae6-4720-aa55-08176be66929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
90161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1461290161
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1339779493
Short name T527
Test name
Test status
Simulation time 8408413842 ps
CPU time 8.61 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204168 kb
Host smart-98e50bb1-1f29-41e0-abfe-85585f6922d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13397
79493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1339779493
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2682289999
Short name T631
Test name
Test status
Simulation time 8458344357 ps
CPU time 7.84 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 203992 kb
Host smart-ff5e624b-2531-40e5-b948-6b71efe5fee2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2682289999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2682289999
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.54767071
Short name T1197
Test name
Test status
Simulation time 8382686572 ps
CPU time 8.29 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:10 PM PDT 24
Peak memory 204116 kb
Host smart-86763c79-15b2-43a5-a111-596a07875850
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=54767071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.54767071
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.220972255
Short name T537
Test name
Test status
Simulation time 8402013962 ps
CPU time 8.36 seconds
Started Apr 28 02:14:55 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204112 kb
Host smart-bdddcf19-9284-45a0-8620-0a477e778692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22097
2255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.220972255
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.418753109
Short name T741
Test name
Test status
Simulation time 8375156877 ps
CPU time 9.76 seconds
Started Apr 28 02:14:50 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204076 kb
Host smart-ba0ba3fe-4aa3-4cae-b6c1-3b76ffaa9ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
3109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.418753109
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.485380632
Short name T679
Test name
Test status
Simulation time 8379912600 ps
CPU time 7.86 seconds
Started Apr 28 02:14:54 PM PDT 24
Finished Apr 28 02:15:02 PM PDT 24
Peak memory 204088 kb
Host smart-8bb1609b-2cc7-45d6-8774-b11bbd5cdad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48538
0632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.485380632
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2607134900
Short name T1092
Test name
Test status
Simulation time 63818858 ps
CPU time 1.62 seconds
Started Apr 28 02:14:59 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204208 kb
Host smart-bbfae9e6-5f8f-4299-b44a-8a60151a2808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26071
34900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2607134900
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1651522943
Short name T699
Test name
Test status
Simulation time 8453870713 ps
CPU time 8.04 seconds
Started Apr 28 02:14:55 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204116 kb
Host smart-71980551-260c-4a0a-a8bb-4b50e22027c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
22943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1651522943
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1758436205
Short name T1284
Test name
Test status
Simulation time 8364511062 ps
CPU time 9.93 seconds
Started Apr 28 02:14:57 PM PDT 24
Finished Apr 28 02:15:08 PM PDT 24
Peak memory 204068 kb
Host smart-650d8f51-a049-4d1d-b7e8-68d33dd0ccd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17584
36205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1758436205
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1072930855
Short name T151
Test name
Test status
Simulation time 8448486285 ps
CPU time 8.34 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204120 kb
Host smart-d68ea136-02fe-4d40-868e-252c14cc523c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729
30855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1072930855
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1920070581
Short name T1078
Test name
Test status
Simulation time 8424751271 ps
CPU time 8.71 seconds
Started Apr 28 02:14:57 PM PDT 24
Finished Apr 28 02:15:06 PM PDT 24
Peak memory 204044 kb
Host smart-9c6f0a9c-6eed-4c12-8518-2fab49b22665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19200
70581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1920070581
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.443832518
Short name T287
Test name
Test status
Simulation time 8371037297 ps
CPU time 7.53 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204084 kb
Host smart-54d160f1-266e-4773-bf6b-8b5d593e1e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44383
2518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.443832518
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.529961652
Short name T809
Test name
Test status
Simulation time 8386821133 ps
CPU time 8.64 seconds
Started Apr 28 02:14:59 PM PDT 24
Finished Apr 28 02:15:09 PM PDT 24
Peak memory 204128 kb
Host smart-fbe20bf1-75d8-49bd-9a95-cc89d3080dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52996
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.529961652
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3530655119
Short name T1239
Test name
Test status
Simulation time 8399753389 ps
CPU time 7.96 seconds
Started Apr 28 02:14:59 PM PDT 24
Finished Apr 28 02:15:07 PM PDT 24
Peak memory 204160 kb
Host smart-c6720fe8-66bc-45fd-8969-a4b9c747a6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
55119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3530655119
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.568295263
Short name T178
Test name
Test status
Simulation time 8417596387 ps
CPU time 8.04 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204092 kb
Host smart-3ef4e35d-985c-4ef6-9466-70a9e03cd141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56829
5263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.568295263
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.4128185428
Short name T1072
Test name
Test status
Simulation time 8368781187 ps
CPU time 7.84 seconds
Started Apr 28 02:14:55 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204076 kb
Host smart-fa906eab-354b-4483-ba0d-82be737ca880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
85428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.4128185428
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2444862582
Short name T1117
Test name
Test status
Simulation time 34070013 ps
CPU time 0.68 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:14:58 PM PDT 24
Peak memory 204008 kb
Host smart-966d6361-b4e2-4642-b103-9840adef6994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24448
62582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2444862582
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3018419060
Short name T14
Test name
Test status
Simulation time 21680304019 ps
CPU time 42.54 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:40 PM PDT 24
Peak memory 204348 kb
Host smart-fa266fe3-0e54-4888-b370-a0736156d75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30184
19060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3018419060
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2851077722
Short name T554
Test name
Test status
Simulation time 8421931994 ps
CPU time 8.06 seconds
Started Apr 28 02:14:58 PM PDT 24
Finished Apr 28 02:15:06 PM PDT 24
Peak memory 204128 kb
Host smart-a245e7e8-fe03-411f-8210-e378b2740389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
77722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2851077722
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1801462757
Short name T752
Test name
Test status
Simulation time 8447733386 ps
CPU time 10.26 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204072 kb
Host smart-b98f2ff3-bddb-4704-9350-1be546a463c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18014
62757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1801462757
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.452434422
Short name T1317
Test name
Test status
Simulation time 8382449703 ps
CPU time 9.05 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:06 PM PDT 24
Peak memory 204116 kb
Host smart-25c2ddc8-c4e6-4c87-9418-ff585f594de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45243
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.452434422
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2620433179
Short name T561
Test name
Test status
Simulation time 8378941751 ps
CPU time 7.74 seconds
Started Apr 28 02:14:58 PM PDT 24
Finished Apr 28 02:15:06 PM PDT 24
Peak memory 204112 kb
Host smart-0bb1d64f-7b1f-4efd-84dd-1476a19caafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26204
33179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2620433179
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.4084888365
Short name T27
Test name
Test status
Simulation time 8362285872 ps
CPU time 7.57 seconds
Started Apr 28 02:14:55 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204140 kb
Host smart-c44ba194-123b-4837-9c47-afdfa0b595c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
88365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.4084888365
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2998672311
Short name T973
Test name
Test status
Simulation time 8448409839 ps
CPU time 7.92 seconds
Started Apr 28 02:14:53 PM PDT 24
Finished Apr 28 02:15:01 PM PDT 24
Peak memory 204116 kb
Host smart-afe62f9a-33ee-4356-89ca-3d3a742be8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29986
72311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2998672311
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1532342322
Short name T425
Test name
Test status
Simulation time 8388850282 ps
CPU time 8.68 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:10 PM PDT 24
Peak memory 204112 kb
Host smart-76be29b8-b1f6-45c6-9979-42d853a7e9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
42322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1532342322
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2526244745
Short name T811
Test name
Test status
Simulation time 8405866746 ps
CPU time 8.54 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:09 PM PDT 24
Peak memory 204080 kb
Host smart-38fc24f9-aa8a-4620-b804-b782bdbfd295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25262
44745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2526244745
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.1106270199
Short name T446
Test name
Test status
Simulation time 8458454336 ps
CPU time 8.03 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204120 kb
Host smart-372ab465-7c46-4341-8c69-2f557d5411e1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1106270199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.1106270199
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.729392303
Short name T1106
Test name
Test status
Simulation time 8375847664 ps
CPU time 7.69 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204068 kb
Host smart-2a3e85f8-13f6-45d1-b9e3-0be98248826f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=729392303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.729392303
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3746496775
Short name T377
Test name
Test status
Simulation time 8421976769 ps
CPU time 7.64 seconds
Started Apr 28 02:15:02 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204020 kb
Host smart-0b415908-81c8-470e-b24d-abb8d4e28333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464
96775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3746496775
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3373774970
Short name T472
Test name
Test status
Simulation time 8381246021 ps
CPU time 8.2 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 203996 kb
Host smart-dfdad20c-3855-41cb-9ebc-3197b40d9edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33737
74970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3373774970
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.2013894879
Short name T748
Test name
Test status
Simulation time 8381458528 ps
CPU time 7.79 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:09 PM PDT 24
Peak memory 204156 kb
Host smart-deaec5c1-8599-479c-a5a4-eb776d601845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20138
94879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2013894879
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1785768573
Short name T1009
Test name
Test status
Simulation time 73162801 ps
CPU time 1.87 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 204248 kb
Host smart-c4e1ffda-904f-46e8-bf45-49a63d96c988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17857
68573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1785768573
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2956028783
Short name T145
Test name
Test status
Simulation time 8442344635 ps
CPU time 7.45 seconds
Started Apr 28 02:15:02 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204108 kb
Host smart-15bd319a-bc0e-4d11-a000-b7378d0b6a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
28783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2956028783
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.456180026
Short name T188
Test name
Test status
Simulation time 8366859581 ps
CPU time 7.88 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204076 kb
Host smart-12dfe554-9c79-4dfd-b38b-6f5b0152a43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45618
0026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.456180026
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1591695080
Short name T868
Test name
Test status
Simulation time 8453388770 ps
CPU time 7.56 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:09 PM PDT 24
Peak memory 204084 kb
Host smart-55e7e783-800e-4ffe-8b47-b0d75ebba511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15916
95080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1591695080
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.4244694126
Short name T1134
Test name
Test status
Simulation time 8427359581 ps
CPU time 8.02 seconds
Started Apr 28 02:14:58 PM PDT 24
Finished Apr 28 02:15:06 PM PDT 24
Peak memory 204088 kb
Host smart-0bdae876-2573-44ec-9283-3b96b7b00fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42446
94126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4244694126
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3008938095
Short name T708
Test name
Test status
Simulation time 8368577660 ps
CPU time 8.46 seconds
Started Apr 28 02:14:58 PM PDT 24
Finished Apr 28 02:15:07 PM PDT 24
Peak memory 204100 kb
Host smart-e5e67a5e-fab8-4948-a971-ebfd37414db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30089
38095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3008938095
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2303281108
Short name T942
Test name
Test status
Simulation time 8424347886 ps
CPU time 9.05 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204156 kb
Host smart-157a18b3-4ccb-47f7-a229-b3a439198df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23032
81108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2303281108
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1409459822
Short name T435
Test name
Test status
Simulation time 8402662472 ps
CPU time 8.52 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:06 PM PDT 24
Peak memory 204112 kb
Host smart-a6ae4109-36c7-48ea-8e5a-aec7b98dbe34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14094
59822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1409459822
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2026745603
Short name T582
Test name
Test status
Simulation time 8414178503 ps
CPU time 7.67 seconds
Started Apr 28 02:14:55 PM PDT 24
Finished Apr 28 02:15:03 PM PDT 24
Peak memory 204120 kb
Host smart-35909060-f792-4dd0-a689-7f29e0ec0b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20267
45603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2026745603
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3988506371
Short name T196
Test name
Test status
Simulation time 8389319127 ps
CPU time 8.02 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204124 kb
Host smart-a82a4720-bddd-4ba6-ae0c-7c6191799c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
06371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3988506371
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2348899040
Short name T394
Test name
Test status
Simulation time 8367971664 ps
CPU time 8.18 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204096 kb
Host smart-ce047a11-7688-457a-a3e6-0709d7526456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23488
99040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2348899040
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.935267550
Short name T672
Test name
Test status
Simulation time 138530738 ps
CPU time 0.75 seconds
Started Apr 28 02:15:02 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 203972 kb
Host smart-22069226-e377-4223-8b6d-e368f5c5098a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93526
7550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.935267550
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.604053534
Short name T239
Test name
Test status
Simulation time 15161307921 ps
CPU time 24.88 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:28 PM PDT 24
Peak memory 204288 kb
Host smart-834e3b1d-ec69-406f-9b81-6cba21dbc1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60405
3534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.604053534
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2976120360
Short name T1199
Test name
Test status
Simulation time 8421100598 ps
CPU time 7.85 seconds
Started Apr 28 02:14:56 PM PDT 24
Finished Apr 28 02:15:05 PM PDT 24
Peak memory 204112 kb
Host smart-417d1db1-8bbd-4b25-8ec1-16151b2fa936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
20360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2976120360
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.124414289
Short name T375
Test name
Test status
Simulation time 8424474140 ps
CPU time 7.24 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204116 kb
Host smart-41b23665-372e-4cb8-896e-e8676e9d2daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
4289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.124414289
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3012226272
Short name T305
Test name
Test status
Simulation time 8414844571 ps
CPU time 9.63 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204084 kb
Host smart-d0cea87d-9c78-4741-acc0-6e3ce86fc9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30122
26272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3012226272
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1380528574
Short name T166
Test name
Test status
Simulation time 8378869808 ps
CPU time 8.32 seconds
Started Apr 28 02:15:02 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204076 kb
Host smart-d28ef817-46e9-4380-bf52-f31ca3184bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
28574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1380528574
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1453239467
Short name T1063
Test name
Test status
Simulation time 8367420970 ps
CPU time 8.27 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204028 kb
Host smart-ca8e418b-8657-4c63-a84b-47395d08862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14532
39467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1453239467
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2849052171
Short name T387
Test name
Test status
Simulation time 8426580859 ps
CPU time 8.37 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204156 kb
Host smart-ed0a2227-1664-473b-8fbe-3df41f8f9a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
52171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2849052171
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.21808644
Short name T616
Test name
Test status
Simulation time 8389073500 ps
CPU time 7.35 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204080 kb
Host smart-bd53e552-0d3b-4cc1-9bae-aff39fc3ec36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21808
644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.21808644
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.641585293
Short name T290
Test name
Test status
Simulation time 8402252670 ps
CPU time 8.23 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204104 kb
Host smart-5294ebd2-adbd-4e96-99e6-86ae783bff31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64158
5293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.641585293
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.3794389239
Short name T966
Test name
Test status
Simulation time 8469661287 ps
CPU time 9.14 seconds
Started Apr 28 02:15:08 PM PDT 24
Finished Apr 28 02:15:19 PM PDT 24
Peak memory 204116 kb
Host smart-2717c5e9-5195-4a8a-bd9b-c3bf3f673833
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3794389239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.3794389239
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.1996831031
Short name T401
Test name
Test status
Simulation time 8387503110 ps
CPU time 7.79 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204164 kb
Host smart-30cb3722-e641-4b02-a124-b095f44c6782
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1996831031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.1996831031
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1330732647
Short name T540
Test name
Test status
Simulation time 8455340375 ps
CPU time 7.91 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204092 kb
Host smart-171e4aec-5b5e-482d-96cf-432865721a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13307
32647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1330732647
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.270934410
Short name T620
Test name
Test status
Simulation time 8379774819 ps
CPU time 8.41 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204140 kb
Host smart-7d6ed01e-a66c-4e06-8899-c66d3bf8048a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27093
4410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.270934410
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.726510592
Short name T1307
Test name
Test status
Simulation time 8388100348 ps
CPU time 7.8 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204076 kb
Host smart-43533b6f-52a2-46c2-9099-76cd64ab79a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72651
0592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.726510592
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.541581489
Short name T914
Test name
Test status
Simulation time 99937201 ps
CPU time 1.13 seconds
Started Apr 28 02:15:02 PM PDT 24
Finished Apr 28 02:15:05 PM PDT 24
Peak memory 204228 kb
Host smart-267fda12-6bfb-4cd2-8fc1-3baae4b50cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54158
1489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.541581489
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2708205176
Short name T365
Test name
Test status
Simulation time 8392669156 ps
CPU time 8.9 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204112 kb
Host smart-a5f1bd01-182d-4e9d-af26-302d05175118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27082
05176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2708205176
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.4256267449
Short name T895
Test name
Test status
Simulation time 8378518470 ps
CPU time 8.45 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204120 kb
Host smart-e3484c5a-3739-4f8f-a755-4c39c890e94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42562
67449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.4256267449
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3524019087
Short name T852
Test name
Test status
Simulation time 8445681656 ps
CPU time 7.62 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204072 kb
Host smart-f43cfbc2-bf20-4260-acb4-f5bda08a4fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35240
19087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3524019087
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.157612415
Short name T1034
Test name
Test status
Simulation time 8419038979 ps
CPU time 7.59 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204136 kb
Host smart-cb70c97a-fe27-43f4-9a8b-3aa4d15ff296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15761
2415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.157612415
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3501627902
Short name T440
Test name
Test status
Simulation time 8368621241 ps
CPU time 9.56 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204072 kb
Host smart-0e25d805-45a7-4412-af96-13def73ca513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
27902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3501627902
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3569121592
Short name T998
Test name
Test status
Simulation time 8488234350 ps
CPU time 7.96 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204064 kb
Host smart-9c6a87dd-9de2-4c18-999b-d1a2361a1648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35691
21592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3569121592
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.779793298
Short name T1201
Test name
Test status
Simulation time 8402612026 ps
CPU time 8.11 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204104 kb
Host smart-73070a51-e250-4896-9fe8-7837ed3be41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77979
3298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.779793298
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.367476657
Short name T1379
Test name
Test status
Simulation time 8407758624 ps
CPU time 7.69 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204144 kb
Host smart-e8b638fc-37c6-409d-8013-a68d5c1a07da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
6657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.367476657
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.630621793
Short name T902
Test name
Test status
Simulation time 8365694514 ps
CPU time 9.04 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204120 kb
Host smart-ec680c06-a82d-47be-9f38-90d6df383d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63062
1793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.630621793
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2032418794
Short name T835
Test name
Test status
Simulation time 56588960 ps
CPU time 0.69 seconds
Started Apr 28 02:15:02 PM PDT 24
Finished Apr 28 02:15:04 PM PDT 24
Peak memory 203876 kb
Host smart-d0da18f8-4fae-4cf0-859f-371c7eed6a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20324
18794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2032418794
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.4266638080
Short name T817
Test name
Test status
Simulation time 28838549895 ps
CPU time 57.2 seconds
Started Apr 28 02:15:00 PM PDT 24
Finished Apr 28 02:15:59 PM PDT 24
Peak memory 204368 kb
Host smart-91376e2c-078e-476d-a193-9a34c2da01ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
38080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.4266638080
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2263296893
Short name T772
Test name
Test status
Simulation time 8456110567 ps
CPU time 9.57 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204104 kb
Host smart-f806e34c-4afb-4db4-89e8-b73cdb8e4447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22632
96893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2263296893
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.182583528
Short name T73
Test name
Test status
Simulation time 8407279844 ps
CPU time 8.06 seconds
Started Apr 28 02:15:01 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204136 kb
Host smart-4c51db5f-b2fd-4431-b971-50aee1a3b81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18258
3528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.182583528
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3663117215
Short name T1138
Test name
Test status
Simulation time 8408606899 ps
CPU time 8.39 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204000 kb
Host smart-f92e12ea-92f1-4a0a-882a-f288d90e1acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
17215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3663117215
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2835584099
Short name T1094
Test name
Test status
Simulation time 8378084086 ps
CPU time 8.01 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204000 kb
Host smart-eaaea595-2592-4b7d-ac38-f90b5ffc3ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28355
84099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2835584099
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2379114449
Short name T1216
Test name
Test status
Simulation time 8415253657 ps
CPU time 7.75 seconds
Started Apr 28 02:15:03 PM PDT 24
Finished Apr 28 02:15:12 PM PDT 24
Peak memory 204168 kb
Host smart-6d764067-257e-45c3-bcd3-f2ef34f49f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
14449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2379114449
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1684550337
Short name T1362
Test name
Test status
Simulation time 8450423209 ps
CPU time 7.71 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204100 kb
Host smart-fe7b7ebc-42e7-4c7c-8488-88c58b0c9660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
50337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1684550337
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.51487606
Short name T1055
Test name
Test status
Simulation time 8408738178 ps
CPU time 7.88 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204108 kb
Host smart-c1fc5094-52c6-4d11-b786-144c82c18e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51487
606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.51487606
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3464583476
Short name T1225
Test name
Test status
Simulation time 8412556727 ps
CPU time 8.5 seconds
Started Apr 28 02:15:04 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204120 kb
Host smart-d1d6d54f-2f02-4743-943f-bc99b02e1c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34645
83476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3464583476
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1238815205
Short name T936
Test name
Test status
Simulation time 8466285018 ps
CPU time 8.52 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204108 kb
Host smart-aa463a77-288f-4460-8d30-66a25397fb91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1238815205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1238815205
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.3216428360
Short name T668
Test name
Test status
Simulation time 8379978697 ps
CPU time 7.35 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204152 kb
Host smart-69afabf2-451b-46dd-923e-4a787ef948da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3216428360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.3216428360
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.4207216034
Short name T1259
Test name
Test status
Simulation time 8387273694 ps
CPU time 7.83 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204052 kb
Host smart-0898e780-3367-4e94-a7de-5fe249bb6976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
16034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.4207216034
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1228885613
Short name T424
Test name
Test status
Simulation time 8429274903 ps
CPU time 8.21 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:15:18 PM PDT 24
Peak memory 204148 kb
Host smart-d3d6cd9e-701a-4c76-9a68-917bf216bc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
85613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1228885613
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.660300443
Short name T757
Test name
Test status
Simulation time 8375953247 ps
CPU time 8.6 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:15:18 PM PDT 24
Peak memory 204008 kb
Host smart-a139de73-41ca-45c5-8f85-0be3ff766294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66030
0443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.660300443
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.925864635
Short name T830
Test name
Test status
Simulation time 194075330 ps
CPU time 1.95 seconds
Started Apr 28 02:15:08 PM PDT 24
Finished Apr 28 02:15:11 PM PDT 24
Peak memory 204148 kb
Host smart-b355b376-bb27-442b-8a3a-6473cb486e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92586
4635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.925864635
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3007657451
Short name T972
Test name
Test status
Simulation time 8500588679 ps
CPU time 8.51 seconds
Started Apr 28 02:15:10 PM PDT 24
Finished Apr 28 02:15:19 PM PDT 24
Peak memory 204080 kb
Host smart-1c5e03f4-c955-4a4e-9155-1a715f461f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30076
57451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3007657451
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3173175448
Short name T556
Test name
Test status
Simulation time 8384181572 ps
CPU time 8.22 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:15:18 PM PDT 24
Peak memory 204120 kb
Host smart-52dbb685-7a38-42f4-bb3c-0bee057b98bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31731
75448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3173175448
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4120307351
Short name T500
Test name
Test status
Simulation time 8404259618 ps
CPU time 10.1 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204092 kb
Host smart-cfb7c66c-4628-4a9f-9de3-8ae47ad8a3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41203
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4120307351
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1906846406
Short name T7
Test name
Test status
Simulation time 8416878763 ps
CPU time 7.79 seconds
Started Apr 28 02:15:08 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204096 kb
Host smart-1b84d26a-2b51-44b4-b482-21589d3ba8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19068
46406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1906846406
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2346086871
Short name T342
Test name
Test status
Simulation time 8370565454 ps
CPU time 7.28 seconds
Started Apr 28 02:15:08 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204096 kb
Host smart-b2a9dade-c87f-4882-998f-322e6fab7ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23460
86871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2346086871
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3123468238
Short name T107
Test name
Test status
Simulation time 8440226013 ps
CPU time 8.96 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:15:19 PM PDT 24
Peak memory 204088 kb
Host smart-324bd6b6-6c33-4ae8-a016-910fb31feb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31234
68238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3123468238
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.423557963
Short name T1348
Test name
Test status
Simulation time 8417311015 ps
CPU time 7.65 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204108 kb
Host smart-d63b0fbf-5496-446a-a7f1-b1004d9f2531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355
7963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.423557963
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3509860824
Short name T1269
Test name
Test status
Simulation time 8405295423 ps
CPU time 9.49 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204096 kb
Host smart-6149794b-3178-4370-808d-dd9627966ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
60824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3509860824
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1548014101
Short name T1288
Test name
Test status
Simulation time 8386071132 ps
CPU time 9.29 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204104 kb
Host smart-393b2f5a-23dc-4e44-87e1-f906f6e96c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
14101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1548014101
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2091914687
Short name T348
Test name
Test status
Simulation time 8377772561 ps
CPU time 8.77 seconds
Started Apr 28 02:15:08 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204144 kb
Host smart-cf05b567-7fad-4c45-92b1-7d499f677af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919
14687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2091914687
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1566425513
Short name T664
Test name
Test status
Simulation time 41141463 ps
CPU time 0.67 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:15:10 PM PDT 24
Peak memory 203976 kb
Host smart-d3b8c10f-a9bf-4d91-9d43-ffebb8e6e4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
25513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1566425513
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.212145302
Short name T570
Test name
Test status
Simulation time 25750476556 ps
CPU time 58.94 seconds
Started Apr 28 02:15:09 PM PDT 24
Finished Apr 28 02:16:09 PM PDT 24
Peak memory 204372 kb
Host smart-e1fc0262-028d-4dc5-84d7-f2c5c5928333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21214
5302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.212145302
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3857077923
Short name T396
Test name
Test status
Simulation time 8471016495 ps
CPU time 9.56 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204120 kb
Host smart-f593830d-110f-44ee-94f2-230f68b68782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
77923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3857077923
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.170703715
Short name T578
Test name
Test status
Simulation time 8427841182 ps
CPU time 9.74 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204148 kb
Host smart-70f96611-ea3f-4ac5-bd90-8f729a0ae5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17070
3715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.170703715
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3888393328
Short name T1033
Test name
Test status
Simulation time 8389059869 ps
CPU time 7.73 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204132 kb
Host smart-06dddc7a-372f-4abe-95f9-7197b8cf7d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38883
93328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3888393328
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1160598714
Short name T1100
Test name
Test status
Simulation time 8390413295 ps
CPU time 8.1 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 204100 kb
Host smart-20bea58b-395d-4986-b281-fd609446409f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11605
98714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1160598714
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1399496541
Short name T1213
Test name
Test status
Simulation time 8374658611 ps
CPU time 8.69 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204120 kb
Host smart-691bdc16-a8f6-4f05-8f5a-d33f5cc4f3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13994
96541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1399496541
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1233314763
Short name T720
Test name
Test status
Simulation time 8451699656 ps
CPU time 7.87 seconds
Started Apr 28 02:15:11 PM PDT 24
Finished Apr 28 02:15:20 PM PDT 24
Peak memory 204076 kb
Host smart-a4bacfa6-c21c-4054-8d32-fadce351c508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
14763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1233314763
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.4178073621
Short name T636
Test name
Test status
Simulation time 8400259575 ps
CPU time 7.93 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204108 kb
Host smart-2be745ac-a976-4fe5-b4ad-313bfc676c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41780
73621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.4178073621
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.200367386
Short name T738
Test name
Test status
Simulation time 8378248249 ps
CPU time 7.37 seconds
Started Apr 28 02:15:08 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204136 kb
Host smart-cd562c40-537d-42ab-bc85-d3397b7a534b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036
7386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.200367386
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.2094045659
Short name T1187
Test name
Test status
Simulation time 8468311608 ps
CPU time 8.38 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 203908 kb
Host smart-87cdb97e-5073-49a4-a7d9-368fb2f4d4da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2094045659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.2094045659
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.4223908683
Short name T1065
Test name
Test status
Simulation time 8381208983 ps
CPU time 8.08 seconds
Started Apr 28 02:15:22 PM PDT 24
Finished Apr 28 02:15:31 PM PDT 24
Peak memory 204136 kb
Host smart-55bedeef-44a1-4506-ad71-9dadf39ed7fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4223908683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.4223908683
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.492974571
Short name T448
Test name
Test status
Simulation time 8467415591 ps
CPU time 8.16 seconds
Started Apr 28 02:15:22 PM PDT 24
Finished Apr 28 02:15:31 PM PDT 24
Peak memory 204028 kb
Host smart-6f561fd0-8984-4e9b-8eff-d1f63b59ce03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49297
4571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.492974571
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.959419528
Short name T1120
Test name
Test status
Simulation time 8406134735 ps
CPU time 7.98 seconds
Started Apr 28 02:15:06 PM PDT 24
Finished Apr 28 02:15:15 PM PDT 24
Peak memory 204120 kb
Host smart-22dd59f7-046e-4209-b95f-2ded37ff655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95941
9528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.959419528
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.501620239
Short name T1018
Test name
Test status
Simulation time 8386355182 ps
CPU time 7.73 seconds
Started Apr 28 02:15:05 PM PDT 24
Finished Apr 28 02:15:14 PM PDT 24
Peak memory 204140 kb
Host smart-bfef274d-6471-40d6-a2c1-6f15052ae0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50162
0239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.501620239
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.250508954
Short name T642
Test name
Test status
Simulation time 69075823 ps
CPU time 1.74 seconds
Started Apr 28 02:15:11 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204104 kb
Host smart-fcf6eda4-ed2b-44f9-822d-b7cc7a1ec169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.250508954
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3133527575
Short name T51
Test name
Test status
Simulation time 8411920723 ps
CPU time 8.2 seconds
Started Apr 28 02:15:17 PM PDT 24
Finished Apr 28 02:15:26 PM PDT 24
Peak memory 204156 kb
Host smart-bfad88b2-7af0-48fd-805c-0b837a687a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31335
27575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3133527575
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.681946951
Short name T1111
Test name
Test status
Simulation time 8368411317 ps
CPU time 8.76 seconds
Started Apr 28 02:15:16 PM PDT 24
Finished Apr 28 02:15:26 PM PDT 24
Peak memory 204140 kb
Host smart-f6baf0f5-37bc-42bf-88fd-38c6726513f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68194
6951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.681946951
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.4230891020
Short name T1184
Test name
Test status
Simulation time 8453552589 ps
CPU time 9.9 seconds
Started Apr 28 02:15:10 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 204088 kb
Host smart-b7ef0a68-add7-4d1b-95d7-fa0c5994f56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42308
91020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.4230891020
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1719610543
Short name T641
Test name
Test status
Simulation time 8419430961 ps
CPU time 10.01 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:18 PM PDT 24
Peak memory 204128 kb
Host smart-2580077f-acde-42b4-94a3-3572faccc948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
10543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1719610543
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3774237705
Short name T887
Test name
Test status
Simulation time 8365598782 ps
CPU time 7.81 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204120 kb
Host smart-7d02d3f7-6ea8-4163-a56f-fc89631709ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
37705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3774237705
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1319344148
Short name T99
Test name
Test status
Simulation time 8427646986 ps
CPU time 7.76 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204120 kb
Host smart-f5c4f057-58cf-42d0-8c85-133597829905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193
44148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1319344148
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.186351175
Short name T1007
Test name
Test status
Simulation time 8402392995 ps
CPU time 8.63 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:16 PM PDT 24
Peak memory 204112 kb
Host smart-e14f7b0d-5cbd-4281-bc9b-271bfb221287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18635
1175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.186351175
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.741076459
Short name T76
Test name
Test status
Simulation time 8419348895 ps
CPU time 8.12 seconds
Started Apr 28 02:15:13 PM PDT 24
Finished Apr 28 02:15:23 PM PDT 24
Peak memory 204120 kb
Host smart-2b72d421-ec85-445b-8ebb-3dd5c331a5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74107
6459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.741076459
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3457376154
Short name T1159
Test name
Test status
Simulation time 8414264619 ps
CPU time 7.71 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 204020 kb
Host smart-d7c7f579-2258-404b-9b8e-d2a70dfaeb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34573
76154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3457376154
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2642063607
Short name T788
Test name
Test status
Simulation time 8368905461 ps
CPU time 7.87 seconds
Started Apr 28 02:15:21 PM PDT 24
Finished Apr 28 02:15:30 PM PDT 24
Peak memory 204032 kb
Host smart-7263e30a-c8ca-4eb7-87c1-afc4df94abea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26420
63607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2642063607
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1217463545
Short name T949
Test name
Test status
Simulation time 99277764 ps
CPU time 0.72 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:13 PM PDT 24
Peak memory 204004 kb
Host smart-931c1d0c-de34-440f-9199-5427f86dbbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12174
63545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1217463545
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3477676943
Short name T1250
Test name
Test status
Simulation time 21688041187 ps
CPU time 45.51 seconds
Started Apr 28 02:15:20 PM PDT 24
Finished Apr 28 02:16:06 PM PDT 24
Peak memory 204436 kb
Host smart-6e7a6d98-960a-4f7b-b6cf-d9acb1355d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34776
76943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3477676943
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2946377161
Short name T598
Test name
Test status
Simulation time 8389124103 ps
CPU time 7.32 seconds
Started Apr 28 02:15:13 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 204108 kb
Host smart-0b8c027e-8e82-4ab1-9f28-46c7f275e806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463
77161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2946377161
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1842027207
Short name T1012
Test name
Test status
Simulation time 8405152885 ps
CPU time 7.73 seconds
Started Apr 28 02:15:14 PM PDT 24
Finished Apr 28 02:15:23 PM PDT 24
Peak memory 204136 kb
Host smart-74a06618-6719-4834-9095-1636bb7107ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
27207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1842027207
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.429251017
Short name T990
Test name
Test status
Simulation time 8404676713 ps
CPU time 7.63 seconds
Started Apr 28 02:15:21 PM PDT 24
Finished Apr 28 02:15:29 PM PDT 24
Peak memory 204036 kb
Host smart-6449e4ce-6eaf-46fb-8de8-8c5b00dcc9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925
1017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.429251017
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1479538150
Short name T1162
Test name
Test status
Simulation time 8374714219 ps
CPU time 7.92 seconds
Started Apr 28 02:15:11 PM PDT 24
Finished Apr 28 02:15:19 PM PDT 24
Peak memory 204136 kb
Host smart-32dadfbd-4f6b-447c-8d90-62ae2ac05038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14795
38150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1479538150
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3361628391
Short name T451
Test name
Test status
Simulation time 8374882455 ps
CPU time 9.54 seconds
Started Apr 28 02:15:13 PM PDT 24
Finished Apr 28 02:15:23 PM PDT 24
Peak memory 204080 kb
Host smart-21ab5969-ec60-40f6-9b85-851f1029d211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33616
28391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3361628391
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4260068976
Short name T1128
Test name
Test status
Simulation time 8447042698 ps
CPU time 9.61 seconds
Started Apr 28 02:15:07 PM PDT 24
Finished Apr 28 02:15:17 PM PDT 24
Peak memory 204136 kb
Host smart-a7d61172-09b3-4b9a-a711-d9e4c94e9a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42600
68976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4260068976
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1244414227
Short name T463
Test name
Test status
Simulation time 8422479983 ps
CPU time 7.48 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:20 PM PDT 24
Peak memory 203948 kb
Host smart-f77e0600-fc9e-429a-975d-cf74fd19fa83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12444
14227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1244414227
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2430272987
Short name T20
Test name
Test status
Simulation time 8398777810 ps
CPU time 7.52 seconds
Started Apr 28 02:15:19 PM PDT 24
Finished Apr 28 02:15:27 PM PDT 24
Peak memory 204132 kb
Host smart-13d695fa-db97-424a-a5e4-27d806333e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
72987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2430272987
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3655159601
Short name T857
Test name
Test status
Simulation time 8462610160 ps
CPU time 8.3 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204120 kb
Host smart-e90e3a5e-d30b-4a94-8430-7f2e79ddad74
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3655159601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3655159601
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.179515774
Short name T566
Test name
Test status
Simulation time 8375502311 ps
CPU time 7.66 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204040 kb
Host smart-b4ba2161-0a66-4fa5-9277-644606012bdf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=179515774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.179515774
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.1972937415
Short name T1215
Test name
Test status
Simulation time 8424563890 ps
CPU time 7.56 seconds
Started Apr 28 02:15:17 PM PDT 24
Finished Apr 28 02:15:26 PM PDT 24
Peak memory 204156 kb
Host smart-dcfcd74b-e82d-480a-a041-be8b803c3692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
37415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.1972937415
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2171143953
Short name T762
Test name
Test status
Simulation time 8370667606 ps
CPU time 7.36 seconds
Started Apr 28 02:15:19 PM PDT 24
Finished Apr 28 02:15:27 PM PDT 24
Peak memory 204136 kb
Host smart-ed81ee3a-a046-4708-bfe8-792f5c0480c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
43953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2171143953
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.4280837902
Short name T863
Test name
Test status
Simulation time 8380918537 ps
CPU time 8.96 seconds
Started Apr 28 02:15:16 PM PDT 24
Finished Apr 28 02:15:26 PM PDT 24
Peak memory 204072 kb
Host smart-7fe90ff9-786b-4e7b-a1dd-bbf8d81d8c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
37902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.4280837902
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3677803789
Short name T846
Test name
Test status
Simulation time 87740880 ps
CPU time 1.69 seconds
Started Apr 28 02:15:21 PM PDT 24
Finished Apr 28 02:15:23 PM PDT 24
Peak memory 204136 kb
Host smart-22d46fd0-2b73-4bad-a9d7-183b07a4ab5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
03789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3677803789
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2209515447
Short name T608
Test name
Test status
Simulation time 8400733910 ps
CPU time 7.72 seconds
Started Apr 28 02:15:26 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 204020 kb
Host smart-f85532df-5f35-4eb3-9e46-27dc438cc57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22095
15447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2209515447
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2425284321
Short name T75
Test name
Test status
Simulation time 8369151425 ps
CPU time 8.34 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 204000 kb
Host smart-8116abaf-da62-4316-aef0-0af24112fe21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24252
84321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2425284321
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2069494958
Short name T1154
Test name
Test status
Simulation time 8421806547 ps
CPU time 7.78 seconds
Started Apr 28 02:15:13 PM PDT 24
Finished Apr 28 02:15:22 PM PDT 24
Peak memory 204124 kb
Host smart-eb61aec2-3d69-407c-b38d-ee0dd981fe31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20694
94958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2069494958
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3947808894
Short name T651
Test name
Test status
Simulation time 8419747880 ps
CPU time 8.09 seconds
Started Apr 28 02:15:21 PM PDT 24
Finished Apr 28 02:15:30 PM PDT 24
Peak memory 204116 kb
Host smart-e8a3af5a-4059-4c9a-8547-8381df2d47c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39478
08894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3947808894
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.552325092
Short name T1183
Test name
Test status
Simulation time 8371850061 ps
CPU time 7.84 seconds
Started Apr 28 02:15:16 PM PDT 24
Finished Apr 28 02:15:25 PM PDT 24
Peak memory 204108 kb
Host smart-dae629f1-35af-442a-a53d-0886a95cf594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55232
5092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.552325092
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.954860971
Short name T1369
Test name
Test status
Simulation time 8428383858 ps
CPU time 8.05 seconds
Started Apr 28 02:15:13 PM PDT 24
Finished Apr 28 02:15:22 PM PDT 24
Peak memory 204008 kb
Host smart-8107ca3a-472b-4d27-bd00-2d13abcaa8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95486
0971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.954860971
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3443259378
Short name T606
Test name
Test status
Simulation time 8420534523 ps
CPU time 8.08 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 204104 kb
Host smart-14b66012-09e7-40d2-9996-cb1165ccb80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34432
59378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3443259378
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2241924632
Short name T926
Test name
Test status
Simulation time 8417631265 ps
CPU time 8.91 seconds
Started Apr 28 02:15:16 PM PDT 24
Finished Apr 28 02:15:26 PM PDT 24
Peak memory 204072 kb
Host smart-f6c1b1b1-89cc-4ef0-84ee-35661b8f818b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
24632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2241924632
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3977443834
Short name T529
Test name
Test status
Simulation time 8461212785 ps
CPU time 7.69 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 204092 kb
Host smart-81f64a65-2819-40df-a9fa-d06543d6a3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39774
43834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3977443834
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3819641722
Short name T539
Test name
Test status
Simulation time 8401262614 ps
CPU time 8.47 seconds
Started Apr 28 02:15:29 PM PDT 24
Finished Apr 28 02:15:38 PM PDT 24
Peak memory 204124 kb
Host smart-f678d15d-3629-4da4-882c-76313c294ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38196
41722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3819641722
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2261030213
Short name T42
Test name
Test status
Simulation time 39857144 ps
CPU time 0.65 seconds
Started Apr 28 02:15:19 PM PDT 24
Finished Apr 28 02:15:21 PM PDT 24
Peak memory 203868 kb
Host smart-63b84e4f-b3d7-4d28-83f0-9f06b3caccfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22610
30213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2261030213
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1730287225
Short name T1178
Test name
Test status
Simulation time 17627860533 ps
CPU time 31.87 seconds
Started Apr 28 02:15:15 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 204332 kb
Host smart-6c36fe89-0ec9-4ff3-9e16-6594bee37342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17302
87225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1730287225
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2622871987
Short name T1365
Test name
Test status
Simulation time 8426743954 ps
CPU time 8.42 seconds
Started Apr 28 02:15:12 PM PDT 24
Finished Apr 28 02:15:22 PM PDT 24
Peak memory 204100 kb
Host smart-9ed9e416-5b97-4843-ac9d-4783c86bf70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26228
71987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2622871987
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.462817813
Short name T1088
Test name
Test status
Simulation time 8485605698 ps
CPU time 9.46 seconds
Started Apr 28 02:15:19 PM PDT 24
Finished Apr 28 02:15:28 PM PDT 24
Peak memory 204116 kb
Host smart-1503aa91-2867-4e35-a36f-b1cb9a9c9d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46281
7813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.462817813
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.4165282283
Short name T413
Test name
Test status
Simulation time 8386393123 ps
CPU time 8.08 seconds
Started Apr 28 02:15:20 PM PDT 24
Finished Apr 28 02:15:29 PM PDT 24
Peak memory 204148 kb
Host smart-9f35e039-be1c-4098-a9c9-2a3193a4e346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41652
82283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.4165282283
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.459376665
Short name T1253
Test name
Test status
Simulation time 8379950938 ps
CPU time 8.01 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 204016 kb
Host smart-7956820c-5632-494b-96b1-9f162ee11012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45937
6665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.459376665
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.480409407
Short name T1176
Test name
Test status
Simulation time 8376108487 ps
CPU time 9.09 seconds
Started Apr 28 02:15:31 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 204152 kb
Host smart-726ffbbb-f4de-45d8-8cbb-04d7c09e23f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48040
9407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.480409407
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3542599430
Short name T152
Test name
Test status
Simulation time 8406734884 ps
CPU time 8.85 seconds
Started Apr 28 02:15:25 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 204128 kb
Host smart-49e621ae-c7e5-4424-bc6f-0e6d080ecb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
99430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3542599430
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3621581277
Short name T364
Test name
Test status
Simulation time 8399538988 ps
CPU time 10.16 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:39 PM PDT 24
Peak memory 204068 kb
Host smart-7aaf24a8-ad14-4f7c-91bf-564c5420f2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
81277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3621581277
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2574261239
Short name T1001
Test name
Test status
Simulation time 8448835131 ps
CPU time 8.8 seconds
Started Apr 28 02:15:14 PM PDT 24
Finished Apr 28 02:15:24 PM PDT 24
Peak memory 204128 kb
Host smart-ed99613f-f8b7-4269-bda4-09bb1a976978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25742
61239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2574261239
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.611616255
Short name T798
Test name
Test status
Simulation time 8463614062 ps
CPU time 7.69 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 204000 kb
Host smart-a21e1fc0-0040-43cd-bb0d-f28a490b5a01
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=611616255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.611616255
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.1563150707
Short name T799
Test name
Test status
Simulation time 8385784254 ps
CPU time 7.92 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 204128 kb
Host smart-6f17b61a-1c03-449d-93bc-64682d9dc8a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1563150707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.1563150707
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.769484092
Short name T1002
Test name
Test status
Simulation time 8400670191 ps
CPU time 8.16 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 204088 kb
Host smart-ab922539-b115-4fdc-a7dc-819eef8d652d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76948
4092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.769484092
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2628681448
Short name T1095
Test name
Test status
Simulation time 8394072816 ps
CPU time 7.33 seconds
Started Apr 28 02:15:17 PM PDT 24
Finished Apr 28 02:15:25 PM PDT 24
Peak memory 204064 kb
Host smart-534d6639-31fa-4823-a15c-fd1cadb1fda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26286
81448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2628681448
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.1461253097
Short name T1130
Test name
Test status
Simulation time 8380699241 ps
CPU time 10.25 seconds
Started Apr 28 02:15:21 PM PDT 24
Finished Apr 28 02:15:32 PM PDT 24
Peak memory 204120 kb
Host smart-b2ac5c24-fb85-4181-a479-ff2bb9fedfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
53097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1461253097
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2469147130
Short name T688
Test name
Test status
Simulation time 244035038 ps
CPU time 2.45 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 204172 kb
Host smart-544fcc23-263e-4ec2-a73d-d66c3accf584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24691
47130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2469147130
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.790319040
Short name T1339
Test name
Test status
Simulation time 8431287541 ps
CPU time 8.31 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 204004 kb
Host smart-ca0ad880-1495-4a97-962c-166956ade61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79031
9040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.790319040
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2267644313
Short name T433
Test name
Test status
Simulation time 8365769392 ps
CPU time 7.68 seconds
Started Apr 28 02:15:26 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 204004 kb
Host smart-0700afd3-9030-4071-873d-ea7ce6379c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22676
44313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2267644313
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1197632889
Short name T358
Test name
Test status
Simulation time 8415100312 ps
CPU time 8.42 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:39 PM PDT 24
Peak memory 204056 kb
Host smart-a24cf5de-07e8-4e5b-a92a-f29156bc551f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11976
32889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1197632889
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.4183388683
Short name T851
Test name
Test status
Simulation time 8446678465 ps
CPU time 7.95 seconds
Started Apr 28 02:15:26 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 204120 kb
Host smart-ffb7062f-7094-4ba2-986e-c8cfce2688fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
88683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.4183388683
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2433174259
Short name T997
Test name
Test status
Simulation time 8442131371 ps
CPU time 7.42 seconds
Started Apr 28 02:15:31 PM PDT 24
Finished Apr 28 02:15:39 PM PDT 24
Peak memory 204144 kb
Host smart-3edf2270-afe0-4502-b7cf-4343acc8ff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24331
74259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2433174259
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1856213056
Short name T129
Test name
Test status
Simulation time 8448059760 ps
CPU time 9.14 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:43 PM PDT 24
Peak memory 204008 kb
Host smart-39c16b78-6d01-45c5-b506-17959a5e74bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18562
13056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1856213056
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.679433575
Short name T624
Test name
Test status
Simulation time 8396546994 ps
CPU time 7.67 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204124 kb
Host smart-526134a9-f4d1-4a5e-aaff-65d739314de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67943
3575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.679433575
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3303410728
Short name T617
Test name
Test status
Simulation time 8394739601 ps
CPU time 8.22 seconds
Started Apr 28 02:15:32 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 204096 kb
Host smart-976f464f-b8d0-4e90-bd85-945b0e9e61ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034
10728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3303410728
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3161642124
Short name T22
Test name
Test status
Simulation time 8408144168 ps
CPU time 7.75 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204092 kb
Host smart-b710ddc9-f440-46e2-bc08-11e1a6f9178f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
42124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3161642124
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3654968253
Short name T580
Test name
Test status
Simulation time 8396887629 ps
CPU time 9.91 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:38 PM PDT 24
Peak memory 204148 kb
Host smart-d6d071e3-d0cb-4ad7-8d55-96a98c8f67a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36549
68253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3654968253
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1277501449
Short name T494
Test name
Test status
Simulation time 50879531 ps
CPU time 0.68 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:29 PM PDT 24
Peak memory 204028 kb
Host smart-988472f5-1170-4721-9b0d-9e189a40166e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12775
01449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1277501449
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1072159495
Short name T243
Test name
Test status
Simulation time 17604446062 ps
CPU time 29.52 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:58 PM PDT 24
Peak memory 204416 kb
Host smart-fd77812b-8e16-497a-9734-93bc05d33ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10721
59495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1072159495
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2620534016
Short name T382
Test name
Test status
Simulation time 8400770372 ps
CPU time 8.45 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204128 kb
Host smart-8860c8e0-ec06-4b7a-b4c1-2c35ab2b4b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26205
34016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2620534016
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1873111885
Short name T1364
Test name
Test status
Simulation time 8433089041 ps
CPU time 10.64 seconds
Started Apr 28 02:15:23 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 204072 kb
Host smart-db4a4bdd-1e20-480d-a104-1d2706f54b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18731
11885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1873111885
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3703550414
Short name T1109
Test name
Test status
Simulation time 8411594343 ps
CPU time 8.47 seconds
Started Apr 28 02:15:25 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 204068 kb
Host smart-2d92ad06-76b9-4f37-9fe7-814fdbacde9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37035
50414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3703550414
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3738629824
Short name T585
Test name
Test status
Simulation time 8377451584 ps
CPU time 7.82 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 204012 kb
Host smart-89b17f05-432e-42b8-9403-c2f8148db2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
29824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3738629824
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.4108219170
Short name T1222
Test name
Test status
Simulation time 8369588420 ps
CPU time 10.17 seconds
Started Apr 28 02:15:26 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 204080 kb
Host smart-a109b117-fdad-439e-b635-403fba966f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41082
19170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.4108219170
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2935720847
Short name T505
Test name
Test status
Simulation time 8439065970 ps
CPU time 8.09 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204064 kb
Host smart-e725a76f-0e21-4f61-a11c-b46028439c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29357
20847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2935720847
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.816782806
Short name T1064
Test name
Test status
Simulation time 8394050618 ps
CPU time 7.68 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:40 PM PDT 24
Peak memory 204068 kb
Host smart-562a869d-22ad-4af6-8696-9fb08bac4259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81678
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.816782806
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2757968955
Short name T1090
Test name
Test status
Simulation time 8428491115 ps
CPU time 7.72 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204068 kb
Host smart-57df2007-2253-43d7-9605-6bb99d2afa85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
68955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2757968955
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3047561022
Short name T1310
Test name
Test status
Simulation time 8468428059 ps
CPU time 9.56 seconds
Started Apr 28 02:15:31 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 204128 kb
Host smart-2ec94062-c051-4930-bc27-6a22dd279491
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3047561022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3047561022
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.1677492723
Short name T881
Test name
Test status
Simulation time 8382813543 ps
CPU time 8.83 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 204092 kb
Host smart-4263e06b-36d3-48b5-a8ac-8434da213656
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1677492723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.1677492723
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2901154456
Short name T381
Test name
Test status
Simulation time 8399098412 ps
CPU time 8.02 seconds
Started Apr 28 02:15:28 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204128 kb
Host smart-02518320-6edf-4694-8cfc-ae1179f72a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29011
54456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2901154456
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.563955222
Short name T770
Test name
Test status
Simulation time 8415139735 ps
CPU time 9.02 seconds
Started Apr 28 02:15:26 PM PDT 24
Finished Apr 28 02:15:36 PM PDT 24
Peak memory 204076 kb
Host smart-c470f0ae-1908-4c5f-b49e-b17d7530e332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56395
5222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.563955222
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.2907470483
Short name T1133
Test name
Test status
Simulation time 8380123025 ps
CPU time 8.29 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 204096 kb
Host smart-68ba96a7-0a94-4f28-b849-e6e70021fe18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
70483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2907470483
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.914507219
Short name T1131
Test name
Test status
Simulation time 218598548 ps
CPU time 1.69 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 204172 kb
Host smart-0fa0c028-33e7-46a1-84a6-e9e4e9c43d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91450
7219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.914507219
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2369183472
Short name T522
Test name
Test status
Simulation time 8442382197 ps
CPU time 8.37 seconds
Started Apr 28 02:15:35 PM PDT 24
Finished Apr 28 02:15:44 PM PDT 24
Peak memory 204112 kb
Host smart-68652212-4173-4b6c-bf50-9e66111fbad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
83472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2369183472
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2859949151
Short name T180
Test name
Test status
Simulation time 8377265283 ps
CPU time 9.09 seconds
Started Apr 28 02:15:34 PM PDT 24
Finished Apr 28 02:15:44 PM PDT 24
Peak memory 204160 kb
Host smart-1c04fb01-36b3-4599-8a50-2b6ccb62160e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
49151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2859949151
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1399095441
Short name T1004
Test name
Test status
Simulation time 8403634456 ps
CPU time 9.35 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:40 PM PDT 24
Peak memory 204132 kb
Host smart-929b1487-bae3-418d-860e-6b5d137958ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
95441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1399095441
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.430782538
Short name T311
Test name
Test status
Simulation time 8421902829 ps
CPU time 8.26 seconds
Started Apr 28 02:15:23 PM PDT 24
Finished Apr 28 02:15:31 PM PDT 24
Peak memory 204096 kb
Host smart-b02d4a37-881e-4397-985a-3de6dec426ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43078
2538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.430782538
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.762986316
Short name T962
Test name
Test status
Simulation time 8370638924 ps
CPU time 8.06 seconds
Started Apr 28 02:15:29 PM PDT 24
Finished Apr 28 02:15:38 PM PDT 24
Peak memory 204084 kb
Host smart-2e5278ad-cd00-4b80-b5ea-968225397677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76298
6316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.762986316
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2945635252
Short name T121
Test name
Test status
Simulation time 8441329195 ps
CPU time 8.12 seconds
Started Apr 28 02:15:24 PM PDT 24
Finished Apr 28 02:15:33 PM PDT 24
Peak memory 204084 kb
Host smart-d02897f7-5356-4ca1-8550-fc869e22a9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29456
35252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2945635252
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3541185036
Short name T789
Test name
Test status
Simulation time 8410228473 ps
CPU time 7.44 seconds
Started Apr 28 02:15:36 PM PDT 24
Finished Apr 28 02:15:44 PM PDT 24
Peak memory 204108 kb
Host smart-b4f56fe8-f09e-4300-b9f8-adaf4387c528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35411
85036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3541185036
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3210153243
Short name T1227
Test name
Test status
Simulation time 8413880388 ps
CPU time 7.99 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:58 PM PDT 24
Peak memory 204104 kb
Host smart-85895d9a-4550-43d0-b4fc-59a10bb5dc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32101
53243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3210153243
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1147513607
Short name T168
Test name
Test status
Simulation time 8391839312 ps
CPU time 7.84 seconds
Started Apr 28 02:15:29 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 204076 kb
Host smart-d0dc111a-1cd2-465b-ac0a-d9e089e1a23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11475
13607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1147513607
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3953629108
Short name T24
Test name
Test status
Simulation time 8368258781 ps
CPU time 7.35 seconds
Started Apr 28 02:15:29 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 203632 kb
Host smart-a3bf6fba-d109-4af0-bfaf-6a367b0100f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39536
29108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3953629108
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4223048396
Short name T662
Test name
Test status
Simulation time 55555747 ps
CPU time 0.65 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:45 PM PDT 24
Peak memory 203964 kb
Host smart-1c7d0c71-dfad-4922-b7f1-5cebf80d4cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42230
48396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4223048396
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2302180553
Short name T1041
Test name
Test status
Simulation time 26992574634 ps
CPU time 49.2 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 204404 kb
Host smart-5005b5db-3654-40e0-84e7-465f2ff10851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23021
80553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2302180553
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3702751477
Short name T318
Test name
Test status
Simulation time 8422092056 ps
CPU time 8.01 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 204112 kb
Host smart-08834122-ec71-421e-a47e-56e031e6346f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37027
51477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3702751477
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1331783112
Short name T372
Test name
Test status
Simulation time 8462708807 ps
CPU time 7.84 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 204036 kb
Host smart-f68596fe-ba95-432c-a906-c64e30565b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13317
83112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1331783112
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2377483304
Short name T504
Test name
Test status
Simulation time 8415446293 ps
CPU time 7.96 seconds
Started Apr 28 02:15:25 PM PDT 24
Finished Apr 28 02:15:33 PM PDT 24
Peak memory 204084 kb
Host smart-b09e3510-62f2-4e06-a8fc-1c929c99a8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774
83304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2377483304
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3406298840
Short name T1207
Test name
Test status
Simulation time 8383693481 ps
CPU time 7.72 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 204068 kb
Host smart-3fd5b81f-94b6-4c7c-9fb6-8403ed51f607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
98840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3406298840
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1195041817
Short name T1226
Test name
Test status
Simulation time 8369686617 ps
CPU time 7.56 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 204028 kb
Host smart-7d2ff389-13dc-4ca1-8602-b683540f2719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11950
41817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1195041817
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.704920259
Short name T865
Test name
Test status
Simulation time 8431530856 ps
CPU time 7.68 seconds
Started Apr 28 02:15:41 PM PDT 24
Finished Apr 28 02:15:50 PM PDT 24
Peak memory 204104 kb
Host smart-2f326171-884d-4254-b68c-b1688e7dfe3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70492
0259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.704920259
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1724903375
Short name T361
Test name
Test status
Simulation time 8400019621 ps
CPU time 7.97 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 204088 kb
Host smart-a894b0ba-cf43-415b-a1bb-6e77d8f7fc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
03375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1724903375
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3404179887
Short name T323
Test name
Test status
Simulation time 8417136336 ps
CPU time 8.59 seconds
Started Apr 28 02:15:27 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 204000 kb
Host smart-b6bfe62a-3dad-4ab0-83ed-af87490de333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34041
79887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3404179887
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2008286229
Short name T837
Test name
Test status
Simulation time 8486270125 ps
CPU time 8.38 seconds
Started Apr 28 02:11:37 PM PDT 24
Finished Apr 28 02:11:46 PM PDT 24
Peak memory 204080 kb
Host smart-ba09b247-1088-4b31-b29a-656e2624a50b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2008286229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2008286229
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1931963784
Short name T1238
Test name
Test status
Simulation time 8392143630 ps
CPU time 7.44 seconds
Started Apr 28 02:11:37 PM PDT 24
Finished Apr 28 02:11:45 PM PDT 24
Peak memory 204168 kb
Host smart-550ad5ab-1bd6-4840-a86e-2f333cccbb1c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1931963784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1931963784
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.3572131069
Short name T344
Test name
Test status
Simulation time 8453991254 ps
CPU time 8.85 seconds
Started Apr 28 02:11:38 PM PDT 24
Finished Apr 28 02:11:48 PM PDT 24
Peak memory 204108 kb
Host smart-08b65eda-543e-4c55-abbd-bcd6193ae6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35721
31069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.3572131069
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1319121191
Short name T1135
Test name
Test status
Simulation time 8384519850 ps
CPU time 7.69 seconds
Started Apr 28 02:11:32 PM PDT 24
Finished Apr 28 02:11:40 PM PDT 24
Peak memory 204140 kb
Host smart-150223e0-9d02-4071-8f41-3a38547c035b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
21191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1319121191
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.682598706
Short name T763
Test name
Test status
Simulation time 8379597838 ps
CPU time 8.08 seconds
Started Apr 28 02:11:31 PM PDT 24
Finished Apr 28 02:11:39 PM PDT 24
Peak memory 204144 kb
Host smart-d561fd5e-165b-4ec0-b9f6-48fdd26557eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68259
8706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.682598706
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.382650283
Short name T831
Test name
Test status
Simulation time 115195878 ps
CPU time 1.44 seconds
Started Apr 28 02:11:31 PM PDT 24
Finished Apr 28 02:11:33 PM PDT 24
Peak memory 204152 kb
Host smart-fec7274b-fe5a-455d-9d58-466dc88bf19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38265
0283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.382650283
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.820646295
Short name T134
Test name
Test status
Simulation time 8480090106 ps
CPU time 9.57 seconds
Started Apr 28 02:11:39 PM PDT 24
Finished Apr 28 02:11:49 PM PDT 24
Peak memory 204116 kb
Host smart-dfee9a07-16ed-4c56-b026-87dd24d5887d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82064
6295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.820646295
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3959901634
Short name T386
Test name
Test status
Simulation time 8362404819 ps
CPU time 8.32 seconds
Started Apr 28 02:11:38 PM PDT 24
Finished Apr 28 02:11:46 PM PDT 24
Peak memory 204080 kb
Host smart-a5b50614-e9f8-4b61-b747-d9f78d5ee11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39599
01634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3959901634
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3817214147
Short name T1082
Test name
Test status
Simulation time 8468498282 ps
CPU time 8 seconds
Started Apr 28 02:11:32 PM PDT 24
Finished Apr 28 02:11:41 PM PDT 24
Peak memory 204056 kb
Host smart-08c63b03-49bc-4673-a9b5-b1576cb25ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38172
14147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3817214147
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3084026081
Short name T1119
Test name
Test status
Simulation time 8417843613 ps
CPU time 7.86 seconds
Started Apr 28 02:11:30 PM PDT 24
Finished Apr 28 02:11:38 PM PDT 24
Peak memory 204120 kb
Host smart-0955ed7e-a6ae-494d-af58-fe80a5c7567c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840
26081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3084026081
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2681436792
Short name T1299
Test name
Test status
Simulation time 8438843564 ps
CPU time 8.46 seconds
Started Apr 28 02:11:31 PM PDT 24
Finished Apr 28 02:11:40 PM PDT 24
Peak memory 204140 kb
Host smart-31f2a538-9d24-4351-b6f0-a2eb8e290bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814
36792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2681436792
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1652538537
Short name T954
Test name
Test status
Simulation time 8419078727 ps
CPU time 7.41 seconds
Started Apr 28 02:11:45 PM PDT 24
Finished Apr 28 02:11:53 PM PDT 24
Peak memory 204112 kb
Host smart-6b602d3e-614f-4a60-9f24-03601fbeacce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16525
38537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1652538537
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.4094236747
Short name T482
Test name
Test status
Simulation time 8387754663 ps
CPU time 8.09 seconds
Started Apr 28 02:11:31 PM PDT 24
Finished Apr 28 02:11:40 PM PDT 24
Peak memory 204112 kb
Host smart-1dc6cb20-d068-4a78-a4d5-6de98c3b55f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40942
36747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.4094236747
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2711775799
Short name T292
Test name
Test status
Simulation time 8415594512 ps
CPU time 7.7 seconds
Started Apr 28 02:11:37 PM PDT 24
Finished Apr 28 02:11:46 PM PDT 24
Peak memory 204112 kb
Host smart-33bca513-ea01-46bf-a6bb-ebd85b9cafe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
75799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2711775799
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1067343449
Short name T200
Test name
Test status
Simulation time 8429059292 ps
CPU time 7.33 seconds
Started Apr 28 02:11:36 PM PDT 24
Finished Apr 28 02:11:44 PM PDT 24
Peak memory 204020 kb
Host smart-ee46a14f-6892-4c8e-afb5-177b7924153e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673
43449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1067343449
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.738849024
Short name T25
Test name
Test status
Simulation time 8371929456 ps
CPU time 7.67 seconds
Started Apr 28 02:11:38 PM PDT 24
Finished Apr 28 02:11:46 PM PDT 24
Peak memory 204136 kb
Host smart-33a3b978-48ae-424d-9b43-0e463e45c19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73884
9024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.738849024
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2786747646
Short name T801
Test name
Test status
Simulation time 117633259 ps
CPU time 0.71 seconds
Started Apr 28 02:11:36 PM PDT 24
Finished Apr 28 02:11:37 PM PDT 24
Peak memory 203952 kb
Host smart-2854f360-b599-4392-8579-4f1df0f2daad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
47646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2786747646
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1680243432
Short name T885
Test name
Test status
Simulation time 22658861070 ps
CPU time 44.25 seconds
Started Apr 28 02:11:35 PM PDT 24
Finished Apr 28 02:12:20 PM PDT 24
Peak memory 204444 kb
Host smart-e7df89c9-72f0-499a-af67-53ee32751814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802
43432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1680243432
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3390794331
Short name T18
Test name
Test status
Simulation time 8387974095 ps
CPU time 7.37 seconds
Started Apr 28 02:11:40 PM PDT 24
Finished Apr 28 02:11:48 PM PDT 24
Peak memory 204112 kb
Host smart-6970e6fa-1f04-49d2-a059-34f96d5b74cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
94331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3390794331
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2451992427
Short name T143
Test name
Test status
Simulation time 8401563193 ps
CPU time 8.97 seconds
Started Apr 28 02:11:35 PM PDT 24
Finished Apr 28 02:11:44 PM PDT 24
Peak memory 204064 kb
Host smart-7bf3125a-224a-42a8-9f64-503bffb3746a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24519
92427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2451992427
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3815355979
Short name T535
Test name
Test status
Simulation time 8397107952 ps
CPU time 7.75 seconds
Started Apr 28 02:11:38 PM PDT 24
Finished Apr 28 02:11:47 PM PDT 24
Peak memory 204092 kb
Host smart-4bdcbc4f-2a86-45da-89e9-e89c3a4f26e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
55979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3815355979
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.575590255
Short name T576
Test name
Test status
Simulation time 8374078098 ps
CPU time 7.15 seconds
Started Apr 28 02:11:39 PM PDT 24
Finished Apr 28 02:11:46 PM PDT 24
Peak memory 204132 kb
Host smart-5f98451a-02aa-4f90-a4fd-1328f3948a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57559
0255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.575590255
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1564343200
Short name T660
Test name
Test status
Simulation time 8374104123 ps
CPU time 7.58 seconds
Started Apr 28 02:11:37 PM PDT 24
Finished Apr 28 02:11:45 PM PDT 24
Peak memory 204112 kb
Host smart-b32a423a-feab-4bea-9e68-fc98b390dd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
43200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1564343200
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3195868058
Short name T652
Test name
Test status
Simulation time 8417518209 ps
CPU time 9.78 seconds
Started Apr 28 02:11:32 PM PDT 24
Finished Apr 28 02:11:43 PM PDT 24
Peak memory 204108 kb
Host smart-59d9ca47-14f0-4f17-9143-2da96bbd709e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31958
68058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3195868058
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1598024954
Short name T1035
Test name
Test status
Simulation time 8417677870 ps
CPU time 8.52 seconds
Started Apr 28 02:11:35 PM PDT 24
Finished Apr 28 02:11:44 PM PDT 24
Peak memory 203996 kb
Host smart-d590a7ae-53fa-459f-a462-11aea1e42160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
24954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1598024954
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2857078500
Short name T553
Test name
Test status
Simulation time 8377439692 ps
CPU time 7.93 seconds
Started Apr 28 02:11:38 PM PDT 24
Finished Apr 28 02:11:47 PM PDT 24
Peak memory 204040 kb
Host smart-d24ff1e1-fb54-4194-8856-7c98643760c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28570
78500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2857078500
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.498002918
Short name T603
Test name
Test status
Simulation time 8473769976 ps
CPU time 9.29 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204128 kb
Host smart-c1fdec04-f368-4a67-b4a2-f9be3fa579a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=498002918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.498002918
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.4158340436
Short name T1017
Test name
Test status
Simulation time 8377000912 ps
CPU time 8.04 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:55 PM PDT 24
Peak memory 204008 kb
Host smart-7866cd98-f4a3-40c1-8f1c-69e6895cc938
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4158340436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.4158340436
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.3673004102
Short name T1037
Test name
Test status
Simulation time 8484262679 ps
CPU time 9.28 seconds
Started Apr 28 02:11:40 PM PDT 24
Finished Apr 28 02:11:50 PM PDT 24
Peak memory 204028 kb
Host smart-dfe09f2f-a405-45c7-b991-6f11d5a4564a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36730
04102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.3673004102
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2773420151
Short name T324
Test name
Test status
Simulation time 8399696665 ps
CPU time 9.79 seconds
Started Apr 28 02:11:39 PM PDT 24
Finished Apr 28 02:11:49 PM PDT 24
Peak memory 204124 kb
Host smart-8c273fa8-757d-4b3f-92c9-5e8fd8279d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
20151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2773420151
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.3540189357
Short name T306
Test name
Test status
Simulation time 8374214674 ps
CPU time 8 seconds
Started Apr 28 02:11:39 PM PDT 24
Finished Apr 28 02:11:48 PM PDT 24
Peak memory 204076 kb
Host smart-d96ecd6d-c45e-4cf5-b0cd-f4b2bfc34e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35401
89357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3540189357
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.880737765
Short name T584
Test name
Test status
Simulation time 115647883 ps
CPU time 1.22 seconds
Started Apr 28 02:11:39 PM PDT 24
Finished Apr 28 02:11:41 PM PDT 24
Peak memory 204196 kb
Host smart-bdd1359d-62da-4ddf-b5ea-b138666834bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88073
7765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.880737765
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1928624625
Short name T591
Test name
Test status
Simulation time 8403229109 ps
CPU time 7.56 seconds
Started Apr 28 02:11:43 PM PDT 24
Finished Apr 28 02:11:51 PM PDT 24
Peak memory 204108 kb
Host smart-46d0103b-0c05-4784-b624-68e375227e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19286
24625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1928624625
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3960800702
Short name T1140
Test name
Test status
Simulation time 8374832181 ps
CPU time 10.13 seconds
Started Apr 28 02:11:41 PM PDT 24
Finished Apr 28 02:11:52 PM PDT 24
Peak memory 204068 kb
Host smart-1a502e31-255c-4856-a403-f5901a67dd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
00702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3960800702
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2449969180
Short name T1024
Test name
Test status
Simulation time 8391589494 ps
CPU time 9.51 seconds
Started Apr 28 02:11:42 PM PDT 24
Finished Apr 28 02:11:52 PM PDT 24
Peak memory 204120 kb
Host smart-70993a49-af9c-43b0-b8ff-b7a764498b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24499
69180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2449969180
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1550666567
Short name T938
Test name
Test status
Simulation time 8421531868 ps
CPU time 8.68 seconds
Started Apr 28 02:11:41 PM PDT 24
Finished Apr 28 02:11:51 PM PDT 24
Peak memory 204156 kb
Host smart-33214390-c72e-4c4f-95d8-1d214141b830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15506
66567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1550666567
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4015815979
Short name T655
Test name
Test status
Simulation time 8405790188 ps
CPU time 7.24 seconds
Started Apr 28 02:11:40 PM PDT 24
Finished Apr 28 02:11:48 PM PDT 24
Peak memory 204124 kb
Host smart-7fd9a17b-6b9c-406b-a595-9f9b594a612c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
15979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4015815979
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3755130434
Short name T119
Test name
Test status
Simulation time 8418895738 ps
CPU time 8.27 seconds
Started Apr 28 02:11:42 PM PDT 24
Finished Apr 28 02:11:51 PM PDT 24
Peak memory 204140 kb
Host smart-87f11237-2fb5-44f4-a577-a97df226dcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
30434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3755130434
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1893318618
Short name T1303
Test name
Test status
Simulation time 8390542426 ps
CPU time 8.18 seconds
Started Apr 28 02:11:42 PM PDT 24
Finished Apr 28 02:11:51 PM PDT 24
Peak memory 204168 kb
Host smart-6547931a-e88a-4dc7-8982-6063e337faec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
18618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1893318618
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.634485024
Short name T391
Test name
Test status
Simulation time 8385101166 ps
CPU time 8.37 seconds
Started Apr 28 02:11:42 PM PDT 24
Finished Apr 28 02:11:51 PM PDT 24
Peak memory 204100 kb
Host smart-b9878033-6016-4de3-a0ee-51a4b3b2b1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63448
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.634485024
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.771950973
Short name T549
Test name
Test status
Simulation time 8404576133 ps
CPU time 7.45 seconds
Started Apr 28 02:11:41 PM PDT 24
Finished Apr 28 02:11:49 PM PDT 24
Peak memory 204064 kb
Host smart-0f6426b5-b3b9-4e87-a85f-6f84bc8d2951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77195
0973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.771950973
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.78808426
Short name T645
Test name
Test status
Simulation time 8373592573 ps
CPU time 8.12 seconds
Started Apr 28 02:11:48 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204080 kb
Host smart-078f15be-2060-4417-ac93-8d54218abc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78808
426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.78808426
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2677120158
Short name T418
Test name
Test status
Simulation time 46471147 ps
CPU time 0.67 seconds
Started Apr 28 02:11:47 PM PDT 24
Finished Apr 28 02:11:48 PM PDT 24
Peak memory 203984 kb
Host smart-f63529bb-849c-4e31-bdc8-82115647ed7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26771
20158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2677120158
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3206682571
Short name T634
Test name
Test status
Simulation time 27593770541 ps
CPU time 53.03 seconds
Started Apr 28 02:11:42 PM PDT 24
Finished Apr 28 02:12:36 PM PDT 24
Peak memory 204404 kb
Host smart-11e20a53-bbac-4509-9f72-17133acff7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
82571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3206682571
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.862735688
Short name T960
Test name
Test status
Simulation time 8406829490 ps
CPU time 8.36 seconds
Started Apr 28 02:11:40 PM PDT 24
Finished Apr 28 02:11:49 PM PDT 24
Peak memory 204116 kb
Host smart-d9200879-54a7-40a6-8b7f-96811dcf0047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86273
5688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.862735688
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3428039637
Short name T889
Test name
Test status
Simulation time 8416092470 ps
CPU time 7.75 seconds
Started Apr 28 02:11:48 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204068 kb
Host smart-b7cc5904-a788-437b-932e-4ea0ae569744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
39637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3428039637
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1668725299
Short name T1137
Test name
Test status
Simulation time 8411710799 ps
CPU time 8.06 seconds
Started Apr 28 02:11:41 PM PDT 24
Finished Apr 28 02:11:49 PM PDT 24
Peak memory 204116 kb
Host smart-3c220a78-5a63-4d14-94af-c1bea1247a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16687
25299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1668725299
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3792818655
Short name T712
Test name
Test status
Simulation time 8371023477 ps
CPU time 7.44 seconds
Started Apr 28 02:11:43 PM PDT 24
Finished Apr 28 02:11:50 PM PDT 24
Peak memory 204084 kb
Host smart-79f157f6-d8ba-4917-9a8c-61db571c6852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
18655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3792818655
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1022189640
Short name T745
Test name
Test status
Simulation time 8369818553 ps
CPU time 8.14 seconds
Started Apr 28 02:11:42 PM PDT 24
Finished Apr 28 02:11:50 PM PDT 24
Peak memory 204088 kb
Host smart-45da7c72-bb97-4e6f-a259-153c22d5e684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10221
89640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1022189640
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3812702971
Short name T1256
Test name
Test status
Simulation time 8438038225 ps
CPU time 8.76 seconds
Started Apr 28 02:11:38 PM PDT 24
Finished Apr 28 02:11:47 PM PDT 24
Peak memory 204088 kb
Host smart-5c19cc31-ad4d-4d87-9e71-653ab328ff23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
02971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3812702971
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.208698430
Short name T909
Test name
Test status
Simulation time 8375862472 ps
CPU time 8.34 seconds
Started Apr 28 02:11:48 PM PDT 24
Finished Apr 28 02:11:57 PM PDT 24
Peak memory 204068 kb
Host smart-5852c617-2ee7-4cba-aef2-94201cb23d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20869
8430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.208698430
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1080849627
Short name T359
Test name
Test status
Simulation time 8410863028 ps
CPU time 10.11 seconds
Started Apr 28 02:11:40 PM PDT 24
Finished Apr 28 02:11:51 PM PDT 24
Peak memory 204104 kb
Host smart-735a2654-9bd4-4ae1-a686-76a362bd6e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
49627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1080849627
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.2309592592
Short name T214
Test name
Test status
Simulation time 8467549792 ps
CPU time 7.91 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 204156 kb
Host smart-ff33faf7-6a2f-4f9d-9980-27b7faec1db2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2309592592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.2309592592
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.15819088
Short name T1220
Test name
Test status
Simulation time 8392561648 ps
CPU time 9.3 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:03 PM PDT 24
Peak memory 204100 kb
Host smart-77f8945a-45b3-4bc2-98f8-4645dea50138
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=15819088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.15819088
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3984427569
Short name T1353
Test name
Test status
Simulation time 8396073183 ps
CPU time 8.79 seconds
Started Apr 28 02:11:52 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 204092 kb
Host smart-1a3f657a-4b80-41f3-b070-6c0e9548c9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39844
27569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3984427569
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.111471668
Short name T465
Test name
Test status
Simulation time 8387296269 ps
CPU time 9.56 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:57 PM PDT 24
Peak memory 204000 kb
Host smart-f5a01d76-53b6-46a4-8f70-9ee7e87202db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11147
1668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.111471668
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.3453533796
Short name T656
Test name
Test status
Simulation time 8381650131 ps
CPU time 9.19 seconds
Started Apr 28 02:11:45 PM PDT 24
Finished Apr 28 02:11:55 PM PDT 24
Peak memory 204144 kb
Host smart-940aba2c-9ffe-4f33-abe2-447d3ccca709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
33796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3453533796
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.455474797
Short name T1044
Test name
Test status
Simulation time 234144690 ps
CPU time 2.03 seconds
Started Apr 28 02:11:48 PM PDT 24
Finished Apr 28 02:11:50 PM PDT 24
Peak memory 204164 kb
Host smart-12472047-78b3-4986-bfdd-df067675cbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45547
4797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.455474797
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.640574194
Short name T1278
Test name
Test status
Simulation time 8456779317 ps
CPU time 9.71 seconds
Started Apr 28 02:11:51 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 204080 kb
Host smart-015c14e6-47c1-46d6-a412-a8072b42a267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64057
4194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.640574194
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1313716957
Short name T1308
Test name
Test status
Simulation time 8374456450 ps
CPU time 7.76 seconds
Started Apr 28 02:11:52 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 204056 kb
Host smart-bcfd2956-00bb-4540-8ee7-67e6ae29819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
16957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1313716957
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1904001024
Short name T1182
Test name
Test status
Simulation time 8400700154 ps
CPU time 7.63 seconds
Started Apr 28 02:11:45 PM PDT 24
Finished Apr 28 02:11:53 PM PDT 24
Peak memory 204132 kb
Host smart-a141dd9e-b11e-407a-9c06-fe53af64d2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
01024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1904001024
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1264251833
Short name T399
Test name
Test status
Simulation time 8420187854 ps
CPU time 8.06 seconds
Started Apr 28 02:11:49 PM PDT 24
Finished Apr 28 02:11:57 PM PDT 24
Peak memory 204112 kb
Host smart-5521f977-02bb-47be-bd1d-0223434f1060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12642
51833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1264251833
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2281326698
Short name T41
Test name
Test status
Simulation time 8368492130 ps
CPU time 8.35 seconds
Started Apr 28 02:11:47 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204044 kb
Host smart-26afcc1a-1297-4c52-bf70-af97de5ab598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813
26698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2281326698
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.4012594919
Short name T1180
Test name
Test status
Simulation time 8478050373 ps
CPU time 7.86 seconds
Started Apr 28 02:11:49 PM PDT 24
Finished Apr 28 02:11:57 PM PDT 24
Peak memory 204084 kb
Host smart-123a39ee-bab2-40e6-b4fb-234e20bea693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
94919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.4012594919
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2020680155
Short name T877
Test name
Test status
Simulation time 8372289753 ps
CPU time 7.62 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:54 PM PDT 24
Peak memory 204060 kb
Host smart-304a7bf0-6f08-46e5-aacf-86118a3fde10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
80155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2020680155
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.656995225
Short name T1231
Test name
Test status
Simulation time 8388144990 ps
CPU time 10.35 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:57 PM PDT 24
Peak memory 204100 kb
Host smart-6d32280f-ea6e-421c-ba3f-a2426dab9069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65699
5225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.656995225
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.936597806
Short name T199
Test name
Test status
Simulation time 8402680678 ps
CPU time 10.23 seconds
Started Apr 28 02:11:54 PM PDT 24
Finished Apr 28 02:12:05 PM PDT 24
Peak memory 204108 kb
Host smart-618b5917-128b-444b-83b1-9427714e2c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93659
7806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.936597806
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1078194737
Short name T524
Test name
Test status
Simulation time 8378262104 ps
CPU time 7.87 seconds
Started Apr 28 02:11:47 PM PDT 24
Finished Apr 28 02:11:55 PM PDT 24
Peak memory 204156 kb
Host smart-79071725-f404-49be-b6a1-ee0f5213c324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
94737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1078194737
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.4030894926
Short name T723
Test name
Test status
Simulation time 42698206 ps
CPU time 0.67 seconds
Started Apr 28 02:11:52 PM PDT 24
Finished Apr 28 02:11:54 PM PDT 24
Peak memory 203904 kb
Host smart-1e41ea2c-7219-44f6-837b-f7ba02d97bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40308
94926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.4030894926
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2962849097
Short name T258
Test name
Test status
Simulation time 30512123674 ps
CPU time 66.97 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:12:53 PM PDT 24
Peak memory 204392 kb
Host smart-828d14e8-b529-4a6e-b1d3-f3b30149e29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628
49097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2962849097
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1949476287
Short name T621
Test name
Test status
Simulation time 8371494454 ps
CPU time 7.77 seconds
Started Apr 28 02:11:49 PM PDT 24
Finished Apr 28 02:11:57 PM PDT 24
Peak memory 204160 kb
Host smart-9ed37b8c-660c-4e5b-a5fc-fb76aa179865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19494
76287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1949476287
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3995094447
Short name T1264
Test name
Test status
Simulation time 8432767389 ps
CPU time 7.42 seconds
Started Apr 28 02:11:48 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204120 kb
Host smart-c056223a-3182-4083-a237-a7b3a54b7701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39950
94447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3995094447
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2538712727
Short name T677
Test name
Test status
Simulation time 8408123148 ps
CPU time 9.59 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204084 kb
Host smart-5beb5604-dc97-4a7e-aaac-fb9e42576ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25387
12727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2538712727
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1187005166
Short name T1367
Test name
Test status
Simulation time 8381853490 ps
CPU time 7.96 seconds
Started Apr 28 02:11:52 PM PDT 24
Finished Apr 28 02:12:00 PM PDT 24
Peak memory 204116 kb
Host smart-88d85544-4359-4b6b-9f87-b654b4c4ee68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11870
05166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1187005166
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.584159279
Short name T1380
Test name
Test status
Simulation time 8372468384 ps
CPU time 7.94 seconds
Started Apr 28 02:11:47 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204152 kb
Host smart-065cf632-4cd2-4330-820a-a2bcfb94639b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58415
9279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.584159279
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1064663382
Short name T710
Test name
Test status
Simulation time 8470140330 ps
CPU time 8.37 seconds
Started Apr 28 02:11:45 PM PDT 24
Finished Apr 28 02:11:53 PM PDT 24
Peak memory 204120 kb
Host smart-99778320-2dff-4473-a441-6b2ad69cbff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10646
63382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1064663382
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.169466909
Short name T924
Test name
Test status
Simulation time 8397699614 ps
CPU time 7.34 seconds
Started Apr 28 02:11:45 PM PDT 24
Finished Apr 28 02:11:53 PM PDT 24
Peak memory 204104 kb
Host smart-d1857dbf-82cc-424c-8095-c82bc1bc13ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
6909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.169466909
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3362206429
Short name T920
Test name
Test status
Simulation time 8403774796 ps
CPU time 8.08 seconds
Started Apr 28 02:11:46 PM PDT 24
Finished Apr 28 02:11:55 PM PDT 24
Peak memory 204172 kb
Host smart-95e30cef-90ed-4548-a506-28720472c5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33622
06429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3362206429
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.234492224
Short name T1099
Test name
Test status
Simulation time 8463606849 ps
CPU time 7.72 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:12:05 PM PDT 24
Peak memory 204152 kb
Host smart-0d9f75b1-a8e3-49f2-b5f8-ec8f81cf3d89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=234492224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.234492224
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.377256450
Short name T965
Test name
Test status
Simulation time 8382886426 ps
CPU time 8.71 seconds
Started Apr 28 02:11:58 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204100 kb
Host smart-3bc58be1-6475-4bb2-84e2-cfff647f9b19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=377256450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.377256450
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1783022112
Short name T836
Test name
Test status
Simulation time 8449350218 ps
CPU time 7.9 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:12:06 PM PDT 24
Peak memory 204072 kb
Host smart-a2148f38-08bc-4845-9915-ed0e2bf839a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17830
22112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1783022112
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.498500744
Short name T485
Test name
Test status
Simulation time 8376215651 ps
CPU time 7.9 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 204076 kb
Host smart-fe4b96bd-8cb1-435d-b160-2e6ae07e382f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49850
0744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.498500744
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.1839493908
Short name T829
Test name
Test status
Simulation time 8379465272 ps
CPU time 8.68 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:02 PM PDT 24
Peak memory 204116 kb
Host smart-dafe998b-5c06-413a-92e7-bc4a6907c6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18394
93908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1839493908
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1404609413
Short name T558
Test name
Test status
Simulation time 255732303 ps
CPU time 2.25 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:11:56 PM PDT 24
Peak memory 204224 kb
Host smart-853bc714-6963-43c9-912b-ccc417a61629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14046
09413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1404609413
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.15589611
Short name T1243
Test name
Test status
Simulation time 8446222449 ps
CPU time 7.61 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:12:05 PM PDT 24
Peak memory 204132 kb
Host smart-b3ca9073-4c43-4386-8155-24645dbc9f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.15589611
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3188217101
Short name T197
Test name
Test status
Simulation time 8368364878 ps
CPU time 7.96 seconds
Started Apr 28 02:11:58 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204124 kb
Host smart-3f459657-7dfb-4cb3-b967-416b13d570bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31882
17101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3188217101
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.4130948760
Short name T1373
Test name
Test status
Simulation time 8380468270 ps
CPU time 7.65 seconds
Started Apr 28 02:11:55 PM PDT 24
Finished Apr 28 02:12:03 PM PDT 24
Peak memory 204124 kb
Host smart-9d2eeec4-db07-40d8-91b7-0c794188e423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41309
48760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4130948760
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.483187321
Short name T878
Test name
Test status
Simulation time 8436224732 ps
CPU time 8.05 seconds
Started Apr 28 02:11:55 PM PDT 24
Finished Apr 28 02:12:03 PM PDT 24
Peak memory 204116 kb
Host smart-6281421f-1044-4731-98e5-c87811d89aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48318
7321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.483187321
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.219499737
Short name T1262
Test name
Test status
Simulation time 8369623541 ps
CPU time 9.74 seconds
Started Apr 28 02:11:56 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204076 kb
Host smart-2949bcb0-9e88-4d0a-a5c9-595b33732f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21949
9737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.219499737
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2425472833
Short name T111
Test name
Test status
Simulation time 8436087649 ps
CPU time 8.54 seconds
Started Apr 28 02:11:56 PM PDT 24
Finished Apr 28 02:12:05 PM PDT 24
Peak memory 204068 kb
Host smart-b6c4603a-46d6-4ce9-a3fe-3ac0efc41171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24254
72833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2425472833
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2322198515
Short name T286
Test name
Test status
Simulation time 8408774612 ps
CPU time 7.31 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 204128 kb
Host smart-c6b46ec0-99c2-42d4-b89f-b1a75be444d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
98515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2322198515
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1015083973
Short name T791
Test name
Test status
Simulation time 8479166954 ps
CPU time 7.6 seconds
Started Apr 28 02:11:51 PM PDT 24
Finished Apr 28 02:11:59 PM PDT 24
Peak memory 204080 kb
Host smart-5979c3b2-b628-4fdd-aec1-bc15cf314831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
83973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1015083973
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1449625937
Short name T175
Test name
Test status
Simulation time 8385107248 ps
CPU time 7.99 seconds
Started Apr 28 02:12:00 PM PDT 24
Finished Apr 28 02:12:09 PM PDT 24
Peak memory 204092 kb
Host smart-20fc24f6-0ea9-4168-8edc-235a44f6629b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
25937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1449625937
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.666538682
Short name T839
Test name
Test status
Simulation time 8371173533 ps
CPU time 9.07 seconds
Started Apr 28 02:11:56 PM PDT 24
Finished Apr 28 02:12:06 PM PDT 24
Peak memory 204108 kb
Host smart-ecfdbc47-2a87-4e11-aca8-e997eba7c742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66653
8682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.666538682
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3834763002
Short name T948
Test name
Test status
Simulation time 32090079 ps
CPU time 0.63 seconds
Started Apr 28 02:12:00 PM PDT 24
Finished Apr 28 02:12:01 PM PDT 24
Peak memory 203992 kb
Host smart-e3870360-333f-4532-9f6a-2170e11737f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38347
63002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3834763002
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2488959568
Short name T785
Test name
Test status
Simulation time 27252316899 ps
CPU time 51.92 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:45 PM PDT 24
Peak memory 204420 kb
Host smart-46ae07d7-cab1-489d-a450-54b3d918c996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24889
59568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2488959568
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.4160221672
Short name T335
Test name
Test status
Simulation time 8455173127 ps
CPU time 8.33 seconds
Started Apr 28 02:11:54 PM PDT 24
Finished Apr 28 02:12:02 PM PDT 24
Peak memory 204092 kb
Host smart-92c5454c-758f-4512-9012-7f054a68717b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
21672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.4160221672
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.114404128
Short name T550
Test name
Test status
Simulation time 8508869517 ps
CPU time 8.64 seconds
Started Apr 28 02:11:54 PM PDT 24
Finished Apr 28 02:12:03 PM PDT 24
Peak memory 204124 kb
Host smart-67155b95-6853-4525-8825-d444fa34cbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11440
4128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.114404128
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.162334546
Short name T511
Test name
Test status
Simulation time 8396392916 ps
CPU time 8.23 seconds
Started Apr 28 02:11:59 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204140 kb
Host smart-e2e59720-4fcd-4de4-9b54-523ffc855ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16233
4546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.162334546
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4026470404
Short name T164
Test name
Test status
Simulation time 8385080542 ps
CPU time 8.08 seconds
Started Apr 28 02:11:59 PM PDT 24
Finished Apr 28 02:12:08 PM PDT 24
Peak memory 204108 kb
Host smart-3802fc6a-66e3-475b-8757-7811bfced36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40264
70404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4026470404
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.240638530
Short name T841
Test name
Test status
Simulation time 8405810477 ps
CPU time 7.46 seconds
Started Apr 28 02:11:58 PM PDT 24
Finished Apr 28 02:12:06 PM PDT 24
Peak memory 204088 kb
Host smart-e67788ab-989b-4861-9d5d-e2ff3c6af017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
8530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.240638530
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1100757637
Short name T557
Test name
Test status
Simulation time 8431068408 ps
CPU time 7.71 seconds
Started Apr 28 02:11:53 PM PDT 24
Finished Apr 28 02:12:02 PM PDT 24
Peak memory 204128 kb
Host smart-da54051d-b396-4573-a4df-9533968da9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
57637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1100757637
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2074123489
Short name T551
Test name
Test status
Simulation time 8401849830 ps
CPU time 8.07 seconds
Started Apr 28 02:12:00 PM PDT 24
Finished Apr 28 02:12:09 PM PDT 24
Peak memory 204080 kb
Host smart-885af8a3-6d57-4a6f-951a-8b81ab01039e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
23489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2074123489
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3482850385
Short name T333
Test name
Test status
Simulation time 8399718758 ps
CPU time 7.49 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:12:05 PM PDT 24
Peak memory 204072 kb
Host smart-eeffafc0-794a-4d64-8b24-6ae34aac26e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34828
50385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3482850385
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3604189735
Short name T607
Test name
Test status
Simulation time 8470983304 ps
CPU time 8.49 seconds
Started Apr 28 02:12:04 PM PDT 24
Finished Apr 28 02:12:12 PM PDT 24
Peak memory 204092 kb
Host smart-2519c548-08be-48cf-bf62-6ed75a73eaa5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3604189735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3604189735
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.4146510322
Short name T307
Test name
Test status
Simulation time 8382572807 ps
CPU time 8.37 seconds
Started Apr 28 02:12:03 PM PDT 24
Finished Apr 28 02:12:12 PM PDT 24
Peak memory 204140 kb
Host smart-36b7b12e-8a15-449f-b8a5-3cb00160a26f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4146510322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.4146510322
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.362282805
Short name T301
Test name
Test status
Simulation time 8409961228 ps
CPU time 9.35 seconds
Started Apr 28 02:12:03 PM PDT 24
Finished Apr 28 02:12:13 PM PDT 24
Peak memory 204132 kb
Host smart-6ec8959e-299c-409d-882a-78cb323fbae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36228
2805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.362282805
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.855375864
Short name T1132
Test name
Test status
Simulation time 8377526269 ps
CPU time 10.12 seconds
Started Apr 28 02:11:56 PM PDT 24
Finished Apr 28 02:12:06 PM PDT 24
Peak memory 204136 kb
Host smart-cb76397e-04cc-41f3-b509-ffc341d8ce3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85537
5864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.855375864
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.644900477
Short name T729
Test name
Test status
Simulation time 8377512496 ps
CPU time 9.31 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204088 kb
Host smart-c66c7b2c-bbdf-405b-ad46-ca8531559a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64490
0477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.644900477
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4293434948
Short name T700
Test name
Test status
Simulation time 169355972 ps
CPU time 1.92 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:11:59 PM PDT 24
Peak memory 204256 kb
Host smart-8c27f112-00d2-42a9-9ccc-d7e00bef3f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42934
34948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4293434948
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2558158937
Short name T525
Test name
Test status
Simulation time 8458190360 ps
CPU time 9.56 seconds
Started Apr 28 02:12:03 PM PDT 24
Finished Apr 28 02:12:13 PM PDT 24
Peak memory 204128 kb
Host smart-33c9d006-b75b-4cd2-89a8-218e511c33a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581
58937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2558158937
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3711959635
Short name T760
Test name
Test status
Simulation time 8372937252 ps
CPU time 8.47 seconds
Started Apr 28 02:12:01 PM PDT 24
Finished Apr 28 02:12:10 PM PDT 24
Peak memory 204048 kb
Host smart-09a7c799-422e-414b-8781-32b8f57d068a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37119
59635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3711959635
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1116335579
Short name T1087
Test name
Test status
Simulation time 8419160875 ps
CPU time 8.91 seconds
Started Apr 28 02:11:59 PM PDT 24
Finished Apr 28 02:12:08 PM PDT 24
Peak memory 204108 kb
Host smart-63d84721-6ab7-4218-955b-6cb6a5c0167f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11163
35579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1116335579
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1743580391
Short name T678
Test name
Test status
Simulation time 8427962368 ps
CPU time 8.71 seconds
Started Apr 28 02:11:58 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204124 kb
Host smart-8eeaf828-581a-4733-8afc-6ffb144e8d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17435
80391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1743580391
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4044717866
Short name T426
Test name
Test status
Simulation time 8397234886 ps
CPU time 9.04 seconds
Started Apr 28 02:11:59 PM PDT 24
Finished Apr 28 02:12:08 PM PDT 24
Peak memory 204032 kb
Host smart-a492d0c4-eaf5-4be6-97b6-c15d3b40f622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
17866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4044717866
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.671034941
Short name T114
Test name
Test status
Simulation time 8445516615 ps
CPU time 7.96 seconds
Started Apr 28 02:11:58 PM PDT 24
Finished Apr 28 02:12:06 PM PDT 24
Peak memory 204068 kb
Host smart-78b03f7d-a761-498b-aa8a-0a65e15bf073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67103
4941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.671034941
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2379134814
Short name T1080
Test name
Test status
Simulation time 8431393355 ps
CPU time 7.77 seconds
Started Apr 28 02:11:57 PM PDT 24
Finished Apr 28 02:12:06 PM PDT 24
Peak memory 204148 kb
Host smart-7c46ad7c-d562-4d5a-8db0-4d59537764af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
34814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2379134814
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1505896373
Short name T1189
Test name
Test status
Simulation time 8399916609 ps
CPU time 8 seconds
Started Apr 28 02:11:59 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204124 kb
Host smart-0215bb9d-c930-425f-adb5-7a42287099fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
96373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1505896373
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3600632113
Short name T928
Test name
Test status
Simulation time 8411875140 ps
CPU time 7.62 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:12:11 PM PDT 24
Peak memory 204072 kb
Host smart-1eb92878-e3f2-4bfc-a9af-caa85d744ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006
32113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3600632113
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.130402743
Short name T303
Test name
Test status
Simulation time 8364759493 ps
CPU time 8.31 seconds
Started Apr 28 02:12:03 PM PDT 24
Finished Apr 28 02:12:12 PM PDT 24
Peak memory 204004 kb
Host smart-7547e27a-7df1-4255-846e-2010169ab4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13040
2743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.130402743
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.4094046290
Short name T1323
Test name
Test status
Simulation time 52044731 ps
CPU time 0.66 seconds
Started Apr 28 02:12:03 PM PDT 24
Finished Apr 28 02:12:04 PM PDT 24
Peak memory 203904 kb
Host smart-fd2aebdb-2ab4-46d0-aec5-6cb57950883d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40940
46290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.4094046290
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.4234946213
Short name T1352
Test name
Test status
Simulation time 33019574948 ps
CPU time 73.73 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:13:16 PM PDT 24
Peak memory 204396 kb
Host smart-f1dcbd23-c1ee-4a91-9252-dfe05b5d5a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
46213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.4234946213
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1371369135
Short name T680
Test name
Test status
Simulation time 8381868565 ps
CPU time 7.46 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:12:10 PM PDT 24
Peak memory 204068 kb
Host smart-04b703d5-ec5c-4506-bb0e-3b5a450d93f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13713
69135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1371369135
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2646380076
Short name T135
Test name
Test status
Simulation time 8446822658 ps
CPU time 7.84 seconds
Started Apr 28 02:12:03 PM PDT 24
Finished Apr 28 02:12:11 PM PDT 24
Peak memory 204100 kb
Host smart-2d4dbd18-c138-4098-9477-3322452e4032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26463
80076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2646380076
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2858317649
Short name T890
Test name
Test status
Simulation time 8390247014 ps
CPU time 9.46 seconds
Started Apr 28 02:12:01 PM PDT 24
Finished Apr 28 02:12:11 PM PDT 24
Peak memory 204136 kb
Host smart-17e40e08-88ef-440a-8542-34b2499fffe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
17649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2858317649
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3594678355
Short name T483
Test name
Test status
Simulation time 8430913020 ps
CPU time 7.98 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:12:11 PM PDT 24
Peak memory 204164 kb
Host smart-c103916b-499f-4243-b0eb-dcedfca12b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
78355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3594678355
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3259102238
Short name T28
Test name
Test status
Simulation time 8409732874 ps
CPU time 7.37 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:12:10 PM PDT 24
Peak memory 204036 kb
Host smart-f78153eb-6eff-4316-b27a-4f9fae3130ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591
02238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3259102238
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3720142336
Short name T172
Test name
Test status
Simulation time 8465968605 ps
CPU time 8.2 seconds
Started Apr 28 02:11:59 PM PDT 24
Finished Apr 28 02:12:07 PM PDT 24
Peak memory 204124 kb
Host smart-87116af6-38f4-41db-9b45-47a188dced13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37201
42336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3720142336
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1577767575
Short name T988
Test name
Test status
Simulation time 8386602080 ps
CPU time 8.36 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:12:11 PM PDT 24
Peak memory 204100 kb
Host smart-73e09620-8a60-4e27-8598-26d5191ff75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
67575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1577767575
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3932461745
Short name T453
Test name
Test status
Simulation time 8381003453 ps
CPU time 7.64 seconds
Started Apr 28 02:12:02 PM PDT 24
Finished Apr 28 02:12:11 PM PDT 24
Peak memory 204148 kb
Host smart-ad5a81c0-7046-4b08-8fa0-3a6fcf2736a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39324
61745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3932461745
Directory /workspace/9.usbdev_stall_trans/latest
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