Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	25516	1		T1	2		T2	3		T3	2
all_values[1]	25516	1		T1	2		T2	3		T3	2
all_values[2]	25516	1		T1	2		T2	3		T3	2
all_values[3]	25516	1		T1	2		T2	3		T3	2
all_values[4]	25516	1		T1	2		T2	3		T3	2
all_values[5]	25516	1		T1	2		T2	3		T3	2
all_values[6]	25516	1		T1	2		T2	3		T3	2
all_values[7]	25516	1		T1	2		T2	3		T3	2
all_values[8]	25516	1		T1	2		T2	3		T3	2
all_values[9]	25516	1		T1	2		T2	3		T3	2
all_values[10]	25516	1		T1	2		T2	3		T3	2
all_values[11]	25516	1		T1	2		T2	3		T3	2
all_values[12]	25516	1		T1	2		T2	3		T3	2
all_values[13]	25516	1		T1	2		T2	3		T3	2
all_values[14]	25516	1		T1	2		T2	3		T3	2
all_values[15]	25516	1		T1	2		T2	3		T3	2
all_values[16]	25516	1		T1	2		T2	3		T3	2
all_values[17]	25516	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	455229	1		T1	36		T2	51		T3	36
auto[1]	4059	1		T2	3		T12	3		T8	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	454126	1		T1	36		T2	54		T3	36
auto[1]	5162	1		T62	123		T65	73		T63	128

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24506	1		T1	2		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	147	1		T62	4		T63	5		T64	4
all_values[0]	auto[1]	auto[0]	727	1		T12	3		T8	3		T16	4
all_values[0]	auto[1]	auto[1]	136	1		T62	4		T65	4		T63	3
all_values[1]	auto[0]	auto[0]	24888	1		T1	2		T3	2		T12	3
all_values[1]	auto[0]	auto[1]	157	1		T62	3		T65	1		T64	6
all_values[1]	auto[1]	auto[0]	325	1		T2	3		T17	3		T45	3
all_values[1]	auto[1]	auto[1]	146	1		T62	5		T65	3		T63	8
all_values[2]	auto[0]	auto[0]	25191	1		T1	2		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	154	1		T62	6		T65	4		T63	2
all_values[2]	auto[1]	auto[0]	29	1		T62	1		T63	1		T66	3
all_values[2]	auto[1]	auto[1]	142	1		T62	1		T63	5		T64	1
all_values[3]	auto[0]	auto[0]	25203	1		T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	146	1		T62	6		T65	3		T63	3
all_values[3]	auto[1]	auto[0]	29	1		T65	1		T63	2		T67	2
all_values[3]	auto[1]	auto[1]	138	1		T62	2		T65	1		T63	3
all_values[4]	auto[0]	auto[0]	25197	1		T1	2		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	136	1		T62	4		T65	1		T63	4
all_values[4]	auto[1]	auto[0]	23	1		T247	2		T246	2		T248	5
all_values[4]	auto[1]	auto[1]	160	1		T62	4		T65	4		T63	4
all_values[5]	auto[0]	auto[0]	25200	1		T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	134	1		T62	1		T65	2		T63	5
all_values[5]	auto[1]	auto[0]	20	1		T64	1		T67	1		T247	4
all_values[5]	auto[1]	auto[1]	162	1		T62	7		T65	3		T63	3
all_values[6]	auto[0]	auto[0]	25203	1		T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	140	1		T62	2		T65	3		T63	4
all_values[6]	auto[1]	auto[0]	22	1		T67	1		T249	1		T246	1
all_values[6]	auto[1]	auto[1]	151	1		T62	6		T65	2		T63	4
all_values[7]	auto[0]	auto[0]	25202	1		T1	2		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	150	1		T62	4		T65	4		T63	1
all_values[7]	auto[1]	auto[0]	29	1		T67	1		T246	1		T250	1
all_values[7]	auto[1]	auto[1]	135	1		T65	1		T63	7		T64	2
all_values[8]	auto[0]	auto[0]	25208	1		T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	146	1		T62	6		T64	3		T66	5
all_values[8]	auto[1]	auto[0]	32	1		T65	4		T63	2		T66	2
all_values[8]	auto[1]	auto[1]	130	1		T62	2		T63	3		T64	4
all_values[9]	auto[0]	auto[0]	25204	1		T1	2		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	134	1		T62	3		T63	3		T64	4
all_values[9]	auto[1]	auto[0]	49	1		T62	2		T65	1		T64	1
all_values[9]	auto[1]	auto[1]	129	1		T62	3		T65	3		T63	4
all_values[10]	auto[0]	auto[0]	25204	1		T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	145	1		T62	3		T63	4		T64	3
all_values[10]	auto[1]	auto[0]	33	1		T62	2		T64	2		T66	1
all_values[10]	auto[1]	auto[1]	134	1		T62	3		T65	5		T63	3
all_values[11]	auto[0]	auto[0]	25195	1		T1	2		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	161	1		T62	4		T63	3		T66	4
all_values[11]	auto[1]	auto[0]	32	1		T62	1		T65	5		T63	2
all_values[11]	auto[1]	auto[1]	128	1		T62	2		T63	2		T64	6
all_values[12]	auto[0]	auto[0]	25200	1		T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	148	1		T62	5		T64	4		T66	8
all_values[12]	auto[1]	auto[0]	30	1		T63	1		T64	2		T247	1
all_values[12]	auto[1]	auto[1]	138	1		T62	3		T65	5		T63	5
all_values[13]	auto[0]	auto[0]	25192	1		T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	170	1		T62	5		T65	2		T63	6
all_values[13]	auto[1]	auto[0]	31	1		T62	1		T247	1		T250	2
all_values[13]	auto[1]	auto[1]	123	1		T62	1		T65	3		T63	2
all_values[14]	auto[0]	auto[0]	25205	1		T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	124	1		T65	3		T63	3		T64	4
all_values[14]	auto[1]	auto[0]	27	1		T62	3		T64	1		T251	2
all_values[14]	auto[1]	auto[1]	160	1		T65	1		T63	5		T64	1
all_values[15]	auto[0]	auto[0]	25211	1		T1	2		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	139	1		T62	5		T65	5		T63	1
all_values[15]	auto[1]	auto[0]	29	1		T64	1		T66	1		T67	1
all_values[15]	auto[1]	auto[1]	137	1		T62	3		T63	7		T64	4
all_values[16]	auto[0]	auto[0]	25198	1		T1	2		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	159	1		T62	3		T65	5		T63	5
all_values[16]	auto[1]	auto[0]	24	1		T66	1		T67	1		T247	1
all_values[16]	auto[1]	auto[1]	135	1		T62	5		T63	3		T64	7
all_values[17]	auto[0]	auto[0]	25201	1		T1	2		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	131	1		T62	1		T65	1		T63	4
all_values[17]	auto[1]	auto[0]	27	1		T251	2		T252	1		T253	4
all_values[17]	auto[1]	auto[1]	157	1		T62	7		T65	4		T63	4