Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.42 95.60 88.87 96.47 50.00 94.10 97.35 96.58


Total test records in report: 1480
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T1322 /workspace/coverage/default/39.usbdev_setup_trans_ignored.1091962473 Apr 30 02:49:43 PM PDT 24 Apr 30 02:49:52 PM PDT 24 8369640463 ps
T1323 /workspace/coverage/default/47.usbdev_av_buffer.652867789 Apr 30 02:50:16 PM PDT 24 Apr 30 02:50:26 PM PDT 24 8372579374 ps
T1324 /workspace/coverage/default/17.usbdev_smoke.4143826417 Apr 30 02:47:54 PM PDT 24 Apr 30 02:48:03 PM PDT 24 8436583228 ps
T115 /workspace/coverage/default/23.usbdev_nak_trans.377740340 Apr 30 02:48:31 PM PDT 24 Apr 30 02:48:39 PM PDT 24 8397985315 ps
T1325 /workspace/coverage/default/42.usbdev_fifo_rst.3311803685 Apr 30 02:49:59 PM PDT 24 Apr 30 02:50:02 PM PDT 24 120350417 ps
T1326 /workspace/coverage/default/7.usbdev_enable.2650757538 Apr 30 02:47:09 PM PDT 24 Apr 30 02:47:18 PM PDT 24 8417882753 ps
T1327 /workspace/coverage/default/18.usbdev_max_length_out_transaction.745769678 Apr 30 02:48:11 PM PDT 24 Apr 30 02:48:20 PM PDT 24 8482813261 ps
T1328 /workspace/coverage/default/2.usbdev_out_trans_nak.2006360268 Apr 30 02:46:40 PM PDT 24 Apr 30 02:46:49 PM PDT 24 8416157509 ps
T1329 /workspace/coverage/default/32.usbdev_pkt_buffer.725175923 Apr 30 02:49:20 PM PDT 24 Apr 30 02:49:50 PM PDT 24 16957373313 ps
T1330 /workspace/coverage/default/31.usbdev_out_trans_nak.3094027692 Apr 30 02:49:16 PM PDT 24 Apr 30 02:49:27 PM PDT 24 8422351314 ps
T1331 /workspace/coverage/default/22.usbdev_max_length_out_transaction.2923485702 Apr 30 02:48:33 PM PDT 24 Apr 30 02:48:42 PM PDT 24 8420349197 ps
T1332 /workspace/coverage/default/34.usbdev_pending_in_trans.3532398504 Apr 30 02:49:34 PM PDT 24 Apr 30 02:49:43 PM PDT 24 8382777748 ps
T1333 /workspace/coverage/default/9.usbdev_min_length_out_transaction.1248082082 Apr 30 02:47:30 PM PDT 24 Apr 30 02:47:38 PM PDT 24 8369189384 ps
T1334 /workspace/coverage/default/29.usbdev_min_length_out_transaction.3832614189 Apr 30 02:49:00 PM PDT 24 Apr 30 02:49:08 PM PDT 24 8381651251 ps
T1335 /workspace/coverage/default/18.usbdev_in_stall.4235683513 Apr 30 02:48:18 PM PDT 24 Apr 30 02:48:28 PM PDT 24 8371394206 ps
T1336 /workspace/coverage/default/3.usbdev_out_stall.1536592177 Apr 30 02:46:50 PM PDT 24 Apr 30 02:46:59 PM PDT 24 8404796853 ps
T1337 /workspace/coverage/default/4.usbdev_out_trans_nak.2813930238 Apr 30 02:46:54 PM PDT 24 Apr 30 02:47:03 PM PDT 24 8383859880 ps
T1338 /workspace/coverage/default/17.usbdev_fifo_rst.3560458513 Apr 30 02:48:12 PM PDT 24 Apr 30 02:48:13 PM PDT 24 110902820 ps
T1339 /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2761821448 Apr 30 02:49:50 PM PDT 24 Apr 30 02:49:59 PM PDT 24 8420063048 ps
T1340 /workspace/coverage/default/2.usbdev_max_length_out_transaction.3635642056 Apr 30 02:46:37 PM PDT 24 Apr 30 02:46:45 PM PDT 24 8414526391 ps
T1341 /workspace/coverage/default/46.usbdev_random_length_out_trans.1187667898 Apr 30 02:50:22 PM PDT 24 Apr 30 02:50:31 PM PDT 24 8388392118 ps
T1342 /workspace/coverage/default/24.max_length_in_transaction.3592951801 Apr 30 02:48:41 PM PDT 24 Apr 30 02:48:50 PM PDT 24 8470722695 ps
T1343 /workspace/coverage/default/5.usbdev_pkt_sent.2249786813 Apr 30 02:47:01 PM PDT 24 Apr 30 02:47:10 PM PDT 24 8487584849 ps
T1344 /workspace/coverage/default/39.usbdev_max_length_out_transaction.3498944771 Apr 30 02:49:46 PM PDT 24 Apr 30 02:49:55 PM PDT 24 8421229519 ps
T1345 /workspace/coverage/default/38.usbdev_fifo_rst.3831382611 Apr 30 02:49:40 PM PDT 24 Apr 30 02:49:43 PM PDT 24 202151027 ps
T1346 /workspace/coverage/default/7.usbdev_phy_pins_sense.2622740448 Apr 30 02:47:16 PM PDT 24 Apr 30 02:47:18 PM PDT 24 61124077 ps
T1347 /workspace/coverage/default/46.usbdev_nak_trans.1406477863 Apr 30 02:50:18 PM PDT 24 Apr 30 02:50:28 PM PDT 24 8430540269 ps
T1348 /workspace/coverage/default/7.usbdev_fifo_rst.1032289961 Apr 30 02:47:08 PM PDT 24 Apr 30 02:47:11 PM PDT 24 125900305 ps
T1349 /workspace/coverage/default/23.usbdev_fifo_rst.2538329651 Apr 30 02:48:33 PM PDT 24 Apr 30 02:48:36 PM PDT 24 65018040 ps
T1350 /workspace/coverage/default/18.usbdev_pkt_received.819865356 Apr 30 02:48:11 PM PDT 24 Apr 30 02:48:20 PM PDT 24 8397230497 ps
T1351 /workspace/coverage/default/3.usbdev_stall_trans.2579217100 Apr 30 02:46:50 PM PDT 24 Apr 30 02:47:00 PM PDT 24 8411897462 ps
T1352 /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2928105471 Apr 30 02:46:32 PM PDT 24 Apr 30 02:46:41 PM PDT 24 8367222954 ps
T1353 /workspace/coverage/default/49.usbdev_fifo_rst.3510501664 Apr 30 02:50:27 PM PDT 24 Apr 30 02:50:29 PM PDT 24 176263614 ps
T1354 /workspace/coverage/default/44.usbdev_fifo_rst.668352082 Apr 30 02:50:12 PM PDT 24 Apr 30 02:50:15 PM PDT 24 70777243 ps
T1355 /workspace/coverage/default/29.usbdev_phy_pins_sense.1858494353 Apr 30 02:49:10 PM PDT 24 Apr 30 02:49:11 PM PDT 24 51115757 ps
T1356 /workspace/coverage/default/16.usbdev_min_length_out_transaction.2590555309 Apr 30 02:47:53 PM PDT 24 Apr 30 02:48:02 PM PDT 24 8373982571 ps
T1357 /workspace/coverage/default/19.usbdev_max_length_out_transaction.4031747333 Apr 30 02:48:22 PM PDT 24 Apr 30 02:48:31 PM PDT 24 8444838922 ps
T1358 /workspace/coverage/default/22.usbdev_phy_pins_sense.3657959757 Apr 30 02:48:33 PM PDT 24 Apr 30 02:48:40 PM PDT 24 52350867 ps
T1359 /workspace/coverage/default/27.max_length_in_transaction.143354342 Apr 30 02:48:45 PM PDT 24 Apr 30 02:48:56 PM PDT 24 8518673476 ps
T1360 /workspace/coverage/default/3.usbdev_av_buffer.1012350252 Apr 30 02:46:45 PM PDT 24 Apr 30 02:46:53 PM PDT 24 8379479160 ps
T1361 /workspace/coverage/default/49.usbdev_av_buffer.10950210 Apr 30 02:50:24 PM PDT 24 Apr 30 02:50:33 PM PDT 24 8384335048 ps
T1362 /workspace/coverage/default/26.usbdev_in_iso.3456800333 Apr 30 02:48:54 PM PDT 24 Apr 30 02:49:03 PM PDT 24 8455203031 ps
T1363 /workspace/coverage/default/29.usbdev_smoke.3488858256 Apr 30 02:49:00 PM PDT 24 Apr 30 02:49:11 PM PDT 24 8453474379 ps
T1364 /workspace/coverage/default/2.usbdev_fifo_rst.1965819414 Apr 30 02:46:41 PM PDT 24 Apr 30 02:46:44 PM PDT 24 199767173 ps
T1365 /workspace/coverage/default/49.usbdev_in_trans.3814470037 Apr 30 02:50:37 PM PDT 24 Apr 30 02:50:45 PM PDT 24 8442032654 ps
T1366 /workspace/coverage/default/30.usbdev_pkt_received.1762794806 Apr 30 02:49:18 PM PDT 24 Apr 30 02:49:28 PM PDT 24 8396647469 ps
T1367 /workspace/coverage/default/6.usbdev_phy_pins_sense.4040972797 Apr 30 02:47:07 PM PDT 24 Apr 30 02:47:09 PM PDT 24 34321635 ps
T1368 /workspace/coverage/default/40.usbdev_out_stall.3533278587 Apr 30 02:49:54 PM PDT 24 Apr 30 02:50:04 PM PDT 24 8394818998 ps
T1369 /workspace/coverage/default/30.usbdev_smoke.103251021 Apr 30 02:49:10 PM PDT 24 Apr 30 02:49:19 PM PDT 24 8446489932 ps
T1370 /workspace/coverage/default/36.usbdev_in_trans.3005426395 Apr 30 02:49:23 PM PDT 24 Apr 30 02:49:32 PM PDT 24 8420147405 ps
T1371 /workspace/coverage/default/43.usbdev_setup_stage.1111570509 Apr 30 02:50:05 PM PDT 24 Apr 30 02:50:15 PM PDT 24 8374882981 ps
T1372 /workspace/coverage/default/39.usbdev_pkt_sent.2649425771 Apr 30 02:49:49 PM PDT 24 Apr 30 02:49:59 PM PDT 24 8417574552 ps
T1373 /workspace/coverage/default/33.usbdev_pkt_received.2604033564 Apr 30 02:49:19 PM PDT 24 Apr 30 02:49:27 PM PDT 24 8461253258 ps
T1374 /workspace/coverage/default/40.usbdev_in_stall.1594475075 Apr 30 02:49:52 PM PDT 24 Apr 30 02:50:00 PM PDT 24 8369248205 ps
T1375 /workspace/coverage/default/16.usbdev_setup_stage.745035981 Apr 30 02:47:58 PM PDT 24 Apr 30 02:48:07 PM PDT 24 8379105286 ps
T60 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3121521987 Apr 30 02:42:20 PM PDT 24 Apr 30 02:42:22 PM PDT 24 154517176 ps
T50 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2322072419 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:18 PM PDT 24 323474379 ps
T61 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1087326345 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:17 PM PDT 24 111054458 ps
T62 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.548077380 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:01 PM PDT 24 39227645 ps
T51 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.360705192 Apr 30 02:42:12 PM PDT 24 Apr 30 02:42:14 PM PDT 24 205089212 ps
T227 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2168813432 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:09 PM PDT 24 93928642 ps
T65 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3039614115 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:08 PM PDT 24 38080552 ps
T90 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3626044790 Apr 30 02:42:05 PM PDT 24 Apr 30 02:42:06 PM PDT 24 31135379 ps
T63 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3450076654 Apr 30 02:42:11 PM PDT 24 Apr 30 02:42:13 PM PDT 24 68758603 ps
T52 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3757046788 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:16 PM PDT 24 84425256 ps
T196 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4213262644 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:11 PM PDT 24 168502126 ps
T58 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1526883038 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:08 PM PDT 24 85009694 ps
T199 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1686035774 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:12 PM PDT 24 97355734 ps
T210 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3829325310 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:13 PM PDT 24 86714554 ps
T59 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1852079964 Apr 30 02:42:05 PM PDT 24 Apr 30 02:42:08 PM PDT 24 478816339 ps
T64 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1327070897 Apr 30 02:42:25 PM PDT 24 Apr 30 02:42:26 PM PDT 24 35624497 ps
T91 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3080666162 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:04 PM PDT 24 255244566 ps
T92 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3459554492 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:13 PM PDT 24 552809067 ps
T93 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1024279949 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 67295454 ps
T66 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3149807191 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:18 PM PDT 24 34215200 ps
T67 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4072637430 Apr 30 02:42:26 PM PDT 24 Apr 30 02:42:28 PM PDT 24 30695029 ps
T251 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.294096801 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:24 PM PDT 24 34032983 ps
T208 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2714539275 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:11 PM PDT 24 86600765 ps
T247 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.88260288 Apr 30 02:42:24 PM PDT 24 Apr 30 02:42:25 PM PDT 24 40454700 ps
T249 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3592086066 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:02 PM PDT 24 27116833 ps
T216 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3964165563 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:21 PM PDT 24 436439518 ps
T246 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.822375179 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:24 PM PDT 24 58460189 ps
T218 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3981813591 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:16 PM PDT 24 626369308 ps
T228 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3253420194 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:09 PM PDT 24 67731383 ps
T229 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3788099288 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:03 PM PDT 24 101803197 ps
T254 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3246846797 Apr 30 02:42:22 PM PDT 24 Apr 30 02:42:23 PM PDT 24 33378905 ps
T237 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2261869349 Apr 30 02:41:58 PM PDT 24 Apr 30 02:42:00 PM PDT 24 96744951 ps
T217 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2102272821 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:09 PM PDT 24 74990774 ps
T238 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2908172014 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:08 PM PDT 24 75175077 ps
T230 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1836906718 Apr 30 02:41:59 PM PDT 24 Apr 30 02:42:04 PM PDT 24 827586318 ps
T250 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.134383145 Apr 30 02:42:22 PM PDT 24 Apr 30 02:42:23 PM PDT 24 31771079 ps
T242 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.797105859 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:15 PM PDT 24 145963465 ps
T239 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3050448501 Apr 30 02:42:12 PM PDT 24 Apr 30 02:42:14 PM PDT 24 188061168 ps
T255 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1822802272 Apr 30 02:42:24 PM PDT 24 Apr 30 02:42:25 PM PDT 24 28562963 ps
T197 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3321033297 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:19 PM PDT 24 90744977 ps
T243 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1001065122 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 90157137 ps
T1376 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1732653298 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 153468384 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1945306891 Apr 30 02:42:04 PM PDT 24 Apr 30 02:42:09 PM PDT 24 388032688 ps
T1377 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2255829870 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:05 PM PDT 24 95981090 ps
T1378 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3549701876 Apr 30 02:42:19 PM PDT 24 Apr 30 02:42:22 PM PDT 24 499192846 ps
T198 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.298422747 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:12 PM PDT 24 155706543 ps
T244 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1225353025 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:18 PM PDT 24 121134200 ps
T248 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1800102740 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:17 PM PDT 24 97978881 ps
T257 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3118364686 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:24 PM PDT 24 36368662 ps
T252 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2232421807 Apr 30 02:41:59 PM PDT 24 Apr 30 02:42:01 PM PDT 24 26949728 ps
T1379 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.509472107 Apr 30 02:41:58 PM PDT 24 Apr 30 02:42:03 PM PDT 24 474385232 ps
T256 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2491190394 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:22 PM PDT 24 30493730 ps
T253 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.64418862 Apr 30 02:42:30 PM PDT 24 Apr 30 02:42:31 PM PDT 24 35483997 ps
T211 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1092551620 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:19 PM PDT 24 114921483 ps
T245 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2917303632 Apr 30 02:42:04 PM PDT 24 Apr 30 02:42:06 PM PDT 24 87446710 ps
T1380 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4146596885 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:17 PM PDT 24 43652084 ps
T1381 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3647979834 Apr 30 02:42:24 PM PDT 24 Apr 30 02:42:27 PM PDT 24 126194221 ps
T213 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2677653709 Apr 30 02:41:59 PM PDT 24 Apr 30 02:42:00 PM PDT 24 45847025 ps
T1382 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.686696332 Apr 30 02:42:29 PM PDT 24 Apr 30 02:42:30 PM PDT 24 30032207 ps
T1383 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1773376355 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:05 PM PDT 24 161622307 ps
T1384 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.422836509 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:22 PM PDT 24 31981911 ps
T212 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3154613726 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:18 PM PDT 24 77245884 ps
T1385 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1538479719 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:25 PM PDT 24 26431243 ps
T1386 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3598498311 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:24 PM PDT 24 41353799 ps
T259 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2620255127 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:13 PM PDT 24 844524655 ps
T1387 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4181366672 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:17 PM PDT 24 129951003 ps
T232 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1702892258 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:04 PM PDT 24 73775927 ps
T209 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2144187763 Apr 30 02:41:59 PM PDT 24 Apr 30 02:42:02 PM PDT 24 269868037 ps
T1388 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2352102447 Apr 30 02:42:22 PM PDT 24 Apr 30 02:42:23 PM PDT 24 33425627 ps
T258 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2506095259 Apr 30 02:42:19 PM PDT 24 Apr 30 02:42:20 PM PDT 24 33004105 ps
T1389 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1972262777 Apr 30 02:42:11 PM PDT 24 Apr 30 02:42:15 PM PDT 24 274579128 ps
T260 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.203326051 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:07 PM PDT 24 740806008 ps
T1390 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3499958505 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:16 PM PDT 24 32825461 ps
T1391 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2470164292 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:17 PM PDT 24 101946156 ps
T1392 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1570596674 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:14 PM PDT 24 26000502 ps
T1393 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3626779739 Apr 30 02:42:18 PM PDT 24 Apr 30 02:42:20 PM PDT 24 35867950 ps
T1394 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.813867774 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:27 PM PDT 24 146260674 ps
T1395 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1722951320 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:22 PM PDT 24 71394625 ps
T1396 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2638892372 Apr 30 02:42:18 PM PDT 24 Apr 30 02:42:21 PM PDT 24 71989601 ps
T1397 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3514597100 Apr 30 02:42:20 PM PDT 24 Apr 30 02:42:23 PM PDT 24 86503000 ps
T1398 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3136158449 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:03 PM PDT 24 237729117 ps
T1399 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4102393650 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:08 PM PDT 24 344757876 ps
T261 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1490875346 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:12 PM PDT 24 1739112613 ps
T1400 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3762539609 Apr 30 02:42:27 PM PDT 24 Apr 30 02:42:28 PM PDT 24 30152081 ps
T233 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2651973975 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:17 PM PDT 24 751946866 ps
T234 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2644431706 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:12 PM PDT 24 535113231 ps
T235 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3680206446 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:03 PM PDT 24 126533787 ps
T1401 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3361281982 Apr 30 02:42:31 PM PDT 24 Apr 30 02:42:32 PM PDT 24 30855658 ps
T56 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.947958018 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:01 PM PDT 24 123374954 ps
T1402 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.797211702 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:24 PM PDT 24 77272823 ps
T1403 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1193461787 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:18 PM PDT 24 93272196 ps
T1404 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1168377676 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:17 PM PDT 24 169440878 ps
T1405 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2010420808 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:14 PM PDT 24 469152312 ps
T214 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3428507587 Apr 30 02:42:03 PM PDT 24 Apr 30 02:42:04 PM PDT 24 138753669 ps
T236 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3062060862 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 71184948 ps
T1406 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3482676038 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:14 PM PDT 24 27116164 ps
T57 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1920202213 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:08 PM PDT 24 74091379 ps
T1407 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4187392440 Apr 30 02:41:59 PM PDT 24 Apr 30 02:42:01 PM PDT 24 133808376 ps
T1408 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2712272610 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:16 PM PDT 24 47803847 ps
T1409 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1316311628 Apr 30 02:42:22 PM PDT 24 Apr 30 02:42:24 PM PDT 24 34381699 ps
T1410 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1054104891 Apr 30 02:42:12 PM PDT 24 Apr 30 02:42:14 PM PDT 24 76646500 ps
T1411 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1284272564 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:02 PM PDT 24 163419641 ps
T1412 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1895013591 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:11 PM PDT 24 29080212 ps
T264 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2613048107 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:19 PM PDT 24 555646345 ps
T1413 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2548024287 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:12 PM PDT 24 68640946 ps
T1414 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2455392479 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:14 PM PDT 24 37753735 ps
T1415 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1576899199 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:22 PM PDT 24 84971276 ps
T1416 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3987079900 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:25 PM PDT 24 30789864 ps
T1417 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2321132966 Apr 30 02:42:22 PM PDT 24 Apr 30 02:42:23 PM PDT 24 25200535 ps
T1418 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.38694314 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:04 PM PDT 24 74980531 ps
T1419 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3292732079 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:15 PM PDT 24 80991689 ps
T1420 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2566208685 Apr 30 02:42:17 PM PDT 24 Apr 30 02:42:19 PM PDT 24 97266261 ps
T1421 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.459585636 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 104825610 ps
T1422 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3515238212 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:11 PM PDT 24 70580327 ps
T1423 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3560735264 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 49029433 ps
T1424 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.363728711 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:05 PM PDT 24 157494126 ps
T1425 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.518443819 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:04 PM PDT 24 74928196 ps
T1426 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3278449578 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:25 PM PDT 24 36172725 ps
T263 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.622685955 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:26 PM PDT 24 604847369 ps
T1427 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2582029869 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:08 PM PDT 24 96262791 ps
T1428 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2831553133 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:04 PM PDT 24 50337800 ps
T1429 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.251047728 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:15 PM PDT 24 124575025 ps
T1430 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.55457113 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:16 PM PDT 24 42840781 ps
T1431 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.273846732 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:12 PM PDT 24 84300359 ps
T1432 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3852675897 Apr 30 02:42:07 PM PDT 24 Apr 30 02:42:11 PM PDT 24 122772851 ps
T1433 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3978498401 Apr 30 02:42:04 PM PDT 24 Apr 30 02:42:15 PM PDT 24 1264660950 ps
T1434 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1236285710 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:04 PM PDT 24 146915341 ps
T1435 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.996287667 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:13 PM PDT 24 370806069 ps
T1436 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1379869442 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:18 PM PDT 24 224464850 ps
T1437 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.907016950 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:10 PM PDT 24 60482921 ps
T1438 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2432059486 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:09 PM PDT 24 33878611 ps
T1439 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2855196353 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:10 PM PDT 24 106880359 ps
T1440 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1077661186 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:22 PM PDT 24 34807399 ps
T1441 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.937894185 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:17 PM PDT 24 87576612 ps
T1442 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3845213783 Apr 30 02:42:11 PM PDT 24 Apr 30 02:42:13 PM PDT 24 216399707 ps
T1443 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1130344893 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:18 PM PDT 24 369259285 ps
T1444 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1573694462 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:14 PM PDT 24 75972733 ps
T1445 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.375702932 Apr 30 02:42:21 PM PDT 24 Apr 30 02:42:22 PM PDT 24 31555483 ps
T1446 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1696709224 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:11 PM PDT 24 54198925 ps
T1447 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1079632121 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:08 PM PDT 24 40349091 ps
T1448 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2240359468 Apr 30 02:42:23 PM PDT 24 Apr 30 02:42:24 PM PDT 24 41502909 ps
T1449 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2393386669 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:19 PM PDT 24 389590278 ps
T1450 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.43437809 Apr 30 02:42:11 PM PDT 24 Apr 30 02:42:13 PM PDT 24 81075176 ps
T1451 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1087836533 Apr 30 02:42:06 PM PDT 24 Apr 30 02:42:08 PM PDT 24 53994385 ps
T1452 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.187281077 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:15 PM PDT 24 131310869 ps
T1453 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2567110824 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:03 PM PDT 24 137325970 ps
T1454 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.139692805 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:06 PM PDT 24 626305505 ps
T1455 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2467798350 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:12 PM PDT 24 171042391 ps
T1456 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.901432460 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:02 PM PDT 24 39597872 ps
T1457 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2095304334 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:17 PM PDT 24 115702932 ps
T1458 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.936988177 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:02 PM PDT 24 47889558 ps
T1459 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.250945652 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:17 PM PDT 24 234197371 ps
T1460 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3355003521 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:19 PM PDT 24 716632033 ps
T1461 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2096140053 Apr 30 02:42:22 PM PDT 24 Apr 30 02:42:24 PM PDT 24 36897873 ps
T1462 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2462774454 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:01 PM PDT 24 61302365 ps
T1463 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3168882436 Apr 30 02:42:24 PM PDT 24 Apr 30 02:42:25 PM PDT 24 38592247 ps
T1464 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.889655517 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:16 PM PDT 24 87967954 ps
T1465 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3483580015 Apr 30 02:42:24 PM PDT 24 Apr 30 02:42:26 PM PDT 24 51114173 ps
T1466 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2942224635 Apr 30 02:42:10 PM PDT 24 Apr 30 02:42:11 PM PDT 24 33806910 ps
T1467 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1586698243 Apr 30 02:42:15 PM PDT 24 Apr 30 02:42:22 PM PDT 24 679401837 ps
T1468 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.382227782 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:15 PM PDT 24 166222443 ps
T1469 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2469684166 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:18 PM PDT 24 68706633 ps
T215 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1976875296 Apr 30 02:42:16 PM PDT 24 Apr 30 02:42:20 PM PDT 24 364501975 ps
T1470 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3199752746 Apr 30 02:42:00 PM PDT 24 Apr 30 02:42:04 PM PDT 24 119773041 ps
T1471 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.233906609 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:11 PM PDT 24 65368580 ps
T1472 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1920266598 Apr 30 02:42:13 PM PDT 24 Apr 30 02:42:14 PM PDT 24 85770352 ps
T1473 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1381789985 Apr 30 02:42:12 PM PDT 24 Apr 30 02:42:14 PM PDT 24 85345975 ps
T1474 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1734136146 Apr 30 02:42:08 PM PDT 24 Apr 30 02:42:12 PM PDT 24 229021086 ps
T1475 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4050646285 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:04 PM PDT 24 53924856 ps
T1476 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1395790421 Apr 30 02:41:59 PM PDT 24 Apr 30 02:42:01 PM PDT 24 110761896 ps
T1477 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2086743949 Apr 30 02:42:14 PM PDT 24 Apr 30 02:42:16 PM PDT 24 82670164 ps
T1478 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2722842696 Apr 30 02:42:19 PM PDT 24 Apr 30 02:42:21 PM PDT 24 149722832 ps
T1479 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2894849820 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:04 PM PDT 24 62241110 ps
T1480 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2665680635 Apr 30 02:42:01 PM PDT 24 Apr 30 02:42:03 PM PDT 24 150684972 ps
T262 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.437209188 Apr 30 02:42:09 PM PDT 24 Apr 30 02:42:15 PM PDT 24 1271408523 ps

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.940453588
Short name T9
Test name
Test status
Simulation time 18186938468 ps
CPU time 35.99 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:48 PM PDT 24
Peak memory 204404 kb
Host smart-c5b5020e-d0e7-4478-a4cd-48c3d4a701ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94045
3588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.940453588
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3149807191
Short name T66
Test name
Test status
Simulation time 34215200 ps
CPU time 0.65 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 203248 kb
Host smart-84a63c5c-83cb-4728-b3c5-f49247166677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149807191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3149807191
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3948764236
Short name T11
Test name
Test status
Simulation time 21552317308 ps
CPU time 38.98 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:49:11 PM PDT 24
Peak memory 204428 kb
Host smart-ac269802-24d8-4def-9a15-154bc2b1f8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
64236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3948764236
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2322072419
Short name T50
Test name
Test status
Simulation time 323474379 ps
CPU time 2.9 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 203928 kb
Host smart-6f3487da-b202-4a21-a38a-c68e07f9b043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2322072419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2322072419
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3364953352
Short name T8
Test name
Test status
Simulation time 8444838458 ps
CPU time 8.77 seconds
Started Apr 30 02:49:25 PM PDT 24
Finished Apr 30 02:49:35 PM PDT 24
Peak memory 204072 kb
Host smart-fe37b09d-9b64-4ebc-85c7-01b778f63719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
53352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3364953352
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.134383145
Short name T250
Test name
Test status
Simulation time 31771079 ps
CPU time 0.66 seconds
Started Apr 30 02:42:22 PM PDT 24
Finished Apr 30 02:42:23 PM PDT 24
Peak memory 203308 kb
Host smart-ec60d28d-26b8-4be0-bc25-faa0f70d6336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=134383145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.134383145
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2714539275
Short name T208
Test name
Test status
Simulation time 86600765 ps
CPU time 2.69 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 204056 kb
Host smart-a428d3c4-5ccb-4c96-8174-6d6ba0b99f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2714539275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2714539275
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2444848137
Short name T27
Test name
Test status
Simulation time 36831121 ps
CPU time 0.64 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:36 PM PDT 24
Peak memory 203976 kb
Host smart-df214312-dc32-47e1-8d83-5d0abf7ecc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24448
48137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2444848137
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1610957279
Short name T142
Test name
Test status
Simulation time 8466037970 ps
CPU time 7.91 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204108 kb
Host smart-ce057a69-e67f-4d55-a028-929774756a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16109
57279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1610957279
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2093751530
Short name T1
Test name
Test status
Simulation time 8365806143 ps
CPU time 8.87 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204056 kb
Host smart-93e6a043-16b1-4c64-a908-0c6babb7dc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
51530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2093751530
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.4188989635
Short name T20
Test name
Test status
Simulation time 8369502965 ps
CPU time 8.31 seconds
Started Apr 30 02:49:04 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 204044 kb
Host smart-7257887f-ed1f-4001-a4d1-df6c2a5d2bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41889
89635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.4188989635
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.194571602
Short name T24
Test name
Test status
Simulation time 8413321304 ps
CPU time 8.29 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:21 PM PDT 24
Peak memory 204044 kb
Host smart-f5b40509-2a2e-41a5-a4fa-088f71729d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19457
1602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.194571602
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3644743268
Short name T53
Test name
Test status
Simulation time 699653176 ps
CPU time 1.44 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:36 PM PDT 24
Peak memory 220316 kb
Host smart-5504c467-e250-4c42-abcc-f4c48f5dbe3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3644743268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3644743268
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.88260288
Short name T247
Test name
Test status
Simulation time 40454700 ps
CPU time 0.68 seconds
Started Apr 30 02:42:24 PM PDT 24
Finished Apr 30 02:42:25 PM PDT 24
Peak memory 203256 kb
Host smart-16df8947-ee47-4f15-a55c-9b732c8e4b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=88260288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.88260288
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.561329840
Short name T17
Test name
Test status
Simulation time 8467796941 ps
CPU time 10.46 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204112 kb
Host smart-d9ff1736-7b24-45fb-ac68-ea60590d8ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56132
9840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.561329840
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2204920752
Short name T312
Test name
Test status
Simulation time 205086184 ps
CPU time 1.86 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:41 PM PDT 24
Peak memory 204160 kb
Host smart-ec44d342-bcc2-4521-baf0-f0391917e992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22049
20752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2204920752
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3253420194
Short name T228
Test name
Test status
Simulation time 67731383 ps
CPU time 0.98 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:09 PM PDT 24
Peak memory 203868 kb
Host smart-5f93426d-cc31-47c1-b53a-6017faa92a10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3253420194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3253420194
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.797211702
Short name T1402
Test name
Test status
Simulation time 77272823 ps
CPU time 0.76 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203272 kb
Host smart-8fe11b92-86e1-46d3-b615-be7d09f4cbd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=797211702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.797211702
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1490875346
Short name T261
Test name
Test status
Simulation time 1739112613 ps
CPU time 5.49 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 204008 kb
Host smart-0d393525-59fc-463b-bfd7-d903cf437e21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1490875346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1490875346
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.4101469864
Short name T79
Test name
Test status
Simulation time 8420715410 ps
CPU time 8.04 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:07 PM PDT 24
Peak memory 204048 kb
Host smart-bb60952e-92ef-43ce-bf67-043a7bc16ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41014
69864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.4101469864
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3118364686
Short name T257
Test name
Test status
Simulation time 36368662 ps
CPU time 0.68 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203260 kb
Host smart-3aeea10e-9aac-453a-806e-7aef37e0642b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3118364686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3118364686
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.947958018
Short name T56
Test name
Test status
Simulation time 123374954 ps
CPU time 0.84 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 203744 kb
Host smart-391ad593-bf24-443d-90c1-0d502fc6aeb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=947958018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.947958018
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.582926316
Short name T96
Test name
Test status
Simulation time 5111432056 ps
CPU time 33.4 seconds
Started Apr 30 02:46:26 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 204328 kb
Host smart-2a9e5281-6f13-41f6-bfd6-3d10a3d40fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58292
6316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.582926316
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3459554492
Short name T92
Test name
Test status
Simulation time 552809067 ps
CPU time 4.3 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 204208 kb
Host smart-62442a48-55fe-40a8-a039-77a80a161141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3459554492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3459554492
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1976875296
Short name T215
Test name
Test status
Simulation time 364501975 ps
CPU time 4.13 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:20 PM PDT 24
Peak memory 203936 kb
Host smart-888f274e-67a7-45c0-975f-19fb17b8f787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1976875296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1976875296
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1800102740
Short name T248
Test name
Test status
Simulation time 97978881 ps
CPU time 0.75 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 203280 kb
Host smart-3ad82a45-e171-446b-9d2a-02c544adf2d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800102740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1800102740
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.622685955
Short name T263
Test name
Test status
Simulation time 604847369 ps
CPU time 4.06 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:26 PM PDT 24
Peak memory 204028 kb
Host smart-9cf2ea77-373d-46f6-9eca-8cb15ade888b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=622685955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.622685955
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3121521987
Short name T60
Test name
Test status
Simulation time 154517176 ps
CPU time 1.36 seconds
Started Apr 30 02:42:20 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203964 kb
Host smart-12661680-cacd-4551-9fe4-03c0321b546c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3121521987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3121521987
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1972262777
Short name T1389
Test name
Test status
Simulation time 274579128 ps
CPU time 3.2 seconds
Started Apr 30 02:42:11 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 212180 kb
Host smart-84779dce-e2c2-426e-a5f9-e4cb5f0c160b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1972262777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1972262777
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3124271290
Short name T28
Test name
Test status
Simulation time 79872088 ps
CPU time 0.68 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:21 PM PDT 24
Peak memory 203912 kb
Host smart-2f540296-588a-49d6-8012-f1d3a2380ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31242
71290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3124271290
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4130214401
Short name T749
Test name
Test status
Simulation time 8441083514 ps
CPU time 10.27 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:49 PM PDT 24
Peak memory 204000 kb
Host smart-138bb5dc-62b1-4481-ae9a-57c161e727ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41302
14401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4130214401
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3728387049
Short name T642
Test name
Test status
Simulation time 8442486965 ps
CPU time 10.08 seconds
Started Apr 30 02:46:32 PM PDT 24
Finished Apr 30 02:46:43 PM PDT 24
Peak memory 204084 kb
Host smart-80155b8d-df1c-4e27-83e7-7d4b30cefedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283
87049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3728387049
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2332689008
Short name T883
Test name
Test status
Simulation time 8397412677 ps
CPU time 7.51 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:45 PM PDT 24
Peak memory 204124 kb
Host smart-1ab66d7c-5048-478b-9a51-e72aec03a1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23326
89008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2332689008
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1868440644
Short name T1090
Test name
Test status
Simulation time 8438819889 ps
CPU time 7.98 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204076 kb
Host smart-6338ef97-2f8d-48d1-873d-5f9ac642c555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18684
40644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1868440644
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3274172492
Short name T689
Test name
Test status
Simulation time 8448613902 ps
CPU time 10.13 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204060 kb
Host smart-711cef48-2688-41b2-8db4-726f0aac991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741
72492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3274172492
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1754637335
Short name T991
Test name
Test status
Simulation time 8448833135 ps
CPU time 9.67 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204100 kb
Host smart-0ff56a2c-dd39-4420-8007-dacc06dba556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
37335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1754637335
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2944428144
Short name T750
Test name
Test status
Simulation time 8376617256 ps
CPU time 8.4 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:47:58 PM PDT 24
Peak memory 204100 kb
Host smart-adf8158b-9df9-451a-abc1-adfab4bface3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29444
28144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2944428144
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.577107053
Short name T154
Test name
Test status
Simulation time 8410906994 ps
CPU time 9.78 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:21 PM PDT 24
Peak memory 204112 kb
Host smart-4bd701c1-152c-46b8-9d9d-8f2ba79d9e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57710
7053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.577107053
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.524665599
Short name T931
Test name
Test status
Simulation time 8407924151 ps
CPU time 7.68 seconds
Started Apr 30 02:48:27 PM PDT 24
Finished Apr 30 02:48:35 PM PDT 24
Peak memory 204112 kb
Host smart-994ae896-e8a6-4363-aed5-8418a6009f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52466
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.524665599
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.550214639
Short name T187
Test name
Test status
Simulation time 8398027504 ps
CPU time 8.29 seconds
Started Apr 30 02:48:47 PM PDT 24
Finished Apr 30 02:48:55 PM PDT 24
Peak memory 204084 kb
Host smart-a2f6e735-db40-4e5e-934c-14e8e9c30352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55021
4639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.550214639
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2982517894
Short name T32
Test name
Test status
Simulation time 8424506342 ps
CPU time 8.77 seconds
Started Apr 30 02:49:05 PM PDT 24
Finished Apr 30 02:49:15 PM PDT 24
Peak memory 204120 kb
Host smart-b07ddef0-b4bb-41aa-a21a-30c861eb7e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29825
17894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2982517894
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.234305523
Short name T13
Test name
Test status
Simulation time 8394245077 ps
CPU time 9.59 seconds
Started Apr 30 02:46:32 PM PDT 24
Finished Apr 30 02:46:42 PM PDT 24
Peak memory 204064 kb
Host smart-1a426cdc-a9fc-4d34-b21a-c7acc99761d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
5523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.234305523
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1353875473
Short name T12
Test name
Test status
Simulation time 8380882054 ps
CPU time 7.54 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:37 PM PDT 24
Peak memory 204116 kb
Host smart-42f870cf-a328-4f25-abd3-9527185efd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13538
75473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1353875473
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2520102321
Short name T138
Test name
Test status
Simulation time 8392295272 ps
CPU time 8.54 seconds
Started Apr 30 02:46:30 PM PDT 24
Finished Apr 30 02:46:39 PM PDT 24
Peak memory 204028 kb
Host smart-276d0a71-8662-418a-9a4b-06b51db89d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
02321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2520102321
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2434524130
Short name T190
Test name
Test status
Simulation time 8364005167 ps
CPU time 7.94 seconds
Started Apr 30 02:46:32 PM PDT 24
Finished Apr 30 02:46:40 PM PDT 24
Peak memory 204140 kb
Host smart-b844cea7-447c-4c0f-ab0e-792cccd33b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
24130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2434524130
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.701414918
Short name T353
Test name
Test status
Simulation time 8451362370 ps
CPU time 7.27 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:41 PM PDT 24
Peak memory 204112 kb
Host smart-223318c9-16b6-4c7b-999e-f916fed90e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70141
4918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.701414918
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2209216122
Short name T1093
Test name
Test status
Simulation time 8428088214 ps
CPU time 7.71 seconds
Started Apr 30 02:46:36 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204004 kb
Host smart-949832a0-f4ed-49be-ad08-b6ffc4672c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
16122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2209216122
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3899562671
Short name T706
Test name
Test status
Simulation time 8388734631 ps
CPU time 8.3 seconds
Started Apr 30 02:46:32 PM PDT 24
Finished Apr 30 02:46:41 PM PDT 24
Peak memory 204136 kb
Host smart-25cd9061-e2de-4dd2-b6fe-4887e361aa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995
62671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3899562671
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2038616678
Short name T442
Test name
Test status
Simulation time 8398414213 ps
CPU time 8.09 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204060 kb
Host smart-8d72bf99-dd28-4894-916f-7f577050dace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
16678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2038616678
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1215399058
Short name T904
Test name
Test status
Simulation time 8395866533 ps
CPU time 8.6 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204016 kb
Host smart-b6c4acef-198f-432f-a9e2-4efc35e8b2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12153
99058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1215399058
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2290967152
Short name T768
Test name
Test status
Simulation time 8436058619 ps
CPU time 8.6 seconds
Started Apr 30 02:47:33 PM PDT 24
Finished Apr 30 02:47:42 PM PDT 24
Peak memory 204076 kb
Host smart-06169dde-ee3b-43ed-895d-22da87b2995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22909
67152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2290967152
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3778359055
Short name T510
Test name
Test status
Simulation time 8411588967 ps
CPU time 7.99 seconds
Started Apr 30 02:47:33 PM PDT 24
Finished Apr 30 02:47:42 PM PDT 24
Peak memory 204112 kb
Host smart-cc471eeb-603e-4670-bb64-7798d6459b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37783
59055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3778359055
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.646803575
Short name T94
Test name
Test status
Simulation time 8426291823 ps
CPU time 7.81 seconds
Started Apr 30 02:47:38 PM PDT 24
Finished Apr 30 02:47:47 PM PDT 24
Peak memory 204056 kb
Host smart-9a0f3e87-578d-4876-836b-82ff06d90536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64680
3575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.646803575
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.504816323
Short name T134
Test name
Test status
Simulation time 8469247303 ps
CPU time 8.03 seconds
Started Apr 30 02:47:42 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204148 kb
Host smart-4112fe7a-e1fc-4700-a4f0-ef97e67003b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50481
6323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.504816323
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2668820272
Short name T95
Test name
Test status
Simulation time 8439961898 ps
CPU time 8.74 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204124 kb
Host smart-59420a57-03de-458e-a53a-336a15483ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26688
20272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2668820272
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3961722203
Short name T387
Test name
Test status
Simulation time 31934637275 ps
CPU time 66.18 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:48:56 PM PDT 24
Peak memory 204400 kb
Host smart-e46ec548-3285-4fa8-af66-a186beaac879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
22203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3961722203
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4018105073
Short name T1218
Test name
Test status
Simulation time 8431158308 ps
CPU time 7.61 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:00 PM PDT 24
Peak memory 204300 kb
Host smart-0ba3ee9b-86df-43cf-8826-f74cfaea25f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40181
05073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4018105073
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3312664565
Short name T879
Test name
Test status
Simulation time 8386033939 ps
CPU time 8.92 seconds
Started Apr 30 02:48:08 PM PDT 24
Finished Apr 30 02:48:18 PM PDT 24
Peak memory 204112 kb
Host smart-12652607-f5ef-40e4-bf4f-1cebc67dd363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
64565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3312664565
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2106025734
Short name T114
Test name
Test status
Simulation time 8454681754 ps
CPU time 7.81 seconds
Started Apr 30 02:48:09 PM PDT 24
Finished Apr 30 02:48:17 PM PDT 24
Peak memory 203984 kb
Host smart-63d07957-9898-45ad-aa2c-79e41072be53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21060
25734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2106025734
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2414767671
Short name T123
Test name
Test status
Simulation time 8389543328 ps
CPU time 8.36 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 204104 kb
Host smart-bfa8e5f7-f6a8-4789-8e37-c15fd27a8059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
67671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2414767671
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2744454892
Short name T100
Test name
Test status
Simulation time 8434506002 ps
CPU time 7.99 seconds
Started Apr 30 02:46:30 PM PDT 24
Finished Apr 30 02:46:38 PM PDT 24
Peak memory 204124 kb
Host smart-a424a0db-b408-4fa4-850c-3d8e7c5593dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27444
54892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2744454892
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3981129915
Short name T98
Test name
Test status
Simulation time 8412001377 ps
CPU time 7.71 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:27 PM PDT 24
Peak memory 204116 kb
Host smart-d21f0e87-074a-4180-a65f-c26a5de8e230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39811
29915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3981129915
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.927065703
Short name T176
Test name
Test status
Simulation time 8373102717 ps
CPU time 8.11 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 203980 kb
Host smart-3e4f900c-7323-43ee-87a1-162ee58032da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92706
5703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.927065703
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3052389452
Short name T116
Test name
Test status
Simulation time 8404230296 ps
CPU time 10.58 seconds
Started Apr 30 02:49:54 PM PDT 24
Finished Apr 30 02:50:05 PM PDT 24
Peak memory 204096 kb
Host smart-be2dd750-7e36-4077-9f14-cff39c79cd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523
89452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3052389452
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3199752746
Short name T1470
Test name
Test status
Simulation time 119773041 ps
CPU time 3.36 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 203960 kb
Host smart-c2e88cd1-6d16-4c15-9862-3b0be4869b5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3199752746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3199752746
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1836906718
Short name T230
Test name
Test status
Simulation time 827586318 ps
CPU time 4.48 seconds
Started Apr 30 02:41:59 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 203936 kb
Host smart-b7278772-3e6f-47cd-b5be-c5934ee3623e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1836906718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1836906718
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3428507587
Short name T214
Test name
Test status
Simulation time 138753669 ps
CPU time 0.9 seconds
Started Apr 30 02:42:03 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 203704 kb
Host smart-acc9fd91-1edc-4040-876f-11324b9aabb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3428507587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3428507587
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1236285710
Short name T1434
Test name
Test status
Simulation time 146915341 ps
CPU time 2.13 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 212228 kb
Host smart-efd6d4a0-c0c4-41b9-9c3f-da64be09e3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236285710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1236285710
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3680206446
Short name T235
Test name
Test status
Simulation time 126533787 ps
CPU time 1.04 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 203916 kb
Host smart-0a4c456f-4942-49c2-9f2b-67762fb071cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3680206446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3680206446
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2232421807
Short name T252
Test name
Test status
Simulation time 26949728 ps
CPU time 0.66 seconds
Started Apr 30 02:41:59 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 203228 kb
Host smart-c0a1001f-74f4-44ad-8256-b896131b8282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2232421807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2232421807
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2831553133
Short name T1428
Test name
Test status
Simulation time 50337800 ps
CPU time 1.37 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 212176 kb
Host smart-d40b1a49-fa27-4a68-b9f6-24b1795f2279
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2831553133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2831553133
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.363728711
Short name T1424
Test name
Test status
Simulation time 157494126 ps
CPU time 3.98 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:05 PM PDT 24
Peak memory 203964 kb
Host smart-4ee18356-3fd3-4a9a-9527-e52942746cb7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=363728711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.363728711
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2261869349
Short name T237
Test name
Test status
Simulation time 96744951 ps
CPU time 1.23 seconds
Started Apr 30 02:41:58 PM PDT 24
Finished Apr 30 02:42:00 PM PDT 24
Peak memory 203956 kb
Host smart-2a7ebd86-3993-4e16-baf4-b92e2b778dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2261869349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2261869349
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4187392440
Short name T1407
Test name
Test status
Simulation time 133808376 ps
CPU time 1.88 seconds
Started Apr 30 02:41:59 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 204132 kb
Host smart-04664f1c-72ee-4074-b27d-951558014f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4187392440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.4187392440
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.203326051
Short name T260
Test name
Test status
Simulation time 740806008 ps
CPU time 4.52 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:07 PM PDT 24
Peak memory 203980 kb
Host smart-864253bb-55e0-4493-967b-5e12d60641e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=203326051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.203326051
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.518443819
Short name T1425
Test name
Test status
Simulation time 74928196 ps
CPU time 1.93 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 203804 kb
Host smart-0021dcab-217d-43d4-99b6-e034189188cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=518443819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.518443819
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3978498401
Short name T1433
Test name
Test status
Simulation time 1264660950 ps
CPU time 10.16 seconds
Started Apr 30 02:42:04 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 203836 kb
Host smart-a72dcfa7-3217-437e-8e6f-cd1ec673f930
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3978498401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3978498401
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2665680635
Short name T1480
Test name
Test status
Simulation time 150684972 ps
CPU time 1.81 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 212228 kb
Host smart-0567c967-3bae-4100-845d-8a4dae189fe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665680635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2665680635
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2462774454
Short name T1462
Test name
Test status
Simulation time 61302365 ps
CPU time 1.07 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 204028 kb
Host smart-95976bc9-93ba-4667-aa4b-f90f5e711a46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2462774454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2462774454
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.901432460
Short name T1456
Test name
Test status
Simulation time 39597872 ps
CPU time 0.68 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:02 PM PDT 24
Peak memory 203108 kb
Host smart-81e938a3-c051-4fa9-a9fd-7a5e5045df32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=901432460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.901432460
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3788099288
Short name T229
Test name
Test status
Simulation time 101803197 ps
CPU time 1.43 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 203896 kb
Host smart-2f1de3f5-12f3-467b-a463-ac4f1b651415
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3788099288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3788099288
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.509472107
Short name T1379
Test name
Test status
Simulation time 474385232 ps
CPU time 4.5 seconds
Started Apr 30 02:41:58 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 203880 kb
Host smart-66a4cc99-533f-4cee-8d8b-e6a50e55cb79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=509472107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.509472107
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1395790421
Short name T1476
Test name
Test status
Simulation time 110761896 ps
CPU time 1.18 seconds
Started Apr 30 02:41:59 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 204000 kb
Host smart-fdc1a890-4e14-4340-8258-2e9155072b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1395790421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1395790421
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2144187763
Short name T209
Test name
Test status
Simulation time 269868037 ps
CPU time 3.01 seconds
Started Apr 30 02:41:59 PM PDT 24
Finished Apr 30 02:42:02 PM PDT 24
Peak memory 204048 kb
Host smart-1d2efe0f-36c0-4d00-b757-1db1fa9dd2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2144187763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2144187763
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.139692805
Short name T1454
Test name
Test status
Simulation time 626305505 ps
CPU time 4.72 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:06 PM PDT 24
Peak memory 203952 kb
Host smart-67c83803-49f1-4bac-8f31-963cd6308f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=139692805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.139692805
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3757046788
Short name T52
Test name
Test status
Simulation time 84425256 ps
CPU time 1.54 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 212284 kb
Host smart-4fadca0e-6ad3-4425-a2d4-9e4d87537077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757046788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3757046788
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.55457113
Short name T1430
Test name
Test status
Simulation time 42840781 ps
CPU time 0.83 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 203776 kb
Host smart-c31d2cca-fd6a-4865-b7ee-5edcd7fc1e3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=55457113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.55457113
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1054104891
Short name T1410
Test name
Test status
Simulation time 76646500 ps
CPU time 0.75 seconds
Started Apr 30 02:42:12 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 203228 kb
Host smart-8d430677-a028-4a15-b497-133b44b68722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1054104891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1054104891
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1920266598
Short name T1472
Test name
Test status
Simulation time 85770352 ps
CPU time 1.15 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 204000 kb
Host smart-fbc869aa-1e97-44bc-a4bb-6f4ebca71fdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1920266598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1920266598
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3829325310
Short name T210
Test name
Test status
Simulation time 86714554 ps
CPU time 2.33 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 203824 kb
Host smart-ad6d1795-3682-453e-8951-6756250e1be8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3829325310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3829325310
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1130344893
Short name T1443
Test name
Test status
Simulation time 369259285 ps
CPU time 2.82 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 203964 kb
Host smart-e3f989e5-37c0-4cd4-9937-beb54488a047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1130344893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1130344893
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.382227782
Short name T1468
Test name
Test status
Simulation time 166222443 ps
CPU time 1.96 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 220408 kb
Host smart-a87c1b21-cf00-4b16-9871-155d122ce8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382227782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.382227782
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.937894185
Short name T1441
Test name
Test status
Simulation time 87576612 ps
CPU time 1.01 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 203944 kb
Host smart-ee0d10b5-e8d4-4e14-80fd-9e7dfae1ed9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=937894185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.937894185
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4146596885
Short name T1380
Test name
Test status
Simulation time 43652084 ps
CPU time 0.69 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 203240 kb
Host smart-654d01d9-b1ca-4a6f-b869-da792f5c82a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4146596885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4146596885
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.43437809
Short name T1450
Test name
Test status
Simulation time 81075176 ps
CPU time 1.17 seconds
Started Apr 30 02:42:11 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 203996 kb
Host smart-30b7ed3d-3c1c-4ad3-9575-f0876dc37059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=43437809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.43437809
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2469684166
Short name T1469
Test name
Test status
Simulation time 68706633 ps
CPU time 1.79 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 203976 kb
Host smart-be9eaf21-66a0-4215-84fc-b2dc0145ed45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2469684166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2469684166
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1586698243
Short name T1467
Test name
Test status
Simulation time 679401837 ps
CPU time 5.41 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 204032 kb
Host smart-8db8e0f1-b6ca-4a93-a72c-f4d49556ff18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1586698243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1586698243
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.797105859
Short name T242
Test name
Test status
Simulation time 145963465 ps
CPU time 1.72 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 212276 kb
Host smart-6e0ab2ab-4833-4d61-967a-edca4d9c7fa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797105859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.797105859
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2470164292
Short name T1391
Test name
Test status
Simulation time 101946156 ps
CPU time 0.94 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 203704 kb
Host smart-5a82628c-5fbb-4541-aeeb-386b95161088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2470164292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2470164292
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2566208685
Short name T1420
Test name
Test status
Simulation time 97266261 ps
CPU time 1.07 seconds
Started Apr 30 02:42:17 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 203968 kb
Host smart-67aadfd0-df2b-4af2-80db-7cd34f947401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2566208685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2566208685
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1092551620
Short name T211
Test name
Test status
Simulation time 114921483 ps
CPU time 2.82 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 204040 kb
Host smart-78f2b3f4-28df-4607-af95-889139ae3841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1092551620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1092551620
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2613048107
Short name T264
Test name
Test status
Simulation time 555646345 ps
CPU time 4.46 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 203996 kb
Host smart-1841154a-fa61-4cbf-8332-07da35a4f0df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2613048107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2613048107
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2722842696
Short name T1478
Test name
Test status
Simulation time 149722832 ps
CPU time 1.98 seconds
Started Apr 30 02:42:19 PM PDT 24
Finished Apr 30 02:42:21 PM PDT 24
Peak memory 212168 kb
Host smart-759344ad-cfbf-4e80-a7f2-563f4d65b5cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722842696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2722842696
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3499958505
Short name T1390
Test name
Test status
Simulation time 32825461 ps
CPU time 0.93 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 203916 kb
Host smart-56396658-2bac-438c-86c6-806583524216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3499958505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3499958505
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.250945652
Short name T1459
Test name
Test status
Simulation time 234197371 ps
CPU time 1.67 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 203944 kb
Host smart-8b174dcc-a0d9-4517-a44b-f4085083f61f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=250945652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.250945652
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1379869442
Short name T1436
Test name
Test status
Simulation time 224464850 ps
CPU time 2.02 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 204016 kb
Host smart-ce1abb2b-2a78-4fc4-b719-2fb7381102d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1379869442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1379869442
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3549701876
Short name T1378
Test name
Test status
Simulation time 499192846 ps
CPU time 2.66 seconds
Started Apr 30 02:42:19 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203984 kb
Host smart-53197529-212b-421d-ade8-ae85371d7dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3549701876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3549701876
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.251047728
Short name T1429
Test name
Test status
Simulation time 124575025 ps
CPU time 1.43 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 212284 kb
Host smart-8ca9390b-a22c-4b3b-9acc-b8057a453db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251047728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.251047728
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.889655517
Short name T1464
Test name
Test status
Simulation time 87967954 ps
CPU time 0.95 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 203960 kb
Host smart-f6833cfa-02ff-4d47-80ea-89758dade724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=889655517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.889655517
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3450076654
Short name T63
Test name
Test status
Simulation time 68758603 ps
CPU time 0.73 seconds
Started Apr 30 02:42:11 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 203360 kb
Host smart-ed6efb05-18d9-4207-aa84-862f3b4bc432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3450076654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3450076654
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1381789985
Short name T1473
Test name
Test status
Simulation time 85345975 ps
CPU time 1.05 seconds
Started Apr 30 02:42:12 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 204028 kb
Host smart-b800b7c4-13bb-4bf1-9aa6-1b2ea6f74afb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1381789985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1381789985
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2638892372
Short name T1396
Test name
Test status
Simulation time 71989601 ps
CPU time 1.87 seconds
Started Apr 30 02:42:18 PM PDT 24
Finished Apr 30 02:42:21 PM PDT 24
Peak memory 204004 kb
Host smart-7c64b20d-044e-464e-a3b2-6f3ef780f833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2638892372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2638892372
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2095304334
Short name T1457
Test name
Test status
Simulation time 115702932 ps
CPU time 1.79 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 212196 kb
Host smart-c8089540-ff52-48a7-a3d6-14f09fe3afad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095304334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2095304334
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1573694462
Short name T1444
Test name
Test status
Simulation time 75972733 ps
CPU time 0.85 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 203760 kb
Host smart-990393db-0683-484a-9682-4827d7f3d263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573694462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1573694462
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3482676038
Short name T1406
Test name
Test status
Simulation time 27116164 ps
CPU time 0.66 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 203288 kb
Host smart-e8e2730c-21a4-4787-8c79-9e90b3f68a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3482676038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3482676038
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1168377676
Short name T1404
Test name
Test status
Simulation time 169440878 ps
CPU time 1.66 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 204044 kb
Host smart-a77941e9-c43b-45f4-bacc-eeabc8073293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1168377676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1168377676
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3292732079
Short name T1419
Test name
Test status
Simulation time 80991689 ps
CPU time 1.55 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 204012 kb
Host smart-4c2fdb03-66f9-4ca9-bbcd-324fb70ed006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3292732079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3292732079
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2393386669
Short name T1449
Test name
Test status
Simulation time 389590278 ps
CPU time 2.72 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 203976 kb
Host smart-45fd8c67-e7e5-4147-b0cf-e3538afef6a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2393386669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2393386669
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.187281077
Short name T1452
Test name
Test status
Simulation time 131310869 ps
CPU time 2.02 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 212204 kb
Host smart-acfa097b-0e1e-4db5-9f20-04f7a26c3cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187281077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.187281077
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1087326345
Short name T61
Test name
Test status
Simulation time 111054458 ps
CPU time 1 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 204060 kb
Host smart-f94bea58-c047-4848-a8e2-d3b6c8646989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1087326345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1087326345
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2086743949
Short name T1477
Test name
Test status
Simulation time 82670164 ps
CPU time 0.72 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 203280 kb
Host smart-bd726b0a-1cec-4230-9226-118b03ea55f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2086743949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2086743949
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3050448501
Short name T239
Test name
Test status
Simulation time 188061168 ps
CPU time 1.69 seconds
Started Apr 30 02:42:12 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 204000 kb
Host smart-50bc8da0-409a-4803-91e4-d82e4058b510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3050448501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3050448501
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1193461787
Short name T1403
Test name
Test status
Simulation time 93272196 ps
CPU time 2.47 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 204220 kb
Host smart-abd76aed-c14a-42c8-a8e6-32e7cb17b278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1193461787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1193461787
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3355003521
Short name T1460
Test name
Test status
Simulation time 716632033 ps
CPU time 4.31 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 203956 kb
Host smart-2a1978f6-d714-47e4-8911-bf2fa3f1fa89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3355003521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3355003521
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3321033297
Short name T197
Test name
Test status
Simulation time 90744977 ps
CPU time 2.32 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:19 PM PDT 24
Peak memory 212172 kb
Host smart-320357e9-dcd6-420f-882d-8b194348121e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321033297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3321033297
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2455392479
Short name T1414
Test name
Test status
Simulation time 37753735 ps
CPU time 0.94 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 203916 kb
Host smart-f19a318a-4105-4228-8646-82a1312575ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2455392479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2455392479
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1570596674
Short name T1392
Test name
Test status
Simulation time 26000502 ps
CPU time 0.71 seconds
Started Apr 30 02:42:13 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 203280 kb
Host smart-87d01e11-b5d7-4bb8-a613-327fa7fb13a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1570596674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1570596674
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4181366672
Short name T1387
Test name
Test status
Simulation time 129951003 ps
CPU time 1.61 seconds
Started Apr 30 02:42:14 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 204004 kb
Host smart-f9a8862f-aae7-4cf0-a6e9-136e16368d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4181366672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4181366672
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.360705192
Short name T51
Test name
Test status
Simulation time 205089212 ps
CPU time 1.78 seconds
Started Apr 30 02:42:12 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 204016 kb
Host smart-9e3596bb-381b-406d-bc90-689872efa962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=360705192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.360705192
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3964165563
Short name T216
Test name
Test status
Simulation time 436439518 ps
CPU time 4.04 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:21 PM PDT 24
Peak memory 203904 kb
Host smart-97330e8f-0674-46af-9f48-1fdbfe4d3ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3964165563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3964165563
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3514597100
Short name T1397
Test name
Test status
Simulation time 86503000 ps
CPU time 2.58 seconds
Started Apr 30 02:42:20 PM PDT 24
Finished Apr 30 02:42:23 PM PDT 24
Peak memory 212236 kb
Host smart-1fdc511c-0a6f-4021-9330-f538d3dda6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514597100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3514597100
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2712272610
Short name T1408
Test name
Test status
Simulation time 47803847 ps
CPU time 0.85 seconds
Started Apr 30 02:42:15 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 203704 kb
Host smart-e0a79400-19aa-4ca8-8211-bda37d947788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2712272610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2712272610
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3626779739
Short name T1393
Test name
Test status
Simulation time 35867950 ps
CPU time 0.69 seconds
Started Apr 30 02:42:18 PM PDT 24
Finished Apr 30 02:42:20 PM PDT 24
Peak memory 203292 kb
Host smart-767bf58e-9a74-43b0-8813-f21e4472ee34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3626779739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3626779739
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1225353025
Short name T244
Test name
Test status
Simulation time 121134200 ps
CPU time 1.15 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 203884 kb
Host smart-3c19f1c5-eb0c-45bf-ad8f-5d9e82cf7f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1225353025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1225353025
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3154613726
Short name T212
Test name
Test status
Simulation time 77245884 ps
CPU time 1.84 seconds
Started Apr 30 02:42:16 PM PDT 24
Finished Apr 30 02:42:18 PM PDT 24
Peak memory 204024 kb
Host smart-d1dca1d0-34c2-46b8-bd02-8f5f5d3518d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154613726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3154613726
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3647979834
Short name T1381
Test name
Test status
Simulation time 126194221 ps
CPU time 1.9 seconds
Started Apr 30 02:42:24 PM PDT 24
Finished Apr 30 02:42:27 PM PDT 24
Peak memory 215792 kb
Host smart-4132b31b-3682-405b-8112-849d184edd8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647979834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3647979834
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2096140053
Short name T1461
Test name
Test status
Simulation time 36897873 ps
CPU time 1 seconds
Started Apr 30 02:42:22 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 204004 kb
Host smart-21b6f209-cd28-4a5c-81cf-d27af9168a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2096140053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2096140053
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.375702932
Short name T1445
Test name
Test status
Simulation time 31555483 ps
CPU time 0.65 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203328 kb
Host smart-c4b5b68e-9743-45ff-bc2b-450b38282f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375702932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.375702932
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.813867774
Short name T1394
Test name
Test status
Simulation time 146260674 ps
CPU time 2.51 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:27 PM PDT 24
Peak memory 204088 kb
Host smart-80826d7b-788a-47c5-9f59-b2d917a51d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=813867774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.813867774
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2894849820
Short name T1479
Test name
Test status
Simulation time 62241110 ps
CPU time 1.9 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 203948 kb
Host smart-3f5edbfa-95ec-4b9a-8929-9a13c2a50864
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2894849820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2894849820
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1945306891
Short name T231
Test name
Test status
Simulation time 388032688 ps
CPU time 4.71 seconds
Started Apr 30 02:42:04 PM PDT 24
Finished Apr 30 02:42:09 PM PDT 24
Peak memory 203880 kb
Host smart-aaa1831f-2015-462e-a97f-70e397299a0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1945306891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1945306891
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2677653709
Short name T213
Test name
Test status
Simulation time 45847025 ps
CPU time 0.86 seconds
Started Apr 30 02:41:59 PM PDT 24
Finished Apr 30 02:42:00 PM PDT 24
Peak memory 203732 kb
Host smart-95d0cfdd-9fdf-493f-92d2-8d3c7ad52a27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2677653709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2677653709
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1001065122
Short name T243
Test name
Test status
Simulation time 90157137 ps
CPU time 1.2 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 212192 kb
Host smart-69e3d82a-f857-4ea4-8ff9-210233a518b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001065122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1001065122
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.907016950
Short name T1437
Test name
Test status
Simulation time 60482921 ps
CPU time 0.99 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 203864 kb
Host smart-2105a32a-8b8e-45ac-8f0e-c3e47d622408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=907016950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.907016950
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.548077380
Short name T62
Test name
Test status
Simulation time 39227645 ps
CPU time 0.68 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 203336 kb
Host smart-343e6511-329c-4607-8090-b04e3cf5f611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=548077380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.548077380
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1702892258
Short name T232
Test name
Test status
Simulation time 73775927 ps
CPU time 2.1 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 212224 kb
Host smart-3bbd534b-6f11-4b70-af8f-94285e7a77bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1702892258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1702892258
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1773376355
Short name T1383
Test name
Test status
Simulation time 161622307 ps
CPU time 4.09 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:05 PM PDT 24
Peak memory 203864 kb
Host smart-a2d2bdf0-fbd7-4719-9b45-fee08468f5e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1773376355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1773376355
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2917303632
Short name T245
Test name
Test status
Simulation time 87446710 ps
CPU time 1.12 seconds
Started Apr 30 02:42:04 PM PDT 24
Finished Apr 30 02:42:06 PM PDT 24
Peak memory 203980 kb
Host smart-b4dc290c-7796-4f82-abf2-4b37de7d3e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2917303632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2917303632
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3136158449
Short name T1398
Test name
Test status
Simulation time 237729117 ps
CPU time 3.06 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 203948 kb
Host smart-52e58e33-01c6-4891-b3de-40de4984cdc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136158449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3136158449
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3080666162
Short name T91
Test name
Test status
Simulation time 255244566 ps
CPU time 2.41 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 204052 kb
Host smart-b4a7ebf7-a086-4207-a16f-0c0f2d648171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3080666162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3080666162
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1077661186
Short name T1440
Test name
Test status
Simulation time 34807399 ps
CPU time 0.65 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203304 kb
Host smart-4f0ea4d0-45f4-411e-b12d-b3d5f558b980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077661186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1077661186
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3278449578
Short name T1426
Test name
Test status
Simulation time 36172725 ps
CPU time 0.71 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:25 PM PDT 24
Peak memory 203200 kb
Host smart-c8569d6b-d34a-44ad-bf46-53db17dc865d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278449578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3278449578
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2352102447
Short name T1388
Test name
Test status
Simulation time 33425627 ps
CPU time 0.68 seconds
Started Apr 30 02:42:22 PM PDT 24
Finished Apr 30 02:42:23 PM PDT 24
Peak memory 203504 kb
Host smart-ae3e6cd9-2ee1-44f9-b7d0-c8f363d56303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352102447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2352102447
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3246846797
Short name T254
Test name
Test status
Simulation time 33378905 ps
CPU time 0.61 seconds
Started Apr 30 02:42:22 PM PDT 24
Finished Apr 30 02:42:23 PM PDT 24
Peak memory 203244 kb
Host smart-37b3e313-3072-4097-8791-14d799317ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3246846797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3246846797
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3598498311
Short name T1386
Test name
Test status
Simulation time 41353799 ps
CPU time 0.73 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203236 kb
Host smart-60fb2d47-b13a-42a3-91a3-c970d37bf71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3598498311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3598498311
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1538479719
Short name T1385
Test name
Test status
Simulation time 26431243 ps
CPU time 0.67 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:25 PM PDT 24
Peak memory 203272 kb
Host smart-3e198bb9-cfc8-42d0-903a-ef80b962df28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1538479719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1538479719
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3483580015
Short name T1465
Test name
Test status
Simulation time 51114173 ps
CPU time 0.66 seconds
Started Apr 30 02:42:24 PM PDT 24
Finished Apr 30 02:42:26 PM PDT 24
Peak memory 203212 kb
Host smart-b1d3ab2f-130b-434a-8341-ff5325a29e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3483580015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3483580015
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1316311628
Short name T1409
Test name
Test status
Simulation time 34381699 ps
CPU time 0.67 seconds
Started Apr 30 02:42:22 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203228 kb
Host smart-797c63a6-60e6-4929-a0bd-c4760bd38dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1316311628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1316311628
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2240359468
Short name T1448
Test name
Test status
Simulation time 41502909 ps
CPU time 0.68 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203280 kb
Host smart-dcec1580-3e0d-4408-81ac-0fc7ff154a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2240359468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2240359468
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3852675897
Short name T1432
Test name
Test status
Simulation time 122772851 ps
CPU time 3.26 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 203896 kb
Host smart-760db1a7-4fe9-4b96-b15c-9cdaa7fe96ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3852675897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3852675897
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2651973975
Short name T233
Test name
Test status
Simulation time 751946866 ps
CPU time 8.38 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:17 PM PDT 24
Peak memory 203888 kb
Host smart-54d37ca1-a863-486f-82f4-3ef56e9cef0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2651973975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2651973975
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.38694314
Short name T1418
Test name
Test status
Simulation time 74980531 ps
CPU time 0.84 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 203720 kb
Host smart-4c0ad1b8-15c8-4ebd-8487-78b1a73d124e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=38694314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.38694314
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2567110824
Short name T1453
Test name
Test status
Simulation time 137325970 ps
CPU time 1.81 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 212244 kb
Host smart-9fba5cd1-905f-4e11-8092-d9b04b06f284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567110824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2567110824
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1024279949
Short name T93
Test name
Test status
Simulation time 67295454 ps
CPU time 0.99 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 203896 kb
Host smart-37dd90a8-3fc9-4936-ad78-91f56e7e8a90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1024279949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1024279949
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3592086066
Short name T249
Test name
Test status
Simulation time 27116833 ps
CPU time 0.68 seconds
Started Apr 30 02:42:01 PM PDT 24
Finished Apr 30 02:42:02 PM PDT 24
Peak memory 203152 kb
Host smart-dd1d73b3-7c8f-47d6-87c8-293e40244c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3592086066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3592086066
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.936988177
Short name T1458
Test name
Test status
Simulation time 47889558 ps
CPU time 1.43 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:02 PM PDT 24
Peak memory 212220 kb
Host smart-1105a9f9-f9bb-4bd5-bcaa-49efde05d3e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=936988177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.936988177
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2255829870
Short name T1377
Test name
Test status
Simulation time 95981090 ps
CPU time 2.36 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:05 PM PDT 24
Peak memory 203964 kb
Host smart-522c457b-9bc9-4bf3-b2a0-a9acdaf8c459
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2255829870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2255829870
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1284272564
Short name T1411
Test name
Test status
Simulation time 163419641 ps
CPU time 1.7 seconds
Started Apr 30 02:42:00 PM PDT 24
Finished Apr 30 02:42:02 PM PDT 24
Peak memory 203980 kb
Host smart-ecc30612-f715-498c-81e3-9a05cd32003d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1284272564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1284272564
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4050646285
Short name T1475
Test name
Test status
Simulation time 53924856 ps
CPU time 1.49 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:04 PM PDT 24
Peak memory 204092 kb
Host smart-cdea751e-0282-44b0-872a-14a415134c40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4050646285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4050646285
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.996287667
Short name T1435
Test name
Test status
Simulation time 370806069 ps
CPU time 4.07 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 204020 kb
Host smart-a1172c4f-a06a-4068-9b11-45a127352dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=996287667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.996287667
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.422836509
Short name T1384
Test name
Test status
Simulation time 31981911 ps
CPU time 0.66 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203220 kb
Host smart-61e8a3d3-e5f4-42df-bc06-db055b7ec3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=422836509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.422836509
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1822802272
Short name T255
Test name
Test status
Simulation time 28562963 ps
CPU time 0.64 seconds
Started Apr 30 02:42:24 PM PDT 24
Finished Apr 30 02:42:25 PM PDT 24
Peak memory 203284 kb
Host smart-537ce361-30bb-455b-bd76-8c3e7be984ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1822802272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1822802272
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3987079900
Short name T1416
Test name
Test status
Simulation time 30789864 ps
CPU time 0.71 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:25 PM PDT 24
Peak memory 203204 kb
Host smart-2106d2dc-2d9b-47a7-b3e1-f11765c19136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987079900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3987079900
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2506095259
Short name T258
Test name
Test status
Simulation time 33004105 ps
CPU time 0.65 seconds
Started Apr 30 02:42:19 PM PDT 24
Finished Apr 30 02:42:20 PM PDT 24
Peak memory 203256 kb
Host smart-818f79f2-079a-48de-b5a4-e98c98c3a47f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2506095259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2506095259
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2491190394
Short name T256
Test name
Test status
Simulation time 30493730 ps
CPU time 0.69 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203316 kb
Host smart-d414f650-910d-479f-b38a-b3d8592d4c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2491190394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2491190394
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1722951320
Short name T1395
Test name
Test status
Simulation time 71394625 ps
CPU time 0.64 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203216 kb
Host smart-c5468f5a-b988-431d-975d-69366f2ce695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1722951320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1722951320
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3168882436
Short name T1463
Test name
Test status
Simulation time 38592247 ps
CPU time 0.67 seconds
Started Apr 30 02:42:24 PM PDT 24
Finished Apr 30 02:42:25 PM PDT 24
Peak memory 203292 kb
Host smart-b1312026-f731-4b22-9901-edb594aa0564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3168882436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3168882436
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2321132966
Short name T1417
Test name
Test status
Simulation time 25200535 ps
CPU time 0.66 seconds
Started Apr 30 02:42:22 PM PDT 24
Finished Apr 30 02:42:23 PM PDT 24
Peak memory 203268 kb
Host smart-d3fc1a3a-34d2-476f-a58b-d24a188e9604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321132966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2321132966
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2548024287
Short name T1413
Test name
Test status
Simulation time 68640946 ps
CPU time 1.85 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 203912 kb
Host smart-f1007ce7-21c0-417e-9da2-d86c317b712a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2548024287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2548024287
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2644431706
Short name T234
Test name
Test status
Simulation time 535113231 ps
CPU time 4.33 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 203968 kb
Host smart-8f9d8130-4e5a-4d4b-b04f-24e717b2919d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2644431706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2644431706
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1920202213
Short name T57
Test name
Test status
Simulation time 74091379 ps
CPU time 0.83 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 203768 kb
Host smart-ad92b02d-05e3-467e-bdc6-e3d73415ea21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1920202213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1920202213
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.459585636
Short name T1421
Test name
Test status
Simulation time 104825610 ps
CPU time 1.47 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 212232 kb
Host smart-9493d30b-0685-437c-b0f0-d1b59e3cc810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459585636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.459585636
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.233906609
Short name T1471
Test name
Test status
Simulation time 65368580 ps
CPU time 0.84 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 203788 kb
Host smart-94160688-7fc3-4723-8d3b-8af4358ba95e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=233906609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.233906609
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1079632121
Short name T1447
Test name
Test status
Simulation time 40349091 ps
CPU time 0.66 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 203228 kb
Host smart-ca948034-66a6-4e50-a0b7-0dc25aa764e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1079632121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1079632121
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2168813432
Short name T227
Test name
Test status
Simulation time 93928642 ps
CPU time 1.41 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:09 PM PDT 24
Peak memory 203984 kb
Host smart-e86513fa-74db-485a-9e67-7b17dc39c68b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2168813432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2168813432
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2010420808
Short name T1405
Test name
Test status
Simulation time 469152312 ps
CPU time 4.32 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:14 PM PDT 24
Peak memory 203896 kb
Host smart-685f7018-27cf-4b03-b20b-c5777ab2bc9d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2010420808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2010420808
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2582029869
Short name T1427
Test name
Test status
Simulation time 96262791 ps
CPU time 1.06 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 204012 kb
Host smart-40ad1645-6693-4cb2-9659-6911db19a24a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2582029869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2582029869
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2620255127
Short name T259
Test name
Test status
Simulation time 844524655 ps
CPU time 4.83 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 204016 kb
Host smart-1ccb89c5-650a-437d-8a4f-d333fb6f7db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2620255127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2620255127
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.822375179
Short name T246
Test name
Test status
Simulation time 58460189 ps
CPU time 0.67 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203252 kb
Host smart-465e8c31-8384-4214-842f-2bbed0006c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=822375179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.822375179
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1576899199
Short name T1415
Test name
Test status
Simulation time 84971276 ps
CPU time 0.74 seconds
Started Apr 30 02:42:21 PM PDT 24
Finished Apr 30 02:42:22 PM PDT 24
Peak memory 203312 kb
Host smart-e48ceeb0-10fa-449e-a699-906ef101fd1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1576899199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1576899199
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.294096801
Short name T251
Test name
Test status
Simulation time 34032983 ps
CPU time 0.67 seconds
Started Apr 30 02:42:23 PM PDT 24
Finished Apr 30 02:42:24 PM PDT 24
Peak memory 203300 kb
Host smart-b58d96d2-cb54-4068-b049-f1ac993993c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=294096801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.294096801
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1327070897
Short name T64
Test name
Test status
Simulation time 35624497 ps
CPU time 0.66 seconds
Started Apr 30 02:42:25 PM PDT 24
Finished Apr 30 02:42:26 PM PDT 24
Peak memory 203224 kb
Host smart-01d2e473-3f1f-4129-95e5-95d7ef3bf80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327070897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1327070897
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.686696332
Short name T1382
Test name
Test status
Simulation time 30032207 ps
CPU time 0.66 seconds
Started Apr 30 02:42:29 PM PDT 24
Finished Apr 30 02:42:30 PM PDT 24
Peak memory 203268 kb
Host smart-37d953d8-9795-4605-9f22-f9c8af8921d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686696332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.686696332
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3762539609
Short name T1400
Test name
Test status
Simulation time 30152081 ps
CPU time 0.64 seconds
Started Apr 30 02:42:27 PM PDT 24
Finished Apr 30 02:42:28 PM PDT 24
Peak memory 203240 kb
Host smart-b78ba2f0-c417-4330-b068-e035d331255c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762539609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3762539609
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4072637430
Short name T67
Test name
Test status
Simulation time 30695029 ps
CPU time 0.66 seconds
Started Apr 30 02:42:26 PM PDT 24
Finished Apr 30 02:42:28 PM PDT 24
Peak memory 203220 kb
Host smart-7260ea19-8d11-4305-a2da-3f2799ebfe75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4072637430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.4072637430
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.64418862
Short name T253
Test name
Test status
Simulation time 35483997 ps
CPU time 0.67 seconds
Started Apr 30 02:42:30 PM PDT 24
Finished Apr 30 02:42:31 PM PDT 24
Peak memory 203276 kb
Host smart-4241703c-acf1-47f4-83b0-2e86342cd0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=64418862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.64418862
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3361281982
Short name T1401
Test name
Test status
Simulation time 30855658 ps
CPU time 0.66 seconds
Started Apr 30 02:42:31 PM PDT 24
Finished Apr 30 02:42:32 PM PDT 24
Peak memory 203296 kb
Host smart-99525e34-a840-4501-81d3-66eca7920455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3361281982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3361281982
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.298422747
Short name T198
Test name
Test status
Simulation time 155706543 ps
CPU time 1.74 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 212244 kb
Host smart-1e6a4222-8443-4878-bb59-75323b154c4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298422747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.298422747
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3039614115
Short name T65
Test name
Test status
Simulation time 38080552 ps
CPU time 0.67 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 203320 kb
Host smart-4bf05d85-e6d7-486b-ba64-fa4cc26e477d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3039614115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3039614115
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4102393650
Short name T1399
Test name
Test status
Simulation time 344757876 ps
CPU time 2.01 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 204000 kb
Host smart-f83e2e1d-2e98-406f-a28b-1bd76aab8444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4102393650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.4102393650
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4213262644
Short name T196
Test name
Test status
Simulation time 168502126 ps
CPU time 1.93 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 204060 kb
Host smart-07555bc0-3214-4b03-9b06-25e753bde76f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4213262644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4213262644
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1087836533
Short name T1451
Test name
Test status
Simulation time 53994385 ps
CPU time 1.31 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 212256 kb
Host smart-9fbafb47-cc2a-4d77-b40d-f759ea5cd040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087836533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1087836533
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3515238212
Short name T1422
Test name
Test status
Simulation time 70580327 ps
CPU time 0.8 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 203664 kb
Host smart-ebb74606-a1b0-449e-8b44-91796d4e925b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3515238212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3515238212
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2432059486
Short name T1438
Test name
Test status
Simulation time 33878611 ps
CPU time 0.7 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:09 PM PDT 24
Peak memory 203220 kb
Host smart-b30a9911-050e-4223-b54b-e273de658b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2432059486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2432059486
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2908172014
Short name T238
Test name
Test status
Simulation time 75175077 ps
CPU time 1.46 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 204016 kb
Host smart-98cb12e9-dafc-46de-8432-174c1a5965ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2908172014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2908172014
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3845213783
Short name T1442
Test name
Test status
Simulation time 216399707 ps
CPU time 1.97 seconds
Started Apr 30 02:42:11 PM PDT 24
Finished Apr 30 02:42:13 PM PDT 24
Peak memory 204036 kb
Host smart-a6be8c3e-f9f3-4a1a-ba45-d651d898cd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845213783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3845213783
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3981813591
Short name T218
Test name
Test status
Simulation time 626369308 ps
CPU time 4.87 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:16 PM PDT 24
Peak memory 203940 kb
Host smart-2da2b12b-61b0-41ef-9a54-1e2cb4ae9b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3981813591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3981813591
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.273846732
Short name T1431
Test name
Test status
Simulation time 84300359 ps
CPU time 1.25 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 212148 kb
Host smart-e0459125-437e-4742-bafb-00aac69d9b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273846732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.273846732
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2942224635
Short name T1466
Test name
Test status
Simulation time 33806910 ps
CPU time 0.95 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 203668 kb
Host smart-57a58b10-7432-4846-9421-24c26ec53bf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2942224635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2942224635
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1895013591
Short name T1412
Test name
Test status
Simulation time 29080212 ps
CPU time 0.63 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 203188 kb
Host smart-a4b9947d-e06b-4eeb-abed-0e494cdc8a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1895013591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1895013591
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2855196353
Short name T1439
Test name
Test status
Simulation time 106880359 ps
CPU time 1.23 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 203948 kb
Host smart-60caf6ea-cfe1-4726-a502-4495ccc2f76d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2855196353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2855196353
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1686035774
Short name T199
Test name
Test status
Simulation time 97355734 ps
CPU time 3.01 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 203956 kb
Host smart-8f449a35-e928-458c-a97f-e98b2f3ad93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1686035774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1686035774
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2467798350
Short name T1455
Test name
Test status
Simulation time 171042391 ps
CPU time 1.86 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 212204 kb
Host smart-a30ee18d-95be-403e-b9c4-24dc88a8b6b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467798350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2467798350
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3626044790
Short name T90
Test name
Test status
Simulation time 31135379 ps
CPU time 0.81 seconds
Started Apr 30 02:42:05 PM PDT 24
Finished Apr 30 02:42:06 PM PDT 24
Peak memory 203716 kb
Host smart-3399607b-816e-41ec-9de1-8019c071ad51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3626044790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3626044790
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1696709224
Short name T1446
Test name
Test status
Simulation time 54198925 ps
CPU time 0.72 seconds
Started Apr 30 02:42:10 PM PDT 24
Finished Apr 30 02:42:11 PM PDT 24
Peak memory 203300 kb
Host smart-c37b63f4-f811-4a2b-9e9d-f91cf70b8d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1696709224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1696709224
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1732653298
Short name T1376
Test name
Test status
Simulation time 153468384 ps
CPU time 1.52 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 203980 kb
Host smart-870c7172-4d91-463d-bf17-4d40084eafcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1732653298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1732653298
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1734136146
Short name T1474
Test name
Test status
Simulation time 229021086 ps
CPU time 3.03 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:12 PM PDT 24
Peak memory 204044 kb
Host smart-6fef661c-28c9-45b2-9b03-ce49ca09792a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1734136146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1734136146
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.437209188
Short name T262
Test name
Test status
Simulation time 1271408523 ps
CPU time 5.42 seconds
Started Apr 30 02:42:09 PM PDT 24
Finished Apr 30 02:42:15 PM PDT 24
Peak memory 204076 kb
Host smart-831f1755-d921-4133-a4d5-9bcae035dbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=437209188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.437209188
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2102272821
Short name T217
Test name
Test status
Simulation time 74990774 ps
CPU time 1.39 seconds
Started Apr 30 02:42:07 PM PDT 24
Finished Apr 30 02:42:09 PM PDT 24
Peak memory 212188 kb
Host smart-1e724a24-7e57-4912-a976-a59eab35c2c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102272821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2102272821
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3062060862
Short name T236
Test name
Test status
Simulation time 71184948 ps
CPU time 0.98 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 204128 kb
Host smart-6c5d0cf2-7972-4b78-8ea6-e058d7703ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3062060862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3062060862
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3560735264
Short name T1423
Test name
Test status
Simulation time 49029433 ps
CPU time 0.66 seconds
Started Apr 30 02:42:08 PM PDT 24
Finished Apr 30 02:42:10 PM PDT 24
Peak memory 203196 kb
Host smart-f42a9779-e6ff-4fc8-b828-be3f333fc9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3560735264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3560735264
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1526883038
Short name T58
Test name
Test status
Simulation time 85009694 ps
CPU time 1.08 seconds
Started Apr 30 02:42:06 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 204020 kb
Host smart-d2739fdc-e463-47ef-a407-34eed0de5402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526883038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1526883038
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1852079964
Short name T59
Test name
Test status
Simulation time 478816339 ps
CPU time 2.8 seconds
Started Apr 30 02:42:05 PM PDT 24
Finished Apr 30 02:42:08 PM PDT 24
Peak memory 204024 kb
Host smart-5bc46134-3e69-469d-828b-493edbe1230a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1852079964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1852079964
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.2501830515
Short name T917
Test name
Test status
Simulation time 8467940318 ps
CPU time 9.88 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:49 PM PDT 24
Peak memory 204064 kb
Host smart-29de6325-5bd9-447a-a966-f5b165d19ca8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2501830515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.2501830515
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.918861373
Short name T346
Test name
Test status
Simulation time 8449773589 ps
CPU time 7.83 seconds
Started Apr 30 02:46:30 PM PDT 24
Finished Apr 30 02:46:39 PM PDT 24
Peak memory 204060 kb
Host smart-b38f78eb-96b5-4cbc-9a59-05e23dfb3ec4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=918861373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.918861373
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.1071939273
Short name T1119
Test name
Test status
Simulation time 8420960254 ps
CPU time 8.48 seconds
Started Apr 30 02:46:28 PM PDT 24
Finished Apr 30 02:46:36 PM PDT 24
Peak memory 204048 kb
Host smart-149811cb-6327-4121-a406-bc7123673f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
39273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.1071939273
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.687796059
Short name T987
Test name
Test status
Simulation time 8378337151 ps
CPU time 8.69 seconds
Started Apr 30 02:46:40 PM PDT 24
Finished Apr 30 02:46:49 PM PDT 24
Peak memory 204004 kb
Host smart-ba4fb9f3-6f2a-4cc8-acc1-10c4fe31905d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68779
6059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.687796059
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.2381016392
Short name T1298
Test name
Test status
Simulation time 8387763735 ps
CPU time 8.09 seconds
Started Apr 30 02:46:35 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204128 kb
Host smart-c7dbf9a8-502e-46fd-9b5d-429f15204e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23810
16392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2381016392
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3763103653
Short name T368
Test name
Test status
Simulation time 8435232080 ps
CPU time 8.57 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204124 kb
Host smart-63d5b5f4-cd72-4434-a8a9-2128eaac5c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37631
03653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3763103653
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.4041608723
Short name T747
Test name
Test status
Simulation time 8366210937 ps
CPU time 8.15 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:42 PM PDT 24
Peak memory 204132 kb
Host smart-b6a27c2c-835f-481f-9547-cff8707e2ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40416
08723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.4041608723
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3199326146
Short name T1158
Test name
Test status
Simulation time 8403204037 ps
CPU time 7.86 seconds
Started Apr 30 02:46:36 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204008 kb
Host smart-fb69ca4f-705a-412c-b5fc-6eb022ba42d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
26146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3199326146
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1385194066
Short name T1086
Test name
Test status
Simulation time 8372352870 ps
CPU time 7.41 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:42 PM PDT 24
Peak memory 204104 kb
Host smart-cbf2ec53-cde6-4781-9dce-7d453f1868c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13851
94066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1385194066
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2856945215
Short name T592
Test name
Test status
Simulation time 8371819464 ps
CPU time 7.62 seconds
Started Apr 30 02:46:36 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204124 kb
Host smart-8c411b09-800f-43e9-9fd2-2896f4e18320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
45215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2856945215
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3527611055
Short name T35
Test name
Test status
Simulation time 60144279 ps
CPU time 0.69 seconds
Started Apr 30 02:46:28 PM PDT 24
Finished Apr 30 02:46:29 PM PDT 24
Peak memory 203960 kb
Host smart-199f3633-2adf-4702-8a54-8b8962f02bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
11055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3527611055
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3176652231
Short name T529
Test name
Test status
Simulation time 16473748046 ps
CPU time 28.86 seconds
Started Apr 30 02:46:29 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204416 kb
Host smart-d29fb81c-7fac-4815-b5a6-d7a3c11b93bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31766
52231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3176652231
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.43379279
Short name T1285
Test name
Test status
Simulation time 8379386202 ps
CPU time 7.58 seconds
Started Apr 30 02:46:32 PM PDT 24
Finished Apr 30 02:46:40 PM PDT 24
Peak memory 204140 kb
Host smart-1c07d718-fb62-42a1-92ce-c382c3e49af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43379
279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.43379279
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3978565554
Short name T347
Test name
Test status
Simulation time 8394159593 ps
CPU time 7.86 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:45 PM PDT 24
Peak memory 204104 kb
Host smart-35a372ae-1ff1-4c52-b068-c628a52c5a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
65554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3978565554
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2520725873
Short name T716
Test name
Test status
Simulation time 8375695741 ps
CPU time 7.85 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:42 PM PDT 24
Peak memory 204116 kb
Host smart-479b30ab-655b-4fa2-833c-c06d7384d8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
25873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2520725873
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.240227732
Short name T541
Test name
Test status
Simulation time 8368290598 ps
CPU time 7.55 seconds
Started Apr 30 02:46:35 PM PDT 24
Finished Apr 30 02:46:43 PM PDT 24
Peak memory 204008 kb
Host smart-2719c925-2ff4-4e54-851a-28511d61e021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24022
7732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.240227732
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.758479156
Short name T391
Test name
Test status
Simulation time 8415822530 ps
CPU time 9.11 seconds
Started Apr 30 02:46:30 PM PDT 24
Finished Apr 30 02:46:40 PM PDT 24
Peak memory 204128 kb
Host smart-f5655bff-2238-4898-a5d4-5fb72c909779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75847
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.758479156
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2322069563
Short name T755
Test name
Test status
Simulation time 8395003085 ps
CPU time 8.85 seconds
Started Apr 30 02:46:28 PM PDT 24
Finished Apr 30 02:46:37 PM PDT 24
Peak memory 204120 kb
Host smart-d17e2161-2c87-441c-9701-6d4a8061af0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23220
69563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2322069563
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1163124232
Short name T440
Test name
Test status
Simulation time 8469357205 ps
CPU time 7.87 seconds
Started Apr 30 02:46:35 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204080 kb
Host smart-6091ec96-2aac-42bc-a738-464d21b61e05
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1163124232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1163124232
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.4134864078
Short name T1276
Test name
Test status
Simulation time 8381977678 ps
CPU time 8.76 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204016 kb
Host smart-ee732ed4-2627-42ca-b19a-b721e12599d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4134864078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.4134864078
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.3244540887
Short name T410
Test name
Test status
Simulation time 8404521379 ps
CPU time 8.16 seconds
Started Apr 30 02:46:35 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204104 kb
Host smart-49d95315-c31b-482a-bb61-25b0190db4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32445
40887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.3244540887
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1128927125
Short name T525
Test name
Test status
Simulation time 8374629052 ps
CPU time 7.87 seconds
Started Apr 30 02:46:29 PM PDT 24
Finished Apr 30 02:46:38 PM PDT 24
Peak memory 204064 kb
Host smart-15f5c0af-7037-4e8a-9f76-fe211d486060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
27125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1128927125
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.1670107518
Short name T1083
Test name
Test status
Simulation time 8389512886 ps
CPU time 9.84 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204112 kb
Host smart-6a2728e3-f37a-49c2-910e-6da93a20dfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16701
07518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1670107518
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.964054809
Short name T839
Test name
Test status
Simulation time 79058659 ps
CPU time 1.8 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:36 PM PDT 24
Peak memory 204184 kb
Host smart-26240328-39b4-4f0c-8869-80a23c3452b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96405
4809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.964054809
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.4187032515
Short name T664
Test name
Test status
Simulation time 8388466913 ps
CPU time 8.27 seconds
Started Apr 30 02:46:35 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204104 kb
Host smart-38c837a0-c3ae-403e-868d-98e59f7d59a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41870
32515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.4187032515
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2242561624
Short name T432
Test name
Test status
Simulation time 8371189113 ps
CPU time 8.31 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:42 PM PDT 24
Peak memory 204136 kb
Host smart-519f997f-cfcc-408c-9180-2c80a8976267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22425
61624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2242561624
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.683070849
Short name T360
Test name
Test status
Simulation time 8477303431 ps
CPU time 7.62 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:41 PM PDT 24
Peak memory 204080 kb
Host smart-796be472-6b88-4d62-b4ae-454307faf43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68307
0849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.683070849
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3355163743
Short name T579
Test name
Test status
Simulation time 8440145023 ps
CPU time 8.7 seconds
Started Apr 30 02:46:43 PM PDT 24
Finished Apr 30 02:46:52 PM PDT 24
Peak memory 204144 kb
Host smart-9a8eff88-67aa-4e62-bc47-966ccfd6e651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33551
63743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3355163743
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2851853265
Short name T1181
Test name
Test status
Simulation time 8372088637 ps
CPU time 9.48 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:49 PM PDT 24
Peak memory 204136 kb
Host smart-8d5550f6-e986-46fa-92d1-d87696602144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
53265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2851853265
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.141974662
Short name T106
Test name
Test status
Simulation time 8454457781 ps
CPU time 9.06 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:43 PM PDT 24
Peak memory 204048 kb
Host smart-47a8871a-b7cb-43ff-aa91-6a00037976e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14197
4662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.141974662
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2042169100
Short name T831
Test name
Test status
Simulation time 8445397765 ps
CPU time 7.41 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:45 PM PDT 24
Peak memory 204076 kb
Host smart-9212fa67-1456-4b51-9541-ce0fdfa40406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
69100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2042169100
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2928105471
Short name T1352
Test name
Test status
Simulation time 8367222954 ps
CPU time 8.78 seconds
Started Apr 30 02:46:32 PM PDT 24
Finished Apr 30 02:46:41 PM PDT 24
Peak memory 204136 kb
Host smart-84b8d454-2941-4470-8e56-8503d940c14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29281
05471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2928105471
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2225661327
Short name T759
Test name
Test status
Simulation time 19723256295 ps
CPU time 37.11 seconds
Started Apr 30 02:46:40 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204584 kb
Host smart-30d1ea99-ac00-49a2-a174-b52881b863c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22256
61327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2225661327
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1859310671
Short name T638
Test name
Test status
Simulation time 8389131820 ps
CPU time 7.81 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:45 PM PDT 24
Peak memory 204024 kb
Host smart-4e8f9cbd-2213-43ed-828b-2f4187604600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
10671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1859310671
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1777692904
Short name T855
Test name
Test status
Simulation time 8410271255 ps
CPU time 10.13 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204076 kb
Host smart-811226bd-2ece-45a4-8a6a-7876fbfc60d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
92904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1777692904
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.70284967
Short name T962
Test name
Test status
Simulation time 8375816638 ps
CPU time 9.16 seconds
Started Apr 30 02:46:31 PM PDT 24
Finished Apr 30 02:46:41 PM PDT 24
Peak memory 204048 kb
Host smart-942729dd-7320-4925-bfa0-5c1f89b6ebb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70284
967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.70284967
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1166776999
Short name T68
Test name
Test status
Simulation time 426319917 ps
CPU time 1.33 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:35 PM PDT 24
Peak memory 220200 kb
Host smart-71e0f0a2-d6ae-4cc5-8c3f-880ac9803eef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1166776999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1166776999
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.133378819
Short name T984
Test name
Test status
Simulation time 8378076822 ps
CPU time 9.62 seconds
Started Apr 30 02:46:33 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204168 kb
Host smart-002b89ab-71b0-448e-970d-df963b076b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13337
8819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.133378819
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2837790994
Short name T364
Test name
Test status
Simulation time 8369560278 ps
CPU time 7.99 seconds
Started Apr 30 02:46:41 PM PDT 24
Finished Apr 30 02:46:50 PM PDT 24
Peak memory 204096 kb
Host smart-e22fd65f-e0e9-4756-9a4f-48df5c13dbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28377
90994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2837790994
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.559554312
Short name T1011
Test name
Test status
Simulation time 8448987173 ps
CPU time 9.03 seconds
Started Apr 30 02:46:29 PM PDT 24
Finished Apr 30 02:46:39 PM PDT 24
Peak memory 204072 kb
Host smart-2275cdbc-cf90-482c-967a-0d827bf21cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55955
4312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.559554312
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4039428265
Short name T805
Test name
Test status
Simulation time 8412042640 ps
CPU time 8.02 seconds
Started Apr 30 02:46:43 PM PDT 24
Finished Apr 30 02:46:52 PM PDT 24
Peak memory 204092 kb
Host smart-9891b6e5-f929-4cad-9355-6885da3eb06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40394
28265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4039428265
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.742473262
Short name T769
Test name
Test status
Simulation time 8426227733 ps
CPU time 7.56 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:42 PM PDT 24
Peak memory 204116 kb
Host smart-a53b7cf8-f773-4195-9c14-561f32c20ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74247
3262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.742473262
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.2936258099
Short name T456
Test name
Test status
Simulation time 8486463185 ps
CPU time 7.86 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204056 kb
Host smart-15fd2d74-86d9-4398-b4a4-26616f80f3a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2936258099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.2936258099
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.134709470
Short name T627
Test name
Test status
Simulation time 8379884843 ps
CPU time 7.78 seconds
Started Apr 30 02:47:32 PM PDT 24
Finished Apr 30 02:47:41 PM PDT 24
Peak memory 204116 kb
Host smart-ae790674-60a1-4422-9a8f-7a8b63a8bd58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=134709470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.134709470
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.829440067
Short name T598
Test name
Test status
Simulation time 8379132018 ps
CPU time 7.66 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204104 kb
Host smart-9709efb7-21e4-4dc5-aa5b-a19da026775c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82944
0067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.829440067
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2735423424
Short name T1273
Test name
Test status
Simulation time 8378917721 ps
CPU time 7.51 seconds
Started Apr 30 02:47:31 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204084 kb
Host smart-18113200-bbcd-4740-bf1d-58997a22c7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27354
23424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2735423424
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.2682096064
Short name T1251
Test name
Test status
Simulation time 8390381017 ps
CPU time 8.02 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204124 kb
Host smart-7ba6c8ff-f1c8-4122-9f9e-2385a0e80789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26820
96064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2682096064
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.26801947
Short name T906
Test name
Test status
Simulation time 129925970 ps
CPU time 2.15 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:26 PM PDT 24
Peak memory 204296 kb
Host smart-b7a73fe7-b7c5-4d82-90b2-5ed08ed95f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26801
947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.26801947
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3939129631
Short name T175
Test name
Test status
Simulation time 8424291232 ps
CPU time 7.96 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 204000 kb
Host smart-2efafeac-54ce-409e-82af-d7ffdb960de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39391
29631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3939129631
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1940997037
Short name T681
Test name
Test status
Simulation time 8467350494 ps
CPU time 7.85 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204048 kb
Host smart-5b2aa6c5-cc3a-4418-a96e-8a421ee9f237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
97037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1940997037
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1713189140
Short name T305
Test name
Test status
Simulation time 8427541920 ps
CPU time 8.84 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:37 PM PDT 24
Peak memory 204096 kb
Host smart-11c30694-5830-404a-a5d4-8c28b89ccf0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
89140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1713189140
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.514143874
Short name T1248
Test name
Test status
Simulation time 8402183663 ps
CPU time 8.76 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204100 kb
Host smart-9f1ee041-0e0b-4588-a735-7a3188019da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51414
3874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.514143874
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1402114495
Short name T950
Test name
Test status
Simulation time 8434906586 ps
CPU time 8.38 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204136 kb
Host smart-7d22aef5-117e-4bec-a314-5e45e1e97f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14021
14495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1402114495
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1333228694
Short name T1109
Test name
Test status
Simulation time 8389686928 ps
CPU time 7.53 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 204040 kb
Host smart-7e709fff-805d-44bf-a309-48b1f55eba9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13332
28694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1333228694
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2012603679
Short name T507
Test name
Test status
Simulation time 8400518116 ps
CPU time 7.91 seconds
Started Apr 30 02:47:23 PM PDT 24
Finished Apr 30 02:47:31 PM PDT 24
Peak memory 204060 kb
Host smart-82bb1424-32e2-4649-860d-2f3ce46a3858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20126
03679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2012603679
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1881309102
Short name T1288
Test name
Test status
Simulation time 37767633 ps
CPU time 0.71 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:28 PM PDT 24
Peak memory 204008 kb
Host smart-bf4873b0-fec1-4860-9bfd-0f5032963579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18813
09102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1881309102
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2089969611
Short name T780
Test name
Test status
Simulation time 27139065399 ps
CPU time 53.21 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204336 kb
Host smart-6d2d6d8f-5321-4ca1-8db2-040e250c6a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20899
69611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2089969611
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1581250125
Short name T797
Test name
Test status
Simulation time 8431251988 ps
CPU time 7.98 seconds
Started Apr 30 02:47:23 PM PDT 24
Finished Apr 30 02:47:32 PM PDT 24
Peak memory 204048 kb
Host smart-a45cfa8d-d62b-4e05-b2c1-09abf34db237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15812
50125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1581250125
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2069812161
Short name T715
Test name
Test status
Simulation time 8409081771 ps
CPU time 7.78 seconds
Started Apr 30 02:47:22 PM PDT 24
Finished Apr 30 02:47:30 PM PDT 24
Peak memory 204064 kb
Host smart-66b3f114-4f9c-4324-8511-5f218c5dc516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
12161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2069812161
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.758292132
Short name T1037
Test name
Test status
Simulation time 8385293754 ps
CPU time 8.48 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204136 kb
Host smart-93aba78f-1f4f-40d3-a516-2ede23b33f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75829
2132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.758292132
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3674014156
Short name T1207
Test name
Test status
Simulation time 8377904319 ps
CPU time 9.61 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:37 PM PDT 24
Peak memory 204096 kb
Host smart-e9ec783e-f20e-4cb2-9f03-daab804684ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
14156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3674014156
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.146144985
Short name T559
Test name
Test status
Simulation time 8373933332 ps
CPU time 7.83 seconds
Started Apr 30 02:47:31 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204076 kb
Host smart-e502a56c-db5a-4bd2-8d49-1a1b98acc4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14614
4985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.146144985
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2850915242
Short name T327
Test name
Test status
Simulation time 8397440406 ps
CPU time 8.28 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204080 kb
Host smart-240b535f-4f07-494f-ab9b-1ae7aff96128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28509
15242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2850915242
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2555370656
Short name T812
Test name
Test status
Simulation time 8413138680 ps
CPU time 7.67 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204088 kb
Host smart-11267ea7-414a-4b9a-9db0-180c501b1e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25553
70656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2555370656
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.902607300
Short name T705
Test name
Test status
Simulation time 8500054399 ps
CPU time 8 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204116 kb
Host smart-f5498c36-00cf-4dae-98d3-68375adea48c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=902607300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.902607300
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1174164813
Short name T1289
Test name
Test status
Simulation time 8385694226 ps
CPU time 8.11 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204128 kb
Host smart-08494ae5-4237-496d-a269-368cb7135fb6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1174164813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1174164813
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.888889992
Short name T568
Test name
Test status
Simulation time 8424242495 ps
CPU time 7.89 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204040 kb
Host smart-f0fe41c3-f3a2-44e3-bf55-6a00a67d34de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88888
9992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.888889992
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2847869655
Short name T428
Test name
Test status
Simulation time 8374655537 ps
CPU time 7.63 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204056 kb
Host smart-6ddb06e2-e17b-4889-8301-cddc88f5486c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28478
69655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2847869655
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3500911678
Short name T1151
Test name
Test status
Simulation time 8386719547 ps
CPU time 8.73 seconds
Started Apr 30 02:47:32 PM PDT 24
Finished Apr 30 02:47:41 PM PDT 24
Peak memory 204132 kb
Host smart-761d380a-4cf3-4088-a225-403c5b50a427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35009
11678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3500911678
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1990055901
Short name T48
Test name
Test status
Simulation time 110838022 ps
CPU time 1.17 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:29 PM PDT 24
Peak memory 204152 kb
Host smart-fc159c16-ded0-4b2b-84c2-fd8b45600276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19900
55901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1990055901
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.4109992288
Short name T909
Test name
Test status
Simulation time 8371455696 ps
CPU time 8.49 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:37 PM PDT 24
Peak memory 204124 kb
Host smart-4f760ad2-4ec2-4b29-b4ca-1953f9216552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41099
92288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.4109992288
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1989295473
Short name T852
Test name
Test status
Simulation time 8480251113 ps
CPU time 8.49 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:37 PM PDT 24
Peak memory 204104 kb
Host smart-483ad1cd-0d32-4fe0-b7ec-d5099344b59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
95473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1989295473
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4237152068
Short name T738
Test name
Test status
Simulation time 8411498159 ps
CPU time 7.78 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204044 kb
Host smart-67ffb532-c383-4d0a-b35c-b01561c5dce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42371
52068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4237152068
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.246255460
Short name T1295
Test name
Test status
Simulation time 8399154338 ps
CPU time 8.05 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204140 kb
Host smart-a8dccc65-e88d-4f28-9aa5-edaf6d57eb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24625
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.246255460
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2833435410
Short name T1281
Test name
Test status
Simulation time 8405798101 ps
CPU time 8.08 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:37 PM PDT 24
Peak memory 204084 kb
Host smart-4b7b96ea-e8a0-42a5-9c98-42653104cb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28334
35410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2833435410
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.418540568
Short name T602
Test name
Test status
Simulation time 8410217851 ps
CPU time 7.6 seconds
Started Apr 30 02:47:32 PM PDT 24
Finished Apr 30 02:47:40 PM PDT 24
Peak memory 204084 kb
Host smart-c0b3df44-93d0-48a3-9c01-aa6771232c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41854
0568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.418540568
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1272884317
Short name T188
Test name
Test status
Simulation time 8403989810 ps
CPU time 8.3 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204120 kb
Host smart-99716c5b-1ce3-4cb2-85c6-5ba213637be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
84317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1272884317
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2339556286
Short name T521
Test name
Test status
Simulation time 8363745179 ps
CPU time 9.11 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204068 kb
Host smart-b9c94fe1-0139-42e5-8a4c-58f55d18c2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23395
56286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2339556286
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.4122541030
Short name T1258
Test name
Test status
Simulation time 57557458 ps
CPU time 0.66 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:31 PM PDT 24
Peak memory 203972 kb
Host smart-1adffc53-57fd-4762-9fac-e2b7ab7ba9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41225
41030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.4122541030
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3519867904
Short name T72
Test name
Test status
Simulation time 15716593724 ps
CPU time 27.36 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:58 PM PDT 24
Peak memory 204304 kb
Host smart-93af9b5f-0c89-483f-b517-22fabad68069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35198
67904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3519867904
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.316620330
Short name T1084
Test name
Test status
Simulation time 8400118483 ps
CPU time 8.24 seconds
Started Apr 30 02:47:32 PM PDT 24
Finished Apr 30 02:47:40 PM PDT 24
Peak memory 204080 kb
Host smart-b37c74b7-bc46-49fc-9b57-fab629d41449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
0330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.316620330
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3431861387
Short name T494
Test name
Test status
Simulation time 8408173579 ps
CPU time 8.88 seconds
Started Apr 30 02:47:34 PM PDT 24
Finished Apr 30 02:47:44 PM PDT 24
Peak memory 204116 kb
Host smart-9599e1d3-5d60-4975-bfa9-0c089e06d22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318
61387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3431861387
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.270170412
Short name T422
Test name
Test status
Simulation time 8392023673 ps
CPU time 8.02 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204092 kb
Host smart-b618acf6-39e0-4d95-929b-c384f5124658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27017
0412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.270170412
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2662266174
Short name T171
Test name
Test status
Simulation time 8375426917 ps
CPU time 7.66 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204092 kb
Host smart-01e7746b-b465-4b92-8002-f38fb0b4a0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
66174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2662266174
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3480221787
Short name T1130
Test name
Test status
Simulation time 8421911262 ps
CPU time 9.49 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:40 PM PDT 24
Peak memory 204064 kb
Host smart-b964d632-b971-4987-aecd-f3502bfc6876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
21787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3480221787
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.864066048
Short name T853
Test name
Test status
Simulation time 8408934524 ps
CPU time 7.78 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204080 kb
Host smart-5abdba53-331f-4107-adfa-fd5fb57d9601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86406
6048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.864066048
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1469133556
Short name T993
Test name
Test status
Simulation time 8407944146 ps
CPU time 8.07 seconds
Started Apr 30 02:47:32 PM PDT 24
Finished Apr 30 02:47:41 PM PDT 24
Peak memory 204108 kb
Host smart-6b4bd37d-82a0-4784-9fb1-410167e21b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14691
33556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1469133556
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.4126242120
Short name T660
Test name
Test status
Simulation time 8509652710 ps
CPU time 7.93 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204112 kb
Host smart-3e4ab42f-0789-4886-9b6c-d9026065ad2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4126242120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.4126242120
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.3523522417
Short name T1270
Test name
Test status
Simulation time 8376823651 ps
CPU time 10.57 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204020 kb
Host smart-3698f0f6-d180-4107-b30a-340497015b95
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3523522417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.3523522417
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.1697556821
Short name T669
Test name
Test status
Simulation time 8383130236 ps
CPU time 7.49 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:49 PM PDT 24
Peak memory 204076 kb
Host smart-48645c08-2041-47ec-97aa-526c7a0cff9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
56821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.1697556821
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3258363916
Short name T375
Test name
Test status
Simulation time 8381274059 ps
CPU time 10.52 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:52 PM PDT 24
Peak memory 204140 kb
Host smart-db534dcf-07e1-4095-a296-4ab675064e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32583
63916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3258363916
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.187985450
Short name T1301
Test name
Test status
Simulation time 8432552767 ps
CPU time 8.12 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204144 kb
Host smart-a64dc736-6c77-4bed-a17a-61f7bccaa9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
5450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.187985450
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3943156311
Short name T897
Test name
Test status
Simulation time 64082972 ps
CPU time 1.29 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:41 PM PDT 24
Peak memory 204180 kb
Host smart-aa8fe354-7be7-48a5-ab84-82ee7f8dad8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
56311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3943156311
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3214773693
Short name T854
Test name
Test status
Simulation time 8378262532 ps
CPU time 9.88 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:53 PM PDT 24
Peak memory 204152 kb
Host smart-818a73bd-b861-4322-942f-e8105b42fa11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
73693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3214773693
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1766192927
Short name T370
Test name
Test status
Simulation time 8427011151 ps
CPU time 7.85 seconds
Started Apr 30 02:47:41 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204080 kb
Host smart-b8079c4a-ea7f-46b9-a4fd-bb554b38a437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661
92927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1766192927
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2811486506
Short name T613
Test name
Test status
Simulation time 8466714002 ps
CPU time 7.92 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204116 kb
Host smart-0c0a08e6-595e-4145-a382-a3b5620c472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
86506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2811486506
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.496252665
Short name T30
Test name
Test status
Simulation time 8379383096 ps
CPU time 8 seconds
Started Apr 30 02:47:44 PM PDT 24
Finished Apr 30 02:47:52 PM PDT 24
Peak memory 204132 kb
Host smart-3170ee0d-df6c-476d-b3f7-bce78d886c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49625
2665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.496252665
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1518476993
Short name T595
Test name
Test status
Simulation time 8377169061 ps
CPU time 7.56 seconds
Started Apr 30 02:47:38 PM PDT 24
Finished Apr 30 02:47:47 PM PDT 24
Peak memory 204100 kb
Host smart-6805ff05-c2b4-4fc9-adc1-ce822d028ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15184
76993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1518476993
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1481994755
Short name T872
Test name
Test status
Simulation time 8409989706 ps
CPU time 8.13 seconds
Started Apr 30 02:47:42 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204120 kb
Host smart-9bc2bf62-2a5e-45ef-982a-a3676b8895cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
94755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1481994755
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3899034089
Short name T513
Test name
Test status
Simulation time 8412300928 ps
CPU time 7.67 seconds
Started Apr 30 02:47:37 PM PDT 24
Finished Apr 30 02:47:45 PM PDT 24
Peak memory 204044 kb
Host smart-8508e847-bd49-4a31-b681-7bc2652537bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38990
34089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3899034089
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3370160279
Short name T995
Test name
Test status
Simulation time 8379390911 ps
CPU time 10.09 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204128 kb
Host smart-69596bf7-0a35-4bbf-b428-1ba5c48d45f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33701
60279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3370160279
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.126640960
Short name T1102
Test name
Test status
Simulation time 78212269 ps
CPU time 0.77 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:40 PM PDT 24
Peak memory 203980 kb
Host smart-5444b728-7bef-4dff-9b72-46a50ebaf16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12664
0960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.126640960
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.189243972
Short name T1220
Test name
Test status
Simulation time 19003360008 ps
CPU time 37.52 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:48:18 PM PDT 24
Peak memory 204340 kb
Host smart-984849dc-bd6e-4c11-bfc7-6c8aca4eacbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18924
3972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.189243972
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3835324264
Short name T659
Test name
Test status
Simulation time 8396994716 ps
CPU time 7.48 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204088 kb
Host smart-c8349710-a399-40b2-9cbe-11f2485cff09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38353
24264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3835324264
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1692197793
Short name T654
Test name
Test status
Simulation time 8460047008 ps
CPU time 8.32 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:49 PM PDT 24
Peak memory 204112 kb
Host smart-4910c973-dba3-4038-a0bf-6ecbc68e8161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16921
97793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1692197793
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.4176851148
Short name T382
Test name
Test status
Simulation time 8377313639 ps
CPU time 7.82 seconds
Started Apr 30 02:47:38 PM PDT 24
Finished Apr 30 02:47:47 PM PDT 24
Peak memory 204056 kb
Host smart-55b7d798-0cf9-450a-b18d-4aef85660d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41768
51148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.4176851148
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.4234231382
Short name T40
Test name
Test status
Simulation time 8398337123 ps
CPU time 8.73 seconds
Started Apr 30 02:47:38 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 203988 kb
Host smart-d9b1c501-9c3f-47f2-940a-1e20208135a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42342
31382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.4234231382
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.4241778839
Short name T1124
Test name
Test status
Simulation time 8367581045 ps
CPU time 10.49 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204112 kb
Host smart-e7671d3d-43d5-45e5-ad64-c49cb782f22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42417
78839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.4241778839
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4125847015
Short name T557
Test name
Test status
Simulation time 8462454111 ps
CPU time 8.33 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204076 kb
Host smart-dfb50079-4ddf-4297-a28e-b9e7900420e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41258
47015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4125847015
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1705345442
Short name T355
Test name
Test status
Simulation time 8380705247 ps
CPU time 9.59 seconds
Started Apr 30 02:47:41 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204136 kb
Host smart-b3493713-cb76-4927-b9f0-54f448e2d5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17053
45442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1705345442
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1091418413
Short name T295
Test name
Test status
Simulation time 8374406248 ps
CPU time 8.84 seconds
Started Apr 30 02:47:41 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204144 kb
Host smart-6b533941-5e5e-4b62-af03-2c87f7f1cdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
18413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1091418413
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.324049843
Short name T1145
Test name
Test status
Simulation time 8482175584 ps
CPU time 8.1 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:00 PM PDT 24
Peak memory 204060 kb
Host smart-044e5236-a23b-472e-b8ef-fe455b14f71c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=324049843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.324049843
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.1045438330
Short name T585
Test name
Test status
Simulation time 8379551013 ps
CPU time 8.26 seconds
Started Apr 30 02:47:46 PM PDT 24
Finished Apr 30 02:47:55 PM PDT 24
Peak memory 204040 kb
Host smart-ce09bfa2-70f6-45aa-8b36-45607af9b183
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1045438330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.1045438330
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.49715873
Short name T1061
Test name
Test status
Simulation time 8386620136 ps
CPU time 7.69 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:56 PM PDT 24
Peak memory 204076 kb
Host smart-a5350f05-facc-4fea-96c0-c32924dd661b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49715
873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.49715873
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2882658839
Short name T539
Test name
Test status
Simulation time 8375012192 ps
CPU time 7.69 seconds
Started Apr 30 02:47:38 PM PDT 24
Finished Apr 30 02:47:47 PM PDT 24
Peak memory 204124 kb
Host smart-b07b04cd-d0af-46ab-9bc7-ecb13ce644f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28826
58839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2882658839
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.613045893
Short name T484
Test name
Test status
Simulation time 8378537992 ps
CPU time 9.63 seconds
Started Apr 30 02:47:44 PM PDT 24
Finished Apr 30 02:47:54 PM PDT 24
Peak memory 204128 kb
Host smart-6dcbc5c2-435d-456a-9e5c-7b1ab9e76090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61304
5893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.613045893
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1365538963
Short name T748
Test name
Test status
Simulation time 292447735 ps
CPU time 2.13 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:42 PM PDT 24
Peak memory 204256 kb
Host smart-48b42112-2ab3-4d2c-9cbb-b62c218261a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13655
38963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1365538963
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3924538037
Short name T612
Test name
Test status
Simulation time 8436449510 ps
CPU time 9.9 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:53 PM PDT 24
Peak memory 204076 kb
Host smart-fe6ec0dc-5cf3-4df1-9b35-48d2af263a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39245
38037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3924538037
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2301037499
Short name T1317
Test name
Test status
Simulation time 8362932890 ps
CPU time 8.09 seconds
Started Apr 30 02:47:41 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204088 kb
Host smart-76e1a044-19ee-4512-9e69-c5134faf96c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23010
37499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2301037499
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2992763813
Short name T975
Test name
Test status
Simulation time 8445783701 ps
CPU time 8.03 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204092 kb
Host smart-9840ba93-8400-431a-9233-a21067c6879d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29927
63813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2992763813
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3532882068
Short name T869
Test name
Test status
Simulation time 8415885531 ps
CPU time 10.12 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204056 kb
Host smart-2455b269-236b-4c13-95a0-9e0370b08c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328
82068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3532882068
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.4028712376
Short name T1035
Test name
Test status
Simulation time 8371390866 ps
CPU time 9.93 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204056 kb
Host smart-4f09f101-c61d-422d-b127-96cd92bee527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40287
12376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4028712376
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.35684814
Short name T113
Test name
Test status
Simulation time 8416854666 ps
CPU time 8.06 seconds
Started Apr 30 02:47:42 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204016 kb
Host smart-a5959193-4212-48ee-ad63-059eec3cc2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.35684814
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.915746836
Short name T1239
Test name
Test status
Simulation time 8386589773 ps
CPU time 10.05 seconds
Started Apr 30 02:47:41 PM PDT 24
Finished Apr 30 02:47:52 PM PDT 24
Peak memory 204140 kb
Host smart-abe90d85-af41-4bc1-b836-abf082e3c71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91574
6836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.915746836
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2375920214
Short name T1172
Test name
Test status
Simulation time 8384176998 ps
CPU time 8.04 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204124 kb
Host smart-4c5222ed-4fcc-48fc-bee9-33bfc7286cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
20214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2375920214
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3020108905
Short name T908
Test name
Test status
Simulation time 8373453126 ps
CPU time 8.22 seconds
Started Apr 30 02:47:42 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204008 kb
Host smart-f4e45c63-7bba-4929-b9a9-9e509854aefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201
08905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3020108905
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3686813140
Short name T635
Test name
Test status
Simulation time 44755443 ps
CPU time 0.66 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:42 PM PDT 24
Peak memory 204012 kb
Host smart-c75cc206-bdf3-4bff-ac0e-9a28ec94e3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36868
13140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3686813140
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3762771831
Short name T241
Test name
Test status
Simulation time 25511903910 ps
CPU time 48.7 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 204340 kb
Host smart-fd1d8ebb-ff91-4d6f-a6be-6dd9b75a63c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37627
71831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3762771831
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.436574409
Short name T383
Test name
Test status
Simulation time 8438703930 ps
CPU time 7.71 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204064 kb
Host smart-2ba2eb2a-6f07-4df3-ab0f-fe1a9f55d0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43657
4409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.436574409
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1149290078
Short name T1142
Test name
Test status
Simulation time 8401010211 ps
CPU time 8.69 seconds
Started Apr 30 02:47:40 PM PDT 24
Finished Apr 30 02:47:49 PM PDT 24
Peak memory 204076 kb
Host smart-bd60bfee-fc3f-45c1-838b-3729d6354196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492
90078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1149290078
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1818410355
Short name T158
Test name
Test status
Simulation time 8388430646 ps
CPU time 10.43 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 204136 kb
Host smart-95a37e85-9edc-4eac-adf5-3646b458f3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18184
10355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1818410355
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3270760031
Short name T1261
Test name
Test status
Simulation time 8393212587 ps
CPU time 8.73 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:52 PM PDT 24
Peak memory 204076 kb
Host smart-d667b2cc-0011-4ab5-a303-82d8f57dff3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
60031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3270760031
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.110398533
Short name T163
Test name
Test status
Simulation time 8510386303 ps
CPU time 8.03 seconds
Started Apr 30 02:47:39 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204072 kb
Host smart-18def206-2d44-4701-b634-cbb1c44b7211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11039
8533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.110398533
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2540224505
Short name T923
Test name
Test status
Simulation time 8405452789 ps
CPU time 8.21 seconds
Started Apr 30 02:47:43 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204100 kb
Host smart-083b2045-4392-4bed-8781-43d1ac383f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
24505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2540224505
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1862909973
Short name T1310
Test name
Test status
Simulation time 8409019270 ps
CPU time 8.72 seconds
Started Apr 30 02:47:38 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204120 kb
Host smart-fe9a30c8-3a5f-465f-8afd-6217e0ab62b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18629
09973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1862909973
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.4049921681
Short name T743
Test name
Test status
Simulation time 8472898177 ps
CPU time 7.91 seconds
Started Apr 30 02:47:46 PM PDT 24
Finished Apr 30 02:47:55 PM PDT 24
Peak memory 204080 kb
Host smart-b34a108b-4437-428f-b2b6-6a4c0b18105f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4049921681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.4049921681
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.1116449122
Short name T269
Test name
Test status
Simulation time 8378915867 ps
CPU time 7.69 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:56 PM PDT 24
Peak memory 204112 kb
Host smart-b20667df-4378-42bb-929c-8f84cf45aece
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1116449122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.1116449122
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2309809208
Short name T482
Test name
Test status
Simulation time 8387561137 ps
CPU time 8.92 seconds
Started Apr 30 02:47:46 PM PDT 24
Finished Apr 30 02:47:57 PM PDT 24
Peak memory 204100 kb
Host smart-63e0354d-afe5-47c0-8a1f-971bf627d6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098
09208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2309809208
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3858351595
Short name T1012
Test name
Test status
Simulation time 8385048876 ps
CPU time 8.42 seconds
Started Apr 30 02:47:47 PM PDT 24
Finished Apr 30 02:47:56 PM PDT 24
Peak memory 204056 kb
Host smart-99dcb2a5-d98f-4ec7-a767-84ab1b1926e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38583
51595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3858351595
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.2901325824
Short name T1262
Test name
Test status
Simulation time 8429312726 ps
CPU time 8.15 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:57 PM PDT 24
Peak memory 204108 kb
Host smart-a7b5c785-619c-4bb3-b193-dc2bd4a7fb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29013
25824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2901325824
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1397440848
Short name T966
Test name
Test status
Simulation time 105602431 ps
CPU time 1.3 seconds
Started Apr 30 02:47:45 PM PDT 24
Finished Apr 30 02:47:47 PM PDT 24
Peak memory 204244 kb
Host smart-a6e4ee66-554b-45e0-8ae4-99e96423c83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13974
40848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1397440848
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.94105718
Short name T128
Test name
Test status
Simulation time 8443846552 ps
CPU time 9.67 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:02 PM PDT 24
Peak memory 204304 kb
Host smart-8d888590-052b-4954-8b89-7cd80422db4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94105
718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.94105718
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2738974267
Short name T990
Test name
Test status
Simulation time 8374650637 ps
CPU time 7.97 seconds
Started Apr 30 02:47:45 PM PDT 24
Finished Apr 30 02:47:53 PM PDT 24
Peak memory 204168 kb
Host smart-8847886d-a4af-49a5-8829-3ddd089be8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27389
74267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2738974267
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2084943221
Short name T148
Test name
Test status
Simulation time 8407310246 ps
CPU time 9.64 seconds
Started Apr 30 02:47:45 PM PDT 24
Finished Apr 30 02:47:56 PM PDT 24
Peak memory 204076 kb
Host smart-9f128d4e-17bc-436f-a406-b555bc74ac3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20849
43221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2084943221
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2930415572
Short name T1111
Test name
Test status
Simulation time 8415357638 ps
CPU time 8.31 seconds
Started Apr 30 02:47:50 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204104 kb
Host smart-b112713a-9a9a-483f-84b5-9b9935383754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304
15572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2930415572
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.4103884348
Short name T376
Test name
Test status
Simulation time 8391916281 ps
CPU time 7.53 seconds
Started Apr 30 02:47:50 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204064 kb
Host smart-12f2fceb-84e3-4ea4-aea8-eb774284ae0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41038
84348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.4103884348
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1259789596
Short name T690
Test name
Test status
Simulation time 8408071467 ps
CPU time 8.05 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:00 PM PDT 24
Peak memory 204112 kb
Host smart-5c1fab85-e6d2-4f99-98b2-799649249807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12597
89596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1259789596
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3098489163
Short name T401
Test name
Test status
Simulation time 8423914774 ps
CPU time 7.92 seconds
Started Apr 30 02:47:46 PM PDT 24
Finished Apr 30 02:47:55 PM PDT 24
Peak memory 204128 kb
Host smart-912f562d-e90f-4626-92d1-d517a2a81de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
89163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3098489163
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2937145262
Short name T1007
Test name
Test status
Simulation time 8377666929 ps
CPU time 7.73 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:00 PM PDT 24
Peak memory 204104 kb
Host smart-797a6aa1-8498-4e7c-9f31-29b6c3facb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
45262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2937145262
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3179691283
Short name T650
Test name
Test status
Simulation time 42075218 ps
CPU time 0.68 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:50 PM PDT 24
Peak memory 203940 kb
Host smart-76e36851-cd16-4e24-b2c7-978e05eb5ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31796
91283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3179691283
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.954080078
Short name T268
Test name
Test status
Simulation time 8373402031 ps
CPU time 9.22 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:58 PM PDT 24
Peak memory 204100 kb
Host smart-a3dcb57c-2c7a-46d9-a2d5-8f6b7f5e036e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95408
0078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.954080078
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2407757930
Short name T803
Test name
Test status
Simulation time 8436125170 ps
CPU time 9.93 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:48:00 PM PDT 24
Peak memory 204088 kb
Host smart-8de8aae1-76a2-4bb7-9c5c-a43aea4b84c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24077
57930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2407757930
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3876024461
Short name T436
Test name
Test status
Simulation time 8391899509 ps
CPU time 9.04 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204064 kb
Host smart-88119736-56d0-4ebc-9a9c-70c1343901e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38760
24461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3876024461
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.4228172476
Short name T542
Test name
Test status
Simulation time 8391835926 ps
CPU time 8.22 seconds
Started Apr 30 02:47:46 PM PDT 24
Finished Apr 30 02:47:56 PM PDT 24
Peak memory 204088 kb
Host smart-cec6a67c-c222-480b-bcf4-ebf740057f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42281
72476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.4228172476
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2566694032
Short name T1067
Test name
Test status
Simulation time 8369048398 ps
CPU time 10.28 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:48:01 PM PDT 24
Peak memory 204100 kb
Host smart-d0b1474e-83a7-45e6-b346-8455059e1f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25666
94032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2566694032
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1555906825
Short name T1152
Test name
Test status
Simulation time 8426475668 ps
CPU time 7.6 seconds
Started Apr 30 02:47:47 PM PDT 24
Finished Apr 30 02:47:55 PM PDT 24
Peak memory 204060 kb
Host smart-714a9f69-ad2d-4547-b3a7-82b5574aefa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15559
06825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1555906825
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1477535763
Short name T1001
Test name
Test status
Simulation time 8373047556 ps
CPU time 10.29 seconds
Started Apr 30 02:47:50 PM PDT 24
Finished Apr 30 02:48:02 PM PDT 24
Peak memory 204288 kb
Host smart-09242d40-53da-4c7b-a8a6-f66c2a592ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14775
35763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1477535763
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1867865765
Short name T649
Test name
Test status
Simulation time 8402765669 ps
CPU time 7.65 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:57 PM PDT 24
Peak memory 204052 kb
Host smart-54de641b-2e66-4c5f-be48-5456fef19f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18678
65765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1867865765
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1365938246
Short name T586
Test name
Test status
Simulation time 8468264681 ps
CPU time 8.26 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204120 kb
Host smart-3e663cec-d4e6-4e10-b0f8-b5deadafba9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1365938246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1365938246
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.3128518194
Short name T672
Test name
Test status
Simulation time 8425111776 ps
CPU time 10.31 seconds
Started Apr 30 02:47:56 PM PDT 24
Finished Apr 30 02:48:07 PM PDT 24
Peak memory 204156 kb
Host smart-ba426335-7643-4a60-a8c0-d28ec4228a6a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3128518194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.3128518194
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2134443580
Short name T826
Test name
Test status
Simulation time 8410526619 ps
CPU time 9.39 seconds
Started Apr 30 02:47:58 PM PDT 24
Finished Apr 30 02:48:08 PM PDT 24
Peak memory 204100 kb
Host smart-fc9f019c-cab7-4e67-b8d4-d2217b0b3c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21344
43580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2134443580
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.256951110
Short name T1156
Test name
Test status
Simulation time 8430936119 ps
CPU time 8.26 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204124 kb
Host smart-fe261d49-6d27-4ac1-a109-0714783606a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
1110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.256951110
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.1503708146
Short name T344
Test name
Test status
Simulation time 8387242641 ps
CPU time 7.85 seconds
Started Apr 30 02:47:46 PM PDT 24
Finished Apr 30 02:47:55 PM PDT 24
Peak memory 204148 kb
Host smart-87cfc702-1b0a-4c25-b927-3ea5a3265c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15037
08146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1503708146
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2383719783
Short name T1150
Test name
Test status
Simulation time 93678969 ps
CPU time 1.25 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:47:51 PM PDT 24
Peak memory 204168 kb
Host smart-449cf2b2-0365-43b9-a1ca-d1b58804b27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23837
19783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2383719783
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.420819457
Short name T1013
Test name
Test status
Simulation time 8401335970 ps
CPU time 8.41 seconds
Started Apr 30 02:47:54 PM PDT 24
Finished Apr 30 02:48:03 PM PDT 24
Peak memory 204148 kb
Host smart-88b98de4-2df3-4206-a080-a87913b03d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081
9457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.420819457
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1234652827
Short name T191
Test name
Test status
Simulation time 8373158072 ps
CPU time 9.28 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:05 PM PDT 24
Peak memory 204084 kb
Host smart-69a3e360-5d20-4319-9c2f-2f0ab88ba89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346
52827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1234652827
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.619502463
Short name T1132
Test name
Test status
Simulation time 8417620472 ps
CPU time 9.37 seconds
Started Apr 30 02:47:45 PM PDT 24
Finished Apr 30 02:47:55 PM PDT 24
Peak memory 204060 kb
Host smart-ae172d3b-9552-4f7f-9535-462494e6499d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61950
2463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.619502463
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.897144058
Short name T1307
Test name
Test status
Simulation time 8418825629 ps
CPU time 9.4 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204060 kb
Host smart-a7b36cc0-c6b2-4dd4-94a6-60c5720a999f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89714
4058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.897144058
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3952086125
Short name T472
Test name
Test status
Simulation time 8375730266 ps
CPU time 10.23 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:03 PM PDT 24
Peak memory 204064 kb
Host smart-6fb5eb95-14b8-4c50-9270-fef2f3eb430f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39520
86125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3952086125
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1010077584
Short name T818
Test name
Test status
Simulation time 8409244550 ps
CPU time 8.95 seconds
Started Apr 30 02:47:52 PM PDT 24
Finished Apr 30 02:48:02 PM PDT 24
Peak memory 204304 kb
Host smart-d285b7c6-94cf-406f-968d-8b6a80bc8681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10100
77584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1010077584
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2861200289
Short name T1257
Test name
Test status
Simulation time 8386161513 ps
CPU time 7.63 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:57 PM PDT 24
Peak memory 204076 kb
Host smart-5cc41bf1-b07f-4634-b368-1ed72eaaab34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28612
00289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2861200289
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3172850925
Short name T84
Test name
Test status
Simulation time 8396247733 ps
CPU time 8.02 seconds
Started Apr 30 02:47:59 PM PDT 24
Finished Apr 30 02:48:08 PM PDT 24
Peak memory 204112 kb
Host smart-71b0d048-76f1-40e3-9184-74a244615474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31728
50925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3172850925
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3764029845
Short name T452
Test name
Test status
Simulation time 8377570756 ps
CPU time 7.8 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:47:59 PM PDT 24
Peak memory 204096 kb
Host smart-d655ac4b-9249-4882-84c5-30a877a807f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37640
29845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3764029845
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2804352656
Short name T1183
Test name
Test status
Simulation time 40791880 ps
CPU time 0.71 seconds
Started Apr 30 02:48:01 PM PDT 24
Finished Apr 30 02:48:02 PM PDT 24
Peak memory 203908 kb
Host smart-4715d591-3555-4c77-be7a-62bdcf6f1994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043
52656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2804352656
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1712617155
Short name T870
Test name
Test status
Simulation time 26291285007 ps
CPU time 50.52 seconds
Started Apr 30 02:47:52 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204364 kb
Host smart-186e784d-15f1-43e9-8f1e-6a1f144b02dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17126
17155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1712617155
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3223019961
Short name T971
Test name
Test status
Simulation time 8421642413 ps
CPU time 8.86 seconds
Started Apr 30 02:47:52 PM PDT 24
Finished Apr 30 02:48:01 PM PDT 24
Peak memory 204072 kb
Host smart-00cfe7ab-7d9e-4906-a0fa-900f5350b989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32230
19961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3223019961
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1499321548
Short name T607
Test name
Test status
Simulation time 8408545035 ps
CPU time 8.67 seconds
Started Apr 30 02:47:51 PM PDT 24
Finished Apr 30 02:48:01 PM PDT 24
Peak memory 204080 kb
Host smart-0ce1fbb2-162c-4be6-9a63-3f32850b9bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14993
21548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1499321548
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1589068542
Short name T799
Test name
Test status
Simulation time 8398051560 ps
CPU time 8.63 seconds
Started Apr 30 02:47:47 PM PDT 24
Finished Apr 30 02:47:57 PM PDT 24
Peak memory 204124 kb
Host smart-2053d3dc-c238-4bc3-8d7b-a59faa6c1661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
68542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1589068542
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2063904048
Short name T745
Test name
Test status
Simulation time 8418937289 ps
CPU time 7.51 seconds
Started Apr 30 02:47:53 PM PDT 24
Finished Apr 30 02:48:01 PM PDT 24
Peak memory 204136 kb
Host smart-e27c454e-69c7-4bdd-9534-60e5f4567313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20639
04048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2063904048
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2527433151
Short name T1127
Test name
Test status
Simulation time 8377674341 ps
CPU time 9.95 seconds
Started Apr 30 02:47:47 PM PDT 24
Finished Apr 30 02:47:58 PM PDT 24
Peak memory 204012 kb
Host smart-fdf21f14-92b1-4916-a58b-6673ad7141bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
33151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2527433151
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2418572959
Short name T910
Test name
Test status
Simulation time 8438409451 ps
CPU time 7.83 seconds
Started Apr 30 02:47:49 PM PDT 24
Finished Apr 30 02:47:58 PM PDT 24
Peak memory 204096 kb
Host smart-00c284f1-c8c7-4cc8-a988-7993b1d3a21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24185
72959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2418572959
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1759113981
Short name T1026
Test name
Test status
Simulation time 8391196737 ps
CPU time 8.4 seconds
Started Apr 30 02:47:48 PM PDT 24
Finished Apr 30 02:47:57 PM PDT 24
Peak memory 204060 kb
Host smart-1a9e0adc-28cb-4058-bf5f-0e2f49f45948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17591
13981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1759113981
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1137026166
Short name T900
Test name
Test status
Simulation time 8402752504 ps
CPU time 10.27 seconds
Started Apr 30 02:47:52 PM PDT 24
Finished Apr 30 02:48:03 PM PDT 24
Peak memory 204072 kb
Host smart-042f39b0-7d45-4f49-8555-baff8bc3f76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11370
26166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1137026166
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.1714835505
Short name T992
Test name
Test status
Simulation time 8466825381 ps
CPU time 7.76 seconds
Started Apr 30 02:48:00 PM PDT 24
Finished Apr 30 02:48:08 PM PDT 24
Peak memory 204064 kb
Host smart-bb40e745-a71e-4090-a247-7873e89421ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1714835505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.1714835505
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.1731858354
Short name T675
Test name
Test status
Simulation time 8392237569 ps
CPU time 9.33 seconds
Started Apr 30 02:47:56 PM PDT 24
Finished Apr 30 02:48:06 PM PDT 24
Peak memory 204128 kb
Host smart-b27d9128-3af1-42e8-a45c-bc2fc0a3eb8f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1731858354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.1731858354
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.347561302
Short name T730
Test name
Test status
Simulation time 8443935203 ps
CPU time 8.83 seconds
Started Apr 30 02:48:01 PM PDT 24
Finished Apr 30 02:48:10 PM PDT 24
Peak memory 204036 kb
Host smart-b4499e62-5672-4c2a-a3f0-fb9375ae691a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
1302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.347561302
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.217456221
Short name T744
Test name
Test status
Simulation time 8378458107 ps
CPU time 7.88 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204052 kb
Host smart-0c463333-4374-4600-b60e-73a7727535bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21745
6221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.217456221
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.3711216090
Short name T71
Test name
Test status
Simulation time 8378667849 ps
CPU time 8.1 seconds
Started Apr 30 02:47:56 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204048 kb
Host smart-79691cf6-cb56-4468-9e8c-005e185e5fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37112
16090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3711216090
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2572069347
Short name T512
Test name
Test status
Simulation time 158330718 ps
CPU time 1.78 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:47:58 PM PDT 24
Peak memory 204224 kb
Host smart-4ca7d70c-2ad6-4af2-95fa-0a11eddea0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
69347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2572069347
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2161880656
Short name T550
Test name
Test status
Simulation time 8425916366 ps
CPU time 7.65 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204148 kb
Host smart-bb8f4cb9-e064-4139-b4f4-c84af06846f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21618
80656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2161880656
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2027924229
Short name T898
Test name
Test status
Simulation time 8410077007 ps
CPU time 8.2 seconds
Started Apr 30 02:47:57 PM PDT 24
Finished Apr 30 02:48:06 PM PDT 24
Peak memory 204060 kb
Host smart-06934d11-c06b-40b6-a9f9-04fd67b62927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20279
24229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2027924229
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4193972677
Short name T562
Test name
Test status
Simulation time 8393088429 ps
CPU time 7.52 seconds
Started Apr 30 02:47:59 PM PDT 24
Finished Apr 30 02:48:07 PM PDT 24
Peak memory 204064 kb
Host smart-77b00cdb-126f-4ba2-86f0-3cbe543d7630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41939
72677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4193972677
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3776976684
Short name T549
Test name
Test status
Simulation time 8415501346 ps
CPU time 7.79 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204108 kb
Host smart-bf528018-b26c-47dc-aec7-3d9d60f40a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37769
76684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3776976684
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2590555309
Short name T1356
Test name
Test status
Simulation time 8373982571 ps
CPU time 8.64 seconds
Started Apr 30 02:47:53 PM PDT 24
Finished Apr 30 02:48:02 PM PDT 24
Peak memory 204040 kb
Host smart-4ad83ff6-8764-48ef-ae01-97bbcfe9585f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25905
55309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2590555309
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1043855371
Short name T104
Test name
Test status
Simulation time 8404319831 ps
CPU time 8.08 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204112 kb
Host smart-4a9d74c6-7f8e-42ac-9f28-63d096987c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10438
55371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1043855371
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3926475684
Short name T540
Test name
Test status
Simulation time 8407335293 ps
CPU time 9.08 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204124 kb
Host smart-65ed7e8e-2539-4481-8b87-31a33ffcc9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39264
75684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3926475684
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1360437368
Short name T729
Test name
Test status
Simulation time 8397603474 ps
CPU time 9.16 seconds
Started Apr 30 02:48:00 PM PDT 24
Finished Apr 30 02:48:10 PM PDT 24
Peak memory 204104 kb
Host smart-a83dff48-b4e8-4a27-a989-08ac5d85612f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13604
37368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1360437368
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3870201024
Short name T169
Test name
Test status
Simulation time 8403976306 ps
CPU time 8.92 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:05 PM PDT 24
Peak memory 204144 kb
Host smart-501518e9-6f45-43d5-a7bb-e451dcfb8246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38702
01024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3870201024
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1979559144
Short name T1184
Test name
Test status
Simulation time 8373986302 ps
CPU time 8.85 seconds
Started Apr 30 02:47:54 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204104 kb
Host smart-0ffb931e-abfb-4f98-ad2d-cb1cec4e8445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19795
59144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1979559144
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.481700295
Short name T874
Test name
Test status
Simulation time 39236696 ps
CPU time 0.68 seconds
Started Apr 30 02:48:00 PM PDT 24
Finished Apr 30 02:48:01 PM PDT 24
Peak memory 203976 kb
Host smart-2c8b3126-8d00-4942-ac44-d5546e1d3484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48170
0295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.481700295
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1782873026
Short name T423
Test name
Test status
Simulation time 28944109617 ps
CPU time 56.96 seconds
Started Apr 30 02:47:57 PM PDT 24
Finished Apr 30 02:48:55 PM PDT 24
Peak memory 204368 kb
Host smart-32bb428c-0fd7-4599-af74-c7ce3d64bad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17828
73026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1782873026
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.212817963
Short name T788
Test name
Test status
Simulation time 8399850425 ps
CPU time 8.72 seconds
Started Apr 30 02:47:54 PM PDT 24
Finished Apr 30 02:48:03 PM PDT 24
Peak memory 204084 kb
Host smart-0a19ec15-2e4b-4aa9-b54e-f073a816896d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
7963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.212817963
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1411193375
Short name T687
Test name
Test status
Simulation time 8423045377 ps
CPU time 9.13 seconds
Started Apr 30 02:47:59 PM PDT 24
Finished Apr 30 02:48:09 PM PDT 24
Peak memory 204064 kb
Host smart-aa12afc3-d6ae-4836-9560-7a4065d5dd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14111
93375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1411193375
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1492669680
Short name T1147
Test name
Test status
Simulation time 8380409209 ps
CPU time 8.46 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:04 PM PDT 24
Peak memory 204116 kb
Host smart-fbe715e6-74eb-43d2-9c0f-30db9a506f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14926
69680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1492669680
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.745035981
Short name T1375
Test name
Test status
Simulation time 8379105286 ps
CPU time 8.67 seconds
Started Apr 30 02:47:58 PM PDT 24
Finished Apr 30 02:48:07 PM PDT 24
Peak memory 204140 kb
Host smart-ea8680a3-660c-450a-a223-232202fd77fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74503
5981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.745035981
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3321271442
Short name T453
Test name
Test status
Simulation time 8377105778 ps
CPU time 7.64 seconds
Started Apr 30 02:47:55 PM PDT 24
Finished Apr 30 02:48:03 PM PDT 24
Peak memory 204068 kb
Host smart-c71ed174-c9f8-4f89-b988-0c801764cdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33212
71442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3321271442
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1919943129
Short name T140
Test name
Test status
Simulation time 8446669854 ps
CPU time 8.13 seconds
Started Apr 30 02:47:54 PM PDT 24
Finished Apr 30 02:48:02 PM PDT 24
Peak memory 204132 kb
Host smart-7bfad9f4-8cf2-4075-8c03-eb2b1a634097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19199
43129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1919943129
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2021514503
Short name T628
Test name
Test status
Simulation time 8411088493 ps
CPU time 7.7 seconds
Started Apr 30 02:48:01 PM PDT 24
Finished Apr 30 02:48:09 PM PDT 24
Peak memory 204012 kb
Host smart-573a93bf-2d6a-4ac1-9a73-40976c3420e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20215
14503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2021514503
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.694918617
Short name T1098
Test name
Test status
Simulation time 8410643452 ps
CPU time 7.91 seconds
Started Apr 30 02:48:00 PM PDT 24
Finished Apr 30 02:48:08 PM PDT 24
Peak memory 204068 kb
Host smart-282f3465-2e12-4ab9-9e5f-61d53b073b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69491
8617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.694918617
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2464826978
Short name T1176
Test name
Test status
Simulation time 8514495824 ps
CPU time 8.42 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204156 kb
Host smart-f591c6b6-075a-4377-b694-d2f3c558b1ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2464826978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2464826978
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1615063814
Short name T359
Test name
Test status
Simulation time 8400260626 ps
CPU time 7.94 seconds
Started Apr 30 02:48:08 PM PDT 24
Finished Apr 30 02:48:17 PM PDT 24
Peak memory 204112 kb
Host smart-057d39eb-5730-4758-9f6a-3ca85c6d46e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1615063814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1615063814
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.437396782
Short name T571
Test name
Test status
Simulation time 8385105331 ps
CPU time 7.72 seconds
Started Apr 30 02:48:09 PM PDT 24
Finished Apr 30 02:48:17 PM PDT 24
Peak memory 204124 kb
Host smart-b8e70a32-831d-4c26-999a-523e9b83ab4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43739
6782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.437396782
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1596649551
Short name T1045
Test name
Test status
Simulation time 8370441656 ps
CPU time 8.05 seconds
Started Apr 30 02:47:56 PM PDT 24
Finished Apr 30 02:48:05 PM PDT 24
Peak memory 204152 kb
Host smart-0b993db5-dd4e-4c76-a1dc-250e197e0d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15966
49551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1596649551
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.2468058999
Short name T553
Test name
Test status
Simulation time 8378657956 ps
CPU time 9.27 seconds
Started Apr 30 02:48:01 PM PDT 24
Finished Apr 30 02:48:10 PM PDT 24
Peak memory 204004 kb
Host smart-afdccfe8-f89f-40a3-bb41-adfb023766ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
58999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2468058999
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3560458513
Short name T1338
Test name
Test status
Simulation time 110902820 ps
CPU time 1.1 seconds
Started Apr 30 02:48:12 PM PDT 24
Finished Apr 30 02:48:13 PM PDT 24
Peak memory 204416 kb
Host smart-77e23c99-11e0-464d-a48d-770ee96ced1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
58513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3560458513
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2287183454
Short name T1316
Test name
Test status
Simulation time 8412950953 ps
CPU time 9.64 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:21 PM PDT 24
Peak memory 204048 kb
Host smart-76ae5e6f-7abd-4639-8a7c-f9aed0d382d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
83454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2287183454
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2860132798
Short name T902
Test name
Test status
Simulation time 8427207451 ps
CPU time 10.04 seconds
Started Apr 30 02:48:09 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204124 kb
Host smart-2ed89e2a-9a4f-46ef-a5a0-5fedfd7ae218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28601
32798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2860132798
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2814698039
Short name T524
Test name
Test status
Simulation time 8463609821 ps
CPU time 11.38 seconds
Started Apr 30 02:48:09 PM PDT 24
Finished Apr 30 02:48:21 PM PDT 24
Peak memory 204100 kb
Host smart-14e7caba-603c-4838-9912-621cecc8fe37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28146
98039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2814698039
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1449944816
Short name T280
Test name
Test status
Simulation time 8375418829 ps
CPU time 8.12 seconds
Started Apr 30 02:48:08 PM PDT 24
Finished Apr 30 02:48:16 PM PDT 24
Peak memory 204084 kb
Host smart-31fd5263-838f-4e6a-904c-34a34f8d6184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14499
44816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1449944816
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2357521080
Short name T285
Test name
Test status
Simulation time 8400725589 ps
CPU time 9.63 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204076 kb
Host smart-7a002237-b6b7-41f5-bd56-77395fb0ebe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23575
21080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2357521080
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2239878055
Short name T379
Test name
Test status
Simulation time 8412923441 ps
CPU time 7.58 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204064 kb
Host smart-e627bf4e-64ff-4389-8b47-1d828f9491a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22398
78055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2239878055
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2736307724
Short name T973
Test name
Test status
Simulation time 8381934446 ps
CPU time 8.06 seconds
Started Apr 30 02:48:12 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204064 kb
Host smart-607f4164-5c6f-4220-90ac-ce3f488fac1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27363
07724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2736307724
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2290326682
Short name T891
Test name
Test status
Simulation time 92792334 ps
CPU time 0.72 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:11 PM PDT 24
Peak memory 203912 kb
Host smart-2fa39806-d357-4575-9fd5-3837dbdbb56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22903
26682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2290326682
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1455559085
Short name T1041
Test name
Test status
Simulation time 25674417012 ps
CPU time 51.38 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204412 kb
Host smart-11c1584e-36f6-4121-921d-5206549dc6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14555
59085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1455559085
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3738586911
Short name T390
Test name
Test status
Simulation time 8373843727 ps
CPU time 9.75 seconds
Started Apr 30 02:48:13 PM PDT 24
Finished Apr 30 02:48:24 PM PDT 24
Peak memory 204068 kb
Host smart-e161667e-a301-4e55-b919-e707bebe9fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
86911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3738586911
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.571437871
Short name T655
Test name
Test status
Simulation time 8391136661 ps
CPU time 7.88 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204024 kb
Host smart-3de00ed7-c182-48d8-92d8-34f34f614a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57143
7871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.571437871
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1464941131
Short name T278
Test name
Test status
Simulation time 8371586984 ps
CPU time 7.61 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204080 kb
Host smart-a4de14b0-55c3-4122-bffa-a193ebfe6cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649
41131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1464941131
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.4108770464
Short name T548
Test name
Test status
Simulation time 8370614990 ps
CPU time 7.59 seconds
Started Apr 30 02:48:09 PM PDT 24
Finished Apr 30 02:48:17 PM PDT 24
Peak memory 204048 kb
Host smart-3c220a1e-a1b4-4d05-bf13-5a460c6ca556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
70464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.4108770464
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3828619811
Short name T402
Test name
Test status
Simulation time 8375480852 ps
CPU time 8.58 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204112 kb
Host smart-9ae20ad7-ef81-4526-b23c-95719ab3e083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38286
19811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3828619811
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.4143826417
Short name T1324
Test name
Test status
Simulation time 8436583228 ps
CPU time 8.48 seconds
Started Apr 30 02:47:54 PM PDT 24
Finished Apr 30 02:48:03 PM PDT 24
Peak memory 204128 kb
Host smart-3970c881-d4df-497f-9fc7-a85d8ffa3a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41438
26417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4143826417
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1402442076
Short name T287
Test name
Test status
Simulation time 8406418308 ps
CPU time 10.46 seconds
Started Apr 30 02:48:09 PM PDT 24
Finished Apr 30 02:48:21 PM PDT 24
Peak memory 204104 kb
Host smart-de0c5011-eb83-420c-906f-4d9b9ba1889a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14024
42076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1402442076
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.615697002
Short name T517
Test name
Test status
Simulation time 8414231024 ps
CPU time 8.08 seconds
Started Apr 30 02:48:08 PM PDT 24
Finished Apr 30 02:48:16 PM PDT 24
Peak memory 204088 kb
Host smart-8ab25c8d-f516-4f71-b1e5-aa859fef2f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61569
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.615697002
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.1501071592
Short name T997
Test name
Test status
Simulation time 8461611456 ps
CPU time 7.77 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:28 PM PDT 24
Peak memory 204020 kb
Host smart-6dbe0936-9ed5-4e6c-bfdf-7f24a6d4efec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1501071592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.1501071592
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2865265599
Short name T578
Test name
Test status
Simulation time 8378740982 ps
CPU time 8.31 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 204136 kb
Host smart-d21fd377-96c4-483f-8885-c0d0d4e6feb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2865265599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2865265599
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.781453153
Short name T1303
Test name
Test status
Simulation time 8443270122 ps
CPU time 7.76 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204160 kb
Host smart-a3b777cd-44db-45ea-bf78-e2860243398b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78145
3153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.781453153
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1928452228
Short name T886
Test name
Test status
Simulation time 8404985809 ps
CPU time 7.45 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204052 kb
Host smart-795db7f2-05df-41db-b57a-70d13991c0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284
52228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1928452228
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.1958374716
Short name T408
Test name
Test status
Simulation time 8384609348 ps
CPU time 8.18 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204080 kb
Host smart-60f2d5a3-c253-41c0-a3cc-6208189333bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
74716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1958374716
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2616439388
Short name T528
Test name
Test status
Simulation time 89224965 ps
CPU time 2.02 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:14 PM PDT 24
Peak memory 204144 kb
Host smart-9ff3f927-5a6e-4d79-a92e-1e8d298094c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
39388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2616439388
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3446875373
Short name T151
Test name
Test status
Simulation time 8406429649 ps
CPU time 8.2 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204044 kb
Host smart-1f0c99c3-9471-4124-b8cb-997d6750b21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34468
75373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3446875373
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.4235683513
Short name T1335
Test name
Test status
Simulation time 8371394206 ps
CPU time 8.64 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:28 PM PDT 24
Peak memory 204152 kb
Host smart-ebcbe8b1-2d47-478b-bb3f-5afbeabea17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42356
83513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.4235683513
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1378484595
Short name T842
Test name
Test status
Simulation time 8444818406 ps
CPU time 9.22 seconds
Started Apr 30 02:48:17 PM PDT 24
Finished Apr 30 02:48:27 PM PDT 24
Peak memory 204124 kb
Host smart-5c0e1777-a064-4ca9-a605-9386561c8c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
84595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1378484595
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.745769678
Short name T1327
Test name
Test status
Simulation time 8482813261 ps
CPU time 8.36 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204132 kb
Host smart-56869b0f-b8e2-46f4-aecb-0447154e3858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74576
9678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.745769678
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.57200391
Short name T476
Test name
Test status
Simulation time 8375971527 ps
CPU time 9.98 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204052 kb
Host smart-7fcc7cee-99cf-4dd9-bcc5-39dcf0d693aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57200
391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.57200391
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2866804941
Short name T1139
Test name
Test status
Simulation time 8410675535 ps
CPU time 7.64 seconds
Started Apr 30 02:48:17 PM PDT 24
Finished Apr 30 02:48:25 PM PDT 24
Peak memory 204140 kb
Host smart-a82cdac6-6ecf-4043-988e-c93b78304d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
04941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2866804941
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.297037281
Short name T657
Test name
Test status
Simulation time 8382546789 ps
CPU time 7.94 seconds
Started Apr 30 02:48:17 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204128 kb
Host smart-254576cc-bf55-483c-be99-3e9296997b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
7281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.297037281
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2430794605
Short name T640
Test name
Test status
Simulation time 8412335292 ps
CPU time 8.36 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204040 kb
Host smart-2d23e7e9-c25d-4496-ba8c-600003df33c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24307
94605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2430794605
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4095757226
Short name T315
Test name
Test status
Simulation time 8368784750 ps
CPU time 8.46 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204096 kb
Host smart-790bdee4-ce37-45ae-a7ec-0fcf9c259e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40957
57226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4095757226
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4169168372
Short name T982
Test name
Test status
Simulation time 37623171 ps
CPU time 0.68 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:21 PM PDT 24
Peak memory 204016 kb
Host smart-6b46d27f-444c-4b9f-818d-073ea6ebbecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41691
68372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4169168372
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3361465435
Short name T1078
Test name
Test status
Simulation time 17297578214 ps
CPU time 33.03 seconds
Started Apr 30 02:48:12 PM PDT 24
Finished Apr 30 02:48:46 PM PDT 24
Peak memory 204420 kb
Host smart-f7b229d7-e8be-4b22-be44-3cc61744da11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
65435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3361465435
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.819865356
Short name T1350
Test name
Test status
Simulation time 8397230497 ps
CPU time 8.43 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204120 kb
Host smart-91a57fc7-873f-4913-a9d1-76b613ee7c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81986
5356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.819865356
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2356743446
Short name T409
Test name
Test status
Simulation time 8438224736 ps
CPU time 8.49 seconds
Started Apr 30 02:48:11 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204072 kb
Host smart-dee82d68-b6c5-42e5-a1c0-a67928bf0778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23567
43446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2356743446
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.3763835782
Short name T1065
Test name
Test status
Simulation time 8403726489 ps
CPU time 8.33 seconds
Started Apr 30 02:48:17 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204136 kb
Host smart-3df8ea77-7fc9-4890-80f5-0086a3bbb5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37638
35782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.3763835782
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1181465077
Short name T551
Test name
Test status
Simulation time 8390080098 ps
CPU time 7.88 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 203996 kb
Host smart-d91488d1-38f3-414c-9462-d3acc1a76a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
65077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1181465077
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2412064831
Short name T651
Test name
Test status
Simulation time 8375435470 ps
CPU time 9.89 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204072 kb
Host smart-b672dcf3-20bd-40e9-a73c-0547b118e4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
64831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2412064831
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3000007548
Short name T31
Test name
Test status
Simulation time 8456555363 ps
CPU time 8.02 seconds
Started Apr 30 02:48:10 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204032 kb
Host smart-d85b6e8e-9ec9-4d82-85da-a6a7383b866a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
07548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3000007548
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3742198509
Short name T1302
Test name
Test status
Simulation time 8398615567 ps
CPU time 7.64 seconds
Started Apr 30 02:48:23 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204104 kb
Host smart-fe75e095-0888-4291-9de1-c04d7ed9b1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
98509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3742198509
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.327009674
Short name T294
Test name
Test status
Simulation time 8441249150 ps
CPU time 7.93 seconds
Started Apr 30 02:48:12 PM PDT 24
Finished Apr 30 02:48:20 PM PDT 24
Peak memory 204060 kb
Host smart-4a146302-6093-4182-be0b-cb2c47d3c0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32700
9674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.327009674
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.764697539
Short name T502
Test name
Test status
Simulation time 8466256463 ps
CPU time 10 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 203992 kb
Host smart-3a0c1e67-0440-4685-b81a-bb3ea9eb2b03
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=764697539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.764697539
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1115369323
Short name T624
Test name
Test status
Simulation time 8392634426 ps
CPU time 8.1 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204076 kb
Host smart-e4e12f61-0a2e-446c-8c15-6390a98dea89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1115369323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1115369323
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.1028177928
Short name T955
Test name
Test status
Simulation time 8404349105 ps
CPU time 7.78 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:28 PM PDT 24
Peak memory 204136 kb
Host smart-ff0dece9-6b65-4e40-b858-546c1560dcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10281
77928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.1028177928
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.481235185
Short name T415
Test name
Test status
Simulation time 8436651478 ps
CPU time 7.77 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:27 PM PDT 24
Peak memory 204088 kb
Host smart-fb8411c6-c297-4129-bfcc-24f755db41c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48123
5185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.481235185
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.1816609689
Short name T1024
Test name
Test status
Simulation time 8379062875 ps
CPU time 7.95 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204112 kb
Host smart-b4485472-c36e-4c86-8a2d-95a720e21772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18166
09689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1816609689
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.527536458
Short name T808
Test name
Test status
Simulation time 167139388 ps
CPU time 1.38 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:22 PM PDT 24
Peak memory 204156 kb
Host smart-e78759c4-84c0-4628-8c06-5eb9584c565c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52753
6458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.527536458
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1668098350
Short name T707
Test name
Test status
Simulation time 8389187909 ps
CPU time 7.64 seconds
Started Apr 30 02:48:17 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204088 kb
Host smart-93d2f220-3339-403b-aa90-9b775891ab67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16680
98350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1668098350
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3072229640
Short name T686
Test name
Test status
Simulation time 8368264943 ps
CPU time 9.9 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:33 PM PDT 24
Peak memory 204168 kb
Host smart-0612ca32-845e-44b3-98d9-f43cb26c5e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722
29640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3072229640
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1700008138
Short name T1267
Test name
Test status
Simulation time 8385075901 ps
CPU time 9.19 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 203548 kb
Host smart-76ade56c-0657-49a6-a7bf-3f751b1a131d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17000
08138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1700008138
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4031747333
Short name T1357
Test name
Test status
Simulation time 8444838922 ps
CPU time 7.63 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 203720 kb
Host smart-911b0cb6-f93c-47df-89dc-c86d7fa45803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40317
47333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4031747333
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3689903777
Short name T289
Test name
Test status
Simulation time 8400065107 ps
CPU time 7.82 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204068 kb
Host smart-95161d39-ae07-470e-8fc0-58a2b84954e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899
03777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3689903777
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1579250042
Short name T552
Test name
Test status
Simulation time 8407716338 ps
CPU time 8.64 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204056 kb
Host smart-90dc2c93-a740-4a8f-bde9-bafda709763f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15792
50042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1579250042
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1167183995
Short name T462
Test name
Test status
Simulation time 8387592526 ps
CPU time 8.52 seconds
Started Apr 30 02:48:17 PM PDT 24
Finished Apr 30 02:48:27 PM PDT 24
Peak memory 204092 kb
Host smart-3f08fcda-b001-437b-b116-12cfc931e9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11671
83995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1167183995
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1943428016
Short name T445
Test name
Test status
Simulation time 8405733206 ps
CPU time 7.78 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204120 kb
Host smart-331b1fb9-81e5-4e02-a617-9038625b4560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19434
28016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1943428016
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2312750092
Short name T385
Test name
Test status
Simulation time 8367176561 ps
CPU time 8.7 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204104 kb
Host smart-3d7a3b5a-72d6-40d9-b83e-8a28b2a6f039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23127
50092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2312750092
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2574878722
Short name T719
Test name
Test status
Simulation time 139371779 ps
CPU time 0.76 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:23 PM PDT 24
Peak memory 203924 kb
Host smart-4468ee2b-ca51-4c97-8d70-9ac0212549b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
78722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2574878722
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.4037986521
Short name T1244
Test name
Test status
Simulation time 17669556603 ps
CPU time 30.33 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204340 kb
Host smart-27fc6db9-1b1f-4f4a-bdd7-ee7733583f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40379
86521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.4037986521
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.373258094
Short name T813
Test name
Test status
Simulation time 8415464147 ps
CPU time 8.21 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:27 PM PDT 24
Peak memory 204076 kb
Host smart-c05b350d-aa81-4ce4-b263-d4e44febaaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
8094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.373258094
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.4135529102
Short name T537
Test name
Test status
Simulation time 8410116331 ps
CPU time 9.01 seconds
Started Apr 30 02:48:25 PM PDT 24
Finished Apr 30 02:48:35 PM PDT 24
Peak memory 204068 kb
Host smart-81c5a140-5c97-43d5-b996-71d608a0da1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41355
29102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.4135529102
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2293206965
Short name T334
Test name
Test status
Simulation time 8421844713 ps
CPU time 8.81 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204088 kb
Host smart-981ad131-d3d2-4c6c-9558-a61f50e15cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22932
06965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2293206965
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1721542410
Short name T561
Test name
Test status
Simulation time 8371224423 ps
CPU time 8.17 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204104 kb
Host smart-a1674698-bcbe-4b91-8232-2b93e87abf30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17215
42410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1721542410
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2905278610
Short name T470
Test name
Test status
Simulation time 8375077997 ps
CPU time 7.99 seconds
Started Apr 30 02:48:25 PM PDT 24
Finished Apr 30 02:48:33 PM PDT 24
Peak memory 204080 kb
Host smart-72620779-293a-4929-b7e3-58e969dca337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29052
78610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2905278610
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.651040546
Short name T951
Test name
Test status
Simulation time 8469058566 ps
CPU time 7.63 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204112 kb
Host smart-ff2cc330-7df0-40c9-87ae-345a6a6144dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65104
0546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.651040546
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.531005900
Short name T1050
Test name
Test status
Simulation time 8391868793 ps
CPU time 8.5 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204016 kb
Host smart-43e86e13-0945-4c5f-9333-e11788fc293b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53100
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.531005900
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4203866553
Short name T676
Test name
Test status
Simulation time 8397323817 ps
CPU time 8.47 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204056 kb
Host smart-df5194b0-1aec-419e-a79d-87250969774f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42038
66553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4203866553
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.3297255966
Short name T963
Test name
Test status
Simulation time 8476766866 ps
CPU time 8.64 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204152 kb
Host smart-654c3802-f63b-48df-a1bb-9b0fa2c9c14f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3297255966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.3297255966
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1851959095
Short name T661
Test name
Test status
Simulation time 8391832257 ps
CPU time 10.49 seconds
Started Apr 30 02:46:46 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 204152 kb
Host smart-cb9096b2-36a2-4f83-ad69-f90b2e238796
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1851959095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1851959095
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.3805394694
Short name T400
Test name
Test status
Simulation time 8384187516 ps
CPU time 10.05 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:47:02 PM PDT 24
Peak memory 204104 kb
Host smart-5420a8dd-7d18-4ff0-bad8-a1ee04a7e3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38053
94694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.3805394694
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1810507320
Short name T1246
Test name
Test status
Simulation time 8386164812 ps
CPU time 8.25 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:46 PM PDT 24
Peak memory 204080 kb
Host smart-34af96ad-ad03-4bf4-a70d-e4bdc52d5fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105
07320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1810507320
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.846222975
Short name T673
Test name
Test status
Simulation time 8380311153 ps
CPU time 8.19 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:46 PM PDT 24
Peak memory 204080 kb
Host smart-6f259055-c520-4929-8696-d93e65376591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84622
2975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.846222975
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1965819414
Short name T1364
Test name
Test status
Simulation time 199767173 ps
CPU time 2.15 seconds
Started Apr 30 02:46:41 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 204364 kb
Host smart-546e2ec8-ef1c-48c1-9ad9-08b9aeac60d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19658
19414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1965819414
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1010807852
Short name T888
Test name
Test status
Simulation time 8412306376 ps
CPU time 8.02 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204108 kb
Host smart-86458b9d-0348-4986-be35-640908fedac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
07852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1010807852
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2827758910
Short name T763
Test name
Test status
Simulation time 8371553179 ps
CPU time 7.47 seconds
Started Apr 30 02:46:42 PM PDT 24
Finished Apr 30 02:46:51 PM PDT 24
Peak memory 204072 kb
Host smart-c2902c9e-1942-46d1-9121-ba616550251d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
58910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2827758910
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.593516292
Short name T2
Test name
Test status
Simulation time 8456316405 ps
CPU time 9.19 seconds
Started Apr 30 02:46:40 PM PDT 24
Finished Apr 30 02:46:50 PM PDT 24
Peak memory 204064 kb
Host smart-5c137699-05ee-4ab5-aa7a-8d6fcb02c899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59351
6292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.593516292
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3635642056
Short name T1340
Test name
Test status
Simulation time 8414526391 ps
CPU time 7.56 seconds
Started Apr 30 02:46:37 PM PDT 24
Finished Apr 30 02:46:45 PM PDT 24
Peak memory 204072 kb
Host smart-a4f04339-734b-450b-8ce2-86d2226d541d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36356
42056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3635642056
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2722596475
Short name T1157
Test name
Test status
Simulation time 8371781547 ps
CPU time 7.6 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:46 PM PDT 24
Peak memory 204104 kb
Host smart-ea20136b-7748-4181-b249-ce76b6fa04b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27225
96475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2722596475
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.741960550
Short name T735
Test name
Test status
Simulation time 8439188881 ps
CPU time 8.43 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204048 kb
Host smart-c241ec1a-0469-4c6e-8d04-2e24a3e6b1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74196
0550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.741960550
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2006360268
Short name T1328
Test name
Test status
Simulation time 8416157509 ps
CPU time 8.33 seconds
Started Apr 30 02:46:40 PM PDT 24
Finished Apr 30 02:46:49 PM PDT 24
Peak memory 204004 kb
Host smart-d87fea91-c333-4b83-b866-4c8b3f0ab933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20063
60268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2006360268
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1739383490
Short name T182
Test name
Test status
Simulation time 8400132482 ps
CPU time 8.14 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204068 kb
Host smart-54af6414-8b1a-4ea1-8b0a-b21cd329fadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17393
83490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1739383490
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3316510882
Short name T377
Test name
Test status
Simulation time 8372219274 ps
CPU time 9.94 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204072 kb
Host smart-89d07bda-6396-4a93-8602-e18f4a4f1397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
10882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3316510882
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4076847653
Short name T693
Test name
Test status
Simulation time 52195962 ps
CPU time 0.66 seconds
Started Apr 30 02:46:43 PM PDT 24
Finished Apr 30 02:46:44 PM PDT 24
Peak memory 203944 kb
Host smart-63feaaf6-202a-4134-86ee-92de3ee8fa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40768
47653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4076847653
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.272773402
Short name T205
Test name
Test status
Simulation time 28672189348 ps
CPU time 53.45 seconds
Started Apr 30 02:46:40 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204424 kb
Host smart-b408ee1a-e1fc-4321-93c8-df59126fb9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27277
3402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.272773402
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.994997755
Short name T985
Test name
Test status
Simulation time 8375282570 ps
CPU time 8.74 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204124 kb
Host smart-a5ec531e-6f34-40cf-9356-6d322fab812f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99499
7755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.994997755
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2191645676
Short name T751
Test name
Test status
Simulation time 8442150383 ps
CPU time 8.48 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204132 kb
Host smart-c396dabe-0f98-48ea-988e-16294276860e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
45676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2191645676
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3654639317
Short name T281
Test name
Test status
Simulation time 8409250387 ps
CPU time 8.73 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204052 kb
Host smart-1605b63a-b093-4eef-ba97-b94355d1e0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36546
39317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3654639317
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1742303745
Short name T55
Test name
Test status
Simulation time 151263975 ps
CPU time 0.99 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:50 PM PDT 24
Peak memory 220356 kb
Host smart-c693155c-93ca-4c38-aba6-153a7e7aea9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1742303745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1742303745
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1345923923
Short name T614
Test name
Test status
Simulation time 8375557691 ps
CPU time 7.98 seconds
Started Apr 30 02:46:38 PM PDT 24
Finished Apr 30 02:46:46 PM PDT 24
Peak memory 204020 kb
Host smart-939d6eca-f170-49a0-9d29-a9b4926d336b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
23923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1345923923
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3936594561
Short name T922
Test name
Test status
Simulation time 8373369574 ps
CPU time 10.43 seconds
Started Apr 30 02:46:41 PM PDT 24
Finished Apr 30 02:46:52 PM PDT 24
Peak memory 204108 kb
Host smart-965ee802-f234-43ca-affe-ec889a8021b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39365
94561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3936594561
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2401251019
Short name T694
Test name
Test status
Simulation time 8437998905 ps
CPU time 8.28 seconds
Started Apr 30 02:46:34 PM PDT 24
Finished Apr 30 02:46:43 PM PDT 24
Peak memory 204116 kb
Host smart-e3219729-6a6a-44a6-857e-018137097b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24012
51019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2401251019
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.313746803
Short name T501
Test name
Test status
Simulation time 8375868259 ps
CPU time 7.6 seconds
Started Apr 30 02:46:39 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204080 kb
Host smart-e69b1b69-0220-48c3-bbd2-0a111630788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31374
6803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.313746803
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2515356698
Short name T647
Test name
Test status
Simulation time 8370334254 ps
CPU time 7.74 seconds
Started Apr 30 02:46:40 PM PDT 24
Finished Apr 30 02:46:48 PM PDT 24
Peak memory 204120 kb
Host smart-9d5aef19-78db-481d-9717-6d3d1100dc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25153
56698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2515356698
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.419494699
Short name T847
Test name
Test status
Simulation time 8461403157 ps
CPU time 7.77 seconds
Started Apr 30 02:48:24 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204084 kb
Host smart-c1e55f11-8ac3-48ec-9023-53cec3dbb5f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=419494699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.419494699
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1469589574
Short name T753
Test name
Test status
Simulation time 8376363656 ps
CPU time 7.92 seconds
Started Apr 30 02:48:25 PM PDT 24
Finished Apr 30 02:48:33 PM PDT 24
Peak memory 204084 kb
Host smart-119c9bcc-a732-4d38-8a30-fe295de2547e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1469589574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1469589574
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.120365671
Short name T942
Test name
Test status
Simulation time 8384876559 ps
CPU time 8 seconds
Started Apr 30 02:48:23 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204112 kb
Host smart-33d5e03d-824d-4af9-8482-865d9cbfa800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12036
5671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.120365671
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3160531713
Short name T318
Test name
Test status
Simulation time 8382557988 ps
CPU time 8.32 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204168 kb
Host smart-f9a857d7-09f5-4e32-9862-71f603952d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
31713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3160531713
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.845281688
Short name T899
Test name
Test status
Simulation time 8399068217 ps
CPU time 7.93 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:28 PM PDT 24
Peak memory 204044 kb
Host smart-3960183b-4af1-4cf5-bedd-22ef8262ba87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84528
1688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.845281688
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3482518615
Short name T793
Test name
Test status
Simulation time 134314660 ps
CPU time 1.47 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:22 PM PDT 24
Peak memory 204192 kb
Host smart-e9d1c7ab-1972-4631-b16c-9f6d09def94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
18615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3482518615
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1137707093
Short name T700
Test name
Test status
Simulation time 8442897299 ps
CPU time 8.16 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204072 kb
Host smart-3e197a4e-5ab6-4908-a036-3c624a319a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
07093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1137707093
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2527518725
Short name T430
Test name
Test status
Simulation time 8363190889 ps
CPU time 7.62 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 203508 kb
Host smart-f6958576-af22-426c-b684-e22a374419cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25275
18725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2527518725
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2282283962
Short name T131
Test name
Test status
Simulation time 8400925852 ps
CPU time 8.03 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204084 kb
Host smart-1786247c-3560-4545-ba99-e75baa773e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822
83962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2282283962
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1180109875
Short name T317
Test name
Test status
Simulation time 8421082226 ps
CPU time 8.91 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204100 kb
Host smart-1c354844-9209-4707-b6db-da0a4bed9ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11801
09875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1180109875
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1287781219
Short name T1195
Test name
Test status
Simulation time 8376661596 ps
CPU time 8.23 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204048 kb
Host smart-97c9465a-c08b-4bb0-a151-664f892d209c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
81219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1287781219
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3383731741
Short name T107
Test name
Test status
Simulation time 8388274478 ps
CPU time 7.4 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 203744 kb
Host smart-e67eb323-0b20-45f8-8477-a5a755e948d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33837
31741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3383731741
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.270871071
Short name T779
Test name
Test status
Simulation time 8435077781 ps
CPU time 8.75 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204128 kb
Host smart-36f11953-4628-4a0c-9de7-df851995ef47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27087
1071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.270871071
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1774538675
Short name T1256
Test name
Test status
Simulation time 8388548823 ps
CPU time 7.83 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204076 kb
Host smart-ddc344bc-6e2f-4431-880f-c9a14c6c1589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
38675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1774538675
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3456102868
Short name T1112
Test name
Test status
Simulation time 8378820946 ps
CPU time 8.36 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 204124 kb
Host smart-d1452848-9830-4865-8d2c-ab540da373a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34561
02868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3456102868
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2612830096
Short name T3
Test name
Test status
Simulation time 8372478855 ps
CPU time 8.76 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204140 kb
Host smart-b17b78bf-0e35-49c7-a9a0-d070821d1512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
30096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2612830096
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2816344443
Short name T959
Test name
Test status
Simulation time 63894189 ps
CPU time 0.68 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:22 PM PDT 24
Peak memory 204004 kb
Host smart-d97c67e0-4ff9-457a-9ee3-d3f9043e4f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163
44443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2816344443
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3069286476
Short name T1271
Test name
Test status
Simulation time 22266019348 ps
CPU time 42.66 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:49:02 PM PDT 24
Peak memory 204576 kb
Host smart-f5aa85cd-e9a3-4736-a5d0-86442ff9c256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30692
86476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3069286476
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1926774759
Short name T1314
Test name
Test status
Simulation time 8416640861 ps
CPU time 9.21 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204068 kb
Host smart-e1c7b112-386f-485a-a512-1bdec5e2087b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19267
74759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1926774759
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3332183753
Short name T509
Test name
Test status
Simulation time 8456402081 ps
CPU time 7.96 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 204104 kb
Host smart-75630e11-6db1-486b-a894-440696d29a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
83753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3332183753
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.4118487218
Short name T618
Test name
Test status
Simulation time 8405303775 ps
CPU time 10.07 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204072 kb
Host smart-818378a9-8d8b-439f-bf61-cbd8c0e724bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41184
87218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.4118487218
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2379656494
Short name T527
Test name
Test status
Simulation time 8375837998 ps
CPU time 8.65 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204012 kb
Host smart-125533a4-5dca-4319-a285-55b3597d2509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
56494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2379656494
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2320270904
Short name T1196
Test name
Test status
Simulation time 8371206512 ps
CPU time 7.45 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204076 kb
Host smart-af6474b8-07b7-4bb5-a9d1-24b7404142bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
70904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2320270904
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2071739212
Short name T1136
Test name
Test status
Simulation time 8430750133 ps
CPU time 8.86 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204112 kb
Host smart-2aaa9036-1118-4206-b511-edb40349aa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717
39212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2071739212
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2484834755
Short name T957
Test name
Test status
Simulation time 8385585457 ps
CPU time 7.73 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204112 kb
Host smart-c5201bb4-6cca-4d95-b890-bace7b9ed956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
34755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2484834755
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2034663852
Short name T483
Test name
Test status
Simulation time 8408753069 ps
CPU time 8.16 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204076 kb
Host smart-e943c01e-2818-4e60-be24-5c193259c12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
63852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2034663852
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.863726712
Short name T569
Test name
Test status
Simulation time 8466195578 ps
CPU time 7.6 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204124 kb
Host smart-ffd8650d-a1b9-40de-9269-732355f814e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=863726712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.863726712
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.324141447
Short name T477
Test name
Test status
Simulation time 8375340253 ps
CPU time 7.54 seconds
Started Apr 30 02:48:27 PM PDT 24
Finished Apr 30 02:48:35 PM PDT 24
Peak memory 204132 kb
Host smart-bc922791-ca32-4246-bd09-eebe4237d10d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=324141447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.324141447
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3696712923
Short name T1047
Test name
Test status
Simulation time 8439178617 ps
CPU time 10.01 seconds
Started Apr 30 02:48:27 PM PDT 24
Finished Apr 30 02:48:38 PM PDT 24
Peak memory 204116 kb
Host smart-d7d3cc58-5915-44a1-aba4-a2f690dcb785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36967
12923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3696712923
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1113490713
Short name T1235
Test name
Test status
Simulation time 8373530058 ps
CPU time 7.86 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:29 PM PDT 24
Peak memory 204120 kb
Host smart-dc37084e-d917-4f4b-9cba-6348a1eb5593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
90713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1113490713
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.193332440
Short name T429
Test name
Test status
Simulation time 8382464069 ps
CPU time 7.43 seconds
Started Apr 30 02:48:26 PM PDT 24
Finished Apr 30 02:48:35 PM PDT 24
Peak memory 204080 kb
Host smart-adab8870-945c-41e6-9311-811175d9314a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19333
2440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.193332440
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1974477462
Short name T976
Test name
Test status
Simulation time 64743616 ps
CPU time 1.66 seconds
Started Apr 30 02:48:24 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204156 kb
Host smart-93dab0ac-b009-4b96-83f9-52e2c6263098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19744
77462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1974477462
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1735061900
Short name T739
Test name
Test status
Simulation time 8416803763 ps
CPU time 7.93 seconds
Started Apr 30 02:48:27 PM PDT 24
Finished Apr 30 02:48:35 PM PDT 24
Peak memory 204116 kb
Host smart-879e379b-361d-46df-a298-0ba1ad7f1ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17350
61900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1735061900
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.137713511
Short name T183
Test name
Test status
Simulation time 8378558984 ps
CPU time 7.46 seconds
Started Apr 30 02:48:23 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204124 kb
Host smart-812a5543-2e0b-4f3e-8cf3-22e05acb82ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13771
3511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.137713511
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.16817220
Short name T880
Test name
Test status
Simulation time 8443250660 ps
CPU time 7.62 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204044 kb
Host smart-096f2f31-d50d-4db0-8598-8a407bd5dcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16817
220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.16817220
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3664434515
Short name T741
Test name
Test status
Simulation time 8411642740 ps
CPU time 8.98 seconds
Started Apr 30 02:48:26 PM PDT 24
Finished Apr 30 02:48:36 PM PDT 24
Peak memory 204076 kb
Host smart-5cc32025-bb95-4339-b052-b081f44c2cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36644
34515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3664434515
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.968952214
Short name T1138
Test name
Test status
Simulation time 8383706505 ps
CPU time 7.89 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204096 kb
Host smart-f3a57ef6-f3ac-43e3-b83f-0186d681fcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96895
2214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.968952214
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3642711120
Short name T838
Test name
Test status
Simulation time 8414846247 ps
CPU time 8.13 seconds
Started Apr 30 02:48:23 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204128 kb
Host smart-065f89e4-9dcf-46f7-8667-f5176f2480be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36427
11120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3642711120
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1687640402
Short name T866
Test name
Test status
Simulation time 8401672515 ps
CPU time 7.9 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204120 kb
Host smart-30e15568-4318-4393-81ef-d7f1bb8a3e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16876
40402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1687640402
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1154506116
Short name T1210
Test name
Test status
Simulation time 8378263163 ps
CPU time 8.01 seconds
Started Apr 30 02:48:26 PM PDT 24
Finished Apr 30 02:48:35 PM PDT 24
Peak memory 204132 kb
Host smart-73233ff9-3ffb-4171-a60a-1d68c5b19d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11545
06116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1154506116
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.875048010
Short name T1034
Test name
Test status
Simulation time 40524991 ps
CPU time 0.66 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:24 PM PDT 24
Peak memory 203992 kb
Host smart-04e00b5a-6b40-44b5-a4cf-983fad2fee99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87504
8010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.875048010
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.4087614048
Short name T867
Test name
Test status
Simulation time 23258131885 ps
CPU time 40.52 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204248 kb
Host smart-b30e2420-ef41-46b7-8cdb-108ee41c8010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40876
14048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.4087614048
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.246792316
Short name T380
Test name
Test status
Simulation time 8439361076 ps
CPU time 7.84 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:27 PM PDT 24
Peak memory 204084 kb
Host smart-8de3b5cc-00bf-4222-94bd-c0c6f3fd6ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
2316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.246792316
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2089712305
Short name T912
Test name
Test status
Simulation time 8423107306 ps
CPU time 7.6 seconds
Started Apr 30 02:48:19 PM PDT 24
Finished Apr 30 02:48:28 PM PDT 24
Peak memory 204044 kb
Host smart-d27fe723-3f96-4ca6-afd8-0076884d47c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20897
12305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2089712305
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.3863913358
Short name T86
Test name
Test status
Simulation time 8413440921 ps
CPU time 7.82 seconds
Started Apr 30 02:48:27 PM PDT 24
Finished Apr 30 02:48:36 PM PDT 24
Peak memory 204084 kb
Host smart-927b77d4-dee2-468d-9f8a-5315032657cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38639
13358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.3863913358
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.898542548
Short name T981
Test name
Test status
Simulation time 8376981480 ps
CPU time 8.33 seconds
Started Apr 30 02:48:18 PM PDT 24
Finished Apr 30 02:48:28 PM PDT 24
Peak memory 204080 kb
Host smart-ddfccc57-5747-4e4c-b9d9-39856a872968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89854
2548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.898542548
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3190761330
Short name T22
Test name
Test status
Simulation time 8379474477 ps
CPU time 8.34 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204116 kb
Host smart-c518514d-682b-48c6-9f3c-5cbc61d68f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31907
61330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3190761330
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3241363100
Short name T83
Test name
Test status
Simulation time 8463983957 ps
CPU time 8.31 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204048 kb
Host smart-f4c49cc7-fc63-41c6-9fdd-6a92ef7e735b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32413
63100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3241363100
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1419545958
Short name T1126
Test name
Test status
Simulation time 8423186859 ps
CPU time 7.41 seconds
Started Apr 30 02:48:21 PM PDT 24
Finished Apr 30 02:48:31 PM PDT 24
Peak memory 204104 kb
Host smart-24bd8d9b-c747-4d5c-aa05-a08928c66cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14195
45958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1419545958
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.898479867
Short name T777
Test name
Test status
Simulation time 8388522848 ps
CPU time 7.93 seconds
Started Apr 30 02:48:20 PM PDT 24
Finished Apr 30 02:48:30 PM PDT 24
Peak memory 204112 kb
Host smart-0d06a3d1-c2e6-431c-a474-bf25c09045e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89847
9867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.898479867
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.1682444002
Short name T1068
Test name
Test status
Simulation time 8513727516 ps
CPU time 8.83 seconds
Started Apr 30 02:48:23 PM PDT 24
Finished Apr 30 02:48:33 PM PDT 24
Peak memory 204056 kb
Host smart-6578fa7d-dc37-4f8a-8bcd-29062b0c36fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1682444002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.1682444002
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3136828470
Short name T1144
Test name
Test status
Simulation time 8409809835 ps
CPU time 7.6 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204144 kb
Host smart-a57c3220-aa4e-4278-883f-7a1167edecc4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3136828470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3136828470
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.1131630076
Short name T279
Test name
Test status
Simulation time 8469865250 ps
CPU time 7.58 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204132 kb
Host smart-84cbafc4-d18e-442d-8a01-d7fa80c82003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11316
30076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.1131630076
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1555252498
Short name T219
Test name
Test status
Simulation time 8372154811 ps
CPU time 7.85 seconds
Started Apr 30 02:48:28 PM PDT 24
Finished Apr 30 02:48:36 PM PDT 24
Peak memory 204056 kb
Host smart-bf4db258-9494-4e16-9b03-4d41153e9147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15552
52498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1555252498
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.2887706945
Short name T696
Test name
Test status
Simulation time 8377319407 ps
CPU time 9.46 seconds
Started Apr 30 02:48:28 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204108 kb
Host smart-b14c53a4-d02b-42f1-b4c5-53e7b20f5d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28877
06945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2887706945
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1988983322
Short name T325
Test name
Test status
Simulation time 152893425 ps
CPU time 1.63 seconds
Started Apr 30 02:48:24 PM PDT 24
Finished Apr 30 02:48:26 PM PDT 24
Peak memory 204184 kb
Host smart-3b38c44d-d4bc-4e82-aa53-cb72b719cc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19889
83322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1988983322
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.122192798
Short name T633
Test name
Test status
Simulation time 8467487056 ps
CPU time 7.61 seconds
Started Apr 30 02:48:24 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204120 kb
Host smart-97c4bed9-46b9-4907-bb43-999d3201dbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12219
2798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.122192798
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2546075410
Short name T5
Test name
Test status
Simulation time 8366099167 ps
CPU time 7.69 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204128 kb
Host smart-ade09db0-2a1b-470d-b899-323d1f104cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25460
75410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2546075410
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.924987279
Short name T1241
Test name
Test status
Simulation time 8425937830 ps
CPU time 7.59 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204128 kb
Host smart-c962a580-caa7-493b-805f-4059ae56e2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92498
7279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.924987279
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2923485702
Short name T1331
Test name
Test status
Simulation time 8420349197 ps
CPU time 7.73 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204132 kb
Host smart-d46d386a-9b78-4846-a6ec-8b4a9a4698d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29234
85702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2923485702
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1337634904
Short name T871
Test name
Test status
Simulation time 8380032317 ps
CPU time 7.72 seconds
Started Apr 30 02:48:23 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204108 kb
Host smart-740d5c12-6103-4ab7-8625-e54145daccd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
34904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1337634904
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3230703220
Short name T882
Test name
Test status
Simulation time 8426246602 ps
CPU time 8.98 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204120 kb
Host smart-4593feff-5482-4b14-b8e7-9ab85e0bde05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32307
03220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3230703220
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2543835121
Short name T311
Test name
Test status
Simulation time 8396404587 ps
CPU time 7.28 seconds
Started Apr 30 02:48:34 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204120 kb
Host smart-8a7c1724-c22f-4154-82fc-867f75dfca7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
35121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2543835121
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1197835122
Short name T594
Test name
Test status
Simulation time 8419128608 ps
CPU time 7.86 seconds
Started Apr 30 02:48:25 PM PDT 24
Finished Apr 30 02:48:33 PM PDT 24
Peak memory 204064 kb
Host smart-07756cd9-8317-4c2a-9af8-269587ee3077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11978
35122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1197835122
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1941400812
Short name T783
Test name
Test status
Simulation time 8411952141 ps
CPU time 9.32 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204132 kb
Host smart-1b192a20-a112-4658-ad33-180b0498d659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
00812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1941400812
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1798724758
Short name T1232
Test name
Test status
Simulation time 8376081983 ps
CPU time 8.26 seconds
Started Apr 30 02:48:34 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204132 kb
Host smart-890ae9d5-fef5-4336-8546-723f1929ca1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17987
24758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1798724758
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3657959757
Short name T1358
Test name
Test status
Simulation time 52350867 ps
CPU time 0.65 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204016 kb
Host smart-7e7acb58-447b-48d7-8e24-eded48ad7a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36579
59757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3657959757
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3544225928
Short name T356
Test name
Test status
Simulation time 8380099834 ps
CPU time 8.97 seconds
Started Apr 30 02:48:29 PM PDT 24
Finished Apr 30 02:48:38 PM PDT 24
Peak memory 204048 kb
Host smart-6bd92374-83b5-4349-92d8-9513cd68d677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35442
25928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3544225928
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.4166940014
Short name T632
Test name
Test status
Simulation time 8449929672 ps
CPU time 9.82 seconds
Started Apr 30 02:48:28 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204056 kb
Host smart-ac0423a7-1cf0-4146-be34-ef0cb2534887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41669
40014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.4166940014
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3310256073
Short name T737
Test name
Test status
Simulation time 8387731658 ps
CPU time 8.03 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204132 kb
Host smart-66a54449-0c88-478e-a91e-13aa2c9aabd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
56073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3310256073
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3312536044
Short name T333
Test name
Test status
Simulation time 8423197751 ps
CPU time 8.14 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204120 kb
Host smart-ad25fdee-f4aa-45e4-ac2a-1af2e86599f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
36044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3312536044
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2519636627
Short name T74
Test name
Test status
Simulation time 8362987045 ps
CPU time 7.95 seconds
Started Apr 30 02:48:26 PM PDT 24
Finished Apr 30 02:48:34 PM PDT 24
Peak memory 204076 kb
Host smart-b2961f8e-bd66-4e2f-b3a8-8d109bdc14c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
36627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2519636627
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2603364880
Short name T168
Test name
Test status
Simulation time 8447526137 ps
CPU time 8.22 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204108 kb
Host smart-06d177ad-f32d-42d9-962b-26adb1d399e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26033
64880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2603364880
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2703432135
Short name T970
Test name
Test status
Simulation time 8386025995 ps
CPU time 8.62 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204120 kb
Host smart-4158c51e-75ba-4f6c-b710-bf905356790a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
32135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2703432135
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2968007279
Short name T447
Test name
Test status
Simulation time 8388253598 ps
CPU time 8.44 seconds
Started Apr 30 02:48:28 PM PDT 24
Finished Apr 30 02:48:37 PM PDT 24
Peak memory 204104 kb
Host smart-9c903044-357f-4324-a1d4-a416e0678481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29680
07279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2968007279
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1498131714
Short name T486
Test name
Test status
Simulation time 8469973017 ps
CPU time 9.92 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204124 kb
Host smart-ce1fe690-05c5-4576-bbf1-210642b07edb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1498131714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1498131714
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.1920211544
Short name T711
Test name
Test status
Simulation time 8378685625 ps
CPU time 7.65 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204088 kb
Host smart-ab0f6eb5-68d5-4035-8b4b-8c669c8c1bcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1920211544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.1920211544
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.923032610
Short name T1228
Test name
Test status
Simulation time 8392725677 ps
CPU time 8.88 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204136 kb
Host smart-1bf12ef3-f990-41ee-9569-31c89edfbf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92303
2610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.923032610
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1110550593
Short name T1015
Test name
Test status
Simulation time 8378090899 ps
CPU time 8.73 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204144 kb
Host smart-9a6d0cd2-f1e7-43aa-a492-3fd0aa536264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11105
50593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1110550593
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.1276402431
Short name T903
Test name
Test status
Simulation time 8376964096 ps
CPU time 8.18 seconds
Started Apr 30 02:48:22 PM PDT 24
Finished Apr 30 02:48:32 PM PDT 24
Peak memory 204044 kb
Host smart-b3cad01c-3311-443d-8818-9bb15d02ca5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12764
02431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1276402431
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2538329651
Short name T1349
Test name
Test status
Simulation time 65018040 ps
CPU time 1.47 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:36 PM PDT 24
Peak memory 204216 kb
Host smart-6c17c0b9-c7d9-4175-85ec-3eec9e298b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25383
29651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2538329651
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3448189854
Short name T132
Test name
Test status
Simulation time 8393747943 ps
CPU time 8.43 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204112 kb
Host smart-4d9121cf-857c-4ba1-860c-5d939031baf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34481
89854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3448189854
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.120845593
Short name T1116
Test name
Test status
Simulation time 8382042221 ps
CPU time 7.76 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204148 kb
Host smart-89a929cd-32f2-41b8-97b9-3771ca8018b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12084
5593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.120845593
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1581031940
Short name T1284
Test name
Test status
Simulation time 8438383577 ps
CPU time 7.77 seconds
Started Apr 30 02:48:34 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204128 kb
Host smart-1cb128f8-19a3-4c5c-8bc4-8b830bb49a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
31940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1581031940
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2729083870
Short name T420
Test name
Test status
Simulation time 8409019135 ps
CPU time 7.75 seconds
Started Apr 30 02:48:29 PM PDT 24
Finished Apr 30 02:48:37 PM PDT 24
Peak memory 204044 kb
Host smart-4a481723-05a6-434e-a072-29585c492ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27290
83870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2729083870
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.581493033
Short name T1159
Test name
Test status
Simulation time 8370469519 ps
CPU time 7.9 seconds
Started Apr 30 02:48:42 PM PDT 24
Finished Apr 30 02:48:51 PM PDT 24
Peak memory 204120 kb
Host smart-29042a3d-71ec-44e4-b82d-75ce457582e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58149
3033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.581493033
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.377740340
Short name T115
Test name
Test status
Simulation time 8397985315 ps
CPU time 7.41 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204116 kb
Host smart-d7fa967b-e7d6-429e-a1bb-7169d4e5d09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37774
0340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.377740340
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1510621971
Short name T272
Test name
Test status
Simulation time 8396548223 ps
CPU time 10.03 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204064 kb
Host smart-1602ae96-c169-4f50-9526-95c407d99dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15106
21971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1510621971
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4089600639
Short name T1168
Test name
Test status
Simulation time 8372859482 ps
CPU time 9.51 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204120 kb
Host smart-8689bae5-19c1-4c2d-91b4-f9cac0a9923a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
00639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4089600639
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2180009655
Short name T924
Test name
Test status
Simulation time 8386205964 ps
CPU time 8.31 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204100 kb
Host smart-975f43a5-dad1-4ad3-bada-65b63c4bda59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21800
09655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2180009655
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.491756553
Short name T1018
Test name
Test status
Simulation time 8374383304 ps
CPU time 8.83 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204056 kb
Host smart-e85db386-c49d-447e-af85-7443945bb808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49175
6553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.491756553
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.4001141280
Short name T599
Test name
Test status
Simulation time 75374935 ps
CPU time 0.72 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:34 PM PDT 24
Peak memory 203952 kb
Host smart-12868bb5-c242-4e83-86c8-b3514c168f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
41280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.4001141280
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3842630259
Short name T823
Test name
Test status
Simulation time 25473258541 ps
CPU time 49.54 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 204364 kb
Host smart-9c8c4717-d5f1-42cc-b4eb-6140532b017f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38426
30259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3842630259
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.315284632
Short name T330
Test name
Test status
Simulation time 8408075793 ps
CPU time 7.9 seconds
Started Apr 30 02:48:34 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204136 kb
Host smart-3f5afbdb-fe9b-4c8b-9ba3-f7050dcc4781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528
4632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.315284632
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3010953450
Short name T520
Test name
Test status
Simulation time 8430111266 ps
CPU time 8.68 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204088 kb
Host smart-8a2b603f-1534-485b-bd05-e4255ef057b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30109
53450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3010953450
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2931839151
Short name T740
Test name
Test status
Simulation time 8407491703 ps
CPU time 10.34 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204140 kb
Host smart-7f0eb381-afda-46bc-aff3-32d06013eeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
39151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2931839151
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.219392569
Short name T858
Test name
Test status
Simulation time 8405427649 ps
CPU time 8.01 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204144 kb
Host smart-d2e7bbd3-ae0f-42d7-b476-7a55d2a9c4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21939
2569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.219392569
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2580179493
Short name T396
Test name
Test status
Simulation time 8374678800 ps
CPU time 8.14 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204096 kb
Host smart-d8dda9e5-2c35-4e53-a480-870063409219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25801
79493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2580179493
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.4206970085
Short name T794
Test name
Test status
Simulation time 8422948614 ps
CPU time 9.94 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204108 kb
Host smart-5f7cd13d-f153-498d-a4c7-b6be34f8ab33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42069
70085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.4206970085
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.548230569
Short name T572
Test name
Test status
Simulation time 8399212518 ps
CPU time 9.88 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204104 kb
Host smart-d83c888c-38ac-4519-b1c9-52b4dcb9f483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54823
0569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.548230569
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3481113559
Short name T757
Test name
Test status
Simulation time 8398697034 ps
CPU time 9.58 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204120 kb
Host smart-ef999ccf-407b-4cdf-866f-50bf82bd8bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34811
13559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3481113559
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.3592951801
Short name T1342
Test name
Test status
Simulation time 8470722695 ps
CPU time 8.51 seconds
Started Apr 30 02:48:41 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204056 kb
Host smart-5c1fc47a-3f4e-4c18-9d77-af71ac14ab95
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3592951801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.3592951801
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3025841700
Short name T319
Test name
Test status
Simulation time 8379203926 ps
CPU time 8.82 seconds
Started Apr 30 02:48:38 PM PDT 24
Finished Apr 30 02:48:48 PM PDT 24
Peak memory 204128 kb
Host smart-1250f39d-94c2-4977-afbe-7e366181d6cc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3025841700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3025841700
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.59712133
Short name T1025
Test name
Test status
Simulation time 8443213839 ps
CPU time 8.32 seconds
Started Apr 30 02:48:38 PM PDT 24
Finished Apr 30 02:48:47 PM PDT 24
Peak memory 204140 kb
Host smart-b0a74012-ba71-451c-8ee6-58ed82cbf709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59712
133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.59712133
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.211910530
Short name T1033
Test name
Test status
Simulation time 8385003172 ps
CPU time 7.61 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204084 kb
Host smart-992f701c-7fca-4f92-bf26-1d744af1ab05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.211910530
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.3436387337
Short name T785
Test name
Test status
Simulation time 8383059670 ps
CPU time 8.97 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204148 kb
Host smart-80b664c8-2288-4b9c-aead-ce7d736bee8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
87337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3436387337
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2069678737
Short name T301
Test name
Test status
Simulation time 193885373 ps
CPU time 1.83 seconds
Started Apr 30 02:48:35 PM PDT 24
Finished Apr 30 02:48:37 PM PDT 24
Peak memory 204180 kb
Host smart-88f1e746-483e-4e12-a45f-40763c7fde8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20696
78737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2069678737
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1571326761
Short name T667
Test name
Test status
Simulation time 8442826794 ps
CPU time 8.78 seconds
Started Apr 30 02:48:38 PM PDT 24
Finished Apr 30 02:48:48 PM PDT 24
Peak memory 204000 kb
Host smart-707bedda-c7d1-4468-be19-0668250aae23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15713
26761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1571326761
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.754854068
Short name T1226
Test name
Test status
Simulation time 8364452297 ps
CPU time 7.66 seconds
Started Apr 30 02:48:39 PM PDT 24
Finished Apr 30 02:48:47 PM PDT 24
Peak memory 204148 kb
Host smart-058fe617-3332-45d1-8d7e-017b875451bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75485
4068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.754854068
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1638368143
Short name T896
Test name
Test status
Simulation time 8446892665 ps
CPU time 8.5 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204144 kb
Host smart-50b05b01-ae44-4bc5-b01f-26672e7a1d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
68143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1638368143
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2435687621
Short name T505
Test name
Test status
Simulation time 8414246698 ps
CPU time 8.21 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204064 kb
Host smart-922046d5-6f65-4fe2-9d02-c50cff4628c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24356
87621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2435687621
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1527045226
Short name T597
Test name
Test status
Simulation time 8403661363 ps
CPU time 8.57 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204140 kb
Host smart-75e329ea-e83b-46e7-a43b-ab0b752157db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15270
45226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1527045226
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1387203549
Short name T837
Test name
Test status
Simulation time 8470682256 ps
CPU time 8.06 seconds
Started Apr 30 02:48:35 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204056 kb
Host smart-40963062-641a-4911-bb29-254f6fc23249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13872
03549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1387203549
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1552711411
Short name T307
Test name
Test status
Simulation time 8413159493 ps
CPU time 9.55 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204124 kb
Host smart-05f80101-0b7c-4eae-93e0-09723c05cefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15527
11411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1552711411
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3053462777
Short name T544
Test name
Test status
Simulation time 8400319589 ps
CPU time 8.07 seconds
Started Apr 30 02:48:34 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204124 kb
Host smart-fac69595-2956-486e-b650-999664f0bbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534
62777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3053462777
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3091444293
Short name T82
Test name
Test status
Simulation time 8374291977 ps
CPU time 7.81 seconds
Started Apr 30 02:48:35 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204100 kb
Host smart-ba02fcc0-a779-4cc7-91c7-4837a64b2824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30914
44293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3091444293
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3314355870
Short name T804
Test name
Test status
Simulation time 8365542950 ps
CPU time 9.19 seconds
Started Apr 30 02:48:34 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204048 kb
Host smart-866d71fd-ffb7-4491-9495-7ba790b8c3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33143
55870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3314355870
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2646120262
Short name T37
Test name
Test status
Simulation time 41990944 ps
CPU time 0.66 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:34 PM PDT 24
Peak memory 204000 kb
Host smart-f92bbd4d-dbcf-4a95-97de-d8ec7b886a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26461
20262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2646120262
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2672943236
Short name T680
Test name
Test status
Simulation time 24717855395 ps
CPU time 50.16 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204424 kb
Host smart-4151915b-ec96-4390-a24c-6a39ab33dcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
43236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2672943236
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1948751962
Short name T778
Test name
Test status
Simulation time 8390425099 ps
CPU time 8.56 seconds
Started Apr 30 02:48:35 PM PDT 24
Finished Apr 30 02:48:44 PM PDT 24
Peak memory 204092 kb
Host smart-3ef3971d-f383-40f1-aa7e-8d0a3c3b4dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19487
51962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1948751962
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1652411864
Short name T698
Test name
Test status
Simulation time 8506175828 ps
CPU time 8.68 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204080 kb
Host smart-7c9ab039-bca3-4190-9b69-a80f100347df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16524
11864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1652411864
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.3199909828
Short name T308
Test name
Test status
Simulation time 8409655407 ps
CPU time 7.99 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 204072 kb
Host smart-c2e8f7fc-cbcc-447c-ad09-1866d27bc4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
09828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.3199909828
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2259616169
Short name T173
Test name
Test status
Simulation time 8374933916 ps
CPU time 8.23 seconds
Started Apr 30 02:48:33 PM PDT 24
Finished Apr 30 02:48:43 PM PDT 24
Peak memory 204104 kb
Host smart-f850a69a-e7e1-4857-99d0-e7b0b1809fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22596
16169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2259616169
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1510034937
Short name T1063
Test name
Test status
Simulation time 8374488981 ps
CPU time 8.89 seconds
Started Apr 30 02:48:30 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204092 kb
Host smart-3f0a2981-180b-45c0-9df3-7891e7765404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15100
34937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1510034937
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1545577232
Short name T977
Test name
Test status
Simulation time 8427315107 ps
CPU time 8.65 seconds
Started Apr 30 02:48:32 PM PDT 24
Finished Apr 30 02:48:42 PM PDT 24
Peak memory 204012 kb
Host smart-690fe058-8275-4afd-bf2b-921e085b8d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
77232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1545577232
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2536963882
Short name T994
Test name
Test status
Simulation time 8475355829 ps
CPU time 7.69 seconds
Started Apr 30 02:48:31 PM PDT 24
Finished Apr 30 02:48:39 PM PDT 24
Peak memory 204084 kb
Host smart-79ba94fd-9f2a-41d7-97d4-eeaf6679abc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369
63882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2536963882
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3803371261
Short name T953
Test name
Test status
Simulation time 8400516856 ps
CPU time 7.56 seconds
Started Apr 30 02:48:29 PM PDT 24
Finished Apr 30 02:48:38 PM PDT 24
Peak memory 203988 kb
Host smart-574af76c-7490-4c3e-b24f-83b2754e37cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38033
71261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3803371261
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.3233636943
Short name T480
Test name
Test status
Simulation time 8468368458 ps
CPU time 9.14 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:56 PM PDT 24
Peak memory 204060 kb
Host smart-e9566356-2983-4aa3-8f11-9be11b0a9782
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3233636943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.3233636943
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.967309630
Short name T1121
Test name
Test status
Simulation time 8377207632 ps
CPU time 8.29 seconds
Started Apr 30 02:48:52 PM PDT 24
Finished Apr 30 02:49:01 PM PDT 24
Peak memory 204108 kb
Host smart-00c78402-e9fa-4829-8907-49d66ea15eb3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=967309630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.967309630
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.371159331
Short name T514
Test name
Test status
Simulation time 8452527206 ps
CPU time 9.76 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:51 PM PDT 24
Peak memory 204112 kb
Host smart-90d59422-17ea-44df-962d-0d41c7ebad7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
9331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.371159331
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3146289281
Short name T1264
Test name
Test status
Simulation time 8438055010 ps
CPU time 8.27 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:53 PM PDT 24
Peak memory 204084 kb
Host smart-dd960430-4e61-40a9-891b-b8feb159ded7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31462
89281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3146289281
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.138724462
Short name T1187
Test name
Test status
Simulation time 8380461068 ps
CPU time 7.93 seconds
Started Apr 30 02:48:51 PM PDT 24
Finished Apr 30 02:48:59 PM PDT 24
Peak memory 204092 kb
Host smart-28a05f52-5db2-4ce5-8e9a-8492dca78c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13872
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.138724462
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3669195294
Short name T1031
Test name
Test status
Simulation time 87341299 ps
CPU time 1.21 seconds
Started Apr 30 02:48:38 PM PDT 24
Finished Apr 30 02:48:40 PM PDT 24
Peak memory 204200 kb
Host smart-9353f86c-b0b2-45db-a848-d776786ac719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36691
95294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3669195294
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1063707460
Short name T543
Test name
Test status
Simulation time 8387543838 ps
CPU time 9.8 seconds
Started Apr 30 02:48:49 PM PDT 24
Finished Apr 30 02:48:59 PM PDT 24
Peak memory 204068 kb
Host smart-300d46b9-089c-45f8-a056-7796d5e720d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10637
07460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1063707460
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4123741348
Short name T195
Test name
Test status
Simulation time 8366109059 ps
CPU time 8.09 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:55 PM PDT 24
Peak memory 204120 kb
Host smart-f7ef6436-6d33-4991-9f54-9ef000ef6ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237
41348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4123741348
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1323975287
Short name T1205
Test name
Test status
Simulation time 8460636812 ps
CPU time 8.11 seconds
Started Apr 30 02:48:41 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204112 kb
Host smart-bced1d05-0904-4940-810b-63d70b69a87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13239
75287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1323975287
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4198036267
Short name T326
Test name
Test status
Simulation time 8463578414 ps
CPU time 7.9 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:49 PM PDT 24
Peak memory 204116 kb
Host smart-95a5b389-1f4b-45ac-86b9-d744a0f73969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41980
36267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4198036267
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2915937292
Short name T746
Test name
Test status
Simulation time 8396996603 ps
CPU time 7.86 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:49 PM PDT 24
Peak memory 204080 kb
Host smart-fa25bd16-9bbd-41ab-8fb9-d89fcb3a7e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29159
37292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2915937292
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.602728099
Short name T109
Test name
Test status
Simulation time 8431282568 ps
CPU time 10.84 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204072 kb
Host smart-67f61f8b-4b48-42f8-80d7-7a6092999ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60272
8099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.602728099
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1739504703
Short name T1085
Test name
Test status
Simulation time 8400680378 ps
CPU time 7.7 seconds
Started Apr 30 02:48:43 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204084 kb
Host smart-9febde47-a494-471a-989d-6d5abb08f2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17395
04703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1739504703
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3325464384
Short name T536
Test name
Test status
Simulation time 8419188938 ps
CPU time 9.06 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:53 PM PDT 24
Peak memory 204076 kb
Host smart-cc3af281-3896-49e2-80e9-6366fb4060d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
64384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3325464384
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1271099501
Short name T180
Test name
Test status
Simulation time 8405616317 ps
CPU time 9.96 seconds
Started Apr 30 02:48:39 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204060 kb
Host smart-88216579-85a7-41fc-8f83-9f15e4826bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12710
99501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1271099501
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.855032456
Short name T754
Test name
Test status
Simulation time 8376939943 ps
CPU time 8.54 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204048 kb
Host smart-2c69d31a-e3d7-4038-93a7-4d9bbad5abda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85503
2456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.855032456
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1082080678
Short name T1268
Test name
Test status
Simulation time 47801874 ps
CPU time 0.67 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:41 PM PDT 24
Peak memory 203944 kb
Host smart-bafb2cf9-db40-4b37-ac26-c8d0068a9010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
80678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1082080678
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1452827607
Short name T223
Test name
Test status
Simulation time 19371167935 ps
CPU time 36.78 seconds
Started Apr 30 02:48:39 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204364 kb
Host smart-ba2dc472-39a4-4061-b0aa-1e3f34d4dc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
27607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1452827607
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.553084009
Short name T545
Test name
Test status
Simulation time 8416107323 ps
CPU time 8.87 seconds
Started Apr 30 02:48:52 PM PDT 24
Finished Apr 30 02:49:01 PM PDT 24
Peak memory 204076 kb
Host smart-cf24a9ac-73bb-4621-9a40-1982f5c49500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55308
4009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.553084009
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.321907243
Short name T827
Test name
Test status
Simulation time 8446210687 ps
CPU time 8.42 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:57 PM PDT 24
Peak memory 204044 kb
Host smart-f6f252bc-57f4-4ac1-9a93-2867c7932b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.321907243
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2683031008
Short name T1141
Test name
Test status
Simulation time 8392766480 ps
CPU time 10.14 seconds
Started Apr 30 02:48:49 PM PDT 24
Finished Apr 30 02:49:00 PM PDT 24
Peak memory 204056 kb
Host smart-69bee5d5-9921-414e-907c-f14780e5677e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830
31008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2683031008
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.756422917
Short name T1272
Test name
Test status
Simulation time 8374406339 ps
CPU time 8.73 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:48:49 PM PDT 24
Peak memory 204064 kb
Host smart-b14055e5-d008-4eee-8c7e-da02e1de03f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75642
2917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.756422917
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1619388229
Short name T316
Test name
Test status
Simulation time 8365955868 ps
CPU time 7.93 seconds
Started Apr 30 02:48:41 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204104 kb
Host smart-dbb5a9a0-8530-47bf-aaaa-56162c1d2fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
88229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1619388229
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3414891863
Short name T983
Test name
Test status
Simulation time 8491144887 ps
CPU time 8.82 seconds
Started Apr 30 02:48:49 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204032 kb
Host smart-86448c0b-a4af-4f8a-bef1-1201aedbbfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
91863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3414891863
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3777712346
Short name T313
Test name
Test status
Simulation time 8414191193 ps
CPU time 7.75 seconds
Started Apr 30 02:48:41 PM PDT 24
Finished Apr 30 02:48:49 PM PDT 24
Peak memory 204104 kb
Host smart-9b0ea4bc-c689-4b6e-b49d-ea7d09674719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
12346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3777712346
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3346955264
Short name T1178
Test name
Test status
Simulation time 8378225295 ps
CPU time 8.7 seconds
Started Apr 30 02:48:51 PM PDT 24
Finished Apr 30 02:49:01 PM PDT 24
Peak memory 204132 kb
Host smart-3b626483-00dd-4cba-ac21-a227b22d38a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33469
55264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3346955264
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3064951463
Short name T323
Test name
Test status
Simulation time 8481264170 ps
CPU time 8.07 seconds
Started Apr 30 02:48:45 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204152 kb
Host smart-a19f2f91-5056-4e50-a91a-1092efcedc26
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3064951463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3064951463
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.3958335083
Short name T1194
Test name
Test status
Simulation time 8376204694 ps
CPU time 8.82 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204116 kb
Host smart-61cb31f7-cc40-4bc9-bad1-2d9483033aa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3958335083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.3958335083
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.4103111363
Short name T989
Test name
Test status
Simulation time 8407570680 ps
CPU time 8.7 seconds
Started Apr 30 02:48:49 PM PDT 24
Finished Apr 30 02:48:59 PM PDT 24
Peak memory 204140 kb
Host smart-25c432e7-e8b9-4dd7-9057-66f33ffd038a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
11363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.4103111363
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1621386307
Short name T645
Test name
Test status
Simulation time 8374762571 ps
CPU time 8.04 seconds
Started Apr 30 02:48:41 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204056 kb
Host smart-2372b271-cfb8-4782-8da6-c695151ef2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
86307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1621386307
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.2815190162
Short name T1088
Test name
Test status
Simulation time 8383180217 ps
CPU time 9.21 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204104 kb
Host smart-881dffd1-550e-492c-91c6-66684c3a5416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
90162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2815190162
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1627151097
Short name T1017
Test name
Test status
Simulation time 163694794 ps
CPU time 1.82 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204212 kb
Host smart-cebc097f-49a1-4a2e-822d-7f89b17f1964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
51097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1627151097
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3456800333
Short name T1362
Test name
Test status
Simulation time 8455203031 ps
CPU time 9.3 seconds
Started Apr 30 02:48:54 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204080 kb
Host smart-a749a232-9f8d-41a4-b441-2aca8f5c6242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
00333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3456800333
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2916013671
Short name T822
Test name
Test status
Simulation time 8374612059 ps
CPU time 7.82 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204064 kb
Host smart-8dea4b41-8c95-42eb-ac63-b4b690b51aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
13671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2916013671
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.4072403560
Short name T761
Test name
Test status
Simulation time 8461458286 ps
CPU time 7.68 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204084 kb
Host smart-bd762f98-7efd-4ce0-9f16-6dc8d7cf0d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40724
03560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.4072403560
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3168344594
Short name T1237
Test name
Test status
Simulation time 8443591361 ps
CPU time 9.45 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204060 kb
Host smart-8ec13247-6ca5-4cfd-a957-bf90d3bdd840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31683
44594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3168344594
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.4088372317
Short name T298
Test name
Test status
Simulation time 8376718924 ps
CPU time 8.13 seconds
Started Apr 30 02:48:43 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204076 kb
Host smart-3caf5c36-debb-4fc5-b6dc-54a727f73cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
72317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.4088372317
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1648300316
Short name T15
Test name
Test status
Simulation time 8462402086 ps
CPU time 9.04 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204092 kb
Host smart-a1b4afa6-f0a1-4843-b912-2a1f7425f95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16483
00316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1648300316
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.97599249
Short name T457
Test name
Test status
Simulation time 8378464465 ps
CPU time 10.22 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204004 kb
Host smart-d26112c4-9e48-4156-b062-09397e20dddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97599
249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.97599249
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3937599144
Short name T1191
Test name
Test status
Simulation time 8413401061 ps
CPU time 7.71 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204108 kb
Host smart-6bc2eadb-5fcf-4a89-a9a1-110e25ed2862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375
99144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3937599144
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1017488572
Short name T6
Test name
Test status
Simulation time 8384262961 ps
CPU time 7.93 seconds
Started Apr 30 02:48:51 PM PDT 24
Finished Apr 30 02:49:00 PM PDT 24
Peak memory 204132 kb
Host smart-de9b97f6-930b-4e15-9fca-fcd514622921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
88572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1017488572
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1656973714
Short name T829
Test name
Test status
Simulation time 38183361 ps
CPU time 0.63 seconds
Started Apr 30 02:48:52 PM PDT 24
Finished Apr 30 02:48:53 PM PDT 24
Peak memory 203996 kb
Host smart-c9a56d5d-8e30-41a1-a17a-95d9bd68e7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16569
73714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1656973714
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3820237795
Short name T87
Test name
Test status
Simulation time 22804501421 ps
CPU time 43.35 seconds
Started Apr 30 02:48:40 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204348 kb
Host smart-b342d5ce-be39-4a02-88c7-7b17eb85586e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
37795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3820237795
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2283508276
Short name T431
Test name
Test status
Simulation time 8377580594 ps
CPU time 7.83 seconds
Started Apr 30 02:48:49 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204044 kb
Host smart-970663d2-adc7-4539-b366-66491b940e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22835
08276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2283508276
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2717676778
Short name T929
Test name
Test status
Simulation time 8438841620 ps
CPU time 7.96 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204024 kb
Host smart-cff1c15d-a230-4553-9b93-3315a80974bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
76778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2717676778
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3894058254
Short name T988
Test name
Test status
Simulation time 8415302925 ps
CPU time 9.13 seconds
Started Apr 30 02:48:39 PM PDT 24
Finished Apr 30 02:48:49 PM PDT 24
Peak memory 204124 kb
Host smart-e2e4a45a-8eba-4cbe-b56b-1747140b3769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38940
58254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3894058254
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2539854119
Short name T167
Test name
Test status
Simulation time 8374106478 ps
CPU time 7.98 seconds
Started Apr 30 02:48:45 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204116 kb
Host smart-2d0677a0-573d-4eb2-95f1-ddccf543e379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25398
54119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2539854119
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.186810274
Short name T392
Test name
Test status
Simulation time 8367080545 ps
CPU time 8.31 seconds
Started Apr 30 02:48:42 PM PDT 24
Finished Apr 30 02:48:51 PM PDT 24
Peak memory 204104 kb
Host smart-52e8dc48-06bf-4f8e-bf27-7640dab6a258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681
0274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.186810274
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.952779668
Short name T1308
Test name
Test status
Simulation time 8442817612 ps
CPU time 10.5 seconds
Started Apr 30 02:48:52 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204044 kb
Host smart-bbc7917a-ea19-43ef-a4c6-6c762a1217ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95277
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.952779668
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.757004799
Short name T78
Test name
Test status
Simulation time 8370499679 ps
CPU time 7.7 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204060 kb
Host smart-86222197-2a2b-4951-9524-c4d28f6087be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75700
4799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.757004799
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1864065884
Short name T1259
Test name
Test status
Simulation time 8408412307 ps
CPU time 8.28 seconds
Started Apr 30 02:48:45 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204100 kb
Host smart-bfe74c0a-3b62-46c5-b964-e209c79923d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18640
65884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1864065884
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.143354342
Short name T1359
Test name
Test status
Simulation time 8518673476 ps
CPU time 9.69 seconds
Started Apr 30 02:48:45 PM PDT 24
Finished Apr 30 02:48:56 PM PDT 24
Peak memory 204112 kb
Host smart-00bc0b8e-58a1-4fcf-a9f7-a1ad4a7b24ee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=143354342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.143354342
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.1536402615
Short name T828
Test name
Test status
Simulation time 8380001596 ps
CPU time 8.53 seconds
Started Apr 30 02:48:53 PM PDT 24
Finished Apr 30 02:49:02 PM PDT 24
Peak memory 204140 kb
Host smart-433e2111-d679-4a06-8f54-5c90d2cc7224
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1536402615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.1536402615
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.2334603294
Short name T603
Test name
Test status
Simulation time 8434073554 ps
CPU time 8.35 seconds
Started Apr 30 02:48:54 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204100 kb
Host smart-5d062ea2-019f-495d-8226-ff172d876e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23346
03294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.2334603294
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.82211994
Short name T1000
Test name
Test status
Simulation time 8383202840 ps
CPU time 8.41 seconds
Started Apr 30 02:48:47 PM PDT 24
Finished Apr 30 02:48:56 PM PDT 24
Peak memory 204080 kb
Host smart-123fe21d-caaf-471a-a831-3b2e1b4e2681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82211
994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.82211994
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.296232955
Short name T80
Test name
Test status
Simulation time 8379420992 ps
CPU time 8.45 seconds
Started Apr 30 02:48:45 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204116 kb
Host smart-c6c18f17-f025-40ae-848f-550bd02bdcb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29623
2955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.296232955
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1660034706
Short name T367
Test name
Test status
Simulation time 88026631 ps
CPU time 1.34 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:50 PM PDT 24
Peak memory 204192 kb
Host smart-f02b4984-4f42-4c87-9ca6-caff34452830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16600
34706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1660034706
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1898458641
Short name T144
Test name
Test status
Simulation time 8403606790 ps
CPU time 7.76 seconds
Started Apr 30 02:49:05 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 204084 kb
Host smart-115f9453-a8e5-4e85-a2f6-583f2814fd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18984
58641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1898458641
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2896887694
Short name T1019
Test name
Test status
Simulation time 8376371816 ps
CPU time 7.62 seconds
Started Apr 30 02:48:50 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204140 kb
Host smart-3543d5ad-f81c-4aec-bd27-aa559f7cc381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968
87694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2896887694
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.135988304
Short name T147
Test name
Test status
Simulation time 8433696076 ps
CPU time 8.11 seconds
Started Apr 30 02:49:04 PM PDT 24
Finished Apr 30 02:49:12 PM PDT 24
Peak memory 204132 kb
Host smart-76fb9809-9608-4c1f-a214-8c171d7d9a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13598
8304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.135988304
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1509613552
Short name T288
Test name
Test status
Simulation time 8423949021 ps
CPU time 8.42 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:53 PM PDT 24
Peak memory 204144 kb
Host smart-c9b382c1-3932-4fbb-8927-1e5ad3292228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
13552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1509613552
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3157389436
Short name T267
Test name
Test status
Simulation time 8377930584 ps
CPU time 10.34 seconds
Started Apr 30 02:48:45 PM PDT 24
Finished Apr 30 02:48:56 PM PDT 24
Peak memory 204044 kb
Host smart-aa32fb4d-fc53-4817-a0a1-771d6fbbc191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31573
89436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3157389436
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.866214403
Short name T1114
Test name
Test status
Simulation time 8416507537 ps
CPU time 9.09 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204108 kb
Host smart-49974feb-b684-452c-a058-16f50e867c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86621
4403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.866214403
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2171210258
Short name T772
Test name
Test status
Simulation time 8407296833 ps
CPU time 8.16 seconds
Started Apr 30 02:48:49 PM PDT 24
Finished Apr 30 02:48:58 PM PDT 24
Peak memory 204112 kb
Host smart-8b0e53be-0c73-4549-85f4-06ca23e71d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21712
10258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2171210258
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.186442549
Short name T1240
Test name
Test status
Simulation time 8443432392 ps
CPU time 7.7 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:55 PM PDT 24
Peak memory 204044 kb
Host smart-2d298bdd-c607-4ea0-a893-e3e78a98983e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18644
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.186442549
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4287316510
Short name T174
Test name
Test status
Simulation time 8404438453 ps
CPU time 8.56 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:57 PM PDT 24
Peak memory 204144 kb
Host smart-cc9bb7b9-91eb-4091-ae75-01a64f3b4f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
16510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4287316510
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2673959397
Short name T322
Test name
Test status
Simulation time 8370397724 ps
CPU time 7.89 seconds
Started Apr 30 02:48:47 PM PDT 24
Finished Apr 30 02:48:55 PM PDT 24
Peak memory 204072 kb
Host smart-9f927aea-1eaf-4d9e-afd4-064be02892bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26739
59397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2673959397
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.786490465
Short name T36
Test name
Test status
Simulation time 35082926 ps
CPU time 0.69 seconds
Started Apr 30 02:48:50 PM PDT 24
Finished Apr 30 02:48:51 PM PDT 24
Peak memory 204012 kb
Host smart-eea1098b-75df-4ac5-a8ae-49efa1fab5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78649
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.786490465
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.4153953844
Short name T954
Test name
Test status
Simulation time 18748536265 ps
CPU time 32.86 seconds
Started Apr 30 02:48:53 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204384 kb
Host smart-a4ec60c4-72f5-4791-b242-a0e6a614ae51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41539
53844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.4153953844
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2766291235
Short name T139
Test name
Test status
Simulation time 8389156138 ps
CPU time 8.03 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204124 kb
Host smart-f985f730-cea3-4b19-aae6-4fc33fadffe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27662
91235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2766291235
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2070241787
Short name T1221
Test name
Test status
Simulation time 8401496545 ps
CPU time 7.66 seconds
Started Apr 30 02:48:44 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204040 kb
Host smart-6ae5232e-137b-4282-bcef-eea5cb3dd021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
41787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2070241787
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1808383676
Short name T1290
Test name
Test status
Simulation time 8378001379 ps
CPU time 7.53 seconds
Started Apr 30 02:48:53 PM PDT 24
Finished Apr 30 02:49:01 PM PDT 24
Peak memory 204012 kb
Host smart-492765fc-9e87-49c5-9b77-499535d9760d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18083
83676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1808383676
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3517321964
Short name T1212
Test name
Test status
Simulation time 8367543560 ps
CPU time 7.33 seconds
Started Apr 30 02:48:48 PM PDT 24
Finished Apr 30 02:48:56 PM PDT 24
Peak memory 204124 kb
Host smart-d520acd0-5112-4c3d-b991-967ee40e6f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35173
21964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3517321964
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.270121646
Short name T972
Test name
Test status
Simulation time 8514941506 ps
CPU time 8.41 seconds
Started Apr 30 02:48:46 PM PDT 24
Finished Apr 30 02:48:54 PM PDT 24
Peak memory 204132 kb
Host smart-444ab3fe-389c-4c8c-aa77-de5048515d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27012
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.270121646
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1201498378
Short name T674
Test name
Test status
Simulation time 8412242504 ps
CPU time 9.63 seconds
Started Apr 30 02:48:47 PM PDT 24
Finished Apr 30 02:48:57 PM PDT 24
Peak memory 204072 kb
Host smart-b008dfce-2b24-458a-8208-1d5286e6d56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014
98378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1201498378
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2782022949
Short name T335
Test name
Test status
Simulation time 8397754334 ps
CPU time 8.06 seconds
Started Apr 30 02:48:55 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204056 kb
Host smart-001a1608-de1b-4694-9f48-7dbb2ea5b5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27820
22949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2782022949
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2905506998
Short name T1282
Test name
Test status
Simulation time 8489238246 ps
CPU time 8.73 seconds
Started Apr 30 02:49:06 PM PDT 24
Finished Apr 30 02:49:15 PM PDT 24
Peak memory 204084 kb
Host smart-951d1629-1135-457e-b0ef-bba02f7160cf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2905506998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2905506998
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3186632514
Short name T634
Test name
Test status
Simulation time 8374578436 ps
CPU time 10.12 seconds
Started Apr 30 02:49:01 PM PDT 24
Finished Apr 30 02:49:11 PM PDT 24
Peak memory 204076 kb
Host smart-c0220759-9b7b-4718-a38c-2dec8aa6f49f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3186632514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3186632514
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.4188673677
Short name T314
Test name
Test status
Simulation time 8446814674 ps
CPU time 8.89 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 204144 kb
Host smart-36114132-f806-475d-b055-223c0bf1404d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
73677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.4188673677
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1447760211
Short name T438
Test name
Test status
Simulation time 8378048610 ps
CPU time 9.77 seconds
Started Apr 30 02:49:07 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204052 kb
Host smart-c788d448-156a-4e02-b19f-8057763ffbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14477
60211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1447760211
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.3419311046
Short name T533
Test name
Test status
Simulation time 8385284208 ps
CPU time 8.52 seconds
Started Apr 30 02:48:52 PM PDT 24
Finished Apr 30 02:49:01 PM PDT 24
Peak memory 204084 kb
Host smart-1823b4b2-0c84-46f9-9e7a-293fb111e509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34193
11046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3419311046
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2581426104
Short name T75
Test name
Test status
Simulation time 170507064 ps
CPU time 1.86 seconds
Started Apr 30 02:48:50 PM PDT 24
Finished Apr 30 02:48:52 PM PDT 24
Peak memory 204284 kb
Host smart-a59592c2-5d1e-43b7-8875-18778ac13e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25814
26104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2581426104
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2052391205
Short name T338
Test name
Test status
Simulation time 8413095093 ps
CPU time 9.44 seconds
Started Apr 30 02:49:02 PM PDT 24
Finished Apr 30 02:49:12 PM PDT 24
Peak memory 204028 kb
Host smart-ad6d61b5-16b5-4b9f-a154-fc098c5c9d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
91205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2052391205
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3610842806
Short name T1177
Test name
Test status
Simulation time 8365979430 ps
CPU time 7.51 seconds
Started Apr 30 02:49:03 PM PDT 24
Finished Apr 30 02:49:11 PM PDT 24
Peak memory 204084 kb
Host smart-6abe769f-010f-4850-b743-1c6bf2be74ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108
42806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3610842806
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.398093237
Short name T150
Test name
Test status
Simulation time 8456835581 ps
CPU time 7.91 seconds
Started Apr 30 02:48:57 PM PDT 24
Finished Apr 30 02:49:06 PM PDT 24
Peak memory 204008 kb
Host smart-dc32c05c-895c-4bea-9b1d-828eb783154f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39809
3237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.398093237
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2102707190
Short name T471
Test name
Test status
Simulation time 8444556177 ps
CPU time 10.01 seconds
Started Apr 30 02:48:53 PM PDT 24
Finished Apr 30 02:49:04 PM PDT 24
Peak memory 204016 kb
Host smart-5183c25e-7903-49f7-805e-fd461f5f3545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027
07190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2102707190
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3864054938
Short name T302
Test name
Test status
Simulation time 8368522818 ps
CPU time 7.7 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:07 PM PDT 24
Peak memory 204060 kb
Host smart-90258d39-f94d-4301-bf91-468190c9f795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640
54938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3864054938
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3790871636
Short name T1101
Test name
Test status
Simulation time 8386266008 ps
CPU time 7.79 seconds
Started Apr 30 02:48:57 PM PDT 24
Finished Apr 30 02:49:06 PM PDT 24
Peak memory 204072 kb
Host smart-6ede5831-a02b-4658-ac66-a6b182fcac17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37908
71636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3790871636
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3458660581
Short name T786
Test name
Test status
Simulation time 8413869954 ps
CPU time 7.76 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204044 kb
Host smart-2afd7c63-0c84-4180-91eb-f4faafee521c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
60581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3458660581
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.389335973
Short name T474
Test name
Test status
Simulation time 8419827175 ps
CPU time 10.28 seconds
Started Apr 30 02:48:52 PM PDT 24
Finished Apr 30 02:49:03 PM PDT 24
Peak memory 204140 kb
Host smart-3c98e728-cb94-4647-8c96-7e014d536d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38933
5973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.389335973
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1291810177
Short name T170
Test name
Test status
Simulation time 8390335192 ps
CPU time 9.53 seconds
Started Apr 30 02:48:59 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204076 kb
Host smart-7320348d-28ef-4896-ab88-e3866e3779a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12918
10177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1291810177
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1021432041
Short name T790
Test name
Test status
Simulation time 8373648140 ps
CPU time 7.31 seconds
Started Apr 30 02:49:02 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204104 kb
Host smart-424ca880-d2b6-4a08-a825-5ffa8c53d4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
32041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1021432041
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3493210374
Short name T1202
Test name
Test status
Simulation time 37544734 ps
CPU time 0.65 seconds
Started Apr 30 02:48:59 PM PDT 24
Finished Apr 30 02:49:00 PM PDT 24
Peak memory 203992 kb
Host smart-66fce98b-3f97-4ecc-a2b2-c190cdee049b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34932
10374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3493210374
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2151765081
Short name T89
Test name
Test status
Simulation time 25839516877 ps
CPU time 53.19 seconds
Started Apr 30 02:49:06 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204300 kb
Host smart-033b1b4e-d68e-4910-be6b-414cb804bbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
65081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2151765081
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3923774668
Short name T414
Test name
Test status
Simulation time 8398843209 ps
CPU time 9.97 seconds
Started Apr 30 02:48:59 PM PDT 24
Finished Apr 30 02:49:10 PM PDT 24
Peak memory 204004 kb
Host smart-0fc77933-ef40-4454-ae04-85e53027e45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39237
74668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3923774668
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2059781456
Short name T143
Test name
Test status
Simulation time 8395228022 ps
CPU time 8.26 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 204056 kb
Host smart-c3640d2c-3fe6-473d-8238-80835104be0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597
81456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2059781456
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2477167314
Short name T433
Test name
Test status
Simulation time 8413642811 ps
CPU time 8.99 seconds
Started Apr 30 02:48:59 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204108 kb
Host smart-929bda3e-c5ef-4613-a9c3-496c785cc022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24771
67314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2477167314
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3611354185
Short name T1110
Test name
Test status
Simulation time 8392631149 ps
CPU time 8.59 seconds
Started Apr 30 02:49:03 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 204132 kb
Host smart-32501dc3-0b6d-430c-a17d-0ed560c14d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36113
54185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3611354185
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2128842107
Short name T875
Test name
Test status
Simulation time 8362599971 ps
CPU time 8.23 seconds
Started Apr 30 02:49:01 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204036 kb
Host smart-fcab8559-cba1-4651-8e16-71292ff6c0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21288
42107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2128842107
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2246302099
Short name T830
Test name
Test status
Simulation time 8418837362 ps
CPU time 7.7 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204072 kb
Host smart-e5e87b38-5f8f-4a42-9199-a924d282b990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22463
02099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2246302099
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2653133964
Short name T1245
Test name
Test status
Simulation time 8376197863 ps
CPU time 8.34 seconds
Started Apr 30 02:48:59 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 204112 kb
Host smart-effeb6b6-3d34-415f-b0f7-b167a8e3ace6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26531
33964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2653133964
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3469018884
Short name T276
Test name
Test status
Simulation time 8394671541 ps
CPU time 7.72 seconds
Started Apr 30 02:49:05 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 204112 kb
Host smart-c8587711-8433-4d17-8413-b6c924543cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
18884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3469018884
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3041014443
Short name T1022
Test name
Test status
Simulation time 8474504506 ps
CPU time 8.45 seconds
Started Apr 30 02:49:08 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204100 kb
Host smart-d104adc5-f87a-4723-80e2-3ea6d7f7026c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3041014443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3041014443
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.3039713162
Short name T1070
Test name
Test status
Simulation time 8383752217 ps
CPU time 9.35 seconds
Started Apr 30 02:49:07 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204152 kb
Host smart-dc6e4468-718b-4b8b-b41e-06082427afd8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3039713162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.3039713162
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2608701379
Short name T1092
Test name
Test status
Simulation time 8415489820 ps
CPU time 8.83 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 204112 kb
Host smart-4cdccec8-4185-4f5f-b2ba-c6491c1f6b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26087
01379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2608701379
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1138840757
Short name T789
Test name
Test status
Simulation time 8402951098 ps
CPU time 8.16 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 204152 kb
Host smart-78b2c9fb-5c31-43ab-8270-51c4efaa451b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11388
40757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1138840757
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.2653823432
Short name T200
Test name
Test status
Simulation time 8372793736 ps
CPU time 8.88 seconds
Started Apr 30 02:49:04 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 204108 kb
Host smart-e1fd2636-142a-47b4-9500-cf50cdc97840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26538
23432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2653823432
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2477509674
Short name T713
Test name
Test status
Simulation time 175634787 ps
CPU time 1.94 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:02 PM PDT 24
Peak memory 204184 kb
Host smart-542a3ba9-6aed-4e29-9736-d8413ca401a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24775
09674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2477509674
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1585468255
Short name T1222
Test name
Test status
Simulation time 8398630597 ps
CPU time 7.92 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204092 kb
Host smart-c92471e4-4389-4a56-96e4-cab1f0c83d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15854
68255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1585468255
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3388042081
Short name T1057
Test name
Test status
Simulation time 8367891866 ps
CPU time 7.56 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204060 kb
Host smart-88c14679-16d0-438c-b1dc-af2935559a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33880
42081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3388042081
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2559955521
Short name T1269
Test name
Test status
Simulation time 8460898165 ps
CPU time 7.81 seconds
Started Apr 30 02:49:04 PM PDT 24
Finished Apr 30 02:49:12 PM PDT 24
Peak memory 203976 kb
Host smart-7e38aa8d-7dba-463b-8fd2-054c7d53d21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25599
55521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2559955521
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1297786093
Short name T343
Test name
Test status
Simulation time 8417314924 ps
CPU time 7.61 seconds
Started Apr 30 02:49:05 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 204080 kb
Host smart-1749dc79-0a7a-4408-94cf-f59eb6de1a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12977
86093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1297786093
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3832614189
Short name T1334
Test name
Test status
Simulation time 8381651251 ps
CPU time 7.93 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 204104 kb
Host smart-146b748b-7aff-4784-b735-2672e7a3788c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
14189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3832614189
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.54254160
Short name T99
Test name
Test status
Simulation time 8388446850 ps
CPU time 9.1 seconds
Started Apr 30 02:49:08 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204044 kb
Host smart-8019a069-5754-4bd5-aaa0-06428e0b8868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54254
160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.54254160
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.708859024
Short name T490
Test name
Test status
Simulation time 8411386304 ps
CPU time 7.96 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:06 PM PDT 24
Peak memory 204112 kb
Host smart-6a39d8f9-0e88-48f9-86c6-fcd15227e79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70885
9024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.708859024
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1618874983
Short name T1149
Test name
Test status
Simulation time 8468279788 ps
CPU time 8.28 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204084 kb
Host smart-44302346-0e32-4e32-8857-8f1f041259b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16188
74983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1618874983
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1135201611
Short name T758
Test name
Test status
Simulation time 8403422765 ps
CPU time 8.43 seconds
Started Apr 30 02:49:05 PM PDT 24
Finished Apr 30 02:49:14 PM PDT 24
Peak memory 204064 kb
Host smart-758b2231-1603-4eab-9f18-d4c7800c87d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
01611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1135201611
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1858494353
Short name T1355
Test name
Test status
Simulation time 51115757 ps
CPU time 0.65 seconds
Started Apr 30 02:49:10 PM PDT 24
Finished Apr 30 02:49:11 PM PDT 24
Peak memory 204012 kb
Host smart-4f999aad-1905-437d-971d-10cfbd7a9425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18584
94353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1858494353
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3926548976
Short name T868
Test name
Test status
Simulation time 21988454935 ps
CPU time 42.28 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:43 PM PDT 24
Peak memory 204316 kb
Host smart-564ec4e2-ec61-4a40-be36-89d4c4c3d329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
48976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3926548976
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1886067245
Short name T658
Test name
Test status
Simulation time 8390090472 ps
CPU time 7.91 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:06 PM PDT 24
Peak memory 204080 kb
Host smart-91fcd61a-0a35-429a-9610-fb98ba0ba86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860
67245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1886067245
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1508649463
Short name T1058
Test name
Test status
Simulation time 8463739972 ps
CPU time 8.33 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:07 PM PDT 24
Peak memory 204144 kb
Host smart-a0762500-996c-4bbf-aac9-1321738596bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15086
49463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1508649463
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3245246847
Short name T671
Test name
Test status
Simulation time 8400257069 ps
CPU time 9.59 seconds
Started Apr 30 02:48:58 PM PDT 24
Finished Apr 30 02:49:09 PM PDT 24
Peak memory 204128 kb
Host smart-2d1b0874-760c-4c50-b9e0-5b547d856005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
46847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3245246847
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.456124986
Short name T807
Test name
Test status
Simulation time 8370514674 ps
CPU time 7.78 seconds
Started Apr 30 02:49:01 PM PDT 24
Finished Apr 30 02:49:10 PM PDT 24
Peak memory 204112 kb
Host smart-70a9e8f7-51b8-463b-b79e-29e037de1202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45612
4986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.456124986
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2175123379
Short name T1117
Test name
Test status
Simulation time 8367004058 ps
CPU time 10.3 seconds
Started Apr 30 02:48:59 PM PDT 24
Finished Apr 30 02:49:10 PM PDT 24
Peak memory 204056 kb
Host smart-cb176012-0bbb-4142-b525-daa4e68a403e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
23379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2175123379
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3488858256
Short name T1363
Test name
Test status
Simulation time 8453474379 ps
CPU time 10.36 seconds
Started Apr 30 02:49:00 PM PDT 24
Finished Apr 30 02:49:11 PM PDT 24
Peak memory 204052 kb
Host smart-6db4bd4d-8e1f-45ed-b532-0800b93356a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34888
58256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3488858256
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2117120986
Short name T844
Test name
Test status
Simulation time 8409802288 ps
CPU time 9.86 seconds
Started Apr 30 02:49:07 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204076 kb
Host smart-9be8a6df-6718-4aab-a6ba-3e5289345859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21171
20986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2117120986
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3900626770
Short name T352
Test name
Test status
Simulation time 8382909613 ps
CPU time 9.48 seconds
Started Apr 30 02:49:04 PM PDT 24
Finished Apr 30 02:49:14 PM PDT 24
Peak memory 204132 kb
Host smart-ce6501b3-40e8-46d1-b888-66d466e651be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
26770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3900626770
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.764029513
Short name T389
Test name
Test status
Simulation time 8504749141 ps
CPU time 10.03 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:47:01 PM PDT 24
Peak memory 204128 kb
Host smart-5befde9b-2e66-4b05-b331-317e504c84d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=764029513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.764029513
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2712332232
Short name T969
Test name
Test status
Simulation time 8375873429 ps
CPU time 8.45 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204152 kb
Host smart-4bc4e6d5-1f65-49c2-8337-cf181bc0098a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2712332232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2712332232
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3039048752
Short name T619
Test name
Test status
Simulation time 8408199788 ps
CPU time 7.99 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:58 PM PDT 24
Peak memory 204100 kb
Host smart-dacee6ed-2dda-4ccb-9af8-67a79eee7c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30390
48752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3039048752
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1012350252
Short name T1360
Test name
Test status
Simulation time 8379479160 ps
CPU time 7.94 seconds
Started Apr 30 02:46:45 PM PDT 24
Finished Apr 30 02:46:53 PM PDT 24
Peak memory 204084 kb
Host smart-3f8a645c-8ef4-454f-83f8-8eb2999a714f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
50252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1012350252
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.1196590802
Short name T695
Test name
Test status
Simulation time 8371742003 ps
CPU time 7.88 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:58 PM PDT 24
Peak memory 204128 kb
Host smart-f295c683-f760-45cc-b4e8-3a341dbd3ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11965
90802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1196590802
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1748365859
Short name T986
Test name
Test status
Simulation time 155245156 ps
CPU time 1.56 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:53 PM PDT 24
Peak memory 204264 kb
Host smart-a07223b5-5a84-41f1-9378-dfff3ca2fbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
65859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1748365859
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3751359836
Short name T1122
Test name
Test status
Simulation time 8415355400 ps
CPU time 8.31 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:58 PM PDT 24
Peak memory 204068 kb
Host smart-ff772526-dd48-4410-82e9-0e9ec53f5d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513
59836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3751359836
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1250141028
Short name T136
Test name
Test status
Simulation time 8437432770 ps
CPU time 7.67 seconds
Started Apr 30 02:46:45 PM PDT 24
Finished Apr 30 02:46:54 PM PDT 24
Peak memory 204052 kb
Host smart-6a1ffc09-6644-4f6b-91c4-d0eb0f046baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12501
41028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1250141028
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3703950550
Short name T1104
Test name
Test status
Simulation time 8433194549 ps
CPU time 10.1 seconds
Started Apr 30 02:46:53 PM PDT 24
Finished Apr 30 02:47:04 PM PDT 24
Peak memory 204292 kb
Host smart-207b25bc-0cb2-4fd2-b2c3-79a736fa0f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039
50550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3703950550
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2246393886
Short name T434
Test name
Test status
Simulation time 8371082517 ps
CPU time 9.43 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204096 kb
Host smart-5cde04e0-f9c4-4a12-a9fe-0ceb1ba03118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22463
93886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2246393886
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3133190111
Short name T103
Test name
Test status
Simulation time 8456450394 ps
CPU time 8.77 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:58 PM PDT 24
Peak memory 204108 kb
Host smart-2bdcbc49-c5d9-49ab-ba0a-6d4ac956d56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331
90111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3133190111
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1536592177
Short name T1336
Test name
Test status
Simulation time 8404796853 ps
CPU time 8.42 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204064 kb
Host smart-01162787-b0c3-4b65-93d4-5f24bfef934f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15365
92177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1536592177
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1975722493
Short name T792
Test name
Test status
Simulation time 8414631073 ps
CPU time 8.67 seconds
Started Apr 30 02:46:44 PM PDT 24
Finished Apr 30 02:46:53 PM PDT 24
Peak memory 204048 kb
Host smart-94997bf3-0f08-44a3-8da8-392a1953a5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19757
22493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1975722493
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1085048792
Short name T186
Test name
Test status
Simulation time 8414145003 ps
CPU time 7.91 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204100 kb
Host smart-34f4a786-f51e-428b-9a1b-df706b54db62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10850
48792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1085048792
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1675358276
Short name T1074
Test name
Test status
Simulation time 8365631433 ps
CPU time 8.36 seconds
Started Apr 30 02:46:47 PM PDT 24
Finished Apr 30 02:46:56 PM PDT 24
Peak memory 204060 kb
Host smart-fdf3568d-2141-4386-ab57-a422032323b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16753
58276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1675358276
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2330252227
Short name T876
Test name
Test status
Simulation time 63379330 ps
CPU time 0.67 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:46:53 PM PDT 24
Peak memory 203976 kb
Host smart-6dd25f95-4ee6-4175-aba7-7c63f76a1208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23302
52227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2330252227
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2224036669
Short name T895
Test name
Test status
Simulation time 27363287367 ps
CPU time 60.36 seconds
Started Apr 30 02:46:47 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204336 kb
Host smart-a9ce466d-cd96-46c4-84bb-1f4952856acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
36669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2224036669
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2244962710
Short name T44
Test name
Test status
Simulation time 8381421121 ps
CPU time 9.55 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 204056 kb
Host smart-2d05721c-39f4-4b23-ba02-9057ca67cf34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22449
62710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2244962710
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2719319293
Short name T463
Test name
Test status
Simulation time 8397480237 ps
CPU time 9.42 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 204108 kb
Host smart-3532e162-9efe-4019-8933-755908c3d946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27193
19293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2719319293
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3357694836
Short name T372
Test name
Test status
Simulation time 8386614902 ps
CPU time 8.01 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 204140 kb
Host smart-7585afe7-3836-4bc9-8f31-3756815f5615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33576
94836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3357694836
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.609116965
Short name T69
Test name
Test status
Simulation time 195431412 ps
CPU time 0.99 seconds
Started Apr 30 02:46:53 PM PDT 24
Finished Apr 30 02:46:54 PM PDT 24
Peak memory 220236 kb
Host smart-c6ef1bc0-987c-44d4-a5c5-4bec7ce6d189
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=609116965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.609116965
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2736394245
Short name T162
Test name
Test status
Simulation time 8376050967 ps
CPU time 7.85 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 204136 kb
Host smart-b167e5e1-04bd-40ad-a4df-e483d50427f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27363
94245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2736394245
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.4038387021
Short name T1255
Test name
Test status
Simulation time 8373034559 ps
CPU time 8.4 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204136 kb
Host smart-41e4898b-54c4-4750-8b98-9acf2177ce34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40383
87021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.4038387021
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.219721043
Short name T1216
Test name
Test status
Simulation time 8418256385 ps
CPU time 10.01 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 204120 kb
Host smart-24bbc92c-966a-45d7-9ac1-d6fed21cdaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.219721043
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2737187036
Short name T699
Test name
Test status
Simulation time 8390857485 ps
CPU time 7.63 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:58 PM PDT 24
Peak memory 204072 kb
Host smart-a80b9976-a6a7-4e52-8736-dd5d0a747ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27371
87036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2737187036
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2579217100
Short name T1351
Test name
Test status
Simulation time 8411897462 ps
CPU time 8.8 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 204080 kb
Host smart-1c024788-26f2-4d6f-b9ae-151133a1be8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25792
17100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2579217100
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1220312146
Short name T742
Test name
Test status
Simulation time 8508517745 ps
CPU time 7.42 seconds
Started Apr 30 02:49:10 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204056 kb
Host smart-6968cddf-4183-4fe7-914f-cf35b2aef5f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1220312146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1220312146
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3941498754
Short name T450
Test name
Test status
Simulation time 8380555580 ps
CPU time 8.66 seconds
Started Apr 30 02:49:13 PM PDT 24
Finished Apr 30 02:49:22 PM PDT 24
Peak memory 204140 kb
Host smart-242193b3-1454-4abd-b38a-bbe429a904a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3941498754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3941498754
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.536616827
Short name T306
Test name
Test status
Simulation time 8410617440 ps
CPU time 8.14 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 204120 kb
Host smart-60eb881b-4f6f-4436-9e55-b4dd48c03a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53661
6827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.536616827
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.534165634
Short name T481
Test name
Test status
Simulation time 8370326700 ps
CPU time 8.1 seconds
Started Apr 30 02:49:10 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 204056 kb
Host smart-566af177-d21b-4cb2-ba3a-85576adaaae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53416
5634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.534165634
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.1159823716
Short name T978
Test name
Test status
Simulation time 8377671611 ps
CPU time 7.79 seconds
Started Apr 30 02:49:13 PM PDT 24
Finished Apr 30 02:49:21 PM PDT 24
Peak memory 204292 kb
Host smart-c10033bd-d4d5-44f7-ac8f-d499a2105668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11598
23716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1159823716
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1329203190
Short name T1029
Test name
Test status
Simulation time 254859471 ps
CPU time 2.01 seconds
Started Apr 30 02:49:13 PM PDT 24
Finished Apr 30 02:49:15 PM PDT 24
Peak memory 204252 kb
Host smart-9de6883c-6e8b-4485-beed-015442f96af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13292
03190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1329203190
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.662657095
Short name T998
Test name
Test status
Simulation time 8376400681 ps
CPU time 8.31 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204108 kb
Host smart-17804342-ef1c-4142-9479-dab867dfcb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66265
7095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.662657095
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3924130253
Short name T911
Test name
Test status
Simulation time 8384200936 ps
CPU time 8.32 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 204288 kb
Host smart-56b9ea10-a2d7-4be2-b12b-7a88d01b7307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39241
30253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3924130253
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1564229966
Short name T979
Test name
Test status
Simulation time 8436501855 ps
CPU time 7.53 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204060 kb
Host smart-c4a5c5d0-0bd2-498b-b9df-46dc149a957c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15642
29966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1564229966
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3469787572
Short name T656
Test name
Test status
Simulation time 8420562445 ps
CPU time 7.75 seconds
Started Apr 30 02:49:08 PM PDT 24
Finished Apr 30 02:49:16 PM PDT 24
Peak memory 204040 kb
Host smart-437ee1d5-7cf0-4b04-bf63-346988474f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34697
87572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3469787572
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1793051136
Short name T1023
Test name
Test status
Simulation time 8382150828 ps
CPU time 8.66 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204080 kb
Host smart-db44f581-2d31-42ef-ad79-083cc470a376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17930
51136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1793051136
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.290757494
Short name T965
Test name
Test status
Simulation time 8405745082 ps
CPU time 7.65 seconds
Started Apr 30 02:49:10 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204004 kb
Host smart-eafed5cc-b4e7-4e4a-a805-665337f8f1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29075
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.290757494
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1597718267
Short name T299
Test name
Test status
Simulation time 8414009422 ps
CPU time 8.06 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204104 kb
Host smart-b92e8731-c132-4dad-a06d-15346a8626c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15977
18267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1597718267
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1732559796
Short name T384
Test name
Test status
Simulation time 8413660416 ps
CPU time 8.2 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:18 PM PDT 24
Peak memory 204144 kb
Host smart-0fcb44f8-4691-4223-94b6-07920567cb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
59796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1732559796
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.387302484
Short name T845
Test name
Test status
Simulation time 8369301598 ps
CPU time 8.6 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204040 kb
Host smart-0b24a99c-69d8-4390-9c7d-9cfdab1312a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38730
2484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.387302484
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.731702128
Short name T575
Test name
Test status
Simulation time 8394334855 ps
CPU time 9.76 seconds
Started Apr 30 02:49:08 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 204128 kb
Host smart-c2fc850e-ed4e-4a8b-8424-149fc22c9840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73170
2128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.731702128
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2368274637
Short name T1021
Test name
Test status
Simulation time 160868374 ps
CPU time 0.73 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 203952 kb
Host smart-e164af54-1741-438b-8d12-c2c9272bf34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23682
74637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2368274637
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1516313330
Short name T1056
Test name
Test status
Simulation time 22577432839 ps
CPU time 44.71 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:50:04 PM PDT 24
Peak memory 204336 kb
Host smart-a15d655d-b76a-4a93-94f1-a5821ee40c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
13330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1516313330
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1762794806
Short name T1366
Test name
Test status
Simulation time 8396647469 ps
CPU time 9.22 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204044 kb
Host smart-1e98c0ad-e119-4964-8851-eac735bb0702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17627
94806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1762794806
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3214796335
Short name T1087
Test name
Test status
Simulation time 8466976920 ps
CPU time 10.41 seconds
Started Apr 30 02:49:09 PM PDT 24
Finished Apr 30 02:49:20 PM PDT 24
Peak memory 204056 kb
Host smart-cce15823-0a45-4404-a0b1-fd4dcbef59f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
96335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3214796335
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3012818879
Short name T1230
Test name
Test status
Simulation time 8447512887 ps
CPU time 8.8 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204052 kb
Host smart-062da4e5-c8af-4f4f-b6f2-b9d15c579072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30128
18879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3012818879
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3677898958
Short name T593
Test name
Test status
Simulation time 8396906744 ps
CPU time 8.32 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 204288 kb
Host smart-40ea4421-16e7-4ac2-9f6e-c23a7323a37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
98958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3677898958
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.211540147
Short name T1143
Test name
Test status
Simulation time 8379425583 ps
CPU time 9.79 seconds
Started Apr 30 02:49:08 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 204120 kb
Host smart-0adb45e8-5f6c-4d27-aa75-167eefdad2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
0147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.211540147
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.103251021
Short name T1369
Test name
Test status
Simulation time 8446489932 ps
CPU time 8.16 seconds
Started Apr 30 02:49:10 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 204048 kb
Host smart-034362f1-dd6c-4113-9974-6b1492de0b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10325
1021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.103251021
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.225787579
Short name T1020
Test name
Test status
Simulation time 8427178647 ps
CPU time 7.88 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204052 kb
Host smart-fc0dbbf0-ab3f-41dc-8e52-4425f52f14a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22578
7579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.225787579
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2061401784
Short name T1003
Test name
Test status
Simulation time 8389926542 ps
CPU time 7.64 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204052 kb
Host smart-09a35814-05b5-4b04-b2ff-0bff826cfe4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
01784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2061401784
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.1716256233
Short name T814
Test name
Test status
Simulation time 8466807540 ps
CPU time 8.8 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204144 kb
Host smart-84652de7-d89c-40c6-92f8-52c33c9455ef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1716256233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.1716256233
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2784375941
Short name T724
Test name
Test status
Simulation time 8374429622 ps
CPU time 8.2 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204060 kb
Host smart-84ed9064-6fe7-4ff4-986d-40c61129de09
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2784375941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2784375941
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.4254889666
Short name T499
Test name
Test status
Simulation time 8445269764 ps
CPU time 8.37 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204156 kb
Host smart-332fead8-e1b5-4798-aea1-3e298981b644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42548
89666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.4254889666
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4268348463
Short name T381
Test name
Test status
Simulation time 8371816309 ps
CPU time 7.63 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:22 PM PDT 24
Peak memory 204116 kb
Host smart-52d43d4b-0eef-43ea-9193-8d4eb97c4b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
48463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4268348463
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.507321646
Short name T1206
Test name
Test status
Simulation time 8377947473 ps
CPU time 9.55 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204100 kb
Host smart-a2a0a9f4-ba6c-41a3-be22-2a56a15c6bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50732
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.507321646
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3402031301
Short name T717
Test name
Test status
Simulation time 307405195 ps
CPU time 2.48 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:17 PM PDT 24
Peak memory 204184 kb
Host smart-6752bd22-7f4c-4fcd-8dc4-df5bbab16814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
31301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3402031301
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4198739604
Short name T825
Test name
Test status
Simulation time 8433752473 ps
CPU time 8.27 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204128 kb
Host smart-d1dc650f-912f-4acd-9aeb-b2cac6b81760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
39604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4198739604
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4123331994
Short name T905
Test name
Test status
Simulation time 8370372988 ps
CPU time 7.87 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204080 kb
Host smart-4f88cf84-7a60-4f49-b455-a94cf34e1189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41233
31994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4123331994
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1225754408
Short name T857
Test name
Test status
Simulation time 8427290035 ps
CPU time 8.1 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204048 kb
Host smart-064f6f4a-08dc-4f19-bc50-14fb2d1cc211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12257
54408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1225754408
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.200851006
Short name T556
Test name
Test status
Simulation time 8417048969 ps
CPU time 7.87 seconds
Started Apr 30 02:49:15 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 204080 kb
Host smart-69cc7868-9570-4bcf-89ba-bc3b2a6d26a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085
1006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.200851006
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1287545138
Short name T1182
Test name
Test status
Simulation time 8374115043 ps
CPU time 7.96 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204112 kb
Host smart-d89d6302-3511-4a7d-9984-533d1de94ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875
45138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1287545138
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2387312329
Short name T120
Test name
Test status
Simulation time 8447318856 ps
CPU time 8.08 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204120 kb
Host smart-871a6f50-a77a-40fd-98ec-3ae2662d43eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
12329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2387312329
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1994557009
Short name T393
Test name
Test status
Simulation time 8394196855 ps
CPU time 7.5 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204168 kb
Host smart-032bcd0d-2cf4-486e-b783-029f817bd283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19945
57009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1994557009
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3094027692
Short name T1330
Test name
Test status
Simulation time 8422351314 ps
CPU time 10.13 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204016 kb
Host smart-d166b8fd-c285-447c-b301-46341284562c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940
27692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3094027692
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1591141804
Short name T940
Test name
Test status
Simulation time 8392375669 ps
CPU time 7.35 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204004 kb
Host smart-c2595339-5f44-43bc-b3fd-9e4e35f00102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
41804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1591141804
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1563200087
Short name T756
Test name
Test status
Simulation time 8364231228 ps
CPU time 8.6 seconds
Started Apr 30 02:49:15 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204048 kb
Host smart-de11328b-749a-4f0c-a5a8-e36ee9b9dbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15632
00087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1563200087
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1987453398
Short name T33
Test name
Test status
Simulation time 33384367 ps
CPU time 0.64 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 203936 kb
Host smart-61cf7277-6117-45ff-bb28-c67087bc53a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19874
53398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1987453398
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1067395502
Short name T1190
Test name
Test status
Simulation time 25430385125 ps
CPU time 49.19 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204420 kb
Host smart-7b4e320c-ce0e-4541-b5f4-c95f8f78b21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673
95502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1067395502
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4056091620
Short name T688
Test name
Test status
Simulation time 8404258757 ps
CPU time 9.16 seconds
Started Apr 30 02:49:15 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204076 kb
Host smart-2cc8f8f7-af7c-4805-8873-9d57211fd447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
91620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4056091620
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1941297554
Short name T1140
Test name
Test status
Simulation time 8412809458 ps
CPU time 7.57 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204072 kb
Host smart-78f44d6d-ad6f-4bdb-8f1c-abbe5fb196ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19412
97554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1941297554
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2104669617
Short name T861
Test name
Test status
Simulation time 8375671525 ps
CPU time 10.41 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204116 kb
Host smart-da2538b6-7b4d-4ab1-9d87-beed71e2f29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21046
69617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2104669617
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2274985717
Short name T1214
Test name
Test status
Simulation time 8380770158 ps
CPU time 7.6 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204136 kb
Host smart-5c58e685-bcba-4546-ab8a-c9e8f0471e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
85717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2274985717
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2964663598
Short name T733
Test name
Test status
Simulation time 8392664781 ps
CPU time 7.74 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204112 kb
Host smart-6d5ce4a8-e501-49e3-ac75-dc9214f1d4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29646
63598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2964663598
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.300170752
Short name T1054
Test name
Test status
Simulation time 8394812061 ps
CPU time 8.01 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204052 kb
Host smart-b328a50c-f305-4a72-a15b-31de122d3f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017
0752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.300170752
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1423925793
Short name T1108
Test name
Test status
Simulation time 8447584089 ps
CPU time 8.12 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204044 kb
Host smart-96bdc68e-0d44-4784-8d30-ebbc961a56bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14239
25793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1423925793
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1945957373
Short name T1185
Test name
Test status
Simulation time 8485317472 ps
CPU time 7.41 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204112 kb
Host smart-2c504441-8846-464e-a557-3e863764d5cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1945957373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1945957373
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.202667860
Short name T629
Test name
Test status
Simulation time 8378209993 ps
CPU time 9.47 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 203992 kb
Host smart-52226557-ec84-46a7-9959-5419705e634a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=202667860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.202667860
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.38407745
Short name T1309
Test name
Test status
Simulation time 8426510295 ps
CPU time 9.65 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204068 kb
Host smart-30316621-2647-4a48-a44f-069f33fe0cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.38407745
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2711180100
Short name T418
Test name
Test status
Simulation time 8376669939 ps
CPU time 8.69 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204128 kb
Host smart-5bd55398-4992-4aa1-b4bf-3daad4ff7f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27111
80100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2711180100
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.2387838704
Short name T795
Test name
Test status
Simulation time 8379456253 ps
CPU time 8.51 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204112 kb
Host smart-e4b4faa0-7393-4ffd-91b7-d9a96b6d4b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
38704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2387838704
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.4071423650
Short name T47
Test name
Test status
Simulation time 163788062 ps
CPU time 1.8 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:20 PM PDT 24
Peak memory 204196 kb
Host smart-12ac921e-ad58-4085-8400-9b092d4bb541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
23650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.4071423650
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4250751884
Short name T1004
Test name
Test status
Simulation time 8408536558 ps
CPU time 8.52 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204124 kb
Host smart-6f50d7cb-3c77-477e-8d43-f137317131be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42507
51884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4250751884
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2257061993
Short name T600
Test name
Test status
Simulation time 8370432981 ps
CPU time 7.3 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204056 kb
Host smart-81201a3b-baf3-432c-b52f-903928db6676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
61993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2257061993
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3048068889
Short name T1225
Test name
Test status
Simulation time 8402238084 ps
CPU time 9.07 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 203976 kb
Host smart-8a23efac-1efc-4cfb-9e7d-a6206375489a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30480
68889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3048068889
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1309745728
Short name T833
Test name
Test status
Simulation time 8410149295 ps
CPU time 7.79 seconds
Started Apr 30 02:49:15 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204164 kb
Host smart-a5464009-990a-451b-b034-836394c49f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13097
45728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1309745728
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2941123765
Short name T862
Test name
Test status
Simulation time 8378290012 ps
CPU time 8.74 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204056 kb
Host smart-7f34a8de-72b8-4589-a70a-4cc431ceb816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
23765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2941123765
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3469150086
Short name T101
Test name
Test status
Simulation time 8412646423 ps
CPU time 8.1 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204080 kb
Host smart-e51c9477-bfd5-4526-89d0-a65f8eeb8af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34691
50086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3469150086
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3991681538
Short name T303
Test name
Test status
Simulation time 8417891061 ps
CPU time 7.69 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 204136 kb
Host smart-34877fc7-d5dd-4a84-b73c-dea2fce7bb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39916
81538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3991681538
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.55950005
Short name T1006
Test name
Test status
Simulation time 8386584661 ps
CPU time 8.13 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204108 kb
Host smart-ea234eed-a93d-4b82-8be2-a03813b1db85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55950
005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.55950005
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3925515616
Short name T1291
Test name
Test status
Simulation time 8442799605 ps
CPU time 7.69 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204120 kb
Host smart-59847ab3-dbea-45ab-be2a-933b3a4efeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39255
15616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3925515616
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2760575724
Short name T19
Test name
Test status
Simulation time 8375163625 ps
CPU time 7.83 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204100 kb
Host smart-e248c67e-0aa1-46cd-a3c4-6230ef12effa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27605
75724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2760575724
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.725175923
Short name T1329
Test name
Test status
Simulation time 16957373313 ps
CPU time 29.83 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:50 PM PDT 24
Peak memory 204412 kb
Host smart-da7a9f59-2d05-49e7-ab87-8c6889bb2f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72517
5923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.725175923
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3104713343
Short name T611
Test name
Test status
Simulation time 8436607118 ps
CPU time 8.64 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204136 kb
Host smart-31dcd685-daa6-4ac7-a107-668d3ecfcfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31047
13343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3104713343
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2990064582
Short name T570
Test name
Test status
Simulation time 8456063243 ps
CPU time 9.43 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204100 kb
Host smart-6805d398-caf2-4904-8a16-df9b57edfdb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29900
64582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2990064582
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2637283959
Short name T616
Test name
Test status
Simulation time 8403292578 ps
CPU time 7.8 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204100 kb
Host smart-ca04ce0c-0f51-465f-b5c8-b68360b1689d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
83959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2637283959
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1328887659
Short name T945
Test name
Test status
Simulation time 8379332276 ps
CPU time 7.94 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204132 kb
Host smart-15573892-b4c8-4029-874e-7cc7a943ecc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
87659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1328887659
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1078029253
Short name T832
Test name
Test status
Simulation time 8375191181 ps
CPU time 8.76 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204076 kb
Host smart-f6ec8a13-9d6e-41dc-a7f5-37790ddba198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10780
29253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1078029253
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2711827513
Short name T1247
Test name
Test status
Simulation time 8448779134 ps
CPU time 7.72 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204072 kb
Host smart-3b704dec-9fec-48dd-82f2-d6825e2b0255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27118
27513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2711827513
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.355384583
Short name T636
Test name
Test status
Simulation time 8419258260 ps
CPU time 10.89 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204072 kb
Host smart-fa716c64-c678-418b-ad8d-a91997232c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35538
4583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.355384583
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1143709002
Short name T1223
Test name
Test status
Simulation time 8390927681 ps
CPU time 8.64 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204040 kb
Host smart-f11bb89c-0d77-44cf-807b-eee967cd675f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
09002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1143709002
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.1300014265
Short name T835
Test name
Test status
Simulation time 8468318225 ps
CPU time 9.84 seconds
Started Apr 30 02:49:15 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204100 kb
Host smart-3a50d07a-5099-4c9e-90b0-a1c40b861fd7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1300014265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.1300014265
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.2242425674
Short name T685
Test name
Test status
Simulation time 8387014827 ps
CPU time 7.3 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204100 kb
Host smart-0700e1d7-b544-4f6b-989c-942a488ed4be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2242425674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.2242425674
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.680023083
Short name T1040
Test name
Test status
Simulation time 8526953341 ps
CPU time 7.77 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204080 kb
Host smart-852c9d49-13ab-41dc-984f-fda92050adb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68002
3083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.680023083
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.475046646
Short name T714
Test name
Test status
Simulation time 8380767634 ps
CPU time 9.5 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204084 kb
Host smart-a67311b3-b447-4a91-99fe-4c95b99d8536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47504
6646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.475046646
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.2808193341
Short name T936
Test name
Test status
Simulation time 8380915526 ps
CPU time 8.04 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204016 kb
Host smart-a829f592-ac15-48af-b9b9-2ccf5401dc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28081
93341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2808193341
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2895808490
Short name T889
Test name
Test status
Simulation time 98998718 ps
CPU time 1.22 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:24 PM PDT 24
Peak memory 204156 kb
Host smart-ddce1133-c72b-42b3-b19c-7f11caab70b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
08490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2895808490
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1235746685
Short name T469
Test name
Test status
Simulation time 8446258368 ps
CPU time 10.5 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204108 kb
Host smart-e69d07e1-a26b-4fae-84cc-b9215f34d03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12357
46685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1235746685
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.945254970
Short name T1077
Test name
Test status
Simulation time 8376926672 ps
CPU time 9.5 seconds
Started Apr 30 02:49:16 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204108 kb
Host smart-9c21bc9c-3255-4613-93e6-c5ef8f4f30c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94525
4970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.945254970
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1252943519
Short name T589
Test name
Test status
Simulation time 8459507367 ps
CPU time 7.95 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204084 kb
Host smart-14ba09cc-ce64-4fd9-ba94-10af4a61c240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12529
43519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1252943519
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1717773806
Short name T933
Test name
Test status
Simulation time 8433746090 ps
CPU time 8.39 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204108 kb
Host smart-bbd40399-b86d-4ee5-ae95-b71ed9c992fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
73806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1717773806
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3950966220
Short name T441
Test name
Test status
Simulation time 8391752404 ps
CPU time 7.78 seconds
Started Apr 30 02:49:14 PM PDT 24
Finished Apr 30 02:49:23 PM PDT 24
Peak memory 203444 kb
Host smart-3f838dec-2f45-435f-97fa-daaac56dab54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
66220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3950966220
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1314597407
Short name T111
Test name
Test status
Simulation time 8437098782 ps
CPU time 9.37 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204116 kb
Host smart-b736425f-b078-44d6-9245-770b9ab79d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145
97407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1314597407
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1055735735
Short name T467
Test name
Test status
Simulation time 8396206925 ps
CPU time 7.88 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204116 kb
Host smart-fe51064c-b9ff-4763-9ed8-61a41e60c3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10557
35735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1055735735
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2203509196
Short name T14
Test name
Test status
Simulation time 8412358053 ps
CPU time 7.88 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204092 kb
Host smart-9db3ceaa-4081-4fff-9659-b9a89cb29a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22035
09196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2203509196
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.501844802
Short name T189
Test name
Test status
Simulation time 8395678746 ps
CPU time 8.62 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204060 kb
Host smart-e46548aa-683f-46de-9c69-90229d883ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50184
4802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.501844802
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2972393944
Short name T765
Test name
Test status
Simulation time 8366792979 ps
CPU time 8.16 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204080 kb
Host smart-08203ee5-0901-462a-b726-54765562e678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29723
93944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2972393944
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1914463912
Short name T34
Test name
Test status
Simulation time 31968983 ps
CPU time 0.62 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:19 PM PDT 24
Peak memory 203920 kb
Host smart-a3e83af6-ed34-4385-935a-37a311b64e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144
63912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1914463912
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1309534984
Short name T565
Test name
Test status
Simulation time 24561044962 ps
CPU time 45.81 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:50:05 PM PDT 24
Peak memory 204376 kb
Host smart-9401e9ac-6b92-4b8f-b102-25aabe57936a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
34984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1309534984
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2604033564
Short name T1373
Test name
Test status
Simulation time 8461253258 ps
CPU time 7.85 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204004 kb
Host smart-d4f2a0ca-cd6a-4174-a394-8021e9917edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26040
33564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2604033564
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2765110587
Short name T1081
Test name
Test status
Simulation time 8517258700 ps
CPU time 8.56 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204116 kb
Host smart-e6c8bf6b-7eb1-4d07-b125-28a19295f814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
10587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2765110587
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.4071274784
Short name T342
Test name
Test status
Simulation time 8387776285 ps
CPU time 9.34 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204092 kb
Host smart-0d6d7607-e0bd-44f7-aa75-3b142275df6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40712
74784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.4071274784
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1154675043
Short name T159
Test name
Test status
Simulation time 8391727590 ps
CPU time 7.32 seconds
Started Apr 30 02:49:17 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 204048 kb
Host smart-e7f0032a-f1ff-4d87-b8a2-7b43349cbd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11546
75043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1154675043
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2564548782
Short name T802
Test name
Test status
Simulation time 8376348987 ps
CPU time 7.79 seconds
Started Apr 30 02:49:19 PM PDT 24
Finished Apr 30 02:49:27 PM PDT 24
Peak memory 204092 kb
Host smart-c3fe3d01-3b89-4b4e-99aa-003c98498ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25645
48782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2564548782
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1302999263
Short name T652
Test name
Test status
Simulation time 8414948438 ps
CPU time 8.11 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204140 kb
Host smart-03c8b653-c0f1-42e0-9ae7-318a6fe48530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13029
99263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1302999263
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.4118888138
Short name T878
Test name
Test status
Simulation time 8381559945 ps
CPU time 7.19 seconds
Started Apr 30 02:49:18 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204092 kb
Host smart-2da7cd7b-0831-4969-891b-109f1374b087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41188
88138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.4118888138
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2272119594
Short name T704
Test name
Test status
Simulation time 8414492049 ps
CPU time 7.84 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:28 PM PDT 24
Peak memory 204052 kb
Host smart-8a8521e8-faa4-4d81-a09f-80136d98f5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
19594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2272119594
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2717696922
Short name T324
Test name
Test status
Simulation time 8465810673 ps
CPU time 9.75 seconds
Started Apr 30 02:49:27 PM PDT 24
Finished Apr 30 02:49:38 PM PDT 24
Peak memory 204136 kb
Host smart-8468db6f-59b8-400f-8854-055a28885aff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2717696922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2717696922
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3642788925
Short name T1254
Test name
Test status
Simulation time 8384721826 ps
CPU time 8.75 seconds
Started Apr 30 02:49:32 PM PDT 24
Finished Apr 30 02:49:41 PM PDT 24
Peak memory 204144 kb
Host smart-279a3ada-b363-4bab-8a51-7ff381b6570d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3642788925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3642788925
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1791956721
Short name T495
Test name
Test status
Simulation time 8472131770 ps
CPU time 9.57 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:33 PM PDT 24
Peak memory 204136 kb
Host smart-a9393270-0006-4932-b296-296ae20066ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17919
56721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1791956721
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.311386117
Short name T1242
Test name
Test status
Simulation time 8416972186 ps
CPU time 7.64 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204048 kb
Host smart-83aa2fe5-f8ef-4768-9f5d-4e4ae4651d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
6117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.311386117
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.2486390823
Short name T1299
Test name
Test status
Simulation time 8375351501 ps
CPU time 7.47 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:29 PM PDT 24
Peak memory 204112 kb
Host smart-4c9c93dd-e6fe-4103-a85b-42cbd8cf9fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24863
90823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2486390823
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.921136931
Short name T864
Test name
Test status
Simulation time 59528985 ps
CPU time 1.67 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204180 kb
Host smart-16fa0437-d56c-4d29-9551-ab2d04dc10d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92113
6931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.921136931
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3869019350
Short name T1153
Test name
Test status
Simulation time 8414900953 ps
CPU time 8.19 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204116 kb
Host smart-c2d37e0d-b2c1-4c71-ae04-716f0bfabd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38690
19350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3869019350
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3121082441
Short name T179
Test name
Test status
Simulation time 8376596266 ps
CPU time 9.22 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:33 PM PDT 24
Peak memory 204104 kb
Host smart-6f1d70bf-2328-467b-8e92-e259739ef613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
82441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3121082441
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.59263269
Short name T601
Test name
Test status
Simulation time 8431400350 ps
CPU time 7.83 seconds
Started Apr 30 02:49:35 PM PDT 24
Finished Apr 30 02:49:43 PM PDT 24
Peak memory 204136 kb
Host smart-97278a46-992a-47e8-9d27-19e5d7155a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59263
269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.59263269
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1005631981
Short name T760
Test name
Test status
Simulation time 8415300993 ps
CPU time 7.59 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204104 kb
Host smart-4b996e66-75ed-42c1-930f-03a29ea54405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10056
31981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1005631981
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4227513539
Short name T1125
Test name
Test status
Simulation time 8380382472 ps
CPU time 9.78 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:33 PM PDT 24
Peak memory 204112 kb
Host smart-e17484c6-2269-4e8f-8263-da8132e5373d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42275
13539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4227513539
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.914113302
Short name T1133
Test name
Test status
Simulation time 8390636994 ps
CPU time 8.06 seconds
Started Apr 30 02:49:24 PM PDT 24
Finished Apr 30 02:49:33 PM PDT 24
Peak memory 204064 kb
Host smart-8d08b044-da4f-43e3-9a33-da08c321aa09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91411
3302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.914113302
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3530026766
Short name T321
Test name
Test status
Simulation time 8392262604 ps
CPU time 9.95 seconds
Started Apr 30 02:49:40 PM PDT 24
Finished Apr 30 02:49:51 PM PDT 24
Peak memory 204300 kb
Host smart-96c59161-d0c0-4a13-9919-3d1e164e6c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
26766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3530026766
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2377654998
Short name T819
Test name
Test status
Simulation time 8387773046 ps
CPU time 7.43 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:38 PM PDT 24
Peak memory 204120 kb
Host smart-5c7de6a3-d6b9-4b3c-bcb0-27a53a7ab61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
54998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2377654998
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3532398504
Short name T1332
Test name
Test status
Simulation time 8382777748 ps
CPU time 8.53 seconds
Started Apr 30 02:49:34 PM PDT 24
Finished Apr 30 02:49:43 PM PDT 24
Peak memory 204280 kb
Host smart-1efdccae-7939-4f82-af09-59cfe49e8224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35323
98504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3532398504
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2135315110
Short name T7
Test name
Test status
Simulation time 8393200404 ps
CPU time 7.79 seconds
Started Apr 30 02:49:24 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204144 kb
Host smart-aa5061d8-504b-4ed4-b924-3845c70f95fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21353
15110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2135315110
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3639957144
Short name T419
Test name
Test status
Simulation time 195183122 ps
CPU time 0.8 seconds
Started Apr 30 02:49:31 PM PDT 24
Finished Apr 30 02:49:33 PM PDT 24
Peak memory 203976 kb
Host smart-66c240a8-f35e-45b7-a010-6cc4fd4dea3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36399
57144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3639957144
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2867366912
Short name T225
Test name
Test status
Simulation time 27941030472 ps
CPU time 58.32 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204384 kb
Host smart-e8b3f48c-f918-4f99-a2a1-29d864fa6499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28673
66912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2867366912
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3764041272
Short name T710
Test name
Test status
Simulation time 8403256462 ps
CPU time 8.33 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204080 kb
Host smart-001effef-d031-42af-a086-555365b1324c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37640
41272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3764041272
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1384391419
Short name T927
Test name
Test status
Simulation time 8424690853 ps
CPU time 7.74 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204112 kb
Host smart-31b27a49-3b2f-44d2-97e7-0b7a65acd7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13843
91419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1384391419
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2900020532
Short name T348
Test name
Test status
Simulation time 8414161915 ps
CPU time 9.02 seconds
Started Apr 30 02:49:24 PM PDT 24
Finished Apr 30 02:49:34 PM PDT 24
Peak memory 204144 kb
Host smart-ea016c00-b00b-42fb-a09d-73d577df1e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29000
20532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2900020532
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2206835664
Short name T697
Test name
Test status
Simulation time 8377555771 ps
CPU time 8.69 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204072 kb
Host smart-2be7343d-b3be-4591-ac21-02689a475b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22068
35664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2206835664
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1144569315
Short name T626
Test name
Test status
Simulation time 8368136634 ps
CPU time 7.4 seconds
Started Apr 30 02:49:39 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 204132 kb
Host smart-361aa296-d7a9-4666-8a7f-fcfb60e5ad94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11445
69315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1144569315
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3246852376
Short name T489
Test name
Test status
Simulation time 8421199677 ps
CPU time 8.08 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204148 kb
Host smart-c65f1879-6871-4689-b541-ec1296b950f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32468
52376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3246852376
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.625967257
Short name T622
Test name
Test status
Simulation time 8417234070 ps
CPU time 8.04 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204068 kb
Host smart-bd516c64-09cd-44be-8371-7deeba2fee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62596
7257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.625967257
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2736993355
Short name T1079
Test name
Test status
Simulation time 8377786193 ps
CPU time 8.94 seconds
Started Apr 30 02:49:20 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204124 kb
Host smart-ce9c4f87-bcaf-4ab9-956b-6b5a82051576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369
93355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2736993355
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.357569889
Short name T692
Test name
Test status
Simulation time 8463727057 ps
CPU time 8.29 seconds
Started Apr 30 02:49:31 PM PDT 24
Finished Apr 30 02:49:40 PM PDT 24
Peak memory 204092 kb
Host smart-d4b37211-05ec-42e5-97cd-f1847254f4d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=357569889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.357569889
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2598826713
Short name T764
Test name
Test status
Simulation time 8378828813 ps
CPU time 7.49 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:44 PM PDT 24
Peak memory 204076 kb
Host smart-6e43b130-1b99-4d06-b1ff-fe9f3679577b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2598826713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2598826713
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.741168174
Short name T1028
Test name
Test status
Simulation time 8470049277 ps
CPU time 7.92 seconds
Started Apr 30 02:49:27 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204120 kb
Host smart-f139b994-ccb3-44f4-9a92-4124305823fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74116
8174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.741168174
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1025830842
Short name T881
Test name
Test status
Simulation time 8378017287 ps
CPU time 7.9 seconds
Started Apr 30 02:49:39 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 204140 kb
Host smart-ad9b48a0-aae1-4cfe-8b8b-f979d4e4c51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10258
30842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1025830842
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.4152467320
Short name T273
Test name
Test status
Simulation time 8385663859 ps
CPU time 7.69 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204060 kb
Host smart-0d486b9c-47b4-46e7-8b95-ec8306ea4e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41524
67320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.4152467320
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3852971297
Short name T444
Test name
Test status
Simulation time 301213019 ps
CPU time 2.35 seconds
Started Apr 30 02:49:34 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204252 kb
Host smart-3e711e26-ff80-437a-a020-14b3395a96d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38529
71297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3852971297
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3244524563
Short name T146
Test name
Test status
Simulation time 8453174557 ps
CPU time 8.15 seconds
Started Apr 30 02:49:26 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204084 kb
Host smart-c2cf092f-714b-40eb-b2ff-85b3d7217e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32445
24563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3244524563
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1889599166
Short name T4
Test name
Test status
Simulation time 8367719203 ps
CPU time 7.82 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204100 kb
Host smart-a8dbe6eb-434e-4cf1-bd57-8b6434076478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18895
99166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1889599166
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3963574303
Short name T728
Test name
Test status
Simulation time 8429049581 ps
CPU time 8.08 seconds
Started Apr 30 02:49:39 PM PDT 24
Finished Apr 30 02:49:48 PM PDT 24
Peak memory 204128 kb
Host smart-c8947cd9-0115-4ae4-9131-a0d821d9143d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39635
74303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3963574303
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3547967907
Short name T425
Test name
Test status
Simulation time 8416930866 ps
CPU time 7.96 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204088 kb
Host smart-5d915cfa-3a71-4442-886b-b0b4a068ad20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479
67907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3547967907
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2039795815
Short name T349
Test name
Test status
Simulation time 8369660646 ps
CPU time 8.73 seconds
Started Apr 30 02:49:34 PM PDT 24
Finished Apr 30 02:49:43 PM PDT 24
Peak memory 204132 kb
Host smart-19830d6e-508a-493c-8af0-73250362fa5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20397
95815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2039795815
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2452134253
Short name T124
Test name
Test status
Simulation time 8434666150 ps
CPU time 10.27 seconds
Started Apr 30 02:49:24 PM PDT 24
Finished Apr 30 02:49:35 PM PDT 24
Peak memory 204076 kb
Host smart-de127ed9-893b-498a-8ae2-23db3ccb50b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
34253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2452134253
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3351984117
Short name T1200
Test name
Test status
Simulation time 8378891882 ps
CPU time 8.01 seconds
Started Apr 30 02:49:21 PM PDT 24
Finished Apr 30 02:49:30 PM PDT 24
Peak memory 204144 kb
Host smart-12b92055-3572-4a97-8e21-875141f9171b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33519
84117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3351984117
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.4238956072
Short name T677
Test name
Test status
Simulation time 8414452476 ps
CPU time 8.08 seconds
Started Apr 30 02:49:26 PM PDT 24
Finished Apr 30 02:49:34 PM PDT 24
Peak memory 204068 kb
Host smart-0d58cb96-9253-4bf2-a781-b668215ab429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
56072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.4238956072
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1432427624
Short name T1123
Test name
Test status
Simulation time 8410203432 ps
CPU time 9.35 seconds
Started Apr 30 02:49:26 PM PDT 24
Finished Apr 30 02:49:35 PM PDT 24
Peak memory 204048 kb
Host smart-bb52209e-3d8f-47c3-9d86-5a0ddf0190e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
27624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1432427624
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3853099659
Short name T625
Test name
Test status
Simulation time 45047064 ps
CPU time 0.7 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:25 PM PDT 24
Peak memory 203988 kb
Host smart-bcb55f9a-79b9-4233-bc85-906ec0555450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
99659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3853099659
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1322849609
Short name T224
Test name
Test status
Simulation time 25266276626 ps
CPU time 50.74 seconds
Started Apr 30 02:49:27 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204416 kb
Host smart-e8825946-2059-4b40-a2d3-2a8d1414f4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
49609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1322849609
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.820151297
Short name T590
Test name
Test status
Simulation time 8386492006 ps
CPU time 7.76 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204128 kb
Host smart-bbb2e24a-621d-417c-b122-5006e6f1e59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82015
1297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.820151297
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.996421195
Short name T944
Test name
Test status
Simulation time 8377545641 ps
CPU time 7.81 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204068 kb
Host smart-ef568420-727c-4344-b5f3-e840fc96cd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99642
1195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.996421195
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3351950436
Short name T309
Test name
Test status
Simulation time 8397563544 ps
CPU time 7.32 seconds
Started Apr 30 02:49:35 PM PDT 24
Finished Apr 30 02:49:43 PM PDT 24
Peak memory 204140 kb
Host smart-0b38c8ab-447c-4fa0-89fc-b5e26a04ad76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33519
50436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3351950436
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.15249794
Short name T630
Test name
Test status
Simulation time 8398270029 ps
CPU time 9.74 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:33 PM PDT 24
Peak memory 204168 kb
Host smart-a040fba9-f2c1-41fa-8ab1-c3eadde78417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.15249794
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1098528413
Short name T587
Test name
Test status
Simulation time 8396679000 ps
CPU time 8.32 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204292 kb
Host smart-24a93c6a-d504-488c-a1a2-3c185718b7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985
28413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1098528413
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2710025136
Short name T331
Test name
Test status
Simulation time 8401909592 ps
CPU time 8.12 seconds
Started Apr 30 02:49:26 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204076 kb
Host smart-39e3c24e-da50-4781-82c5-cf2f15efbb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27100
25136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2710025136
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.179132137
Short name T564
Test name
Test status
Simulation time 8386848118 ps
CPU time 8.14 seconds
Started Apr 30 02:49:22 PM PDT 24
Finished Apr 30 02:49:31 PM PDT 24
Peak memory 204020 kb
Host smart-719c3ccf-4a1d-4765-9b85-a28f9d89fb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
2137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.179132137
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3504440793
Short name T588
Test name
Test status
Simulation time 8486419077 ps
CPU time 7.83 seconds
Started Apr 30 02:49:28 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204152 kb
Host smart-66ed0363-2597-4cd4-a7e7-9c8fd69420bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3504440793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3504440793
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.781471684
Short name T413
Test name
Test status
Simulation time 8384476328 ps
CPU time 10.56 seconds
Started Apr 30 02:49:28 PM PDT 24
Finished Apr 30 02:49:39 PM PDT 24
Peak memory 204124 kb
Host smart-85e0a6ae-cec9-48da-a62f-3ad4a388bbd1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=781471684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.781471684
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.169013176
Short name T332
Test name
Test status
Simulation time 8425721712 ps
CPU time 9.23 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:39 PM PDT 24
Peak memory 204132 kb
Host smart-fbff8301-8a18-4c8e-b17f-11838f65203e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16901
3176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.169013176
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.4028317496
Short name T464
Test name
Test status
Simulation time 8383960213 ps
CPU time 7.67 seconds
Started Apr 30 02:49:27 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204096 kb
Host smart-e50960d8-8ddf-4e40-bc45-100d72c59b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40283
17496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.4028317496
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.2931096740
Short name T1249
Test name
Test status
Simulation time 8373822325 ps
CPU time 8.39 seconds
Started Apr 30 02:49:40 PM PDT 24
Finished Apr 30 02:49:49 PM PDT 24
Peak memory 204080 kb
Host smart-b7adb472-905d-40ff-85cf-970175605816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
96740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2931096740
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3098487154
Short name T576
Test name
Test status
Simulation time 110520755 ps
CPU time 1.23 seconds
Started Apr 30 02:49:24 PM PDT 24
Finished Apr 30 02:49:26 PM PDT 24
Peak memory 204216 kb
Host smart-e73afa6c-62d7-4f5b-a0b4-003ee7a29064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
87154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3098487154
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1458793010
Short name T1180
Test name
Test status
Simulation time 8396729359 ps
CPU time 10.18 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:40 PM PDT 24
Peak memory 204052 kb
Host smart-8d7e1e3f-6bca-45ea-a95c-f075dfa33a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587
93010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1458793010
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3307625767
Short name T815
Test name
Test status
Simulation time 8368039382 ps
CPU time 8.49 seconds
Started Apr 30 02:49:27 PM PDT 24
Finished Apr 30 02:49:36 PM PDT 24
Peak memory 204152 kb
Host smart-23421dd4-3951-4bd0-86a4-c4941e38d1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33076
25767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3307625767
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3005426395
Short name T1370
Test name
Test status
Simulation time 8420147405 ps
CPU time 7.99 seconds
Started Apr 30 02:49:23 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204100 kb
Host smart-f079037e-fdb7-49de-a573-65b2cf4d99ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30054
26395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3005426395
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1077593622
Short name T708
Test name
Test status
Simulation time 8418917049 ps
CPU time 7.36 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204132 kb
Host smart-7e564d8b-ce22-4443-bd51-ca8b9646a550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
93622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1077593622
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3497975683
Short name T956
Test name
Test status
Simulation time 8372408257 ps
CPU time 8.29 seconds
Started Apr 30 02:49:41 PM PDT 24
Finished Apr 30 02:49:50 PM PDT 24
Peak memory 204132 kb
Host smart-735f07f3-226a-453c-9568-98be0c76dd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34979
75683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3497975683
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.286129575
Short name T125
Test name
Test status
Simulation time 8458176793 ps
CPU time 7.98 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:44 PM PDT 24
Peak memory 204080 kb
Host smart-43f85b45-43b4-4d7e-8cb4-9953606b8a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28612
9575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.286129575
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.829827034
Short name T958
Test name
Test status
Simulation time 8417368793 ps
CPU time 8.74 seconds
Started Apr 30 02:49:28 PM PDT 24
Finished Apr 30 02:49:37 PM PDT 24
Peak memory 204112 kb
Host smart-ee662379-cd69-4171-84ed-508048f48a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82982
7034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.829827034
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1306492989
Short name T1217
Test name
Test status
Simulation time 8378948186 ps
CPU time 9.03 seconds
Started Apr 30 02:49:28 PM PDT 24
Finished Apr 30 02:49:38 PM PDT 24
Peak memory 204056 kb
Host smart-1a56ad35-2a76-48dc-be3d-57cdf6feee8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
92989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1306492989
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1225932836
Short name T194
Test name
Test status
Simulation time 8427892897 ps
CPU time 8.22 seconds
Started Apr 30 02:49:31 PM PDT 24
Finished Apr 30 02:49:40 PM PDT 24
Peak memory 204044 kb
Host smart-6433f2bb-fb48-4959-9c8b-79c37bf15d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
32836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1225932836
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1528432738
Short name T1292
Test name
Test status
Simulation time 8378727916 ps
CPU time 9.04 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204132 kb
Host smart-1355eb67-c671-4736-8b9d-a21f8ed1c4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15284
32738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1528432738
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3094572539
Short name T596
Test name
Test status
Simulation time 69887305 ps
CPU time 0.68 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:38 PM PDT 24
Peak memory 203968 kb
Host smart-4309f298-40ca-4acb-990b-d5dc404e7015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30945
72539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3094572539
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.696645405
Short name T221
Test name
Test status
Simulation time 27751077909 ps
CPU time 62.21 seconds
Started Apr 30 02:50:05 PM PDT 24
Finished Apr 30 02:51:08 PM PDT 24
Peak memory 204412 kb
Host smart-d42b31f1-644e-4077-b927-33b596e92d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69664
5405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.696645405
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2576978896
Short name T736
Test name
Test status
Simulation time 8396327303 ps
CPU time 8.23 seconds
Started Apr 30 02:49:42 PM PDT 24
Finished Apr 30 02:49:50 PM PDT 24
Peak memory 204132 kb
Host smart-11f6af2a-a295-4402-bcde-213f68be9d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769
78896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2576978896
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3558212720
Short name T386
Test name
Test status
Simulation time 8441738837 ps
CPU time 8.12 seconds
Started Apr 30 02:49:39 PM PDT 24
Finished Apr 30 02:49:49 PM PDT 24
Peak memory 204120 kb
Host smart-b9f858c7-db89-406e-bf0a-28889b0e3ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582
12720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3558212720
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.4213266927
Short name T718
Test name
Test status
Simulation time 8415131604 ps
CPU time 7.69 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204124 kb
Host smart-78232676-4805-4dc6-890a-01a69f2b1188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42132
66927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.4213266927
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3114679226
Short name T1170
Test name
Test status
Simulation time 8377522901 ps
CPU time 7.62 seconds
Started Apr 30 02:49:31 PM PDT 24
Finished Apr 30 02:49:39 PM PDT 24
Peak memory 204064 kb
Host smart-4dced138-d834-4844-a207-5366bd72ea11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31146
79226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3114679226
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1467296915
Short name T366
Test name
Test status
Simulation time 8368048426 ps
CPU time 9.22 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:58 PM PDT 24
Peak memory 204124 kb
Host smart-b23eef75-76a1-40de-b015-e3231eaf524d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14672
96915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1467296915
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2514283517
Short name T506
Test name
Test status
Simulation time 8429068885 ps
CPU time 7.98 seconds
Started Apr 30 02:49:33 PM PDT 24
Finished Apr 30 02:49:41 PM PDT 24
Peak memory 204136 kb
Host smart-29c59d5c-7453-417d-9cd1-b16d9b75a7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142
83517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2514283517
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3388574289
Short name T841
Test name
Test status
Simulation time 8427005548 ps
CPU time 8.5 seconds
Started Apr 30 02:49:40 PM PDT 24
Finished Apr 30 02:49:49 PM PDT 24
Peak memory 204132 kb
Host smart-96446e41-1bc9-4f07-882f-d7ff9d971f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885
74289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3388574289
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.61471002
Short name T374
Test name
Test status
Simulation time 8424351499 ps
CPU time 10.04 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:40 PM PDT 24
Peak memory 204124 kb
Host smart-6c56177a-fedc-4e1c-854f-214fdc413ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61471
002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.61471002
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.590497876
Short name T443
Test name
Test status
Simulation time 8462990852 ps
CPU time 7.59 seconds
Started Apr 30 02:49:53 PM PDT 24
Finished Apr 30 02:50:02 PM PDT 24
Peak memory 204100 kb
Host smart-096b95ee-8f15-4d68-939c-2d25b9dd3f41
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=590497876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.590497876
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.3827646802
Short name T678
Test name
Test status
Simulation time 8387398769 ps
CPU time 8.91 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:46 PM PDT 24
Peak memory 204064 kb
Host smart-1e400efb-793a-4197-85e9-e42ba112d2cf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3827646802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.3827646802
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.827716912
Short name T643
Test name
Test status
Simulation time 8431483599 ps
CPU time 7.87 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204088 kb
Host smart-1cbc8917-1f89-4246-82a0-13c4f0fb1ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82771
6912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.827716912
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.991807967
Short name T1197
Test name
Test status
Simulation time 8373726626 ps
CPU time 7.95 seconds
Started Apr 30 02:49:30 PM PDT 24
Finished Apr 30 02:49:39 PM PDT 24
Peak memory 204156 kb
Host smart-a675801e-c70d-427a-b029-586832ef9f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99180
7967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.991807967
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.4149675202
Short name T1229
Test name
Test status
Simulation time 8407797790 ps
CPU time 7.73 seconds
Started Apr 30 02:49:38 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 204116 kb
Host smart-16256ef7-c308-4e63-92b7-13454632ab45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41496
75202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.4149675202
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3064427691
Short name T798
Test name
Test status
Simulation time 319702906 ps
CPU time 2.67 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:32 PM PDT 24
Peak memory 204144 kb
Host smart-50fc10ba-02e9-48fc-a4f8-fcd0b619701c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30644
27691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3064427691
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1913232271
Short name T605
Test name
Test status
Simulation time 8445650875 ps
CPU time 7.66 seconds
Started Apr 30 02:49:46 PM PDT 24
Finished Apr 30 02:49:54 PM PDT 24
Peak memory 204104 kb
Host smart-a8ff9c17-1b89-49cf-8cd8-a6168a773d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
32271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1913232271
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.904676730
Short name T1071
Test name
Test status
Simulation time 8371305355 ps
CPU time 9.12 seconds
Started Apr 30 02:49:50 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204072 kb
Host smart-daea0367-1e3a-4f39-a529-ba03d0d32481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90467
6730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.904676730
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.176097191
Short name T412
Test name
Test status
Simulation time 8433450865 ps
CPU time 8.67 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204116 kb
Host smart-18997361-38b0-4cc8-b8e9-efd1d8045149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.176097191
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2054942308
Short name T617
Test name
Test status
Simulation time 8425140727 ps
CPU time 8.23 seconds
Started Apr 30 02:49:34 PM PDT 24
Finished Apr 30 02:49:42 PM PDT 24
Peak memory 204020 kb
Host smart-0857e43b-28d8-4ef4-a280-72bc794fe35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20549
42308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2054942308
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1855853916
Short name T948
Test name
Test status
Simulation time 8368651701 ps
CPU time 9.14 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:39 PM PDT 24
Peak memory 204076 kb
Host smart-46ab09d1-c7bf-41d5-a737-356f007d398c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18558
53916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1855853916
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.65279099
Short name T102
Test name
Test status
Simulation time 8437929460 ps
CPU time 8.06 seconds
Started Apr 30 02:49:29 PM PDT 24
Finished Apr 30 02:49:38 PM PDT 24
Peak memory 204084 kb
Host smart-39aa6d38-24d8-436f-a01b-dde0e634d560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65279
099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.65279099
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3144738283
Short name T893
Test name
Test status
Simulation time 8405371858 ps
CPU time 8.41 seconds
Started Apr 30 02:49:30 PM PDT 24
Finished Apr 30 02:49:40 PM PDT 24
Peak memory 204080 kb
Host smart-0d88f193-a6ca-4747-9e3a-29516c389959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31447
38283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3144738283
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1974758727
Short name T73
Test name
Test status
Simulation time 8399593088 ps
CPU time 8.11 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:54 PM PDT 24
Peak memory 204144 kb
Host smart-a81be3c7-c73c-43de-8095-fd5d27d78d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19747
58727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1974758727
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1658981920
Short name T915
Test name
Test status
Simulation time 8377243744 ps
CPU time 7.75 seconds
Started Apr 30 02:49:52 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 203972 kb
Host smart-bcfc44fa-cb1c-46f9-82a9-442b32f4f8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16589
81920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1658981920
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3446852399
Short name T362
Test name
Test status
Simulation time 8370475559 ps
CPU time 7.56 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204116 kb
Host smart-42427e0f-e995-4264-b974-e055d4cdbd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34468
52399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3446852399
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.932609035
Short name T566
Test name
Test status
Simulation time 40972343 ps
CPU time 0.65 seconds
Started Apr 30 02:49:54 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204016 kb
Host smart-de5fa09d-8544-4248-ae0b-6b647ba1fc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93260
9035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.932609035
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.387856405
Short name T1260
Test name
Test status
Simulation time 19814234720 ps
CPU time 37.47 seconds
Started Apr 30 02:49:38 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204332 kb
Host smart-e3b244f2-3aea-4427-bc84-e333e3f937d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38785
6405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.387856405
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3020949668
Short name T873
Test name
Test status
Simulation time 8384894615 ps
CPU time 7.53 seconds
Started Apr 30 02:49:40 PM PDT 24
Finished Apr 30 02:49:48 PM PDT 24
Peak memory 204104 kb
Host smart-754d7cd3-9983-46af-85aa-2e56b910a834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30209
49668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3020949668
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.166655321
Short name T286
Test name
Test status
Simulation time 8428121166 ps
CPU time 7.91 seconds
Started Apr 30 02:49:46 PM PDT 24
Finished Apr 30 02:49:55 PM PDT 24
Peak memory 204124 kb
Host smart-c0102e86-2d49-4793-95c1-c606a85575e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16665
5321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.166655321
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1392750327
Short name T668
Test name
Test status
Simulation time 8396231064 ps
CPU time 10.73 seconds
Started Apr 30 02:49:37 PM PDT 24
Finished Apr 30 02:49:49 PM PDT 24
Peak memory 204112 kb
Host smart-61343aa7-2994-4fcd-b7fb-eb0bc91daddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
50327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1392750327
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.920422258
Short name T172
Test name
Test status
Simulation time 8390441039 ps
CPU time 7.64 seconds
Started Apr 30 02:49:37 PM PDT 24
Finished Apr 30 02:49:46 PM PDT 24
Peak memory 204124 kb
Host smart-fd707425-6720-4cbf-91f4-76de0191e077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92042
2258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.920422258
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4086927281
Short name T848
Test name
Test status
Simulation time 8397494586 ps
CPU time 10.21 seconds
Started Apr 30 02:49:46 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204100 kb
Host smart-a3fac8e3-21cb-40e4-8e24-e9c6b21a7c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40869
27281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4086927281
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3090589503
Short name T531
Test name
Test status
Simulation time 8417774430 ps
CPU time 7.36 seconds
Started Apr 30 02:49:30 PM PDT 24
Finished Apr 30 02:49:38 PM PDT 24
Peak memory 204052 kb
Host smart-1b97d68b-b63a-467e-801c-d285bc5bde20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
89503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3090589503
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.4260719265
Short name T877
Test name
Test status
Simulation time 8381458270 ps
CPU time 8.01 seconds
Started Apr 30 02:49:40 PM PDT 24
Finished Apr 30 02:49:49 PM PDT 24
Peak memory 204048 kb
Host smart-9d92cd90-6441-4836-900c-de6c2c70f596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42607
19265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.4260719265
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.555543252
Short name T1274
Test name
Test status
Simulation time 8375254138 ps
CPU time 8.39 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:54 PM PDT 24
Peak memory 204128 kb
Host smart-b5d085c1-88c1-48c7-a6be-3e977d88dc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55554
3252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.555543252
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.4150448003
Short name T885
Test name
Test status
Simulation time 8468818743 ps
CPU time 7.9 seconds
Started Apr 30 02:49:37 PM PDT 24
Finished Apr 30 02:49:46 PM PDT 24
Peak memory 204084 kb
Host smart-34c87261-30c6-4032-b0a4-703551691309
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4150448003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.4150448003
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.2386744650
Short name T968
Test name
Test status
Simulation time 8384350427 ps
CPU time 7.37 seconds
Started Apr 30 02:49:38 PM PDT 24
Finished Apr 30 02:49:52 PM PDT 24
Peak memory 204056 kb
Host smart-b3dd9051-d900-46a3-b281-ff6a360bdb4e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2386744650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.2386744650
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.170228187
Short name T328
Test name
Test status
Simulation time 8447223570 ps
CPU time 8.6 seconds
Started Apr 30 02:49:54 PM PDT 24
Finished Apr 30 02:50:03 PM PDT 24
Peak memory 204144 kb
Host smart-76db505f-a7ea-4a81-b2fd-7e873c3ba606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
8187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.170228187
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3310695333
Short name T1069
Test name
Test status
Simulation time 8373710592 ps
CPU time 9.79 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204124 kb
Host smart-46bcfd00-2e38-45e3-a2d6-b88e5c991348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106
95333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3310695333
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.1339085097
Short name T336
Test name
Test status
Simulation time 8376981009 ps
CPU time 7.59 seconds
Started Apr 30 02:49:41 PM PDT 24
Finished Apr 30 02:49:49 PM PDT 24
Peak memory 204072 kb
Host smart-4fde2ff0-ac58-4197-9763-b4f203f7a093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390
85097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1339085097
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3831382611
Short name T1345
Test name
Test status
Simulation time 202151027 ps
CPU time 1.83 seconds
Started Apr 30 02:49:40 PM PDT 24
Finished Apr 30 02:49:43 PM PDT 24
Peak memory 204188 kb
Host smart-dd88c1a7-38de-4834-a1a3-0ede3a66fea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38313
82611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3831382611
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3801053125
Short name T511
Test name
Test status
Simulation time 8437415275 ps
CPU time 8.45 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:09 PM PDT 24
Peak memory 204112 kb
Host smart-73117213-2cd3-490f-b92c-e6ff100d79ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38010
53125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3801053125
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1932273249
Short name T184
Test name
Test status
Simulation time 8375227968 ps
CPU time 7.88 seconds
Started Apr 30 02:49:38 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 204052 kb
Host smart-ddd5863d-8a1d-48b8-b382-59c8ef878e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
73249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1932273249
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1771082751
Short name T45
Test name
Test status
Simulation time 8403535097 ps
CPU time 8.67 seconds
Started Apr 30 02:49:51 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204108 kb
Host smart-72288911-f3d1-484f-9ba6-00a83d473da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17710
82751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1771082751
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1396817242
Short name T731
Test name
Test status
Simulation time 8423398696 ps
CPU time 7.64 seconds
Started Apr 30 02:49:39 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 203992 kb
Host smart-499cc8bb-5889-4bf2-92fa-9982ef3528d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968
17242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1396817242
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4125279123
Short name T1304
Test name
Test status
Simulation time 8386309048 ps
CPU time 8.66 seconds
Started Apr 30 02:49:56 PM PDT 24
Finished Apr 30 02:50:05 PM PDT 24
Peak memory 204064 kb
Host smart-2d485564-1678-4d14-8f62-e19290ac7905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41252
79123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4125279123
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3932442547
Short name T121
Test name
Test status
Simulation time 8452561204 ps
CPU time 8.73 seconds
Started Apr 30 02:49:51 PM PDT 24
Finished Apr 30 02:50:01 PM PDT 24
Peak memory 204124 kb
Host smart-2ef672e0-56cf-4498-bf6b-230f7ea8cd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39324
42547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3932442547
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1424868504
Short name T930
Test name
Test status
Simulation time 8411496507 ps
CPU time 8.23 seconds
Started Apr 30 02:49:51 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204120 kb
Host smart-670b7273-7a0e-4236-bb69-ed2f58a27f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14248
68504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1424868504
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1003876632
Short name T1131
Test name
Test status
Simulation time 8386952994 ps
CPU time 9.37 seconds
Started Apr 30 02:49:37 PM PDT 24
Finished Apr 30 02:49:48 PM PDT 24
Peak memory 204136 kb
Host smart-78ebc974-e3b8-4ce4-80d2-963cd2951b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
76632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1003876632
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3235514751
Short name T153
Test name
Test status
Simulation time 8451965929 ps
CPU time 7.32 seconds
Started Apr 30 02:49:52 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204108 kb
Host smart-86e666db-0cf0-43e1-9338-5ca4ee650776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32355
14751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3235514751
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.850436217
Short name T577
Test name
Test status
Simulation time 8368267064 ps
CPU time 8.03 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204144 kb
Host smart-39153075-ed9a-4fb6-a770-94b778f4552c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85043
6217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.850436217
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.613473992
Short name T421
Test name
Test status
Simulation time 36868504 ps
CPU time 0.62 seconds
Started Apr 30 02:49:46 PM PDT 24
Finished Apr 30 02:49:48 PM PDT 24
Peak memory 203880 kb
Host smart-e7420269-df0a-4ab6-8a72-423ea933f7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61347
3992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.613473992
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1940363003
Short name T670
Test name
Test status
Simulation time 16839440503 ps
CPU time 32.76 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204428 kb
Host smart-555b00d1-160f-4849-b455-4f35c87e75c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19403
63003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1940363003
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1446484017
Short name T290
Test name
Test status
Simulation time 8430139857 ps
CPU time 7.76 seconds
Started Apr 30 02:49:39 PM PDT 24
Finished Apr 30 02:49:48 PM PDT 24
Peak memory 204144 kb
Host smart-aaee6117-1335-42b7-bfca-cc9a0946f889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
84017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1446484017
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1794593161
Short name T1027
Test name
Test status
Simulation time 8429371886 ps
CPU time 7.7 seconds
Started Apr 30 02:49:47 PM PDT 24
Finished Apr 30 02:49:55 PM PDT 24
Peak memory 204108 kb
Host smart-b227089a-4bc9-4ca7-b671-9cc6092b70a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
93161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1794593161
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2587196350
Short name T1080
Test name
Test status
Simulation time 8377826424 ps
CPU time 7.87 seconds
Started Apr 30 02:49:36 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204108 kb
Host smart-64f85fbb-4158-4de6-9c85-a6b2fbdeb9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25871
96350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2587196350
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3006769029
Short name T1321
Test name
Test status
Simulation time 8407393146 ps
CPU time 8.12 seconds
Started Apr 30 02:49:37 PM PDT 24
Finished Apr 30 02:49:46 PM PDT 24
Peak memory 204148 kb
Host smart-9cacf493-a345-4e78-b147-6462f6092f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
69029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3006769029
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1689758342
Short name T339
Test name
Test status
Simulation time 8376805155 ps
CPU time 8.11 seconds
Started Apr 30 02:49:38 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 204076 kb
Host smart-965bbca0-77cb-4145-ac98-79413924e789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16897
58342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1689758342
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.981821850
Short name T1231
Test name
Test status
Simulation time 8487020474 ps
CPU time 7.84 seconds
Started Apr 30 02:49:37 PM PDT 24
Finished Apr 30 02:49:45 PM PDT 24
Peak memory 204068 kb
Host smart-f3616fb1-4121-43d0-b30f-df10805aba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98182
1850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.981821850
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2261294754
Short name T1049
Test name
Test status
Simulation time 8393265661 ps
CPU time 7.66 seconds
Started Apr 30 02:49:44 PM PDT 24
Finished Apr 30 02:49:52 PM PDT 24
Peak memory 203984 kb
Host smart-94f66f30-0002-40f6-97dc-f0fa5ddec7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
94754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2261294754
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2323228012
Short name T583
Test name
Test status
Simulation time 8429858718 ps
CPU time 7.62 seconds
Started Apr 30 02:49:49 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204124 kb
Host smart-e8d7a54a-9efa-4b44-9c60-6aa4761e1212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
28012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2323228012
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.218322603
Short name T411
Test name
Test status
Simulation time 8481748724 ps
CPU time 8.17 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:54 PM PDT 24
Peak memory 204052 kb
Host smart-2aecc4ae-dcf3-47a7-b320-c765d4ac14f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=218322603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.218322603
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.3295193028
Short name T1146
Test name
Test status
Simulation time 8382919683 ps
CPU time 8.08 seconds
Started Apr 30 02:49:50 PM PDT 24
Finished Apr 30 02:49:59 PM PDT 24
Peak memory 204040 kb
Host smart-8b53f408-6e1d-4473-9232-ea7ad142ae9a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3295193028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.3295193028
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.3852419611
Short name T371
Test name
Test status
Simulation time 8418272477 ps
CPU time 9.12 seconds
Started Apr 30 02:49:47 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204140 kb
Host smart-93f7bcbe-86ba-4b91-a110-0a9b864bef94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38524
19611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.3852419611
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1820069654
Short name T946
Test name
Test status
Simulation time 8387372002 ps
CPU time 9.81 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204124 kb
Host smart-619311d1-8373-4480-accd-ed2efcef5713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18200
69654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1820069654
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.2926082021
Short name T207
Test name
Test status
Simulation time 8373844006 ps
CPU time 7.86 seconds
Started Apr 30 02:49:49 PM PDT 24
Finished Apr 30 02:49:58 PM PDT 24
Peak memory 204088 kb
Host smart-d87a1fa8-e204-4d0e-be80-ab25cf588560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29260
82021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2926082021
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3035298210
Short name T1161
Test name
Test status
Simulation time 222338752 ps
CPU time 2.35 seconds
Started Apr 30 02:49:44 PM PDT 24
Finished Apr 30 02:49:47 PM PDT 24
Peak memory 204212 kb
Host smart-64d20cb9-9ce1-464d-865f-de518b55261c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
98210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3035298210
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2320988349
Short name T473
Test name
Test status
Simulation time 8462052139 ps
CPU time 7.93 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:54 PM PDT 24
Peak memory 204080 kb
Host smart-85dbfedd-e03b-4f46-b654-6c37758402dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23209
88349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2320988349
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2957756471
Short name T192
Test name
Test status
Simulation time 8367253335 ps
CPU time 8.15 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204084 kb
Host smart-57415acc-3546-4a54-b67b-f1a381922c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
56471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2957756471
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.4136212170
Short name T129
Test name
Test status
Simulation time 8457490267 ps
CPU time 7.64 seconds
Started Apr 30 02:49:46 PM PDT 24
Finished Apr 30 02:49:54 PM PDT 24
Peak memory 204156 kb
Host smart-e6868657-413b-4c8f-bc07-974998172f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41362
12170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.4136212170
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3498944771
Short name T1344
Test name
Test status
Simulation time 8421229519 ps
CPU time 8.42 seconds
Started Apr 30 02:49:46 PM PDT 24
Finished Apr 30 02:49:55 PM PDT 24
Peak memory 204084 kb
Host smart-3a868da6-ed66-41a5-bf54-ec213d9f872e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34989
44771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3498944771
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2623228432
Short name T644
Test name
Test status
Simulation time 8373519424 ps
CPU time 8.26 seconds
Started Apr 30 02:49:56 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204080 kb
Host smart-9070d6fb-4001-477e-af72-1b24d22392f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26232
28432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2623228432
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3454079961
Short name T492
Test name
Test status
Simulation time 8370418966 ps
CPU time 7.82 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204132 kb
Host smart-cc521f7f-8b20-4676-9fd9-838d486c6d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34540
79961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3454079961
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.326904725
Short name T1155
Test name
Test status
Simulation time 8386022364 ps
CPU time 7.64 seconds
Started Apr 30 02:49:54 PM PDT 24
Finished Apr 30 02:50:02 PM PDT 24
Peak memory 204092 kb
Host smart-99208e25-c942-477c-8e3c-4e833ae7a2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690
4725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.326904725
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.420096780
Short name T177
Test name
Test status
Simulation time 8421155140 ps
CPU time 8.06 seconds
Started Apr 30 02:49:45 PM PDT 24
Finished Apr 30 02:49:53 PM PDT 24
Peak memory 204108 kb
Host smart-bbea4645-2675-49ef-8910-3ec4b2f70718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42009
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.420096780
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.510061913
Short name T918
Test name
Test status
Simulation time 8362513640 ps
CPU time 7.82 seconds
Started Apr 30 02:49:49 PM PDT 24
Finished Apr 30 02:49:57 PM PDT 24
Peak memory 204072 kb
Host smart-9fa265a2-b7fc-4852-85ef-cdbffd335efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51006
1913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.510061913
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2852722937
Short name T1306
Test name
Test status
Simulation time 102457695 ps
CPU time 0.75 seconds
Started Apr 30 02:49:55 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204164 kb
Host smart-22bf6a14-75a3-4ee0-ab1f-05bafb738580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
22937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2852722937
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.553105853
Short name T591
Test name
Test status
Simulation time 16531578171 ps
CPU time 28.03 seconds
Started Apr 30 02:49:49 PM PDT 24
Finished Apr 30 02:50:18 PM PDT 24
Peak memory 204304 kb
Host smart-f879be2d-9125-49a3-a8b2-79d8fae5fe02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55310
5853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.553105853
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3979032888
Short name T1311
Test name
Test status
Simulation time 8385184405 ps
CPU time 8.5 seconds
Started Apr 30 02:49:59 PM PDT 24
Finished Apr 30 02:50:08 PM PDT 24
Peak memory 204088 kb
Host smart-ebca75cf-d1a1-4754-b174-5df5a86e2f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39790
32888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3979032888
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2649425771
Short name T1372
Test name
Test status
Simulation time 8417574552 ps
CPU time 8.65 seconds
Started Apr 30 02:49:49 PM PDT 24
Finished Apr 30 02:49:59 PM PDT 24
Peak memory 204124 kb
Host smart-7c98cd42-3c06-4dd4-be00-f4b0fa9dda37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
25771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2649425771
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.618822487
Short name T284
Test name
Test status
Simulation time 8377392271 ps
CPU time 9.44 seconds
Started Apr 30 02:50:03 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204092 kb
Host smart-d956e089-28c0-4766-92f9-8ccef2a5a0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61882
2487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.618822487
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4110538594
Short name T1009
Test name
Test status
Simulation time 8388745309 ps
CPU time 7.88 seconds
Started Apr 30 02:49:48 PM PDT 24
Finished Apr 30 02:49:56 PM PDT 24
Peak memory 204072 kb
Host smart-9c804c39-4ba8-4391-88ff-e280b3f355b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41105
38594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4110538594
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1091962473
Short name T1322
Test name
Test status
Simulation time 8369640463 ps
CPU time 8.42 seconds
Started Apr 30 02:49:43 PM PDT 24
Finished Apr 30 02:49:52 PM PDT 24
Peak memory 204080 kb
Host smart-3b4fd243-f4cc-45af-9fe4-7823d7b35b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10919
62473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1091962473
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1301956712
Short name T137
Test name
Test status
Simulation time 8472897255 ps
CPU time 7.85 seconds
Started Apr 30 02:49:44 PM PDT 24
Finished Apr 30 02:49:52 PM PDT 24
Peak memory 204128 kb
Host smart-e8dd1566-b406-4a19-8aeb-359f656af8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13019
56712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1301956712
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3523487782
Short name T781
Test name
Test status
Simulation time 8371552669 ps
CPU time 8.2 seconds
Started Apr 30 02:49:42 PM PDT 24
Finished Apr 30 02:49:51 PM PDT 24
Peak memory 204048 kb
Host smart-dc9f28a7-7c01-4bd9-9357-371f8fd12082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35234
87782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3523487782
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1553035512
Short name T70
Test name
Test status
Simulation time 8418644617 ps
CPU time 8.38 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204132 kb
Host smart-601c33ce-e758-4385-9088-be13cee9742d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530
35512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1553035512
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3313717513
Short name T38
Test name
Test status
Simulation time 8468606506 ps
CPU time 7.85 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:03 PM PDT 24
Peak memory 204124 kb
Host smart-6d120af9-5c8f-4de3-9940-b7075cbd398b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3313717513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3313717513
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.3239081293
Short name T646
Test name
Test status
Simulation time 8385041108 ps
CPU time 8.04 seconds
Started Apr 30 02:46:59 PM PDT 24
Finished Apr 30 02:47:08 PM PDT 24
Peak memory 204064 kb
Host smart-cc891547-7b79-4bac-82fb-71c5662a9c1e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3239081293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.3239081293
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.4081172458
Short name T1002
Test name
Test status
Simulation time 8407189495 ps
CPU time 7.53 seconds
Started Apr 30 02:47:03 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204104 kb
Host smart-f1ed8ed1-0e1b-4075-b1f7-715efd6fd1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
72458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.4081172458
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3192317530
Short name T458
Test name
Test status
Simulation time 8400955199 ps
CPU time 8.79 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 204088 kb
Host smart-d4b155a9-9800-4a18-b0c2-124faa463041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31923
17530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3192317530
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1798456135
Short name T1164
Test name
Test status
Simulation time 8378864086 ps
CPU time 9.02 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:04 PM PDT 24
Peak memory 204108 kb
Host smart-c11fc6a8-9a47-4484-9a26-b24aba01be7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17984
56135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1798456135
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.687383672
Short name T46
Test name
Test status
Simulation time 75270016 ps
CPU time 1.93 seconds
Started Apr 30 02:46:53 PM PDT 24
Finished Apr 30 02:46:55 PM PDT 24
Peak memory 204200 kb
Host smart-9805e4c6-3bcd-4dc1-9aac-6e03eb7d5d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68738
3672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.687383672
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2969923591
Short name T1154
Test name
Test status
Simulation time 8421895994 ps
CPU time 10.58 seconds
Started Apr 30 02:46:53 PM PDT 24
Finished Apr 30 02:47:05 PM PDT 24
Peak memory 204080 kb
Host smart-013cc086-374d-4290-8bf5-2f4b6a1abd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29699
23591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2969923591
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3943088545
Short name T1174
Test name
Test status
Simulation time 8361139417 ps
CPU time 8.37 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:03 PM PDT 24
Peak memory 204104 kb
Host smart-4c3fdd99-c342-479e-acf1-7edcc104d633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39430
88545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3943088545
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3399630034
Short name T485
Test name
Test status
Simulation time 8419720535 ps
CPU time 10.3 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:47:02 PM PDT 24
Peak memory 204068 kb
Host smart-3e0a29ce-3038-4e11-85b3-fcafff3574db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
30034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3399630034
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3431176733
Short name T683
Test name
Test status
Simulation time 8433418300 ps
CPU time 10 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:47:02 PM PDT 24
Peak memory 204080 kb
Host smart-cec71c77-df30-4d0e-94f6-d337330c9a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
76733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3431176733
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.590245448
Short name T816
Test name
Test status
Simulation time 8373443846 ps
CPU time 7.65 seconds
Started Apr 30 02:46:52 PM PDT 24
Finished Apr 30 02:47:01 PM PDT 24
Peak memory 204104 kb
Host smart-6bc555ee-c857-41fd-9167-f025f0ff58fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59024
5448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.590245448
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3219440304
Short name T1252
Test name
Test status
Simulation time 8435791352 ps
CPU time 8.28 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:47:01 PM PDT 24
Peak memory 204064 kb
Host smart-8ce9c3ce-6753-443d-89c1-54bd4f70bf88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32194
40304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3219440304
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2815631658
Short name T340
Test name
Test status
Simulation time 8470272632 ps
CPU time 7.74 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:58 PM PDT 24
Peak memory 204068 kb
Host smart-4c7c0260-44aa-4a55-89bc-eb3542b039bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
31658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2815631658
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2813930238
Short name T1337
Test name
Test status
Simulation time 8383859880 ps
CPU time 7.93 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:03 PM PDT 24
Peak memory 204076 kb
Host smart-ccde7a7a-1818-494e-8df0-29e26aad90c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
30238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2813930238
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1048679753
Short name T684
Test name
Test status
Simulation time 8413901386 ps
CPU time 8.78 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:04 PM PDT 24
Peak memory 204292 kb
Host smart-3158a1a7-e6b2-497b-83b5-a8a98ea3aa2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
79753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1048679753
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2832837549
Short name T637
Test name
Test status
Simulation time 8375390589 ps
CPU time 9.39 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204140 kb
Host smart-0dcae8c2-54e2-46ce-aad8-e71ef700face
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
37549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2832837549
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3591222901
Short name T416
Test name
Test status
Simulation time 38470846 ps
CPU time 0.66 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:46:55 PM PDT 24
Peak memory 203976 kb
Host smart-deaca841-f16e-488e-ab7a-0a2c96d75953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
22901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3591222901
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.615336561
Short name T1219
Test name
Test status
Simulation time 22799701800 ps
CPU time 44.72 seconds
Started Apr 30 02:46:51 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204352 kb
Host smart-d60e5a3c-93a8-487b-b4af-ddfd8ecdd203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61533
6561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.615336561
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.111461173
Short name T437
Test name
Test status
Simulation time 8412654770 ps
CPU time 8.33 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204052 kb
Host smart-3670650a-899f-4978-934c-77a914fddda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11146
1173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.111461173
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3390745860
Short name T824
Test name
Test status
Simulation time 8457856988 ps
CPU time 8.14 seconds
Started Apr 30 02:46:50 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204100 kb
Host smart-9bbdd36a-6b66-49f0-8620-ec14b6f1c85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
45860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3390745860
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2639496130
Short name T563
Test name
Test status
Simulation time 8392620787 ps
CPU time 8.07 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 204112 kb
Host smart-7598c68f-ffc3-46b8-8d35-9c8fa0aed573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26394
96130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2639496130
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1531742212
Short name T54
Test name
Test status
Simulation time 269184627 ps
CPU time 1.1 seconds
Started Apr 30 02:46:58 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 220340 kb
Host smart-45c1c9de-2c14-4b17-ae59-bf562d49f8fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1531742212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1531742212
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1131537436
Short name T631
Test name
Test status
Simulation time 8378144358 ps
CPU time 10.11 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:47:01 PM PDT 24
Peak memory 204068 kb
Host smart-e96d1e51-6b6a-4e27-b5b8-e667ba1d7303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11315
37436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1131537436
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.4039226114
Short name T1048
Test name
Test status
Simulation time 8367276425 ps
CPU time 8.57 seconds
Started Apr 30 02:46:49 PM PDT 24
Finished Apr 30 02:46:59 PM PDT 24
Peak memory 204108 kb
Host smart-641e0719-d556-4b01-b4e2-d84553ba10c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40392
26114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.4039226114
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.265142937
Short name T519
Test name
Test status
Simulation time 8422507503 ps
CPU time 7.95 seconds
Started Apr 30 02:46:48 PM PDT 24
Finished Apr 30 02:46:57 PM PDT 24
Peak memory 204116 kb
Host smart-92cb887c-970c-4de2-83c2-3e00b0641a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
2937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.265142937
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2233573931
Short name T1179
Test name
Test status
Simulation time 8381531052 ps
CPU time 7.68 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:03 PM PDT 24
Peak memory 204288 kb
Host smart-69b7405c-2764-42b5-8960-2c2b31454681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
73931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2233573931
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.71511386
Short name T665
Test name
Test status
Simulation time 8397826268 ps
CPU time 7.46 seconds
Started Apr 30 02:46:53 PM PDT 24
Finished Apr 30 02:47:02 PM PDT 24
Peak memory 204112 kb
Host smart-05ab4c7e-4846-4f90-85bf-47ee8ebbf6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71511
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.71511386
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3598472504
Short name T849
Test name
Test status
Simulation time 8504238179 ps
CPU time 7.94 seconds
Started Apr 30 02:49:56 PM PDT 24
Finished Apr 30 02:50:05 PM PDT 24
Peak memory 204084 kb
Host smart-515112d2-31d5-4cce-992c-23e8b28c0c01
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3598472504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3598472504
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2827858606
Short name T1315
Test name
Test status
Simulation time 8382245140 ps
CPU time 8 seconds
Started Apr 30 02:49:57 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204092 kb
Host smart-98199503-5fcd-4e27-a6b0-038f594a2ade
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2827858606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2827858606
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.1030198670
Short name T610
Test name
Test status
Simulation time 8449534179 ps
CPU time 8.07 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204080 kb
Host smart-57229312-c380-4546-90f6-961485156fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
98670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.1030198670
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1703595620
Short name T220
Test name
Test status
Simulation time 8377136227 ps
CPU time 7.64 seconds
Started Apr 30 02:49:55 PM PDT 24
Finished Apr 30 02:50:04 PM PDT 24
Peak memory 204084 kb
Host smart-6b08425a-64a0-4af3-ab79-2b0b29d1dd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17035
95620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1703595620
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.3783904765
Short name T774
Test name
Test status
Simulation time 8415106134 ps
CPU time 8.51 seconds
Started Apr 30 02:50:04 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204080 kb
Host smart-4ae40216-0c67-43e6-a96e-a46bb684d641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
04765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3783904765
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2639877935
Short name T916
Test name
Test status
Simulation time 84001335 ps
CPU time 1.92 seconds
Started Apr 30 02:50:04 PM PDT 24
Finished Apr 30 02:50:07 PM PDT 24
Peak memory 204172 kb
Host smart-b75b4300-79ab-4b2b-9518-2ce51bd30772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26398
77935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2639877935
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.698887889
Short name T1076
Test name
Test status
Simulation time 8432125581 ps
CPU time 7.56 seconds
Started Apr 30 02:49:57 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204008 kb
Host smart-5e28b3cd-7a51-420f-89a5-b675e3358a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69888
7889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.698887889
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1594475075
Short name T1374
Test name
Test status
Simulation time 8369248205 ps
CPU time 7.64 seconds
Started Apr 30 02:49:52 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204076 kb
Host smart-3dcca54d-ae7f-47c7-9155-4cd1ae68a519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
75075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1594475075
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2198286577
Short name T1113
Test name
Test status
Simulation time 8422140434 ps
CPU time 7.42 seconds
Started Apr 30 02:49:55 PM PDT 24
Finished Apr 30 02:50:04 PM PDT 24
Peak memory 204112 kb
Host smart-f98a4007-7450-4281-bde6-43fe81ee891b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21982
86577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2198286577
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1967052577
Short name T534
Test name
Test status
Simulation time 8419911750 ps
CPU time 8.04 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204016 kb
Host smart-207c7067-cd00-43e5-b758-7f41ed442c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19670
52577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1967052577
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2926062061
Short name T345
Test name
Test status
Simulation time 8447698530 ps
CPU time 9.41 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:18 PM PDT 24
Peak memory 203996 kb
Host smart-1aeefb4c-6532-42f6-890a-721782f5323b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29260
62061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2926062061
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3971916216
Short name T105
Test name
Test status
Simulation time 8449170941 ps
CPU time 9.47 seconds
Started Apr 30 02:49:52 PM PDT 24
Finished Apr 30 02:50:02 PM PDT 24
Peak memory 204144 kb
Host smart-51f02060-6965-44dc-8cf1-abcd145dafb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39719
16216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3971916216
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3533278587
Short name T1368
Test name
Test status
Simulation time 8394818998 ps
CPU time 9.14 seconds
Started Apr 30 02:49:54 PM PDT 24
Finished Apr 30 02:50:04 PM PDT 24
Peak memory 204100 kb
Host smart-26316161-c114-44be-ab53-10aabac9928a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
78587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3533278587
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1314114120
Short name T809
Test name
Test status
Simulation time 8410762836 ps
CPU time 8.47 seconds
Started Apr 30 02:49:55 PM PDT 24
Finished Apr 30 02:50:04 PM PDT 24
Peak memory 204136 kb
Host smart-55889a83-1e1e-4604-8d0a-6565eda81c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13141
14120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1314114120
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.151920977
Short name T1211
Test name
Test status
Simulation time 8409504306 ps
CPU time 9.62 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:18 PM PDT 24
Peak memory 204104 kb
Host smart-c2640786-e5d5-47d5-9262-1036af6f803e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
0977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.151920977
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.503609937
Short name T1055
Test name
Test status
Simulation time 8371775156 ps
CPU time 7.86 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:09 PM PDT 24
Peak memory 204056 kb
Host smart-537492ea-b077-4c96-9ad0-cf71c47c86a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50360
9937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.503609937
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3967267784
Short name T943
Test name
Test status
Simulation time 32021297 ps
CPU time 0.62 seconds
Started Apr 30 02:49:54 PM PDT 24
Finished Apr 30 02:49:55 PM PDT 24
Peak memory 203952 kb
Host smart-5a88bad2-f87e-4aa3-98f9-8031db9b48c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39672
67784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3967267784
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3035699080
Short name T222
Test name
Test status
Simulation time 21233073233 ps
CPU time 47.77 seconds
Started Apr 30 02:49:50 PM PDT 24
Finished Apr 30 02:50:39 PM PDT 24
Peak memory 204400 kb
Host smart-6dd2ae50-e2e8-435b-bd8a-3ba0a2e06972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356
99080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3035699080
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1903571356
Short name T270
Test name
Test status
Simulation time 8441466571 ps
CPU time 9.73 seconds
Started Apr 30 02:49:50 PM PDT 24
Finished Apr 30 02:50:01 PM PDT 24
Peak memory 204140 kb
Host smart-455aba47-2e68-40e4-9256-bc4fa5edac16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19035
71356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1903571356
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.380787058
Short name T424
Test name
Test status
Simulation time 8483215645 ps
CPU time 7.51 seconds
Started Apr 30 02:49:51 PM PDT 24
Finished Apr 30 02:49:59 PM PDT 24
Peak memory 204052 kb
Host smart-3a9c2f7a-287e-45a8-976f-a50ad836a5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38078
7058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.380787058
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3743400991
Short name T555
Test name
Test status
Simulation time 8387577479 ps
CPU time 8.92 seconds
Started Apr 30 02:49:50 PM PDT 24
Finished Apr 30 02:50:00 PM PDT 24
Peak memory 204128 kb
Host smart-b372e354-763a-46cc-a35f-3fe59caab1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37434
00991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3743400991
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1339071785
Short name T1120
Test name
Test status
Simulation time 8371447630 ps
CPU time 7.53 seconds
Started Apr 30 02:49:58 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204052 kb
Host smart-4b626820-3cc9-44fb-a361-96d834465f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390
71785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1339071785
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.218977221
Short name T459
Test name
Test status
Simulation time 8388381257 ps
CPU time 8.43 seconds
Started Apr 30 02:50:09 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204144 kb
Host smart-6f2b27f8-6029-40f1-83ac-8ae45ad37549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
7221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.218977221
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1087069876
Short name T164
Test name
Test status
Simulation time 8458056972 ps
CPU time 10.34 seconds
Started Apr 30 02:49:47 PM PDT 24
Finished Apr 30 02:49:59 PM PDT 24
Peak memory 204076 kb
Host smart-85b75d3c-17e3-4cc3-be57-b79fec1a45f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870
69876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1087069876
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2761821448
Short name T1339
Test name
Test status
Simulation time 8420063048 ps
CPU time 7.9 seconds
Started Apr 30 02:49:50 PM PDT 24
Finished Apr 30 02:49:59 PM PDT 24
Peak memory 204056 kb
Host smart-8799a5d6-264b-4d31-af1a-feb7ebaf10a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
21448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2761821448
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.687281686
Short name T1203
Test name
Test status
Simulation time 8385237960 ps
CPU time 7.97 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:09 PM PDT 24
Peak memory 204096 kb
Host smart-05ae7df1-5509-4f17-ad7c-7c68e7d40c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68728
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.687281686
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.1211190897
Short name T767
Test name
Test status
Simulation time 8468946697 ps
CPU time 7.75 seconds
Started Apr 30 02:49:57 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204120 kb
Host smart-b03cc842-5b4c-4e3e-be17-0b0e4129e08d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1211190897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.1211190897
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3612219771
Short name T1135
Test name
Test status
Simulation time 8374947940 ps
CPU time 7.98 seconds
Started Apr 30 02:50:02 PM PDT 24
Finished Apr 30 02:50:11 PM PDT 24
Peak memory 204100 kb
Host smart-48a64f11-c0f6-43dc-810a-9fa05bc4337b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3612219771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3612219771
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.3182338802
Short name T817
Test name
Test status
Simulation time 8408898877 ps
CPU time 10.58 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204104 kb
Host smart-580eae7d-99f0-4095-bb7a-c60061646052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31823
38802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.3182338802
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2504132039
Short name T621
Test name
Test status
Simulation time 8377757286 ps
CPU time 8 seconds
Started Apr 30 02:50:05 PM PDT 24
Finished Apr 30 02:50:14 PM PDT 24
Peak memory 204056 kb
Host smart-2a96fe08-9058-47cb-addb-c7e58ef0f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25041
32039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2504132039
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.4281851378
Short name T405
Test name
Test status
Simulation time 8372670232 ps
CPU time 8.08 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204116 kb
Host smart-2783239a-b782-4cce-8617-305df693ac38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42818
51378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.4281851378
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3266630598
Short name T1059
Test name
Test status
Simulation time 84319990 ps
CPU time 1.33 seconds
Started Apr 30 02:49:56 PM PDT 24
Finished Apr 30 02:49:59 PM PDT 24
Peak memory 204120 kb
Host smart-e4bfb169-bf3c-40d9-8d11-9c3055b1b46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32666
30598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3266630598
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2786759300
Short name T723
Test name
Test status
Simulation time 8404327214 ps
CPU time 8.06 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204120 kb
Host smart-1552bd1f-7485-4ab3-9768-f50ebcc385a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
59300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2786759300
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2718080218
Short name T811
Test name
Test status
Simulation time 8413745038 ps
CPU time 7.94 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204080 kb
Host smart-2f995fb7-9ebc-479d-8ac0-069009ad65d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27180
80218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2718080218
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1089298586
Short name T1103
Test name
Test status
Simulation time 8424883727 ps
CPU time 8.67 seconds
Started Apr 30 02:50:02 PM PDT 24
Finished Apr 30 02:50:12 PM PDT 24
Peak memory 204044 kb
Host smart-c419cd4a-32b7-4a54-a270-f2d1ec05121b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10892
98586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1089298586
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.920422292
Short name T1198
Test name
Test status
Simulation time 8377330952 ps
CPU time 8.92 seconds
Started Apr 30 02:49:52 PM PDT 24
Finished Apr 30 02:50:02 PM PDT 24
Peak memory 204140 kb
Host smart-2c9afa97-1ba8-4b6c-b975-a8fcd78bf132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92042
2292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.920422292
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2081099034
Short name T487
Test name
Test status
Simulation time 8439592182 ps
CPU time 7.83 seconds
Started Apr 30 02:50:02 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204012 kb
Host smart-820e43f9-ef3a-4a4d-a67b-1e7cf49a33a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
99034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2081099034
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2008056792
Short name T1042
Test name
Test status
Simulation time 8391669872 ps
CPU time 8.44 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204116 kb
Host smart-4b01e80c-3a40-4e21-af7b-b5deb565269d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20080
56792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2008056792
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.820380393
Short name T1319
Test name
Test status
Simulation time 8415775000 ps
CPU time 10.11 seconds
Started Apr 30 02:49:59 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204144 kb
Host smart-a1d1370a-f645-4232-a3c3-1749a0f0708c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82038
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.820380393
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1390261774
Short name T1010
Test name
Test status
Simulation time 8414716564 ps
CPU time 8.83 seconds
Started Apr 30 02:50:05 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204044 kb
Host smart-b938f578-ade2-45e3-804e-7c4329cc2456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13902
61774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1390261774
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1301039364
Short name T1096
Test name
Test status
Simulation time 8367336281 ps
CPU time 9.17 seconds
Started Apr 30 02:50:03 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204104 kb
Host smart-08f0313f-8fba-4370-bf55-facc9cbc2ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13010
39364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1301039364
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.179719849
Short name T29
Test name
Test status
Simulation time 49619979 ps
CPU time 0.67 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:02 PM PDT 24
Peak memory 204016 kb
Host smart-d867d858-9dfa-43ca-9c1e-09b9db519610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17971
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.179719849
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3452422720
Short name T1128
Test name
Test status
Simulation time 25221624791 ps
CPU time 51.99 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:51:04 PM PDT 24
Peak memory 204412 kb
Host smart-769055b9-c85d-4e41-95c4-2636e84ffafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34524
22720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3452422720
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2124244030
Short name T712
Test name
Test status
Simulation time 8410566723 ps
CPU time 7.73 seconds
Started Apr 30 02:50:05 PM PDT 24
Finished Apr 30 02:50:14 PM PDT 24
Peak memory 204048 kb
Host smart-dbbde7de-832f-454c-b072-f2c56eb9c188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21242
44030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2124244030
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3237031234
Short name T784
Test name
Test status
Simulation time 8395307405 ps
CPU time 7.86 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204044 kb
Host smart-2af83e1d-9630-4569-a30e-fc5f9371eaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
31234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3237031234
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.410105592
Short name T275
Test name
Test status
Simulation time 8398929321 ps
CPU time 8.05 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:09 PM PDT 24
Peak memory 204080 kb
Host smart-754840fd-9b99-4fa9-ae42-95d3c4dcc7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41010
5592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.410105592
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3357142902
Short name T161
Test name
Test status
Simulation time 8375536432 ps
CPU time 8.28 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204016 kb
Host smart-1d3ca752-6eaa-4af2-b6cf-8afbca43e033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33571
42902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3357142902
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2419544833
Short name T337
Test name
Test status
Simulation time 8394089026 ps
CPU time 10.14 seconds
Started Apr 30 02:50:03 PM PDT 24
Finished Apr 30 02:50:14 PM PDT 24
Peak memory 204080 kb
Host smart-d41889bf-0607-4d66-b3a9-6198c8e8533e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24195
44833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2419544833
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2154687559
Short name T1209
Test name
Test status
Simulation time 8433843878 ps
CPU time 7.83 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204052 kb
Host smart-888757c7-2c47-46ee-a391-bc2778b80476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21546
87559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2154687559
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.801162373
Short name T938
Test name
Test status
Simulation time 8395678662 ps
CPU time 7.44 seconds
Started Apr 30 02:49:58 PM PDT 24
Finished Apr 30 02:50:07 PM PDT 24
Peak memory 204060 kb
Host smart-37b8573a-680c-4fad-bca2-c1ab2e411756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80116
2373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.801162373
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1202751338
Short name T304
Test name
Test status
Simulation time 8405755231 ps
CPU time 10 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:11 PM PDT 24
Peak memory 204040 kb
Host smart-b60a4d18-803e-4d45-af33-e56316facba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12027
51338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1202751338
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.4273041564
Short name T567
Test name
Test status
Simulation time 8474746020 ps
CPU time 8.88 seconds
Started Apr 30 02:50:06 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204084 kb
Host smart-7b1f01af-d6f9-424a-baa9-176d7f69896c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4273041564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.4273041564
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3940540995
Short name T1046
Test name
Test status
Simulation time 8436402138 ps
CPU time 8.19 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204020 kb
Host smart-9f7c71ba-25ee-4ae7-96b8-14823bba498d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3940540995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3940540995
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.3916012717
Short name T573
Test name
Test status
Simulation time 8434565541 ps
CPU time 7.59 seconds
Started Apr 30 02:49:57 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204088 kb
Host smart-7067f32f-637f-4d0a-aac9-3df2eb98a6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39160
12717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3916012717
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2483585284
Short name T682
Test name
Test status
Simulation time 8373959547 ps
CPU time 8.04 seconds
Started Apr 30 02:49:59 PM PDT 24
Finished Apr 30 02:50:07 PM PDT 24
Peak memory 204152 kb
Host smart-19d18e4e-06df-4003-a5b0-1eade2a8ec3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24835
85284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2483585284
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.465324224
Short name T1105
Test name
Test status
Simulation time 8405404602 ps
CPU time 7.93 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204052 kb
Host smart-2d10bf71-99db-4e29-a912-653922f184a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46532
4224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.465324224
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3311803685
Short name T1325
Test name
Test status
Simulation time 120350417 ps
CPU time 2.24 seconds
Started Apr 30 02:49:59 PM PDT 24
Finished Apr 30 02:50:02 PM PDT 24
Peak memory 204208 kb
Host smart-a9057722-7afc-4adf-85e2-fce56e524ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
03685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3311803685
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3422627515
Short name T1134
Test name
Test status
Simulation time 8411068304 ps
CPU time 7.89 seconds
Started Apr 30 02:50:03 PM PDT 24
Finished Apr 30 02:50:12 PM PDT 24
Peak memory 204072 kb
Host smart-bcc3cd86-63f9-40a7-88bf-0c8396a2de1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34226
27515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3422627515
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3489251810
Short name T500
Test name
Test status
Simulation time 8369748334 ps
CPU time 9.93 seconds
Started Apr 30 02:50:02 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204288 kb
Host smart-909cd9f5-26c6-4c96-8591-ed8f64d037be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34892
51810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3489251810
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3742207056
Short name T522
Test name
Test status
Simulation time 8428787792 ps
CPU time 9.76 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204112 kb
Host smart-1dc3e717-7f3b-4a65-a958-f2430376a32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37422
07056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3742207056
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1172761408
Short name T960
Test name
Test status
Simulation time 8443959499 ps
CPU time 7.72 seconds
Started Apr 30 02:49:58 PM PDT 24
Finished Apr 30 02:50:06 PM PDT 24
Peak memory 204116 kb
Host smart-eb41a3c6-f8e4-4733-bfa4-d62210aea356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11727
61408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1172761408
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2819258631
Short name T608
Test name
Test status
Simulation time 8369896113 ps
CPU time 7.77 seconds
Started Apr 30 02:50:04 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204104 kb
Host smart-9d5b6477-dff8-4df1-a4c8-d4d0af7ec993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28192
58631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2819258631
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3704000035
Short name T702
Test name
Test status
Simulation time 8422637417 ps
CPU time 8.56 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204120 kb
Host smart-d587f53d-3be6-4f71-95d1-23e4e42e7047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
00035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3704000035
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1893365387
Short name T449
Test name
Test status
Simulation time 8398398218 ps
CPU time 9.82 seconds
Started Apr 30 02:50:20 PM PDT 24
Finished Apr 30 02:50:31 PM PDT 24
Peak memory 204136 kb
Host smart-5e86b4d1-2b80-469c-a562-0ea321a8d442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
65387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1893365387
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.578306021
Short name T407
Test name
Test status
Simulation time 8394776501 ps
CPU time 8.02 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204128 kb
Host smart-e186a9b4-0ab1-43ab-9a23-e64a4eb79090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57830
6021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.578306021
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1308786220
Short name T801
Test name
Test status
Simulation time 8397444987 ps
CPU time 7.39 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204092 kb
Host smart-bf21ea1b-d14d-4b55-9d5a-38a71413c93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13087
86220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1308786220
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.48516275
Short name T939
Test name
Test status
Simulation time 8375368055 ps
CPU time 9.8 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204132 kb
Host smart-85160c77-d2da-4d33-8fea-69d6c1a4ad23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48516
275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.48516275
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.125075536
Short name T925
Test name
Test status
Simulation time 46297847 ps
CPU time 0.7 seconds
Started Apr 30 02:50:02 PM PDT 24
Finished Apr 30 02:50:04 PM PDT 24
Peak memory 203944 kb
Host smart-03ca391a-da94-45c9-a6ca-fce3ba82dff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12507
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.125075536
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3150008499
Short name T88
Test name
Test status
Simulation time 26483857237 ps
CPU time 53.09 seconds
Started Apr 30 02:50:00 PM PDT 24
Finished Apr 30 02:50:54 PM PDT 24
Peak memory 204324 kb
Host smart-885f3792-2b08-43a9-b253-8607f683d806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500
08499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3150008499
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3339237365
Short name T361
Test name
Test status
Simulation time 8373098914 ps
CPU time 7.62 seconds
Started Apr 30 02:50:05 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204048 kb
Host smart-a9428b0b-b0c9-469d-abc2-27a11344e58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33392
37365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3339237365
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.478673049
Short name T127
Test name
Test status
Simulation time 8399083618 ps
CPU time 7.58 seconds
Started Apr 30 02:50:04 PM PDT 24
Finished Apr 30 02:50:13 PM PDT 24
Peak memory 204108 kb
Host smart-6f4c7587-9d33-442a-b320-a53368faf111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47867
3049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.478673049
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3919733290
Short name T941
Test name
Test status
Simulation time 8413255704 ps
CPU time 8.3 seconds
Started Apr 30 02:50:03 PM PDT 24
Finished Apr 30 02:50:12 PM PDT 24
Peak memory 204092 kb
Host smart-2b76a998-7466-4aac-a131-3cf6e04eba50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39197
33290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3919733290
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2520111759
Short name T165
Test name
Test status
Simulation time 8375956251 ps
CPU time 8 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204052 kb
Host smart-515a24db-b234-4cb9-a2f2-ff76a6ddcf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
11759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2520111759
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.519009084
Short name T800
Test name
Test status
Simulation time 8371974357 ps
CPU time 8.29 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204032 kb
Host smart-77a5c63d-a670-456b-8815-8105046f0475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51900
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.519009084
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3920511121
Short name T1095
Test name
Test status
Simulation time 8459829578 ps
CPU time 8.28 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204052 kb
Host smart-bba4a470-051f-41d2-b7b1-9c54f8327fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39205
11121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3920511121
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1902272907
Short name T515
Test name
Test status
Simulation time 8417894404 ps
CPU time 8.43 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204128 kb
Host smart-209ed49a-963e-43d6-a96a-9debec167ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19022
72907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1902272907
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.602772454
Short name T426
Test name
Test status
Simulation time 8407446063 ps
CPU time 8.55 seconds
Started Apr 30 02:50:01 PM PDT 24
Finished Apr 30 02:50:10 PM PDT 24
Peak memory 204144 kb
Host smart-02521590-73f4-47cb-8806-24a848055250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60277
2454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.602772454
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3742848722
Short name T1082
Test name
Test status
Simulation time 8467409951 ps
CPU time 9.15 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204052 kb
Host smart-39c395c1-54ef-47b6-9abf-079288414dd6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3742848722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3742848722
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.374054193
Short name T399
Test name
Test status
Simulation time 8382984397 ps
CPU time 7.66 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204076 kb
Host smart-0d873ff4-46b3-49a6-ac09-3deeedd0f9d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=374054193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.374054193
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3136530959
Short name T1064
Test name
Test status
Simulation time 8463856719 ps
CPU time 8.42 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 203980 kb
Host smart-dcae59ac-7565-4c48-83ba-aea92fdc129a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
30959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3136530959
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1641826559
Short name T369
Test name
Test status
Simulation time 8380888098 ps
CPU time 8.25 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204072 kb
Host smart-c77e837d-afe8-4999-b56b-1d41105cf874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
26559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1641826559
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.2145996250
Short name T964
Test name
Test status
Simulation time 8375416456 ps
CPU time 7.87 seconds
Started Apr 30 02:50:13 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204092 kb
Host smart-f0b52f3a-04ea-401f-9166-dd0b41d64d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21459
96250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2145996250
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1575736934
Short name T773
Test name
Test status
Simulation time 58599643 ps
CPU time 1.51 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204176 kb
Host smart-d69d72a5-96ff-432e-82f0-31a51e1a2902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15757
36934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1575736934
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1221622906
Short name T42
Test name
Test status
Simulation time 8432036351 ps
CPU time 8.51 seconds
Started Apr 30 02:50:21 PM PDT 24
Finished Apr 30 02:50:30 PM PDT 24
Peak memory 204044 kb
Host smart-0a3f1b7b-43b3-43cc-8fbd-cbda9b552b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12216
22906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1221622906
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3932719967
Short name T1091
Test name
Test status
Simulation time 8383607972 ps
CPU time 8.33 seconds
Started Apr 30 02:50:06 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204084 kb
Host smart-6152a027-d2b5-494e-b353-3cd8fd4ac14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39327
19967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3932719967
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.4214573126
Short name T130
Test name
Test status
Simulation time 8438929997 ps
CPU time 9.23 seconds
Started Apr 30 02:50:06 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204044 kb
Host smart-fac00063-8b26-4a25-bf9b-352b0a27d78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
73126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4214573126
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2694523347
Short name T427
Test name
Test status
Simulation time 8433688731 ps
CPU time 8.66 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204140 kb
Host smart-00e674de-e336-4a74-9f6e-43232b21ddb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
23347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2694523347
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3595488835
Short name T1188
Test name
Test status
Simulation time 8392087765 ps
CPU time 8.75 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204044 kb
Host smart-c1199312-9623-41bb-a677-2aeb32505d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35954
88835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3595488835
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4058012926
Short name T112
Test name
Test status
Simulation time 8420286754 ps
CPU time 9.98 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204080 kb
Host smart-298c248d-a9b5-47c0-8dd7-76bf70f47121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40580
12926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4058012926
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.4249537769
Short name T1066
Test name
Test status
Simulation time 8387928393 ps
CPU time 7.56 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204116 kb
Host smart-eaa13654-5045-4014-be33-69d56c249a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42495
37769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.4249537769
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.408303314
Short name T641
Test name
Test status
Simulation time 8442183956 ps
CPU time 7.53 seconds
Started Apr 30 02:50:09 PM PDT 24
Finished Apr 30 02:50:18 PM PDT 24
Peak memory 204108 kb
Host smart-b0178284-a253-46e4-8012-d748c30958c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
3314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.408303314
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2345658045
Short name T926
Test name
Test status
Simulation time 8374178596 ps
CPU time 7.68 seconds
Started Apr 30 02:50:13 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204040 kb
Host smart-51cce26a-4852-455b-9f37-bcab688dcf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23456
58045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2345658045
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.225464590
Short name T1265
Test name
Test status
Simulation time 8373793955 ps
CPU time 7.98 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204056 kb
Host smart-0e737e42-d119-47e7-88fc-067697a2c34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22546
4590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.225464590
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2188758199
Short name T404
Test name
Test status
Simulation time 48967663 ps
CPU time 0.68 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 203992 kb
Host smart-575c40f9-3822-47d0-8ab5-94e5a005cc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887
58199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2188758199
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3400128081
Short name T1192
Test name
Test status
Simulation time 20903239958 ps
CPU time 45.99 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:59 PM PDT 24
Peak memory 204400 kb
Host smart-4160ac2d-567c-4f94-813d-92c0961d8b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34001
28081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3400128081
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.4095272359
Short name T974
Test name
Test status
Simulation time 8395925254 ps
CPU time 7.44 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204048 kb
Host smart-b39e314d-d982-4412-8e3e-27c2c1fc4f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
72359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.4095272359
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.4169126929
Short name T887
Test name
Test status
Simulation time 8449572948 ps
CPU time 10.08 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 204040 kb
Host smart-ffbc97da-0a37-41e3-9f75-020626d025b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41691
26929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.4169126929
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.602444329
Short name T266
Test name
Test status
Simulation time 8379544044 ps
CPU time 8.07 seconds
Started Apr 30 02:50:15 PM PDT 24
Finished Apr 30 02:50:25 PM PDT 24
Peak memory 204108 kb
Host smart-e505be66-6995-4b8d-b6ac-d590605ad206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60244
4329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.602444329
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1111570509
Short name T1371
Test name
Test status
Simulation time 8374882981 ps
CPU time 8.98 seconds
Started Apr 30 02:50:05 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204048 kb
Host smart-2834aa22-f4bc-41bd-bb56-b16b16c41505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11115
70509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1111570509
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2934817575
Short name T1300
Test name
Test status
Simulation time 8363087523 ps
CPU time 8.26 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204052 kb
Host smart-27ff4885-df80-464b-9b32-8395e30900ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348
17575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2934817575
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.94402298
Short name T152
Test name
Test status
Simulation time 8417170363 ps
CPU time 8.68 seconds
Started Apr 30 02:50:15 PM PDT 24
Finished Apr 30 02:50:25 PM PDT 24
Peak memory 204140 kb
Host smart-5b4ade04-90ed-4ee6-9328-4b4368cf220d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94402
298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.94402298
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.545647680
Short name T454
Test name
Test status
Simulation time 8433463269 ps
CPU time 8.02 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204012 kb
Host smart-0e9e15f5-947b-480e-bf11-cfd372db959b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54564
7680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.545647680
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3056706992
Short name T734
Test name
Test status
Simulation time 8403981400 ps
CPU time 7.92 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204084 kb
Host smart-1afb933c-bd32-488d-a2d1-f01ccadd01e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
06992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3056706992
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1580295342
Short name T1030
Test name
Test status
Simulation time 8465875892 ps
CPU time 8.45 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204144 kb
Host smart-a7e613e3-bcd4-4d72-bbba-3c79a517b106
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1580295342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1580295342
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.552017246
Short name T1118
Test name
Test status
Simulation time 8382128432 ps
CPU time 8.02 seconds
Started Apr 30 02:50:09 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204128 kb
Host smart-432a1e98-a727-4a97-95aa-bb87c16a4f7d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=552017246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.552017246
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1869591566
Short name T574
Test name
Test status
Simulation time 8456358684 ps
CPU time 7.62 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204116 kb
Host smart-b04406a0-13d3-4867-bcfd-86a36b8d10d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
91566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1869591566
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4222486113
Short name T662
Test name
Test status
Simulation time 8374851888 ps
CPU time 7.82 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204100 kb
Host smart-9c75be58-3f97-4554-be00-96c0b6f9fb60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42224
86113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4222486113
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.3562849975
Short name T403
Test name
Test status
Simulation time 8379965528 ps
CPU time 7.9 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204292 kb
Host smart-f7de2455-c074-4f55-97ae-c57ea9ebb80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
49975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3562849975
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.668352082
Short name T1354
Test name
Test status
Simulation time 70777243 ps
CPU time 1.67 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:15 PM PDT 24
Peak memory 204172 kb
Host smart-f4a21efb-4262-4795-a4d3-85f76131e155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66835
2082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.668352082
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.543077535
Short name T615
Test name
Test status
Simulation time 8495027373 ps
CPU time 8.21 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204092 kb
Host smart-ddf413f9-bb97-444c-aad3-c151b00edeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54307
7535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.543077535
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.295295836
Short name T720
Test name
Test status
Simulation time 8371500116 ps
CPU time 8.45 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204092 kb
Host smart-feb94c59-81ec-4d42-bdad-2ed986bbf746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
5836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.295295836
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3492760601
Short name T141
Test name
Test status
Simulation time 8467586693 ps
CPU time 8.32 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204288 kb
Host smart-f5f015d3-164b-419d-877a-1ccab0c07dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34927
60601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3492760601
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.337102504
Short name T752
Test name
Test status
Simulation time 8421926671 ps
CPU time 8 seconds
Started Apr 30 02:50:13 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204036 kb
Host smart-44fa43a7-74fc-42b5-b15f-a319ed51f183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33710
2504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.337102504
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.4147818564
Short name T1039
Test name
Test status
Simulation time 8396563234 ps
CPU time 7.86 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204008 kb
Host smart-3ce2340f-8874-4060-add1-8a353b47f74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478
18564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4147818564
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.51788318
Short name T1294
Test name
Test status
Simulation time 8461308614 ps
CPU time 8.26 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204052 kb
Host smart-faf9585a-3dc4-4f6a-aabd-37a3cbaef2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51788
318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.51788318
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1418420739
Short name T496
Test name
Test status
Simulation time 8398572638 ps
CPU time 7.4 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204084 kb
Host smart-29050b93-cd6a-454b-b8c4-83f7f46f00d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14184
20739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1418420739
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3119605084
Short name T907
Test name
Test status
Simulation time 8386115263 ps
CPU time 7.84 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204144 kb
Host smart-950c09e3-3922-4054-b028-5eb58803a1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196
05084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3119605084
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3395691978
Short name T21
Test name
Test status
Simulation time 8441819121 ps
CPU time 7.9 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204104 kb
Host smart-d47c8da7-92e5-4ea8-8ae8-12d8da626278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956
91978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3395691978
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.4126736650
Short name T1163
Test name
Test status
Simulation time 8368659001 ps
CPU time 9.96 seconds
Started Apr 30 02:50:13 PM PDT 24
Finished Apr 30 02:50:24 PM PDT 24
Peak memory 204120 kb
Host smart-448d7a54-6ddc-4d4a-be89-5409932fade0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41267
36650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.4126736650
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2812989835
Short name T1186
Test name
Test status
Simulation time 54141580 ps
CPU time 0.7 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:12 PM PDT 24
Peak memory 203948 kb
Host smart-0e81aca1-b6a3-4c9b-882c-9849379aed19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28129
89835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2812989835
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1703756360
Short name T203
Test name
Test status
Simulation time 23692159105 ps
CPU time 41.25 seconds
Started Apr 30 02:50:18 PM PDT 24
Finished Apr 30 02:51:01 PM PDT 24
Peak memory 204400 kb
Host smart-47c7ae19-28a2-4362-9b87-7e72ae023ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
56360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1703756360
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2273078290
Short name T1296
Test name
Test status
Simulation time 8375339358 ps
CPU time 8.67 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204164 kb
Host smart-8066579c-dc86-4473-9a38-d3362f352a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22730
78290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2273078290
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.462757437
Short name T901
Test name
Test status
Simulation time 8388473913 ps
CPU time 7.93 seconds
Started Apr 30 02:50:07 PM PDT 24
Finished Apr 30 02:50:16 PM PDT 24
Peak memory 204172 kb
Host smart-2e3df311-67fa-462a-b27c-b57436aef80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46275
7437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.462757437
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2527928595
Short name T406
Test name
Test status
Simulation time 8398250012 ps
CPU time 7.99 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:18 PM PDT 24
Peak memory 204116 kb
Host smart-c28f98c2-ad83-4602-80c5-f2ccd151a732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
28595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2527928595
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.592735771
Short name T1305
Test name
Test status
Simulation time 8380451712 ps
CPU time 7.59 seconds
Started Apr 30 02:50:09 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204124 kb
Host smart-4dd2a256-812b-41ce-89e2-6df7038d2f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59273
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.592735771
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1732163300
Short name T1014
Test name
Test status
Simulation time 8372066484 ps
CPU time 8.42 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204128 kb
Host smart-37c7e944-bbd9-4117-a57e-24851441a55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17321
63300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1732163300
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.521055052
Short name T1173
Test name
Test status
Simulation time 8451811428 ps
CPU time 8.22 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204076 kb
Host smart-9e893577-bdd7-4b14-9d60-54d9065cd83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52105
5052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.521055052
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2905448567
Short name T1253
Test name
Test status
Simulation time 8409211125 ps
CPU time 7.92 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204076 kb
Host smart-3145b5a9-a94f-490d-bef2-f326b812b4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
48567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2905448567
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2655570054
Short name T26
Test name
Test status
Simulation time 8380384742 ps
CPU time 7.88 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204116 kb
Host smart-6a6ef0bb-ecf9-43f2-a646-29b6972cda66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
70054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2655570054
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.2907174153
Short name T398
Test name
Test status
Simulation time 8491079254 ps
CPU time 7.57 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:27 PM PDT 24
Peak memory 204068 kb
Host smart-a461062e-979d-49ff-9462-ded5735bf9b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2907174153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.2907174153
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2955046493
Short name T679
Test name
Test status
Simulation time 8375298571 ps
CPU time 7.49 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 204128 kb
Host smart-327fe403-ae37-4e68-98de-129ccdad7347
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2955046493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2955046493
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.734915168
Short name T1032
Test name
Test status
Simulation time 8442554791 ps
CPU time 7.92 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:25 PM PDT 24
Peak memory 204140 kb
Host smart-7a521c2a-d9a6-43e6-a570-df0844efdbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73491
5168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.734915168
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3149748840
Short name T727
Test name
Test status
Simulation time 8422111982 ps
CPU time 8 seconds
Started Apr 30 02:50:08 PM PDT 24
Finished Apr 30 02:50:17 PM PDT 24
Peak memory 204144 kb
Host smart-1b4ceadc-5d8f-4105-abb3-79f44deed4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497
48840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3149748840
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.3939616027
Short name T1160
Test name
Test status
Simulation time 8395541319 ps
CPU time 8.21 seconds
Started Apr 30 02:50:13 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204116 kb
Host smart-8b247c3f-19e3-49ad-9415-88195eaa2c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39396
16027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3939616027
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2779876171
Short name T581
Test name
Test status
Simulation time 80452583 ps
CPU time 1.44 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:27 PM PDT 24
Peak memory 204112 kb
Host smart-f58d91c0-32e5-424d-8903-9e17c8c6ff58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
76171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2779876171
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3352684241
Short name T914
Test name
Test status
Simulation time 8440298235 ps
CPU time 9.47 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:28 PM PDT 24
Peak memory 204104 kb
Host smart-563d3df8-5e5c-476c-9107-33334e8f28bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33526
84241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3352684241
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1176553239
Short name T185
Test name
Test status
Simulation time 8392843871 ps
CPU time 7.87 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:25 PM PDT 24
Peak memory 204040 kb
Host smart-96f525e2-62da-4221-8575-5bb68aae8a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
53239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1176553239
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1534963903
Short name T584
Test name
Test status
Simulation time 8413721305 ps
CPU time 8.38 seconds
Started Apr 30 02:50:12 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204072 kb
Host smart-854442e8-5ebb-4cc1-a6ab-b1417e7722c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15349
63903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1534963903
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2854251391
Short name T446
Test name
Test status
Simulation time 8387446359 ps
CPU time 10.27 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:22 PM PDT 24
Peak memory 204056 kb
Host smart-43055c21-83e1-4f93-bf1d-bb114d1f99dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28542
51391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2854251391
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2305928412
Short name T119
Test name
Test status
Simulation time 8425583586 ps
CPU time 8.21 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 203996 kb
Host smart-c2a5bc60-dc35-4e4a-b72e-cfbf5ecc3696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23059
28412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2305928412
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.256237317
Short name T265
Test name
Test status
Simulation time 8392367268 ps
CPU time 7.53 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204000 kb
Host smart-c76fdf40-dd74-4faf-961b-78a23dbda568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
7317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.256237317
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1715837318
Short name T1165
Test name
Test status
Simulation time 8396772303 ps
CPU time 7.6 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204104 kb
Host smart-c3163344-725a-459c-8114-aa0bd4c8f208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
37318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1715837318
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1153043922
Short name T1166
Test name
Test status
Simulation time 8387039125 ps
CPU time 9.41 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:29 PM PDT 24
Peak memory 204088 kb
Host smart-bbcca3d3-d983-4c30-8cff-b61f14021ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11530
43922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1153043922
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.791158713
Short name T834
Test name
Test status
Simulation time 8367784256 ps
CPU time 7.61 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204092 kb
Host smart-7caeecbb-f4bc-41f3-9279-f0bed3285cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79115
8713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.791158713
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1270474093
Short name T663
Test name
Test status
Simulation time 32886698 ps
CPU time 0.63 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:12 PM PDT 24
Peak memory 203952 kb
Host smart-62aef227-7ad4-4b95-a222-ba7df46e809f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12704
74093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1270474093
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3671378810
Short name T935
Test name
Test status
Simulation time 8412186408 ps
CPU time 8.91 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:24 PM PDT 24
Peak memory 204136 kb
Host smart-1fefa2fe-bf53-4d40-82f6-06e6dc9764b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
78810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3671378810
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2083929498
Short name T508
Test name
Test status
Simulation time 8428905218 ps
CPU time 8.26 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204068 kb
Host smart-e9fe68a5-e563-4046-90ba-b849e89f1414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20839
29498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2083929498
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1689045499
Short name T932
Test name
Test status
Simulation time 8393237551 ps
CPU time 7.87 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204080 kb
Host smart-aaa40ee7-be31-4a89-a2b7-8729a8fbae7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16890
45499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1689045499
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2272770157
Short name T1052
Test name
Test status
Simulation time 8372873418 ps
CPU time 8.04 seconds
Started Apr 30 02:50:15 PM PDT 24
Finished Apr 30 02:50:24 PM PDT 24
Peak memory 204076 kb
Host smart-86828360-e1f3-4eae-9081-028beba0ffc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22727
70157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2272770157
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3630182352
Short name T1233
Test name
Test status
Simulation time 8367830797 ps
CPU time 8.3 seconds
Started Apr 30 02:50:11 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204008 kb
Host smart-895cbcb7-3681-4b5c-9e6f-43880e09353d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36301
82352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3630182352
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2665930140
Short name T1073
Test name
Test status
Simulation time 8438380611 ps
CPU time 8.48 seconds
Started Apr 30 02:50:14 PM PDT 24
Finished Apr 30 02:50:24 PM PDT 24
Peak memory 204072 kb
Host smart-2d99a5d8-acf0-4f3c-a9b3-fb9b50c557d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
30140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2665930140
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.182791322
Short name T1097
Test name
Test status
Simulation time 8434016312 ps
CPU time 8.38 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:20 PM PDT 24
Peak memory 204108 kb
Host smart-e7f6121c-6321-442f-bd86-3c9b2651df85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279
1322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.182791322
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.640708134
Short name T283
Test name
Test status
Simulation time 8410588079 ps
CPU time 8.3 seconds
Started Apr 30 02:50:10 PM PDT 24
Finished Apr 30 02:50:19 PM PDT 24
Peak memory 204128 kb
Host smart-ab40d1e7-5ebf-4578-b9be-267264637b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64070
8134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.640708134
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.1107569559
Short name T1106
Test name
Test status
Simulation time 8467753911 ps
CPU time 7.9 seconds
Started Apr 30 02:50:20 PM PDT 24
Finished Apr 30 02:50:29 PM PDT 24
Peak memory 204112 kb
Host smart-27dc502c-e670-4416-8634-44df433df6cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1107569559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.1107569559
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.4268503733
Short name T282
Test name
Test status
Simulation time 8404524175 ps
CPU time 8.03 seconds
Started Apr 30 02:50:27 PM PDT 24
Finished Apr 30 02:50:36 PM PDT 24
Peak memory 203992 kb
Host smart-b84ebb05-448d-46f1-becc-8e61db49e8fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4268503733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.4268503733
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.879891085
Short name T310
Test name
Test status
Simulation time 8490931004 ps
CPU time 7.79 seconds
Started Apr 30 02:50:19 PM PDT 24
Finished Apr 30 02:50:29 PM PDT 24
Peak memory 204104 kb
Host smart-aa89d236-af79-4248-868c-82ae12ccfc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87989
1085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.879891085
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3613076485
Short name T653
Test name
Test status
Simulation time 8378908378 ps
CPU time 8.63 seconds
Started Apr 30 02:50:18 PM PDT 24
Finished Apr 30 02:50:28 PM PDT 24
Peak memory 203912 kb
Host smart-dc64846b-5047-40d7-a658-84b25ea56432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36130
76485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3613076485
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.856301474
Short name T461
Test name
Test status
Simulation time 8373966142 ps
CPU time 7.7 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 204068 kb
Host smart-c1cac2af-3084-49bd-811a-169d8b9f9f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85630
1474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.856301474
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.4091211230
Short name T820
Test name
Test status
Simulation time 62982852 ps
CPU time 1.3 seconds
Started Apr 30 02:50:20 PM PDT 24
Finished Apr 30 02:50:23 PM PDT 24
Peak memory 204212 kb
Host smart-87a647e2-a3ed-4097-9a91-e48106c9de5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
11230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.4091211230
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2049304178
Short name T41
Test name
Test status
Simulation time 8443299184 ps
CPU time 8.53 seconds
Started Apr 30 02:50:18 PM PDT 24
Finished Apr 30 02:50:29 PM PDT 24
Peak memory 204140 kb
Host smart-964709d7-4604-47dd-98c9-9a621830ea99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20493
04178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2049304178
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.236406102
Short name T947
Test name
Test status
Simulation time 8365160902 ps
CPU time 7.37 seconds
Started Apr 30 02:50:23 PM PDT 24
Finished Apr 30 02:50:31 PM PDT 24
Peak memory 204084 kb
Host smart-c37ff1bd-3faa-4c46-a180-208708674468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640
6102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.236406102
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1763035771
Short name T523
Test name
Test status
Simulation time 8408376239 ps
CPU time 7.81 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:27 PM PDT 24
Peak memory 204084 kb
Host smart-b4b312e8-02ce-43d2-bf26-07ada8fc826a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17630
35771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1763035771
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1089954222
Short name T547
Test name
Test status
Simulation time 8418352138 ps
CPU time 9.12 seconds
Started Apr 30 02:50:15 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 204164 kb
Host smart-22b1537a-4a87-4d1d-a151-e548894a2711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
54222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1089954222
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4012689241
Short name T980
Test name
Test status
Simulation time 8368132977 ps
CPU time 9.69 seconds
Started Apr 30 02:50:28 PM PDT 24
Finished Apr 30 02:50:38 PM PDT 24
Peak memory 204104 kb
Host smart-e4661161-127e-4802-84ab-f8e6119c50eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126
89241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4012689241
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1406477863
Short name T1347
Test name
Test status
Simulation time 8430540269 ps
CPU time 8.64 seconds
Started Apr 30 02:50:18 PM PDT 24
Finished Apr 30 02:50:28 PM PDT 24
Peak memory 203744 kb
Host smart-f68abff5-f0dc-4753-bc18-ff8e151e844b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14064
77863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1406477863
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2042115398
Short name T491
Test name
Test status
Simulation time 8384901430 ps
CPU time 9.55 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:27 PM PDT 24
Peak memory 204064 kb
Host smart-5076dbe0-9740-46e9-a399-e9088a55a3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
15398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2042115398
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3212872660
Short name T503
Test name
Test status
Simulation time 8401110998 ps
CPU time 8.45 seconds
Started Apr 30 02:50:19 PM PDT 24
Finished Apr 30 02:50:29 PM PDT 24
Peak memory 204144 kb
Host smart-88aa850c-a3b1-487c-b014-0cf5d433c12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
72660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3212872660
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2890020555
Short name T580
Test name
Test status
Simulation time 8374929682 ps
CPU time 8.81 seconds
Started Apr 30 02:50:29 PM PDT 24
Finished Apr 30 02:50:38 PM PDT 24
Peak memory 204068 kb
Host smart-8181138e-fdb1-4a5d-bfae-357682d76053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
20555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2890020555
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3979772928
Short name T1199
Test name
Test status
Simulation time 8368048643 ps
CPU time 9.69 seconds
Started Apr 30 02:50:27 PM PDT 24
Finished Apr 30 02:50:37 PM PDT 24
Peak memory 204060 kb
Host smart-65f15241-5fd8-4e3c-8171-7e2d2ab4fc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
72928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3979772928
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1057496362
Short name T1072
Test name
Test status
Simulation time 34269829 ps
CPU time 0.65 seconds
Started Apr 30 02:50:30 PM PDT 24
Finished Apr 30 02:50:31 PM PDT 24
Peak memory 203952 kb
Host smart-0bba841d-e922-4cd7-b262-b23b5695e013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574
96362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1057496362
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.614861941
Short name T493
Test name
Test status
Simulation time 17035603790 ps
CPU time 29.48 seconds
Started Apr 30 02:50:26 PM PDT 24
Finished Apr 30 02:50:56 PM PDT 24
Peak memory 204304 kb
Host smart-4a44516b-6a2d-4dca-8db6-6f7730bbb83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61486
1941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.614861941
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1678329312
Short name T609
Test name
Test status
Simulation time 8418887631 ps
CPU time 10.95 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:28 PM PDT 24
Peak memory 204128 kb
Host smart-d03833b5-6afd-40eb-ae7c-c9fd6feece5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16783
29312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1678329312
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3237315186
Short name T1171
Test name
Test status
Simulation time 8485779817 ps
CPU time 9.91 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:34 PM PDT 24
Peak memory 204100 kb
Host smart-9984d6c8-5a21-4d09-be98-6a2c3d167c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373
15186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3237315186
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1187667898
Short name T1341
Test name
Test status
Simulation time 8388392118 ps
CPU time 8.19 seconds
Started Apr 30 02:50:22 PM PDT 24
Finished Apr 30 02:50:31 PM PDT 24
Peak memory 204016 kb
Host smart-542b30c6-98a0-438a-af4e-7e3aeae25f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11876
67898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1187667898
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1107136411
Short name T1224
Test name
Test status
Simulation time 8375909540 ps
CPU time 8.01 seconds
Started Apr 30 02:50:30 PM PDT 24
Finished Apr 30 02:50:39 PM PDT 24
Peak memory 204132 kb
Host smart-d571c0ce-959c-4634-927a-af047040d75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071
36411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1107136411
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1279639815
Short name T762
Test name
Test status
Simulation time 8367076895 ps
CPU time 10.45 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:30 PM PDT 24
Peak memory 204108 kb
Host smart-dead4178-f6d4-4c58-a77f-2fd7a174b8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12796
39815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1279639815
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2223967940
Short name T479
Test name
Test status
Simulation time 8414083346 ps
CPU time 8.31 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 204092 kb
Host smart-3006bb93-a8f9-46c2-a2d1-def68035aea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
67940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2223967940
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.841280008
Short name T928
Test name
Test status
Simulation time 8402539215 ps
CPU time 8.24 seconds
Started Apr 30 02:50:15 PM PDT 24
Finished Apr 30 02:50:25 PM PDT 24
Peak memory 204144 kb
Host smart-6e56dccd-4ea7-4fd9-b30f-b8eaea11a1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84128
0008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.841280008
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2877942362
Short name T468
Test name
Test status
Simulation time 8405643558 ps
CPU time 8.76 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:33 PM PDT 24
Peak memory 204036 kb
Host smart-add15365-1fa9-4b59-aa2b-6b6f729aeb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28779
42362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2877942362
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1287114076
Short name T455
Test name
Test status
Simulation time 8498003077 ps
CPU time 9.74 seconds
Started Apr 30 02:50:37 PM PDT 24
Finished Apr 30 02:50:47 PM PDT 24
Peak memory 204076 kb
Host smart-ff3891fd-869b-475d-a258-1bd971779746
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1287114076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1287114076
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.1359382826
Short name T498
Test name
Test status
Simulation time 8372487253 ps
CPU time 7.38 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:32 PM PDT 24
Peak memory 204056 kb
Host smart-6a0fc3c6-408d-4860-9365-8d945bc2e82a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1359382826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.1359382826
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3256948173
Short name T1279
Test name
Test status
Simulation time 8445904250 ps
CPU time 7.8 seconds
Started Apr 30 02:50:36 PM PDT 24
Finished Apr 30 02:50:44 PM PDT 24
Peak memory 204120 kb
Host smart-5185783e-3cbc-4fbe-984c-796f9e3cf3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32569
48173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3256948173
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.652867789
Short name T1323
Test name
Test status
Simulation time 8372579374 ps
CPU time 7.54 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 204128 kb
Host smart-12dc3edc-be3c-46ea-af73-3e651dd20d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65286
7789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.652867789
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2708733787
Short name T1115
Test name
Test status
Simulation time 8373081833 ps
CPU time 10.4 seconds
Started Apr 30 02:50:19 PM PDT 24
Finished Apr 30 02:50:32 PM PDT 24
Peak memory 204148 kb
Host smart-a491f9fe-e8c9-4bb0-8e12-5516ba06d60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27087
33787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2708733787
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2579070865
Short name T518
Test name
Test status
Simulation time 77893787 ps
CPU time 1.81 seconds
Started Apr 30 02:50:17 PM PDT 24
Finished Apr 30 02:50:21 PM PDT 24
Peak memory 204144 kb
Host smart-da80843f-9d6e-4875-a80c-05353f62e73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
70865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2579070865
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2232267203
Short name T934
Test name
Test status
Simulation time 8445453555 ps
CPU time 8.19 seconds
Started Apr 30 02:50:25 PM PDT 24
Finished Apr 30 02:50:34 PM PDT 24
Peak memory 204152 kb
Host smart-906261dc-c709-4246-b6fb-7f3803f4e90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
67203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2232267203
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2180476737
Short name T1005
Test name
Test status
Simulation time 8365590317 ps
CPU time 7.75 seconds
Started Apr 30 02:50:36 PM PDT 24
Finished Apr 30 02:50:44 PM PDT 24
Peak memory 204128 kb
Host smart-e6ea07a2-6383-4643-917d-c043780e3459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21804
76737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2180476737
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2272234194
Short name T726
Test name
Test status
Simulation time 8441784872 ps
CPU time 8.52 seconds
Started Apr 30 02:50:16 PM PDT 24
Finished Apr 30 02:50:26 PM PDT 24
Peak memory 203428 kb
Host smart-6610516d-5d2d-43b4-996b-c15817b8b047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22722
34194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2272234194
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2244683703
Short name T1043
Test name
Test status
Simulation time 8414635105 ps
CPU time 8.89 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:33 PM PDT 24
Peak memory 204056 kb
Host smart-7972eb40-1511-4184-b0ac-2ba1c7be80a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
83703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2244683703
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.722237174
Short name T1193
Test name
Test status
Simulation time 8383264041 ps
CPU time 8.82 seconds
Started Apr 30 02:50:36 PM PDT 24
Finished Apr 30 02:50:45 PM PDT 24
Peak memory 204128 kb
Host smart-e1b6c342-ab99-4ad5-b778-95a0efd70987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72223
7174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.722237174
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1417449524
Short name T97
Test name
Test status
Simulation time 8448993501 ps
CPU time 9.39 seconds
Started Apr 30 02:50:25 PM PDT 24
Finished Apr 30 02:50:35 PM PDT 24
Peak memory 204104 kb
Host smart-c9a91868-4dda-43f5-ba71-13c327b9998b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14174
49524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1417449524
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.472645161
Short name T274
Test name
Test status
Simulation time 8393481070 ps
CPU time 8.08 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:32 PM PDT 24
Peak memory 204108 kb
Host smart-5f08fd3f-5355-4ed8-9ef3-129ba6b5aa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47264
5161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.472645161
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2360281514
Short name T532
Test name
Test status
Simulation time 8377930923 ps
CPU time 9.27 seconds
Started Apr 30 02:50:20 PM PDT 24
Finished Apr 30 02:50:31 PM PDT 24
Peak memory 204104 kb
Host smart-f209b60f-62e7-45c0-ac0a-f8013803864f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
81514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2360281514
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2023629937
Short name T703
Test name
Test status
Simulation time 8403221763 ps
CPU time 7.73 seconds
Started Apr 30 02:50:32 PM PDT 24
Finished Apr 30 02:50:40 PM PDT 24
Peak memory 204104 kb
Host smart-0cff9a24-e938-428f-b42f-ecf412fc3174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236
29937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2023629937
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3194591101
Short name T320
Test name
Test status
Simulation time 8375203362 ps
CPU time 8.29 seconds
Started Apr 30 02:50:25 PM PDT 24
Finished Apr 30 02:50:34 PM PDT 24
Peak memory 204108 kb
Host smart-de08e220-af4e-4093-9f2b-fdc6bbaddf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31945
91101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3194591101
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3734553806
Short name T810
Test name
Test status
Simulation time 53977082 ps
CPU time 0.7 seconds
Started Apr 30 02:50:26 PM PDT 24
Finished Apr 30 02:50:28 PM PDT 24
Peak memory 203928 kb
Host smart-c5933c89-e6b6-4600-b209-6da4a413acb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37345
53806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3734553806
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1235178417
Short name T226
Test name
Test status
Simulation time 23771042837 ps
CPU time 44.18 seconds
Started Apr 30 02:50:38 PM PDT 24
Finished Apr 30 02:51:23 PM PDT 24
Peak memory 204436 kb
Host smart-0353cd20-ca56-4e11-9a83-5e66408cdde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12351
78417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1235178417
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1748012879
Short name T582
Test name
Test status
Simulation time 8427038945 ps
CPU time 8.3 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:33 PM PDT 24
Peak memory 204104 kb
Host smart-01e708c9-a0d5-4eee-97a5-63c8e7a7161b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
12879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1748012879
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2671215417
Short name T1318
Test name
Test status
Simulation time 8387799573 ps
CPU time 7.97 seconds
Started Apr 30 02:50:20 PM PDT 24
Finished Apr 30 02:50:30 PM PDT 24
Peak memory 204088 kb
Host smart-1847448e-2f35-4a36-b660-31156e5bb520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26712
15417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2671215417
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.4031330736
Short name T850
Test name
Test status
Simulation time 8378461507 ps
CPU time 7.74 seconds
Started Apr 30 02:50:25 PM PDT 24
Finished Apr 30 02:50:34 PM PDT 24
Peak memory 204136 kb
Host smart-97144be0-bbb9-44ed-94b6-b92f9ae37d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
30736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.4031330736
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3052376758
Short name T157
Test name
Test status
Simulation time 8387865502 ps
CPU time 7.86 seconds
Started Apr 30 02:50:36 PM PDT 24
Finished Apr 30 02:50:44 PM PDT 24
Peak memory 204104 kb
Host smart-d2434511-4b13-4a29-807f-c9d33c2cf3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523
76758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3052376758
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.477148216
Short name T373
Test name
Test status
Simulation time 8390055933 ps
CPU time 9.34 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:34 PM PDT 24
Peak memory 204136 kb
Host smart-24dc91ff-5f5c-4ba2-b9de-3116c2d8660f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47714
8216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.477148216
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3017855234
Short name T1215
Test name
Test status
Simulation time 8422119837 ps
CPU time 8.78 seconds
Started Apr 30 02:50:19 PM PDT 24
Finished Apr 30 02:50:30 PM PDT 24
Peak memory 204108 kb
Host smart-531e3015-cc0a-4363-85d9-8b0d9daec748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30178
55234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3017855234
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1161198950
Short name T435
Test name
Test status
Simulation time 8404286502 ps
CPU time 7.6 seconds
Started Apr 30 02:50:23 PM PDT 24
Finished Apr 30 02:50:31 PM PDT 24
Peak memory 204132 kb
Host smart-980b3385-4c40-4b8b-809c-cf5073ffc2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
98950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1161198950
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.291821571
Short name T277
Test name
Test status
Simulation time 8398642497 ps
CPU time 9.1 seconds
Started Apr 30 02:50:31 PM PDT 24
Finished Apr 30 02:50:41 PM PDT 24
Peak memory 204056 kb
Host smart-2230b3ae-18e7-48de-af7f-e67f50ace69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
1571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.291821571
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.122644336
Short name T648
Test name
Test status
Simulation time 8467645936 ps
CPU time 8.26 seconds
Started Apr 30 02:50:29 PM PDT 24
Finished Apr 30 02:50:38 PM PDT 24
Peak memory 204100 kb
Host smart-6ac8d496-0d88-4b52-bc56-cf3e971a4546
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=122644336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.122644336
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.2551382522
Short name T365
Test name
Test status
Simulation time 8378592141 ps
CPU time 8.29 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:33 PM PDT 24
Peak memory 204152 kb
Host smart-5937b61c-b2b2-4921-aacd-ca2ff9d15c7d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2551382522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.2551382522
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.3643668646
Short name T884
Test name
Test status
Simulation time 8435910594 ps
CPU time 8.38 seconds
Started Apr 30 02:50:26 PM PDT 24
Finished Apr 30 02:50:35 PM PDT 24
Peak memory 204060 kb
Host smart-7ca67938-4e52-4ae8-bba8-0d34915e5813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
68646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.3643668646
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3391041583
Short name T1060
Test name
Test status
Simulation time 8382402416 ps
CPU time 9.04 seconds
Started Apr 30 02:50:32 PM PDT 24
Finished Apr 30 02:50:41 PM PDT 24
Peak memory 204016 kb
Host smart-3fc0531f-bd79-452b-bdb8-f9c7502cb36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910
41583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3391041583
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.302362451
Short name T1280
Test name
Test status
Simulation time 8373943782 ps
CPU time 9.16 seconds
Started Apr 30 02:50:31 PM PDT 24
Finished Apr 30 02:50:40 PM PDT 24
Peak memory 204136 kb
Host smart-1c97657e-a72a-4163-abbd-429bfa39ff19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30236
2451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.302362451
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3029575300
Short name T771
Test name
Test status
Simulation time 183188962 ps
CPU time 1.92 seconds
Started Apr 30 02:50:38 PM PDT 24
Finished Apr 30 02:50:41 PM PDT 24
Peak memory 204252 kb
Host smart-c9c4534f-1d8b-49b1-82ba-2733d51bc77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30295
75300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3029575300
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2656261592
Short name T43
Test name
Test status
Simulation time 8440509592 ps
CPU time 10.38 seconds
Started Apr 30 02:50:26 PM PDT 24
Finished Apr 30 02:50:37 PM PDT 24
Peak memory 204120 kb
Host smart-11e21238-d36f-4b6a-bf60-8593d8b2dade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26562
61592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2656261592
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1459063371
Short name T691
Test name
Test status
Simulation time 8364025795 ps
CPU time 10.31 seconds
Started Apr 30 02:50:32 PM PDT 24
Finished Apr 30 02:50:43 PM PDT 24
Peak memory 204112 kb
Host smart-32fdd6cf-9924-476d-96ff-dcbf76861c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14590
63371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1459063371
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1680789033
Short name T488
Test name
Test status
Simulation time 8412045386 ps
CPU time 9.74 seconds
Started Apr 30 02:50:31 PM PDT 24
Finished Apr 30 02:50:41 PM PDT 24
Peak memory 204100 kb
Host smart-84b5c0ce-2928-4c2f-adef-a0e739ca54f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807
89033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1680789033
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3867083197
Short name T558
Test name
Test status
Simulation time 8417923161 ps
CPU time 10.39 seconds
Started Apr 30 02:50:32 PM PDT 24
Finished Apr 30 02:50:43 PM PDT 24
Peak memory 204292 kb
Host smart-370cc703-47e5-4739-8d69-26d964b3227d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38670
83197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3867083197
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3907389431
Short name T85
Test name
Test status
Simulation time 8401935811 ps
CPU time 7.89 seconds
Started Apr 30 02:50:29 PM PDT 24
Finished Apr 30 02:50:37 PM PDT 24
Peak memory 204132 kb
Host smart-7f1d2473-1b2a-4efe-8923-d41157f40bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39073
89431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3907389431
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1049284343
Short name T996
Test name
Test status
Simulation time 8439487936 ps
CPU time 8.23 seconds
Started Apr 30 02:50:28 PM PDT 24
Finished Apr 30 02:50:37 PM PDT 24
Peak memory 204152 kb
Host smart-01bfa1b6-d132-4fad-84a6-9a4ea0ea7b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10492
84343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1049284343
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1462077980
Short name T840
Test name
Test status
Simulation time 8412938419 ps
CPU time 7.59 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:32 PM PDT 24
Peak memory 204144 kb
Host smart-80c6c7b9-9f79-49b6-8b97-353909fcf689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14620
77980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1462077980
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3330253708
Short name T1320
Test name
Test status
Simulation time 8418049227 ps
CPU time 7.7 seconds
Started Apr 30 02:50:38 PM PDT 24
Finished Apr 30 02:50:47 PM PDT 24
Peak memory 204116 kb
Host smart-e3b6d989-93a4-4e82-baf0-21665f9ce5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33302
53708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3330253708
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1371752469
Short name T775
Test name
Test status
Simulation time 8400938470 ps
CPU time 8.28 seconds
Started Apr 30 02:50:30 PM PDT 24
Finished Apr 30 02:50:39 PM PDT 24
Peak memory 204068 kb
Host smart-a32a7e32-3c3e-4926-b241-2c060a8d4aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
52469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1371752469
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3450485458
Short name T388
Test name
Test status
Simulation time 8398627437 ps
CPU time 8.62 seconds
Started Apr 30 02:50:33 PM PDT 24
Finished Apr 30 02:50:42 PM PDT 24
Peak memory 204104 kb
Host smart-49b89b20-2765-4562-a443-600ff306fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34504
85458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3450485458
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.159843092
Short name T766
Test name
Test status
Simulation time 64390678 ps
CPU time 0.69 seconds
Started Apr 30 02:50:27 PM PDT 24
Finished Apr 30 02:50:28 PM PDT 24
Peak memory 203952 kb
Host smart-44776c31-4872-414b-8f65-1f563e14e43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15984
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.159843092
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1112721812
Short name T821
Test name
Test status
Simulation time 26154470000 ps
CPU time 53.86 seconds
Started Apr 30 02:50:28 PM PDT 24
Finished Apr 30 02:51:23 PM PDT 24
Peak memory 204272 kb
Host smart-cd33cc12-a3fe-4945-ba9a-8438a17afab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11127
21812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1112721812
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2347936361
Short name T16
Test name
Test status
Simulation time 8420572448 ps
CPU time 8.35 seconds
Started Apr 30 02:50:29 PM PDT 24
Finished Apr 30 02:50:38 PM PDT 24
Peak memory 204136 kb
Host smart-8772cdfa-711f-4739-bb1a-4c2887e523c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23479
36361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2347936361
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.350633312
Short name T465
Test name
Test status
Simulation time 8446218197 ps
CPU time 7.91 seconds
Started Apr 30 02:50:27 PM PDT 24
Finished Apr 30 02:50:35 PM PDT 24
Peak memory 204096 kb
Host smart-82e0bff0-26ba-4458-82a7-c27758019e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
3312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.350633312
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.97326324
Short name T516
Test name
Test status
Simulation time 8372576069 ps
CPU time 8 seconds
Started Apr 30 02:50:32 PM PDT 24
Finished Apr 30 02:50:41 PM PDT 24
Peak memory 204132 kb
Host smart-425f9e4c-bd01-4d56-8f0b-5c048b87e52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97326
324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.97326324
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2094783914
Short name T160
Test name
Test status
Simulation time 8397565044 ps
CPU time 7.87 seconds
Started Apr 30 02:50:25 PM PDT 24
Finished Apr 30 02:50:34 PM PDT 24
Peak memory 204148 kb
Host smart-c3067975-78e5-4521-a14a-ad279d8cf23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20947
83914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2094783914
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1379569918
Short name T23
Test name
Test status
Simulation time 8368618013 ps
CPU time 8.14 seconds
Started Apr 30 02:50:32 PM PDT 24
Finished Apr 30 02:50:41 PM PDT 24
Peak memory 204292 kb
Host smart-a04cbeb8-7f09-4b07-ab03-26926482e233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13795
69918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1379569918
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1428002938
Short name T135
Test name
Test status
Simulation time 8428760670 ps
CPU time 8.99 seconds
Started Apr 30 02:50:29 PM PDT 24
Finished Apr 30 02:50:39 PM PDT 24
Peak memory 204072 kb
Host smart-f817a552-0e35-4a5f-ad00-0f779622b3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14280
02938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1428002938
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.43827251
Short name T1278
Test name
Test status
Simulation time 8402142705 ps
CPU time 10.59 seconds
Started Apr 30 02:50:31 PM PDT 24
Finished Apr 30 02:50:42 PM PDT 24
Peak memory 204060 kb
Host smart-e47fd490-3d3c-4cf1-b39c-2a4ba3332082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43827
251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.43827251
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1362960143
Short name T526
Test name
Test status
Simulation time 8397033391 ps
CPU time 7.75 seconds
Started Apr 30 02:50:28 PM PDT 24
Finished Apr 30 02:50:37 PM PDT 24
Peak memory 204088 kb
Host smart-0cfd205c-c6ad-4d40-b978-fe45df3000f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
60143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1362960143
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3189217915
Short name T952
Test name
Test status
Simulation time 8477993056 ps
CPU time 7.93 seconds
Started Apr 30 02:50:37 PM PDT 24
Finished Apr 30 02:50:46 PM PDT 24
Peak memory 204088 kb
Host smart-ed893872-46fa-40f8-b018-d16db80bbcac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3189217915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3189217915
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.912395318
Short name T863
Test name
Test status
Simulation time 8390981061 ps
CPU time 9.39 seconds
Started Apr 30 02:50:37 PM PDT 24
Finished Apr 30 02:50:47 PM PDT 24
Peak memory 204112 kb
Host smart-a535d703-f926-4eec-91c7-066cca1d61fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=912395318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.912395318
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.4283929732
Short name T394
Test name
Test status
Simulation time 8404291482 ps
CPU time 7.47 seconds
Started Apr 30 02:50:43 PM PDT 24
Finished Apr 30 02:50:51 PM PDT 24
Peak memory 204136 kb
Host smart-53d81f45-6b74-40d5-8811-36b7c577ba3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42839
29732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.4283929732
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.10950210
Short name T1361
Test name
Test status
Simulation time 8384335048 ps
CPU time 8.19 seconds
Started Apr 30 02:50:24 PM PDT 24
Finished Apr 30 02:50:33 PM PDT 24
Peak memory 204040 kb
Host smart-2d251635-ea57-41bc-924b-05a4443d182b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.10950210
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.2745745032
Short name T1167
Test name
Test status
Simulation time 8393289965 ps
CPU time 7.7 seconds
Started Apr 30 02:50:27 PM PDT 24
Finished Apr 30 02:50:35 PM PDT 24
Peak memory 204052 kb
Host smart-016dd701-a5c6-4153-89a9-f8746ae267c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
45032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2745745032
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3510501664
Short name T1353
Test name
Test status
Simulation time 176263614 ps
CPU time 1.38 seconds
Started Apr 30 02:50:27 PM PDT 24
Finished Apr 30 02:50:29 PM PDT 24
Peak memory 204140 kb
Host smart-9bc0df83-7ffc-4794-9df8-a472c9a0e847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35105
01664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3510501664
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1481203954
Short name T639
Test name
Test status
Simulation time 8449841526 ps
CPU time 9.72 seconds
Started Apr 30 02:50:40 PM PDT 24
Finished Apr 30 02:50:50 PM PDT 24
Peak memory 204144 kb
Host smart-737d9296-10d7-4958-8b57-3414d8d158dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14812
03954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1481203954
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.210233920
Short name T178
Test name
Test status
Simulation time 8365382635 ps
CPU time 7.74 seconds
Started Apr 30 02:50:35 PM PDT 24
Finished Apr 30 02:50:43 PM PDT 24
Peak memory 204044 kb
Host smart-4dc42ce6-dc39-4663-bcf6-0b01ed825d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
3920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.210233920
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3814470037
Short name T1365
Test name
Test status
Simulation time 8442032654 ps
CPU time 7.74 seconds
Started Apr 30 02:50:37 PM PDT 24
Finished Apr 30 02:50:45 PM PDT 24
Peak memory 204112 kb
Host smart-9e1964a6-0b6c-4011-a843-a7afdbc71d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
70037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3814470037
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.4070730575
Short name T1129
Test name
Test status
Simulation time 8420446991 ps
CPU time 7.98 seconds
Started Apr 30 02:50:41 PM PDT 24
Finished Apr 30 02:50:49 PM PDT 24
Peak memory 204132 kb
Host smart-6e5416ab-05f9-4ab4-b401-3cab4b803030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40707
30575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.4070730575
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1958316388
Short name T296
Test name
Test status
Simulation time 8376601385 ps
CPU time 7.99 seconds
Started Apr 30 02:50:42 PM PDT 24
Finished Apr 30 02:50:50 PM PDT 24
Peak memory 204104 kb
Host smart-30d4f1fa-e3c8-4460-94f6-6c076caba357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
16388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1958316388
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3353876562
Short name T110
Test name
Test status
Simulation time 8458444227 ps
CPU time 8.29 seconds
Started Apr 30 02:50:38 PM PDT 24
Finished Apr 30 02:50:47 PM PDT 24
Peak memory 204120 kb
Host smart-56adf511-a537-45d1-b4bb-71b0147739ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33538
76562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3353876562
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.462263429
Short name T1062
Test name
Test status
Simulation time 8398749027 ps
CPU time 8.5 seconds
Started Apr 30 02:50:35 PM PDT 24
Finished Apr 30 02:50:44 PM PDT 24
Peak memory 204084 kb
Host smart-73209c85-68b3-4e0d-bb52-57cf6cd715e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46226
3429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.462263429
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1923603455
Short name T535
Test name
Test status
Simulation time 8395254594 ps
CPU time 8.14 seconds
Started Apr 30 02:50:38 PM PDT 24
Finished Apr 30 02:50:47 PM PDT 24
Peak memory 204140 kb
Host smart-bf915b89-e1a0-41ee-a1b7-f0788661ebe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19236
03455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1923603455
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1850982704
Short name T155
Test name
Test status
Simulation time 8383371728 ps
CPU time 8.74 seconds
Started Apr 30 02:50:40 PM PDT 24
Finished Apr 30 02:50:50 PM PDT 24
Peak memory 204076 kb
Host smart-696ce7fd-139b-45c1-8330-f8d413076cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18509
82704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1850982704
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.928861314
Short name T606
Test name
Test status
Simulation time 8370727783 ps
CPU time 8.55 seconds
Started Apr 30 02:50:41 PM PDT 24
Finished Apr 30 02:50:50 PM PDT 24
Peak memory 204104 kb
Host smart-39d68703-7511-4950-9288-6cefe1fb59c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92886
1314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.928861314
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2412780456
Short name T1297
Test name
Test status
Simulation time 145653108 ps
CPU time 0.77 seconds
Started Apr 30 02:50:37 PM PDT 24
Finished Apr 30 02:50:38 PM PDT 24
Peak memory 203976 kb
Host smart-f51d43e3-97b7-44b6-83f6-dd847458a67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
80456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2412780456
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2963678336
Short name T201
Test name
Test status
Simulation time 14719813862 ps
CPU time 23.91 seconds
Started Apr 30 02:50:36 PM PDT 24
Finished Apr 30 02:51:00 PM PDT 24
Peak memory 204440 kb
Host smart-3cfd06ac-800d-4ba2-a672-8e176952baa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29636
78336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2963678336
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1586930993
Short name T271
Test name
Test status
Simulation time 8400573408 ps
CPU time 8.23 seconds
Started Apr 30 02:50:35 PM PDT 24
Finished Apr 30 02:50:44 PM PDT 24
Peak memory 204124 kb
Host smart-79a242d1-4222-4b2b-a1c9-502a12c98fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15869
30993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1586930993
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2121338439
Short name T836
Test name
Test status
Simulation time 8412956332 ps
CPU time 9.39 seconds
Started Apr 30 02:50:33 PM PDT 24
Finished Apr 30 02:50:43 PM PDT 24
Peak memory 204084 kb
Host smart-e842ee94-c451-49f6-ab83-df16a181fceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
38439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2121338439
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2407381623
Short name T666
Test name
Test status
Simulation time 8404201911 ps
CPU time 8.01 seconds
Started Apr 30 02:50:41 PM PDT 24
Finished Apr 30 02:50:49 PM PDT 24
Peak memory 204292 kb
Host smart-f5c89a3b-24c4-4a69-943d-592581ba9e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
81623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2407381623
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2488259394
Short name T894
Test name
Test status
Simulation time 8373849504 ps
CPU time 7.68 seconds
Started Apr 30 02:50:34 PM PDT 24
Finished Apr 30 02:50:42 PM PDT 24
Peak memory 204116 kb
Host smart-e649d206-fb0f-4b70-8459-b3a87435d8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24882
59394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2488259394
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4260768583
Short name T451
Test name
Test status
Simulation time 8377918214 ps
CPU time 8.36 seconds
Started Apr 30 02:50:34 PM PDT 24
Finished Apr 30 02:50:43 PM PDT 24
Peak memory 204112 kb
Host smart-f70a5d4e-0683-4c00-ac86-3ea9f2504f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42607
68583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4260768583
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.717211698
Short name T149
Test name
Test status
Simulation time 8435695538 ps
CPU time 8.33 seconds
Started Apr 30 02:50:30 PM PDT 24
Finished Apr 30 02:50:39 PM PDT 24
Peak memory 204076 kb
Host smart-d18b2c26-6b97-42da-9957-a15536fa5577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71721
1698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.717211698
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3176088256
Short name T354
Test name
Test status
Simulation time 8377350252 ps
CPU time 7.96 seconds
Started Apr 30 02:50:34 PM PDT 24
Finished Apr 30 02:50:42 PM PDT 24
Peak memory 204136 kb
Host smart-1741afa1-5964-4403-8890-0f3aeb3c3fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
88256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3176088256
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1329856695
Short name T1204
Test name
Test status
Simulation time 8417704998 ps
CPU time 8.65 seconds
Started Apr 30 02:50:33 PM PDT 24
Finished Apr 30 02:50:43 PM PDT 24
Peak memory 204116 kb
Host smart-0a75367f-5b37-4af0-a360-515504d74ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13298
56695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1329856695
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.3980498157
Short name T1293
Test name
Test status
Simulation time 8490202094 ps
CPU time 8.05 seconds
Started Apr 30 02:47:00 PM PDT 24
Finished Apr 30 02:47:08 PM PDT 24
Peak memory 204152 kb
Host smart-9f458150-0e21-4b9b-91f5-8a212d865b01
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3980498157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.3980498157
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1673258349
Short name T949
Test name
Test status
Simulation time 8382597644 ps
CPU time 7.87 seconds
Started Apr 30 02:47:02 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204100 kb
Host smart-6113c845-91dc-414d-9449-602edcfe9542
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1673258349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1673258349
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.4230027134
Short name T1100
Test name
Test status
Simulation time 8454346572 ps
CPU time 7.9 seconds
Started Apr 30 02:47:03 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204148 kb
Host smart-394b7766-ad7b-46eb-ae43-6009ae1b5011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42300
27134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.4230027134
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.788374868
Short name T860
Test name
Test status
Simulation time 8376869697 ps
CPU time 8.25 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:06 PM PDT 24
Peak memory 204064 kb
Host smart-d07a9768-9bfc-4aa7-9f7f-49bb8f263beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78837
4868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.788374868
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.3447288171
Short name T49
Test name
Test status
Simulation time 8378836953 ps
CPU time 8.67 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:06 PM PDT 24
Peak memory 204052 kb
Host smart-1c0155d3-e85b-4691-8cd5-90f7192b72b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34472
88171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3447288171
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.951596747
Short name T350
Test name
Test status
Simulation time 129053968 ps
CPU time 1.43 seconds
Started Apr 30 02:46:59 PM PDT 24
Finished Apr 30 02:47:02 PM PDT 24
Peak memory 204180 kb
Host smart-787475c5-db39-4d5d-9ffb-48feb9515dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95159
6747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.951596747
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3697082102
Short name T856
Test name
Test status
Simulation time 8413678367 ps
CPU time 7.54 seconds
Started Apr 30 02:47:02 PM PDT 24
Finished Apr 30 02:47:10 PM PDT 24
Peak memory 204060 kb
Host smart-8b741731-599e-4150-93dc-39e3246ebfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36970
82102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3697082102
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2438964409
Short name T919
Test name
Test status
Simulation time 8363302890 ps
CPU time 8.45 seconds
Started Apr 30 02:46:58 PM PDT 24
Finished Apr 30 02:47:07 PM PDT 24
Peak memory 204120 kb
Host smart-6c6ecbf7-483b-4daf-819c-c34f6f8b2d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24389
64409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2438964409
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1598970863
Short name T1208
Test name
Test status
Simulation time 8467012631 ps
CPU time 8.51 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:05 PM PDT 24
Peak memory 204044 kb
Host smart-b69e5f45-0799-4090-aacb-29640de37bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15989
70863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1598970863
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2540826882
Short name T921
Test name
Test status
Simulation time 8429971559 ps
CPU time 7.81 seconds
Started Apr 30 02:46:58 PM PDT 24
Finished Apr 30 02:47:07 PM PDT 24
Peak memory 204116 kb
Host smart-e90caac8-0b43-4fe0-bb7e-274d284e5117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25408
26882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2540826882
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1788369446
Short name T1148
Test name
Test status
Simulation time 8374930099 ps
CPU time 8.21 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:06 PM PDT 24
Peak memory 204292 kb
Host smart-51877f66-4a25-4088-b790-0e16d0cd98b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17883
69446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1788369446
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.4112836116
Short name T108
Test name
Test status
Simulation time 8443118971 ps
CPU time 7.71 seconds
Started Apr 30 02:46:55 PM PDT 24
Finished Apr 30 02:47:04 PM PDT 24
Peak memory 204044 kb
Host smart-84b38095-43e9-447a-8368-3dba133873f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
36116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.4112836116
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.267080810
Short name T329
Test name
Test status
Simulation time 8394010737 ps
CPU time 7.75 seconds
Started Apr 30 02:46:57 PM PDT 24
Finished Apr 30 02:47:06 PM PDT 24
Peak memory 204064 kb
Host smart-63131db4-8508-49a7-8cd0-a1ccea075e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26708
0810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.267080810
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3183003572
Short name T1137
Test name
Test status
Simulation time 8410488209 ps
CPU time 8.11 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:05 PM PDT 24
Peak memory 204104 kb
Host smart-79dff7f3-5802-4e9e-8504-b09eea3fd52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31830
03572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3183003572
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2771816631
Short name T156
Test name
Test status
Simulation time 8401421202 ps
CPU time 8.04 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:06 PM PDT 24
Peak memory 204096 kb
Host smart-c7d023cb-3b67-4c01-a099-b7785edd7f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27718
16631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2771816631
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1630277546
Short name T1277
Test name
Test status
Simulation time 8379271585 ps
CPU time 10.11 seconds
Started Apr 30 02:47:02 PM PDT 24
Finished Apr 30 02:47:13 PM PDT 24
Peak memory 204104 kb
Host smart-cb93d329-8fa5-4854-bfc9-c38d7c534ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16302
77546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1630277546
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.572300074
Short name T357
Test name
Test status
Simulation time 82046478 ps
CPU time 0.71 seconds
Started Apr 30 02:46:58 PM PDT 24
Finished Apr 30 02:47:00 PM PDT 24
Peak memory 203940 kb
Host smart-dfe03f30-6727-429a-aba5-218d55bfff1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57230
0074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.572300074
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2973927238
Short name T10
Test name
Test status
Simulation time 15480076969 ps
CPU time 27.61 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204376 kb
Host smart-8bfb2c92-dc8a-4b31-885a-904a07998afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29739
27238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2973927238
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.340618953
Short name T292
Test name
Test status
Simulation time 8412857358 ps
CPU time 7.77 seconds
Started Apr 30 02:46:55 PM PDT 24
Finished Apr 30 02:47:04 PM PDT 24
Peak memory 204116 kb
Host smart-932ed808-0701-494a-a51c-12ca7932e55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34061
8953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.340618953
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2249786813
Short name T1343
Test name
Test status
Simulation time 8487584849 ps
CPU time 8.37 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:10 PM PDT 24
Peak memory 204068 kb
Host smart-88ef4ea8-9df0-4948-b433-3e96c9efb1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
86813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2249786813
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.4074044357
Short name T1089
Test name
Test status
Simulation time 8383798528 ps
CPU time 9.59 seconds
Started Apr 30 02:46:57 PM PDT 24
Finished Apr 30 02:47:08 PM PDT 24
Peak memory 204076 kb
Host smart-908796c1-b47e-4068-ba09-8082bc887dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40740
44357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.4074044357
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2977455968
Short name T851
Test name
Test status
Simulation time 8375605177 ps
CPU time 9.6 seconds
Started Apr 30 02:46:55 PM PDT 24
Finished Apr 30 02:47:06 PM PDT 24
Peak memory 204140 kb
Host smart-b7a4caae-d4f4-49a0-8e16-ce39e430afef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774
55968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2977455968
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1223672227
Short name T341
Test name
Test status
Simulation time 8370250463 ps
CPU time 8 seconds
Started Apr 30 02:46:56 PM PDT 24
Finished Apr 30 02:47:05 PM PDT 24
Peak memory 204060 kb
Host smart-1f2a46a4-80b0-41fb-8c4f-7d9004a1d86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
72227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1223672227
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.632290022
Short name T859
Test name
Test status
Simulation time 8421336270 ps
CPU time 7.85 seconds
Started Apr 30 02:46:58 PM PDT 24
Finished Apr 30 02:47:07 PM PDT 24
Peak memory 204044 kb
Host smart-b35ec575-c075-4680-8b24-e1fb08b8e318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63229
0022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.632290022
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2309086209
Short name T1189
Test name
Test status
Simulation time 8389947811 ps
CPU time 9.13 seconds
Started Apr 30 02:46:58 PM PDT 24
Finished Apr 30 02:47:08 PM PDT 24
Peak memory 204052 kb
Host smart-08afaaf6-6356-44b5-a130-55d4cf8df6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090
86209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2309086209
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.806885424
Short name T1036
Test name
Test status
Simulation time 8394880949 ps
CPU time 8.14 seconds
Started Apr 30 02:46:54 PM PDT 24
Finished Apr 30 02:47:03 PM PDT 24
Peak memory 204056 kb
Host smart-4d23d476-1f31-4747-8068-00600d40cd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80688
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.806885424
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.4027468189
Short name T1250
Test name
Test status
Simulation time 8483001459 ps
CPU time 10.28 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:20 PM PDT 24
Peak memory 204052 kb
Host smart-b56070c1-d6fa-445d-ae11-20f3b30201f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4027468189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.4027468189
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.968886519
Short name T1287
Test name
Test status
Simulation time 8382954983 ps
CPU time 7.86 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204140 kb
Host smart-2f5bf86c-bdf4-4777-8e7f-7161e86f6044
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=968886519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.968886519
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.39313887
Short name T1016
Test name
Test status
Simulation time 8413392548 ps
CPU time 7.73 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204048 kb
Host smart-1b8d2a51-4981-419f-9c44-6b5960da3d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39313
887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.39313887
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1456262853
Short name T538
Test name
Test status
Simulation time 8373681993 ps
CPU time 8.83 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:10 PM PDT 24
Peak memory 204124 kb
Host smart-8bd417bb-179c-45a0-ac9d-82809628c324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14562
62853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1456262853
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.931119449
Short name T81
Test name
Test status
Simulation time 8387427329 ps
CPU time 8.96 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204108 kb
Host smart-78982077-e8f9-40a5-bca3-e60ab2962dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93111
9449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.931119449
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1502521579
Short name T1263
Test name
Test status
Simulation time 43444367 ps
CPU time 1.26 seconds
Started Apr 30 02:46:59 PM PDT 24
Finished Apr 30 02:47:01 PM PDT 24
Peak memory 204076 kb
Host smart-04494723-96d9-4a07-9618-6cd6df3ecc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15025
21579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1502521579
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.193922677
Short name T1236
Test name
Test status
Simulation time 8450259459 ps
CPU time 7.68 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204116 kb
Host smart-3c8970d2-53b9-44dc-9af7-f4699676e3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19392
2677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.193922677
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.803066940
Short name T770
Test name
Test status
Simulation time 8370637379 ps
CPU time 7.41 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204048 kb
Host smart-292d357f-d586-473d-8c8f-517c4465fca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80306
6940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.803066940
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1590318250
Short name T351
Test name
Test status
Simulation time 8454025369 ps
CPU time 7.72 seconds
Started Apr 30 02:47:02 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204052 kb
Host smart-e0ea8cda-3b49-454c-b869-290ddb6019e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15903
18250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1590318250
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.101998305
Short name T937
Test name
Test status
Simulation time 8452646734 ps
CPU time 7.49 seconds
Started Apr 30 02:47:04 PM PDT 24
Finished Apr 30 02:47:13 PM PDT 24
Peak memory 204052 kb
Host smart-2e35a345-83dd-4f0c-9093-753bec936c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10199
8305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.101998305
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2907759208
Short name T967
Test name
Test status
Simulation time 8373367284 ps
CPU time 7.8 seconds
Started Apr 30 02:46:59 PM PDT 24
Finished Apr 30 02:47:08 PM PDT 24
Peak memory 204040 kb
Host smart-4367e5c8-85dd-4759-af79-17426ac22b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
59208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2907759208
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1558017891
Short name T117
Test name
Test status
Simulation time 8407791457 ps
CPU time 8.48 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:10 PM PDT 24
Peak memory 204124 kb
Host smart-c1ee1d02-f0ca-4df1-b62f-6a6a80b37adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
17891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1558017891
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.4170136464
Short name T892
Test name
Test status
Simulation time 8476853382 ps
CPU time 9.35 seconds
Started Apr 30 02:47:02 PM PDT 24
Finished Apr 30 02:47:12 PM PDT 24
Peak memory 204088 kb
Host smart-52b6abfb-f633-40ac-a0c3-1f2ad8f3cd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
36464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4170136464
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2513627390
Short name T417
Test name
Test status
Simulation time 8387887287 ps
CPU time 7.76 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:10 PM PDT 24
Peak memory 204144 kb
Host smart-87830f09-ada6-4561-abf5-0fea6a1af80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25136
27390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2513627390
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1255355053
Short name T193
Test name
Test status
Simulation time 8420571622 ps
CPU time 8.44 seconds
Started Apr 30 02:47:06 PM PDT 24
Finished Apr 30 02:47:15 PM PDT 24
Peak memory 204048 kb
Host smart-a258a8ea-77d4-435f-b72a-671fcdd0bc54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
55053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1255355053
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.669092897
Short name T378
Test name
Test status
Simulation time 8377195290 ps
CPU time 8.81 seconds
Started Apr 30 02:47:03 PM PDT 24
Finished Apr 30 02:47:13 PM PDT 24
Peak memory 204056 kb
Host smart-57ff9294-5b5d-40b4-99f6-4d177d2b1b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66909
2897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.669092897
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4040972797
Short name T1367
Test name
Test status
Simulation time 34321635 ps
CPU time 0.66 seconds
Started Apr 30 02:47:07 PM PDT 24
Finished Apr 30 02:47:09 PM PDT 24
Peak memory 204020 kb
Host smart-27191a16-5e12-47c1-bb76-c409319a13af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409
72797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4040972797
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2104484869
Short name T202
Test name
Test status
Simulation time 26107554919 ps
CPU time 47.77 seconds
Started Apr 30 02:47:00 PM PDT 24
Finished Apr 30 02:47:48 PM PDT 24
Peak memory 204360 kb
Host smart-20288959-692c-48fd-9bfe-76f86c55f04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21044
84869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2104484869
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1823426196
Short name T796
Test name
Test status
Simulation time 8390154373 ps
CPU time 7.91 seconds
Started Apr 30 02:47:00 PM PDT 24
Finished Apr 30 02:47:08 PM PDT 24
Peak memory 204080 kb
Host smart-f0ea9a9b-e1a2-4228-930f-88346934a822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18234
26196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1823426196
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1171102589
Short name T725
Test name
Test status
Simulation time 8438933867 ps
CPU time 7.64 seconds
Started Apr 30 02:47:04 PM PDT 24
Finished Apr 30 02:47:13 PM PDT 24
Peak memory 204108 kb
Host smart-8f2aed89-ce34-49c6-9e5f-5452c0d906eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
02589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1171102589
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3390695874
Short name T604
Test name
Test status
Simulation time 8377866259 ps
CPU time 7.96 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:10 PM PDT 24
Peak memory 204012 kb
Host smart-71fe7b94-f7c2-4843-86df-889ca906bbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33906
95874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3390695874
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3960045141
Short name T1213
Test name
Test status
Simulation time 8383808592 ps
CPU time 8.38 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204128 kb
Host smart-09400a43-f66a-4f2d-a146-859b68fef82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39600
45141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3960045141
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1461237172
Short name T623
Test name
Test status
Simulation time 8370824118 ps
CPU time 7.67 seconds
Started Apr 30 02:47:00 PM PDT 24
Finished Apr 30 02:47:09 PM PDT 24
Peak memory 204148 kb
Host smart-185a6de1-436a-4912-94af-ae31da7fc422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
37172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1461237172
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.856027838
Short name T497
Test name
Test status
Simulation time 8422041657 ps
CPU time 7.91 seconds
Started Apr 30 02:47:03 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204084 kb
Host smart-82af3152-8857-48f7-a73a-024e1a7f6100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85602
7838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.856027838
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2006511006
Short name T782
Test name
Test status
Simulation time 8440634713 ps
CPU time 7.37 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:09 PM PDT 24
Peak memory 204120 kb
Host smart-b23a348f-0cec-41eb-ae0e-3bbe29523073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20065
11006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2006511006
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.178632579
Short name T1051
Test name
Test status
Simulation time 8412907414 ps
CPU time 8.69 seconds
Started Apr 30 02:47:01 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204144 kb
Host smart-294358e4-e779-491a-a4b8-2243aab8518c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
2579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.178632579
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1002000744
Short name T39
Test name
Test status
Simulation time 8458137038 ps
CPU time 9.6 seconds
Started Apr 30 02:47:14 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204064 kb
Host smart-b5704ae7-e034-4daf-bba6-665be3eb4b69
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1002000744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1002000744
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.1961188729
Short name T722
Test name
Test status
Simulation time 8404107631 ps
CPU time 7.44 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204020 kb
Host smart-60d26277-1197-4e2d-ae1b-2de443a451cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1961188729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.1961188729
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.2688533684
Short name T448
Test name
Test status
Simulation time 8405745589 ps
CPU time 7.92 seconds
Started Apr 30 02:47:23 PM PDT 24
Finished Apr 30 02:47:31 PM PDT 24
Peak memory 204128 kb
Host smart-d4dbb4cf-abd8-43dc-bc5a-fe2463926a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26885
33684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.2688533684
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2978407873
Short name T475
Test name
Test status
Simulation time 8383495341 ps
CPU time 8.15 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204068 kb
Host smart-703491c6-2d1f-47b1-8ae9-9261c03866a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
07873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2978407873
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.2650757538
Short name T1326
Test name
Test status
Simulation time 8417882753 ps
CPU time 7.86 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204088 kb
Host smart-c4eba4bb-4252-4501-a2f5-46d951e172fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
57538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2650757538
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1032289961
Short name T1348
Test name
Test status
Simulation time 125900305 ps
CPU time 2.09 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:11 PM PDT 24
Peak memory 204184 kb
Host smart-a050c418-ddf2-4c8f-b3c8-a8e3c6ff2e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322
89961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1032289961
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.317530749
Short name T776
Test name
Test status
Simulation time 8420887412 ps
CPU time 7.42 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:23 PM PDT 24
Peak memory 204108 kb
Host smart-968ce711-3e74-41b4-97e8-e6256ac01054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31753
0749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.317530749
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.448466933
Short name T1094
Test name
Test status
Simulation time 8371225550 ps
CPU time 9.87 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:27 PM PDT 24
Peak memory 204064 kb
Host smart-4afac0db-1ab6-442d-9f17-0688db698d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44846
6933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.448466933
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3749872667
Short name T1175
Test name
Test status
Simulation time 8431925641 ps
CPU time 7.89 seconds
Started Apr 30 02:47:11 PM PDT 24
Finished Apr 30 02:47:19 PM PDT 24
Peak memory 204068 kb
Host smart-6b56d7ae-bebb-4e6e-a98c-d92a56713a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37498
72667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3749872667
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.59081012
Short name T293
Test name
Test status
Simulation time 8414286082 ps
CPU time 8.22 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204064 kb
Host smart-bc84c47c-f572-4afd-a1df-e4c951817757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59081
012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.59081012
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4005648604
Short name T961
Test name
Test status
Simulation time 8370215925 ps
CPU time 7.96 seconds
Started Apr 30 02:47:07 PM PDT 24
Finished Apr 30 02:47:16 PM PDT 24
Peak memory 204144 kb
Host smart-d5a02ec3-8e76-45b3-851d-86837667c86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
48604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4005648604
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.771309776
Short name T118
Test name
Test status
Simulation time 8430054680 ps
CPU time 8.96 seconds
Started Apr 30 02:47:10 PM PDT 24
Finished Apr 30 02:47:20 PM PDT 24
Peak memory 204068 kb
Host smart-5acf9dc1-5fbb-4ee4-9fa1-43a9e525e4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77130
9776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.771309776
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2290165832
Short name T395
Test name
Test status
Simulation time 8400470018 ps
CPU time 7.69 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204068 kb
Host smart-a8c8f456-1944-4676-93d0-6677f87f70e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22901
65832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2290165832
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.4065786164
Short name T1275
Test name
Test status
Simulation time 8403105493 ps
CPU time 8.18 seconds
Started Apr 30 02:47:11 PM PDT 24
Finished Apr 30 02:47:20 PM PDT 24
Peak memory 204124 kb
Host smart-d573a010-834a-495c-84ed-665c706a66aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40657
86164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.4065786164
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2575792383
Short name T1107
Test name
Test status
Simulation time 8374113961 ps
CPU time 7.81 seconds
Started Apr 30 02:47:14 PM PDT 24
Finished Apr 30 02:47:23 PM PDT 24
Peak memory 204104 kb
Host smart-132f968d-39b2-43b6-ba4b-6b55b1540352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25757
92383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2575792383
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.983737620
Short name T1266
Test name
Test status
Simulation time 8365474662 ps
CPU time 8.14 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204148 kb
Host smart-fbf122d8-17cd-4db8-8aec-8d27715bbfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98373
7620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.983737620
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2622740448
Short name T1346
Test name
Test status
Simulation time 61124077 ps
CPU time 0.69 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 203980 kb
Host smart-7b5f9b99-dffd-4183-ab70-020e0668b006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26227
40448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2622740448
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.838787830
Short name T204
Test name
Test status
Simulation time 27465743974 ps
CPU time 51.52 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:48:00 PM PDT 24
Peak memory 204396 kb
Host smart-db053bfd-cf07-4684-a3f5-8e6b1f1e8ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83878
7830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.838787830
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.357867683
Short name T1053
Test name
Test status
Simulation time 8401191090 ps
CPU time 8.35 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204060 kb
Host smart-9b1be32f-3c77-44e6-ab6b-54458361d38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35786
7683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.357867683
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2219075971
Short name T76
Test name
Test status
Simulation time 8404925601 ps
CPU time 8.96 seconds
Started Apr 30 02:47:10 PM PDT 24
Finished Apr 30 02:47:19 PM PDT 24
Peak memory 204108 kb
Host smart-47862eed-5a4e-4824-89e0-d1fc7ae01d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22190
75971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2219075971
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.921048600
Short name T460
Test name
Test status
Simulation time 8387315578 ps
CPU time 8.62 seconds
Started Apr 30 02:47:06 PM PDT 24
Finished Apr 30 02:47:16 PM PDT 24
Peak memory 204108 kb
Host smart-42ac34bd-5377-4674-aee0-ebbb3e4e4223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92104
8600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.921048600
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3418427163
Short name T560
Test name
Test status
Simulation time 8409572331 ps
CPU time 8.05 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204116 kb
Host smart-8fb5fce6-fef1-4a19-945f-abb64f8a5552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
27163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3418427163
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.4074262226
Short name T297
Test name
Test status
Simulation time 8366212827 ps
CPU time 7.71 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:17 PM PDT 24
Peak memory 204136 kb
Host smart-44ee89f2-b056-4ec0-b009-9dba9593b889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40742
62226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.4074262226
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2661303983
Short name T1243
Test name
Test status
Simulation time 8475477748 ps
CPU time 8.39 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204044 kb
Host smart-194f5547-80f0-49b2-9350-978516af564e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26613
03983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2661303983
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1321595909
Short name T358
Test name
Test status
Simulation time 8370510007 ps
CPU time 7.9 seconds
Started Apr 30 02:47:09 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204056 kb
Host smart-8d3c1ebe-b7a6-40bf-b093-9fefd6cb2078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13215
95909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1321595909
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4113717045
Short name T1008
Test name
Test status
Simulation time 8411761639 ps
CPU time 9.05 seconds
Started Apr 30 02:47:08 PM PDT 24
Finished Apr 30 02:47:18 PM PDT 24
Peak memory 204048 kb
Host smart-a75a07db-dbb8-429d-941b-c9e742b280ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
17045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4113717045
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.1001571198
Short name T291
Test name
Test status
Simulation time 8467136970 ps
CPU time 8.17 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204036 kb
Host smart-1509028e-3bbe-48f0-be97-853bfa68d9f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1001571198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.1001571198
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1885894747
Short name T1238
Test name
Test status
Simulation time 8420549449 ps
CPU time 8.05 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204056 kb
Host smart-3f819974-a72e-4253-a432-98d0cad0bc0c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1885894747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1885894747
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.606352116
Short name T806
Test name
Test status
Simulation time 8402251017 ps
CPU time 8.46 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204044 kb
Host smart-2f4baf8b-d0ab-4a9a-a259-bd6f58947d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60635
2116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.606352116
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2037083061
Short name T1313
Test name
Test status
Simulation time 8417504861 ps
CPU time 8.38 seconds
Started Apr 30 02:47:17 PM PDT 24
Finished Apr 30 02:47:26 PM PDT 24
Peak memory 204144 kb
Host smart-add38a9f-be2f-4071-915d-166452c1d3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20370
83061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2037083061
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.3422555850
Short name T466
Test name
Test status
Simulation time 8437887990 ps
CPU time 7.52 seconds
Started Apr 30 02:47:17 PM PDT 24
Finished Apr 30 02:47:26 PM PDT 24
Peak memory 204160 kb
Host smart-77699073-d21c-4a93-a09e-3fd51fe24803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34225
55850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3422555850
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.544889559
Short name T206
Test name
Test status
Simulation time 208535364 ps
CPU time 2.17 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:28 PM PDT 24
Peak memory 204156 kb
Host smart-7f0dc4d0-33f6-434a-9378-db6adaf504c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54488
9559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.544889559
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.483118381
Short name T133
Test name
Test status
Simulation time 8454035742 ps
CPU time 7.86 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204064 kb
Host smart-4536e532-6c74-4269-972b-d47e8bb8ba99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48311
8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.483118381
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1203677335
Short name T181
Test name
Test status
Simulation time 8370758988 ps
CPU time 8.12 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204060 kb
Host smart-069506a0-c6a9-4e19-bd91-edeb8454e40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12036
77335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1203677335
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1393288879
Short name T1312
Test name
Test status
Simulation time 8498638315 ps
CPU time 10 seconds
Started Apr 30 02:47:14 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204132 kb
Host smart-1a207d04-d9de-4e00-b1e5-804bd5102fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
88879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1393288879
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2535376301
Short name T913
Test name
Test status
Simulation time 8457409739 ps
CPU time 7.71 seconds
Started Apr 30 02:47:17 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204108 kb
Host smart-d5ff9282-694e-434a-8769-514815a51336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
76301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2535376301
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.559152355
Short name T1234
Test name
Test status
Simulation time 8378747375 ps
CPU time 7.77 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204072 kb
Host smart-b9f90566-5a17-406c-9c3b-14d8f2652bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55915
2355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.559152355
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1098738171
Short name T122
Test name
Test status
Simulation time 8476791323 ps
CPU time 7.93 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204084 kb
Host smart-e7ab4765-1f71-41b7-8891-8a106c36313d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10987
38171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1098738171
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3779230067
Short name T1162
Test name
Test status
Simulation time 8396249946 ps
CPU time 7.59 seconds
Started Apr 30 02:47:14 PM PDT 24
Finished Apr 30 02:47:22 PM PDT 24
Peak memory 204116 kb
Host smart-ae611f7e-6c63-48fc-9907-0562f62dc0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37792
30067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3779230067
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1231503111
Short name T77
Test name
Test status
Simulation time 8432994103 ps
CPU time 7.7 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204048 kb
Host smart-08f0504c-f09f-4fd7-8a7c-b16fe8a87379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
03111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1231503111
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.640133585
Short name T18
Test name
Test status
Simulation time 8371197716 ps
CPU time 7.76 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204052 kb
Host smart-ec430f2d-977e-4d81-b303-be249b9ce2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64013
3585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.640133585
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2080488466
Short name T846
Test name
Test status
Simulation time 8371451104 ps
CPU time 7.7 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204076 kb
Host smart-b2267c3f-2dee-4af4-a327-80f16f8945db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20804
88466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2080488466
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3947798639
Short name T920
Test name
Test status
Simulation time 57732642 ps
CPU time 0.7 seconds
Started Apr 30 02:47:22 PM PDT 24
Finished Apr 30 02:47:23 PM PDT 24
Peak memory 203920 kb
Host smart-20749c52-f387-4c92-a134-d511965db794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39477
98639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3947798639
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2214267704
Short name T478
Test name
Test status
Simulation time 30043210800 ps
CPU time 62.65 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:48:19 PM PDT 24
Peak memory 204396 kb
Host smart-01904ebb-eae1-4c88-b8c5-242f55366d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22142
67704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2214267704
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2781606889
Short name T439
Test name
Test status
Simulation time 8426353556 ps
CPU time 9.17 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:27 PM PDT 24
Peak memory 204136 kb
Host smart-473552e4-3a97-455e-93db-72232e261a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27816
06889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2781606889
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.529095705
Short name T1227
Test name
Test status
Simulation time 8406119918 ps
CPU time 9.35 seconds
Started Apr 30 02:47:23 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 204304 kb
Host smart-3b049646-66aa-40f7-bc18-742bc0b3869d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52909
5705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.529095705
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3777068761
Short name T791
Test name
Test status
Simulation time 8408567048 ps
CPU time 8.38 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204080 kb
Host smart-0926587c-25e3-4533-8702-440fcbaa4209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37770
68761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3777068761
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3473128151
Short name T1044
Test name
Test status
Simulation time 8372571191 ps
CPU time 7.45 seconds
Started Apr 30 02:47:17 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204116 kb
Host smart-c63eb2ce-0503-46a6-8b82-c614522520ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
28151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3473128151
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.187573447
Short name T363
Test name
Test status
Simulation time 8368421834 ps
CPU time 8.05 seconds
Started Apr 30 02:47:15 PM PDT 24
Finished Apr 30 02:47:24 PM PDT 24
Peak memory 204108 kb
Host smart-f31d78f8-2f9f-433c-a871-f18bad5c5299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18757
3447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.187573447
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.411794942
Short name T554
Test name
Test status
Simulation time 8468274927 ps
CPU time 7.87 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:25 PM PDT 24
Peak memory 204108 kb
Host smart-14706a33-67af-4896-b89f-49ddd86bc8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41179
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.411794942
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1532334846
Short name T25
Test name
Test status
Simulation time 8437659945 ps
CPU time 7.56 seconds
Started Apr 30 02:47:13 PM PDT 24
Finished Apr 30 02:47:21 PM PDT 24
Peak memory 203988 kb
Host smart-f1f2e3de-3799-4c49-b7da-5a5bb275709c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
34846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1532334846
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3161346669
Short name T1099
Test name
Test status
Simulation time 8399597157 ps
CPU time 8.41 seconds
Started Apr 30 02:47:16 PM PDT 24
Finished Apr 30 02:47:26 PM PDT 24
Peak memory 204056 kb
Host smart-28a69e9d-edd4-411d-9591-8edcb98dd664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31613
46669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3161346669
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3828875719
Short name T999
Test name
Test status
Simulation time 8462158293 ps
CPU time 7.72 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204056 kb
Host smart-d10f0dfd-967f-4110-81ae-8c59338b8ae1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3828875719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3828875719
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.3017729719
Short name T865
Test name
Test status
Simulation time 8388641840 ps
CPU time 7.77 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 204072 kb
Host smart-5396356d-9b0b-443c-926a-c5fda7dff67e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3017729719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3017729719
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2539733535
Short name T890
Test name
Test status
Simulation time 8433569467 ps
CPU time 7.84 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204048 kb
Host smart-ed29974f-8b1f-4f99-8dcf-0198f84a536c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25397
33535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2539733535
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.117758347
Short name T732
Test name
Test status
Simulation time 8378595652 ps
CPU time 7.73 seconds
Started Apr 30 02:47:23 PM PDT 24
Finished Apr 30 02:47:31 PM PDT 24
Peak memory 204116 kb
Host smart-1cc9589d-a387-484f-bc12-6ac480a1e018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11775
8347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.117758347
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.1533545494
Short name T721
Test name
Test status
Simulation time 8376269697 ps
CPU time 8.01 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204112 kb
Host smart-0a89bb3e-521f-426d-91d3-9dc29182e8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335
45494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1533545494
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3765270354
Short name T397
Test name
Test status
Simulation time 203771881 ps
CPU time 1.88 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:28 PM PDT 24
Peak memory 204192 kb
Host smart-3e726bb1-cb91-49c0-8643-b6e022215507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37652
70354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3765270354
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1971081777
Short name T1169
Test name
Test status
Simulation time 8402446556 ps
CPU time 7.5 seconds
Started Apr 30 02:47:28 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204092 kb
Host smart-8d365f9b-ba35-43e0-9c12-07d4bd7e8965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19710
81777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1971081777
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1845108367
Short name T1201
Test name
Test status
Simulation time 8371976544 ps
CPU time 7.86 seconds
Started Apr 30 02:47:29 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204120 kb
Host smart-9479c0a2-bb2c-4093-9481-1cd20b1a6d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18451
08367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1845108367
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1960894397
Short name T145
Test name
Test status
Simulation time 8400098958 ps
CPU time 8.73 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204028 kb
Host smart-0e013b5c-99a1-4060-b139-23918f64aed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608
94397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1960894397
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2154529137
Short name T1283
Test name
Test status
Simulation time 8417141705 ps
CPU time 7.61 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 204072 kb
Host smart-5c38d97e-213e-4b27-accb-4cf2cafe850a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21545
29137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2154529137
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1248082082
Short name T1333
Test name
Test status
Simulation time 8369189384 ps
CPU time 7.51 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:38 PM PDT 24
Peak memory 204076 kb
Host smart-5da64198-4d12-4ad3-8520-c6e1957d8271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12480
82082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1248082082
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2313444835
Short name T126
Test name
Test status
Simulation time 8453252650 ps
CPU time 7.72 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204096 kb
Host smart-2fc00bb4-59af-4ab8-a528-cb7b0241302e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23134
44835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2313444835
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2153203488
Short name T1075
Test name
Test status
Simulation time 8380041513 ps
CPU time 7.46 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204112 kb
Host smart-6441b542-6ade-4ccb-b365-f3d8048569ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21532
03488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2153203488
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.27603650
Short name T1038
Test name
Test status
Simulation time 8397189645 ps
CPU time 8.29 seconds
Started Apr 30 02:47:30 PM PDT 24
Finished Apr 30 02:47:39 PM PDT 24
Peak memory 204056 kb
Host smart-31f03fcb-f5c9-4c20-a4fb-d65ec9ddb9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27603
650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.27603650
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1240867192
Short name T166
Test name
Test status
Simulation time 8419701903 ps
CPU time 7.75 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204044 kb
Host smart-9e67c9fd-4f8f-4475-8e6e-e486dfa174bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12408
67192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1240867192
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1457822045
Short name T300
Test name
Test status
Simulation time 8395918675 ps
CPU time 7.42 seconds
Started Apr 30 02:47:26 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204136 kb
Host smart-461862be-76b7-4a6a-9077-1e389d256647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
22045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1457822045
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2363111224
Short name T620
Test name
Test status
Simulation time 34931747 ps
CPU time 0.67 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:28 PM PDT 24
Peak memory 203904 kb
Host smart-ea936e9c-ff51-4e4a-ae46-29fdcf98750e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
11224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2363111224
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.574279964
Short name T240
Test name
Test status
Simulation time 23704474388 ps
CPU time 50.34 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:48:15 PM PDT 24
Peak memory 204436 kb
Host smart-863f0747-1a86-434a-abbc-fefac9767f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57427
9964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.574279964
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2823854557
Short name T701
Test name
Test status
Simulation time 8406827501 ps
CPU time 7.73 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204084 kb
Host smart-8bddaef9-c840-4067-9703-eae774e3a2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28238
54557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2823854557
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3962739748
Short name T843
Test name
Test status
Simulation time 8431557763 ps
CPU time 9.43 seconds
Started Apr 30 02:47:31 PM PDT 24
Finished Apr 30 02:47:41 PM PDT 24
Peak memory 204080 kb
Host smart-5be2068d-3b95-4a55-bf6d-e3b5bf5dc175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
39748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3962739748
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1023337279
Short name T709
Test name
Test status
Simulation time 8407521463 ps
CPU time 7.78 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 204124 kb
Host smart-5bc4020c-6c6a-47b1-8928-658526320d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10233
37279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1023337279
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1919441531
Short name T530
Test name
Test status
Simulation time 8372059923 ps
CPU time 8.26 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204084 kb
Host smart-4cd1fa70-97d8-4266-81ed-6972d6343cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19194
41531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1919441531
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2035137267
Short name T504
Test name
Test status
Simulation time 8374864880 ps
CPU time 7.76 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:34 PM PDT 24
Peak memory 204068 kb
Host smart-23839786-87da-43da-8267-4824639ba395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20351
37267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2035137267
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2555800821
Short name T1286
Test name
Test status
Simulation time 8469610599 ps
CPU time 8.9 seconds
Started Apr 30 02:47:25 PM PDT 24
Finished Apr 30 02:47:35 PM PDT 24
Peak memory 204136 kb
Host smart-081da3f3-84c3-4a00-b29d-7788b48a2848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
00821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2555800821
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.4050101294
Short name T546
Test name
Test status
Simulation time 8381036082 ps
CPU time 7.93 seconds
Started Apr 30 02:47:27 PM PDT 24
Finished Apr 30 02:47:36 PM PDT 24
Peak memory 204080 kb
Host smart-2acb86ea-ab57-493f-a721-1a18ec5c4851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40501
01294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.4050101294
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.688629308
Short name T787
Test name
Test status
Simulation time 8409807473 ps
CPU time 8.33 seconds
Started Apr 30 02:47:24 PM PDT 24
Finished Apr 30 02:47:33 PM PDT 24
Peak memory 203988 kb
Host smart-056f874f-591f-4983-b921-fa672bc44209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68862
9308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.688629308
Directory /workspace/9.usbdev_stall_trans/latest
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