Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115513	1		T1	3		T2	2		T3	4
all_values[1]	115513	1		T1	3		T2	2		T3	4
all_values[2]	115513	1		T1	3		T2	2		T3	4
all_values[3]	115513	1		T1	3		T2	2		T3	4
all_values[4]	115513	1		T1	3		T2	2		T3	4
all_values[5]	115513	1		T1	3		T2	2		T3	4
all_values[6]	115513	1		T1	3		T2	2		T3	4
all_values[7]	115513	1		T1	3		T2	2		T3	4
all_values[8]	115513	1		T1	3		T2	2		T3	4
all_values[9]	115513	1		T1	3		T2	2		T3	4
all_values[10]	115513	1		T1	3		T2	2		T3	4
all_values[11]	115513	1		T1	3		T2	2		T3	4
all_values[12]	115513	1		T1	3		T2	2		T3	4
all_values[13]	115513	1		T1	3		T2	2		T3	4
all_values[14]	115513	1		T1	3		T2	2		T3	4
all_values[15]	115513	1		T1	3		T2	2		T3	4
all_values[16]	115513	1		T1	3		T2	2		T3	4
all_values[17]	115513	1		T1	3		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2075306	1		T1	51		T2	36		T3	72
auto[1]	3928	1		T1	3		T19	3		T16	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2074130	1		T1	54		T2	36		T3	72
auto[1]	5104	1		T72	62		T73	78		T74	119

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114498	1		T2	2		T3	4		T7	2
all_values[0]	auto[0]	auto[1]	169	1		T72	3		T73	3		T74	4
all_values[0]	auto[1]	auto[0]	715	1		T1	3		T16	3		T29	3
all_values[0]	auto[1]	auto[1]	131	1		T73	1		T74	4		T76	3
all_values[1]	auto[0]	auto[0]	114901	1		T1	3		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	153	1		T72	5		T73	4		T76	4
all_values[1]	auto[1]	auto[0]	329	1		T19	3		T42	3		T43	3
all_values[1]	auto[1]	auto[1]	130	1		T73	1		T80	3		T77	5
all_values[2]	auto[0]	auto[0]	115218	1		T1	3		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	122	1		T73	3		T74	1		T80	3
all_values[2]	auto[1]	auto[0]	22	1		T72	1		T73	2		T76	1
all_values[2]	auto[1]	auto[1]	151	1		T74	7		T80	5		T77	4
all_values[3]	auto[0]	auto[0]	115206	1		T1	3		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	149	1		T72	5		T73	2		T74	5
all_values[3]	auto[1]	auto[0]	34	1		T74	1		T76	1		T78	2
all_values[3]	auto[1]	auto[1]	124	1		T73	3		T74	2		T80	7
all_values[4]	auto[0]	auto[0]	115195	1		T1	3		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	139	1		T72	2		T73	2		T74	3
all_values[4]	auto[1]	auto[0]	19	1		T287	4		T288	1		T289	2
all_values[4]	auto[1]	auto[1]	160	1		T72	3		T73	3		T74	5
all_values[5]	auto[0]	auto[0]	115208	1		T1	3		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	148	1		T72	3		T73	5		T74	4
all_values[5]	auto[1]	auto[0]	28	1		T72	2		T79	1		T290	3
all_values[5]	auto[1]	auto[1]	129	1		T74	4		T80	1		T77	2
all_values[6]	auto[0]	auto[0]	115204	1		T1	3		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	149	1		T72	4		T74	6		T80	5
all_values[6]	auto[1]	auto[0]	16	1		T73	1		T77	2		T79	1
all_values[6]	auto[1]	auto[1]	144	1		T72	1		T73	3		T74	2
all_values[7]	auto[0]	auto[0]	115217	1		T1	3		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	144	1		T72	3		T73	2		T74	4
all_values[7]	auto[1]	auto[0]	37	1		T76	1		T80	1		T79	1
all_values[7]	auto[1]	auto[1]	115	1		T72	2		T73	3		T74	3
all_values[8]	auto[0]	auto[0]	115203	1		T1	3		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	144	1		T73	1		T74	2		T80	3
all_values[8]	auto[1]	auto[0]	23	1		T72	1		T76	4		T80	1
all_values[8]	auto[1]	auto[1]	143	1		T73	4		T74	6		T80	4
all_values[9]	auto[0]	auto[0]	115205	1		T1	3		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	130	1		T73	4		T74	1		T76	1
all_values[9]	auto[1]	auto[0]	25	1		T80	1		T77	1		T79	2
all_values[9]	auto[1]	auto[1]	153	1		T74	6		T76	4		T80	2
all_values[10]	auto[0]	auto[0]	115198	1		T1	3		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	150	1		T72	4		T73	4		T74	2
all_values[10]	auto[1]	auto[0]	17	1		T76	1		T77	2		T291	1
all_values[10]	auto[1]	auto[1]	148	1		T72	1		T73	1		T74	5
all_values[11]	auto[0]	auto[0]	115200	1		T1	3		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	138	1		T72	3		T73	1		T74	1
all_values[11]	auto[1]	auto[0]	27	1		T72	2		T76	1		T80	2
all_values[11]	auto[1]	auto[1]	148	1		T73	4		T74	4		T76	3
all_values[12]	auto[0]	auto[0]	115208	1		T1	3		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	117	1		T74	4		T77	1		T78	3
all_values[12]	auto[1]	auto[0]	45	1		T72	1		T73	1		T74	2
all_values[12]	auto[1]	auto[1]	143	1		T72	3		T73	3		T74	1
all_values[13]	auto[0]	auto[0]	115218	1		T1	3		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	165	1		T72	2		T73	3		T74	2
all_values[13]	auto[1]	auto[0]	20	1		T74	1		T80	1		T77	5
all_values[13]	auto[1]	auto[1]	110	1		T72	3		T73	1		T74	4
all_values[14]	auto[0]	auto[0]	115201	1		T1	3		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	146	1		T73	3		T74	4		T76	4
all_values[14]	auto[1]	auto[0]	26	1		T72	2		T80	1		T78	1
all_values[14]	auto[1]	auto[1]	140	1		T73	2		T74	3		T80	3
all_values[15]	auto[0]	auto[0]	115199	1		T1	3		T2	2		T3	4
all_values[15]	auto[0]	auto[1]	179	1		T72	4		T73	4		T74	4
all_values[15]	auto[1]	auto[0]	21	1		T73	1		T74	1		T77	1
all_values[15]	auto[1]	auto[1]	114	1		T72	1		T74	3		T76	5
all_values[16]	auto[0]	auto[0]	115203	1		T1	3		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	147	1		T72	1		T73	3		T74	2
all_values[16]	auto[1]	auto[0]	26	1		T73	1		T77	3		T78	2
all_values[16]	auto[1]	auto[1]	137	1		T72	4		T74	6		T80	3
all_values[17]	auto[0]	auto[0]	115195	1		T1	3		T2	2		T3	4
all_values[17]	auto[0]	auto[1]	140	1		T72	1		T73	2		T74	3
all_values[17]	auto[1]	auto[0]	23	1		T76	4		T292	2		T291	5
all_values[17]	auto[1]	auto[1]	155	1		T72	4		T73	3		T74	2