Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115513	1		T1	3		T2	2		T3	4
all_pins[1]	115513	1		T1	3		T2	2		T3	4
all_pins[2]	115513	1		T1	3		T2	2		T3	4
all_pins[3]	115513	1		T1	3		T2	2		T3	4
all_pins[4]	115513	1		T1	3		T2	2		T3	4
all_pins[5]	115513	1		T1	3		T2	2		T3	4
all_pins[6]	115513	1		T1	3		T2	2		T3	4
all_pins[7]	115513	1		T1	3		T2	2		T3	4
all_pins[8]	115513	1		T1	3		T2	2		T3	4
all_pins[9]	115513	1		T1	3		T2	2		T3	4
all_pins[10]	115513	1		T1	3		T2	2		T3	4
all_pins[11]	115513	1		T1	3		T2	2		T3	4
all_pins[12]	115513	1		T1	3		T2	2		T3	4
all_pins[13]	115513	1		T1	3		T2	2		T3	4
all_pins[14]	115513	1		T1	3		T2	2		T3	4
all_pins[15]	115513	1		T1	3		T2	2		T3	4
all_pins[16]	115513	1		T1	3		T2	2		T3	4
all_pins[17]	115513	1		T1	3		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2077931	1		T1	54		T2	36		T3	72
values[0x1]	1303	1		T19	1		T42	1		T43	1
transitions[0x0=>0x1]	1021	1		T19	1		T42	1		T43	1
transitions[0x1=>0x0]	1038	1		T19	1		T42	1		T43	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115353	1		T1	3		T2	2		T3	4
all_pins[0]	values[0x1]	160	1		T56	1		T93	1		T94	1
all_pins[0]	transitions[0x0=>0x1]	149	1		T56	1		T93	1		T94	1
all_pins[0]	transitions[0x1=>0x0]	141	1		T19	1		T42	1		T43	1
all_pins[1]	values[0x0]	115361	1		T1	3		T2	2		T3	4
all_pins[1]	values[0x1]	152	1		T19	1		T42	1		T43	1
all_pins[1]	transitions[0x0=>0x1]	140	1		T19	1		T42	1		T43	1
all_pins[1]	transitions[0x1=>0x0]	67	1		T73	1		T74	4		T80	1
all_pins[2]	values[0x0]	115434	1		T1	3		T2	2		T3	4
all_pins[2]	values[0x1]	79	1		T73	2		T74	4		T80	1
all_pins[2]	transitions[0x0=>0x1]	65	1		T73	2		T74	3		T79	1
all_pins[2]	transitions[0x1=>0x0]	38	1		T74	1		T80	3		T77	3
all_pins[3]	values[0x0]	115461	1		T1	3		T2	2		T3	4
all_pins[3]	values[0x1]	52	1		T74	2		T80	4		T77	3
all_pins[3]	transitions[0x0=>0x1]	38	1		T74	2		T80	2		T77	2
all_pins[3]	transitions[0x1=>0x0]	62	1		T73	2		T74	1		T76	1
all_pins[4]	values[0x0]	115437	1		T1	3		T2	2		T3	4
all_pins[4]	values[0x1]	76	1		T73	2		T74	1		T76	1
all_pins[4]	transitions[0x0=>0x1]	64	1		T73	2		T74	1		T76	1
all_pins[4]	transitions[0x1=>0x0]	41	1		T77	1		T78	2		T79	2
all_pins[5]	values[0x0]	115460	1		T1	3		T2	2		T3	4
all_pins[5]	values[0x1]	53	1		T77	2		T78	2		T79	2
all_pins[5]	transitions[0x0=>0x1]	35	1		T77	1		T78	1		T79	2
all_pins[5]	transitions[0x1=>0x0]	59	1		T73	2		T74	1		T76	4
all_pins[6]	values[0x0]	115436	1		T1	3		T2	2		T3	4
all_pins[6]	values[0x1]	77	1		T73	2		T74	1		T76	4
all_pins[6]	transitions[0x0=>0x1]	67	1		T73	2		T76	4		T80	1
all_pins[6]	transitions[0x1=>0x0]	36	1		T72	1		T74	1		T80	1
all_pins[7]	values[0x0]	115467	1		T1	3		T2	2		T3	4
all_pins[7]	values[0x1]	46	1		T72	1		T74	2		T80	1
all_pins[7]	transitions[0x0=>0x1]	32	1		T72	1		T74	2		T80	1
all_pins[7]	transitions[0x1=>0x0]	46	1		T73	2		T74	2		T79	3
all_pins[8]	values[0x0]	115453	1		T1	3		T2	2		T3	4
all_pins[8]	values[0x1]	60	1		T73	2		T74	2		T78	2
all_pins[8]	transitions[0x0=>0x1]	45	1		T73	2		T74	2		T78	2
all_pins[8]	transitions[0x1=>0x0]	53	1		T76	2		T80	2		T77	3
all_pins[9]	values[0x0]	115445	1		T1	3		T2	2		T3	4
all_pins[9]	values[0x1]	68	1		T76	2		T80	2		T77	3
all_pins[9]	transitions[0x0=>0x1]	41	1		T76	2		T80	1		T77	3
all_pins[9]	transitions[0x1=>0x0]	47	1		T73	1		T76	1		T80	2
all_pins[10]	values[0x0]	115439	1		T1	3		T2	2		T3	4
all_pins[10]	values[0x1]	74	1		T73	1		T76	1		T80	3
all_pins[10]	transitions[0x0=>0x1]	54	1		T76	1		T80	1		T78	1
all_pins[10]	transitions[0x1=>0x0]	29	1		T74	1		T80	1		T77	1
all_pins[11]	values[0x0]	115464	1		T1	3		T2	2		T3	4
all_pins[11]	values[0x1]	49	1		T73	1		T74	1		T80	3
all_pins[11]	transitions[0x0=>0x1]	33	1		T73	1		T74	1		T77	2
all_pins[11]	transitions[0x1=>0x0]	52	1		T72	2		T74	1		T76	3
all_pins[12]	values[0x0]	115445	1		T1	3		T2	2		T3	4
all_pins[12]	values[0x1]	68	1		T72	2		T74	1		T76	3
all_pins[12]	transitions[0x0=>0x1]	49	1		T72	2		T74	1		T76	3
all_pins[12]	transitions[0x1=>0x0]	36	1		T73	1		T74	3		T80	1
all_pins[13]	values[0x0]	115458	1		T1	3		T2	2		T3	4
all_pins[13]	values[0x1]	55	1		T73	1		T74	3		T80	4
all_pins[13]	transitions[0x0=>0x1]	46	1		T74	3		T80	2		T78	2
all_pins[13]	transitions[0x1=>0x0]	52	1		T73	1		T80	1		T77	2
all_pins[14]	values[0x0]	115452	1		T1	3		T2	2		T3	4
all_pins[14]	values[0x1]	61	1		T73	2		T80	3		T77	2
all_pins[14]	transitions[0x0=>0x1]	44	1		T73	2		T80	2		T77	2
all_pins[14]	transitions[0x1=>0x0]	35	1		T72	1		T74	2		T78	1
all_pins[15]	values[0x0]	115461	1		T1	3		T2	2		T3	4
all_pins[15]	values[0x1]	52	1		T72	1		T74	2		T80	1
all_pins[15]	transitions[0x0=>0x1]	40	1		T72	1		T74	1		T80	1
all_pins[15]	transitions[0x1=>0x0]	43	1		T72	3		T74	2		T80	1
all_pins[16]	values[0x0]	115458	1		T1	3		T2	2		T3	4
all_pins[16]	values[0x1]	55	1		T72	3		T74	3		T80	1
all_pins[16]	transitions[0x0=>0x1]	44	1		T72	3		T74	2		T80	1
all_pins[16]	transitions[0x1=>0x0]	55	1		T72	1		T80	3		T77	1
all_pins[17]	values[0x0]	115447	1		T1	3		T2	2		T3	4
all_pins[17]	values[0x1]	66	1		T72	1		T74	1		T80	3
all_pins[17]	transitions[0x0=>0x1]	35	1		T72	1		T74	1		T80	1
all_pins[17]	transitions[0x1=>0x0]	146	1		T56	1		T93	1		T94	1