Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T72	4		T73	4		T74	7
all_values[1]	284	1		T72	4		T73	4		T74	7
all_values[2]	284	1		T72	4		T73	4		T74	7
all_values[3]	284	1		T72	4		T73	4		T74	7
all_values[4]	284	1		T72	4		T73	4		T74	7
all_values[5]	284	1		T72	4		T73	4		T74	7
all_values[6]	284	1		T72	4		T73	4		T74	7
all_values[7]	284	1		T72	4		T73	4		T74	7
all_values[8]	284	1		T72	4		T73	4		T74	7
all_values[9]	284	1		T72	4		T73	4		T74	7
all_values[10]	284	1		T72	4		T73	4		T74	7
all_values[11]	284	1		T72	4		T73	4		T74	7
all_values[12]	284	1		T72	4		T73	4		T74	7
all_values[13]	284	1		T72	4		T73	4		T74	7
all_values[14]	284	1		T72	4		T73	4		T74	7
all_values[15]	284	1		T72	4		T73	4		T74	7
all_values[16]	284	1		T72	4		T73	4		T74	7
all_values[17]	284	1		T72	4		T73	4		T74	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2892	1		T72	56		T73	40		T74	60
auto[1]	2220	1		T72	16		T73	32		T74	66

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	851	1		T72	24		T73	12		T74	24
auto[1]	4261	1		T72	48		T73	60		T74	102

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2997	1		T72	52		T73	43		T74	83
auto[1]	2115	1		T72	20		T73	29		T74	43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	21	1		T72	1		T73	1		T77	1
all_values[0]	auto[0]	auto[0]	auto[1]	69	1		T72	1		T73	1		T74	3
all_values[0]	auto[0]	auto[1]	auto[0]	11	1		T72	1		T79	2		T293	1
all_values[0]	auto[0]	auto[1]	auto[1]	54	1		T74	3		T76	1		T80	3
all_values[0]	auto[1]	auto[0]	auto[1]	83	1		T72	1		T73	2		T76	1
all_values[0]	auto[1]	auto[1]	auto[1]	46	1		T74	1		T77	2		T79	2
all_values[1]	auto[0]	auto[0]	auto[0]	26	1		T74	1		T77	1		T79	2
all_values[1]	auto[0]	auto[0]	auto[1]	64	1		T72	2		T73	2		T76	1
all_values[1]	auto[0]	auto[1]	auto[0]	22	1		T74	6		T76	1		T79	2
all_values[1]	auto[0]	auto[1]	auto[1]	56	1		T73	1		T80	2		T77	1
all_values[1]	auto[1]	auto[0]	auto[1]	79	1		T72	2		T76	2		T80	1
all_values[1]	auto[1]	auto[1]	auto[1]	37	1		T73	1		T77	2		T290	1
all_values[2]	auto[0]	auto[0]	auto[0]	42	1		T72	4		T76	2		T77	1
all_values[2]	auto[0]	auto[0]	auto[1]	46	1		T73	1		T80	1		T77	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T73	2		T76	2		T292	1
all_values[2]	auto[0]	auto[1]	auto[1]	66	1		T74	3		T80	3		T77	2
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T73	1		T80	3		T77	1
all_values[2]	auto[1]	auto[1]	auto[1]	58	1		T74	4		T77	1		T78	1
all_values[3]	auto[0]	auto[0]	auto[0]	29	1		T76	1		T78	1		T79	1
all_values[3]	auto[0]	auto[0]	auto[1]	62	1		T72	3		T73	1		T74	3
all_values[3]	auto[0]	auto[1]	auto[0]	26	1		T74	1		T76	1		T78	1
all_values[3]	auto[0]	auto[1]	auto[1]	50	1		T73	1		T80	3		T77	2
all_values[3]	auto[1]	auto[0]	auto[1]	67	1		T72	1		T73	1		T74	1
all_values[3]	auto[1]	auto[1]	auto[1]	50	1		T73	1		T74	2		T80	2
all_values[4]	auto[0]	auto[0]	auto[0]	19	1		T76	1		T284	1		T292	1
all_values[4]	auto[0]	auto[0]	auto[1]	68	1		T73	1		T74	3		T76	1
all_values[4]	auto[0]	auto[1]	auto[0]	15	1		T287	2		T289	2		T294	3
all_values[4]	auto[0]	auto[1]	auto[1]	69	1		T72	2		T73	1		T74	2
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T72	2		T73	1		T80	4
all_values[4]	auto[1]	auto[1]	auto[1]	50	1		T73	1		T74	2		T76	2
all_values[5]	auto[0]	auto[0]	auto[0]	34	1		T72	1		T76	1		T80	1
all_values[5]	auto[0]	auto[0]	auto[1]	67	1		T72	1		T73	2		T74	4
all_values[5]	auto[0]	auto[1]	auto[0]	19	1		T72	1		T79	1		T290	2
all_values[5]	auto[0]	auto[1]	auto[1]	46	1		T74	1		T80	1		T77	1
all_values[5]	auto[1]	auto[0]	auto[1]	71	1		T72	1		T73	2		T74	2
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T77	1		T78	3		T79	3
all_values[6]	auto[0]	auto[0]	auto[0]	31	1		T73	2		T80	2		T77	1
all_values[6]	auto[0]	auto[0]	auto[1]	62	1		T72	3		T74	1		T80	1
all_values[6]	auto[0]	auto[1]	auto[0]	9	1		T77	1		T295	1		T291	1
all_values[6]	auto[0]	auto[1]	auto[1]	62	1		T73	1		T74	2		T76	3
all_values[6]	auto[1]	auto[0]	auto[1]	71	1		T72	1		T74	3		T80	2
all_values[6]	auto[1]	auto[1]	auto[1]	49	1		T73	1		T74	1		T76	1
all_values[7]	auto[0]	auto[0]	auto[0]	46	1		T74	1		T80	3		T290	4
all_values[7]	auto[0]	auto[0]	auto[1]	60	1		T72	2		T73	1		T74	1
all_values[7]	auto[0]	auto[1]	auto[0]	24	1		T76	1		T79	1		T295	3
all_values[7]	auto[0]	auto[1]	auto[1]	46	1		T72	1		T73	2		T74	1
all_values[7]	auto[1]	auto[0]	auto[1]	62	1		T72	1		T73	1		T74	2
all_values[7]	auto[1]	auto[1]	auto[1]	46	1		T74	2		T80	1		T77	2
all_values[8]	auto[0]	auto[0]	auto[0]	31	1		T72	4		T76	2		T80	1
all_values[8]	auto[0]	auto[0]	auto[1]	62	1		T74	2		T80	3		T77	4
all_values[8]	auto[0]	auto[1]	auto[0]	12	1		T76	2		T285	4		T296	1
all_values[8]	auto[0]	auto[1]	auto[1]	58	1		T73	1		T74	3		T80	2
all_values[8]	auto[1]	auto[0]	auto[1]	69	1		T73	2		T74	1		T80	1
all_values[8]	auto[1]	auto[1]	auto[1]	52	1		T73	1		T74	1		T78	2
all_values[9]	auto[0]	auto[0]	auto[0]	34	1		T72	4		T73	1		T74	1
all_values[9]	auto[0]	auto[0]	auto[1]	59	1		T73	2		T76	1		T80	2
all_values[9]	auto[0]	auto[1]	auto[0]	13	1		T79	2		T284	1		T292	1
all_values[9]	auto[0]	auto[1]	auto[1]	63	1		T74	4		T76	1		T77	2
all_values[9]	auto[1]	auto[0]	auto[1]	66	1		T73	1		T74	1		T76	1
all_values[9]	auto[1]	auto[1]	auto[1]	49	1		T74	1		T76	1		T80	2
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T74	1		T77	1		T79	1
all_values[10]	auto[0]	auto[0]	auto[1]	60	1		T72	2		T73	1		T74	2
all_values[10]	auto[0]	auto[1]	auto[0]	11	1		T76	1		T77	2		T297	2
all_values[10]	auto[0]	auto[1]	auto[1]	54	1		T74	3		T80	2		T78	4
all_values[10]	auto[1]	auto[0]	auto[1]	74	1		T72	2		T73	1		T74	1
all_values[10]	auto[1]	auto[1]	auto[1]	61	1		T73	2		T76	2		T80	1
all_values[11]	auto[0]	auto[0]	auto[0]	29	1		T72	1		T74	3		T76	1
all_values[11]	auto[0]	auto[0]	auto[1]	62	1		T72	1		T77	2		T78	5
all_values[11]	auto[0]	auto[1]	auto[0]	16	1		T72	1		T76	1		T80	1
all_values[11]	auto[0]	auto[1]	auto[1]	59	1		T73	2		T74	1		T76	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1		T72	1		T74	2		T80	1
all_values[11]	auto[1]	auto[1]	auto[1]	49	1		T73	2		T74	1		T76	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1		T72	2		T80	1		T77	2
all_values[12]	auto[0]	auto[0]	auto[1]	48	1		T74	1		T78	1		T79	1
all_values[12]	auto[0]	auto[1]	auto[0]	39	1		T73	2		T74	3		T76	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1		T72	1		T73	1		T74	1
all_values[12]	auto[1]	auto[0]	auto[1]	58	1		T74	1		T78	1		T290	1
all_values[12]	auto[1]	auto[1]	auto[1]	49	1		T72	1		T73	1		T74	1
all_values[13]	auto[0]	auto[0]	auto[0]	41	1		T73	1		T74	2		T80	1
all_values[13]	auto[0]	auto[0]	auto[1]	78	1		T72	1		T73	2		T74	1
all_values[13]	auto[0]	auto[1]	auto[0]	13	1		T77	3		T79	1		T285	3
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T72	2		T74	2		T80	2
all_values[13]	auto[1]	auto[0]	auto[1]	65	1		T72	1		T73	1		T74	1
all_values[13]	auto[1]	auto[1]	auto[1]	36	1		T74	1		T80	2		T78	1
all_values[14]	auto[0]	auto[0]	auto[0]	28	1		T72	3		T74	1		T76	1
all_values[14]	auto[0]	auto[0]	auto[1]	69	1		T73	2		T74	3		T76	2
all_values[14]	auto[0]	auto[1]	auto[0]	17	1		T72	1		T80	1		T285	4
all_values[14]	auto[0]	auto[1]	auto[1]	58	1		T74	1		T80	1		T77	2
all_values[14]	auto[1]	auto[0]	auto[1]	67	1		T74	2		T76	1		T77	2
all_values[14]	auto[1]	auto[1]	auto[1]	45	1		T73	2		T80	3		T77	2
all_values[15]	auto[0]	auto[0]	auto[0]	26	1		T80	1		T77	1		T78	1
all_values[15]	auto[0]	auto[0]	auto[1]	70	1		T72	3		T73	2		T74	2
all_values[15]	auto[0]	auto[1]	auto[0]	13	1		T73	1		T74	1		T78	1
all_values[15]	auto[0]	auto[1]	auto[1]	43	1		T74	1		T76	3		T80	2
all_values[15]	auto[1]	auto[0]	auto[1]	72	1		T72	1		T78	1		T79	2
all_values[15]	auto[1]	auto[1]	auto[1]	60	1		T73	1		T74	3		T76	1
all_values[16]	auto[0]	auto[0]	auto[0]	26	1		T76	1		T77	1		T78	1
all_values[16]	auto[0]	auto[0]	auto[1]	57	1		T73	1		T76	1		T80	2
all_values[16]	auto[0]	auto[1]	auto[0]	21	1		T73	2		T77	2		T78	1
all_values[16]	auto[0]	auto[1]	auto[1]	61	1		T72	1		T74	3		T80	2
all_values[16]	auto[1]	auto[0]	auto[1]	69	1		T72	1		T73	1		T74	3
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T72	2		T74	1		T80	1
all_values[17]	auto[0]	auto[0]	auto[0]	23	1		T74	3		T76	2		T286	1
all_values[17]	auto[0]	auto[0]	auto[1]	60	1		T74	1		T80	1		T77	2
all_values[17]	auto[0]	auto[1]	auto[0]	13	1		T76	2		T292	2		T291	3
all_values[17]	auto[0]	auto[1]	auto[1]	68	1		T72	2		T73	2		T74	1
all_values[17]	auto[1]	auto[0]	auto[1]	67	1		T72	2		T73	2		T80	2
all_values[17]	auto[1]	auto[1]	auto[1]	53	1		T74	2		T80	2		T77	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal