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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.97 96.79 89.43 97.32 50.00 94.71 97.96 96.58


Total test records in report: 1481
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T1328 /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1662874169 May 02 03:46:16 PM PDT 24 May 02 03:46:24 PM PDT 24 8380190292 ps
T1329 /workspace/coverage/default/33.max_length_in_transaction.127475641 May 02 03:47:28 PM PDT 24 May 02 03:47:37 PM PDT 24 8486818955 ps
T1330 /workspace/coverage/default/28.usbdev_stall_trans.583777592 May 02 03:46:38 PM PDT 24 May 02 03:46:46 PM PDT 24 8394860966 ps
T1331 /workspace/coverage/default/2.usbdev_setup_stage.4133435604 May 02 03:44:44 PM PDT 24 May 02 03:44:53 PM PDT 24 8375634646 ps
T1332 /workspace/coverage/default/40.max_length_in_transaction.2640508756 May 02 03:48:18 PM PDT 24 May 02 03:48:28 PM PDT 24 8504233467 ps
T1333 /workspace/coverage/default/41.usbdev_pkt_buffer.3260393860 May 02 03:47:53 PM PDT 24 May 02 03:48:56 PM PDT 24 29331741392 ps
T1334 /workspace/coverage/default/19.usbdev_av_buffer.500959209 May 02 03:45:53 PM PDT 24 May 02 03:46:02 PM PDT 24 8376146333 ps
T1335 /workspace/coverage/default/5.usbdev_in_stall.3444758166 May 02 03:44:56 PM PDT 24 May 02 03:45:06 PM PDT 24 8366383153 ps
T1336 /workspace/coverage/default/9.random_length_in_trans.2588914591 May 02 03:45:16 PM PDT 24 May 02 03:45:26 PM PDT 24 8431334974 ps
T1337 /workspace/coverage/default/25.usbdev_smoke.1957630567 May 02 03:46:32 PM PDT 24 May 02 03:46:41 PM PDT 24 8459753429 ps
T1338 /workspace/coverage/default/24.usbdev_pkt_buffer.2203492087 May 02 03:46:21 PM PDT 24 May 02 03:46:54 PM PDT 24 16399220806 ps
T1339 /workspace/coverage/default/19.usbdev_out_stall.3237710628 May 02 03:45:52 PM PDT 24 May 02 03:46:01 PM PDT 24 8389900622 ps
T1340 /workspace/coverage/default/28.usbdev_smoke.3893481985 May 02 03:46:34 PM PDT 24 May 02 03:46:46 PM PDT 24 8459635683 ps
T1341 /workspace/coverage/default/14.random_length_in_trans.3970543291 May 02 03:45:44 PM PDT 24 May 02 03:45:54 PM PDT 24 8420108484 ps
T1342 /workspace/coverage/default/39.usbdev_smoke.55315573 May 02 03:47:44 PM PDT 24 May 02 03:47:55 PM PDT 24 8452957110 ps
T1343 /workspace/coverage/default/30.usbdev_in_trans.2512885758 May 02 03:46:50 PM PDT 24 May 02 03:47:01 PM PDT 24 8443251100 ps
T1344 /workspace/coverage/default/24.usbdev_out_stall.575342025 May 02 03:46:23 PM PDT 24 May 02 03:46:34 PM PDT 24 8453138326 ps
T1345 /workspace/coverage/default/45.usbdev_random_length_out_trans.401120834 May 02 03:48:31 PM PDT 24 May 02 03:48:42 PM PDT 24 8405124792 ps
T1346 /workspace/coverage/default/11.usbdev_in_stall.730608616 May 02 03:45:27 PM PDT 24 May 02 03:45:38 PM PDT 24 8455663985 ps
T1347 /workspace/coverage/default/14.usbdev_av_buffer.527105949 May 02 03:45:48 PM PDT 24 May 02 03:45:58 PM PDT 24 8401744496 ps
T1348 /workspace/coverage/default/2.usbdev_pkt_received.84439702 May 02 03:44:43 PM PDT 24 May 02 03:44:53 PM PDT 24 8391858396 ps
T1349 /workspace/coverage/default/35.usbdev_nak_trans.2205735575 May 02 03:47:43 PM PDT 24 May 02 03:47:54 PM PDT 24 8417261952 ps
T1350 /workspace/coverage/default/46.usbdev_in_trans.3698445389 May 02 03:48:39 PM PDT 24 May 02 03:48:50 PM PDT 24 8404863355 ps
T1351 /workspace/coverage/default/18.usbdev_in_iso.3859479925 May 02 03:45:54 PM PDT 24 May 02 03:46:04 PM PDT 24 8446975800 ps
T1352 /workspace/coverage/default/49.random_length_in_trans.2614694028 May 02 03:48:41 PM PDT 24 May 02 03:48:55 PM PDT 24 8466614221 ps
T1353 /workspace/coverage/default/38.random_length_in_trans.3889371266 May 02 03:47:47 PM PDT 24 May 02 03:48:04 PM PDT 24 8460252364 ps
T1354 /workspace/coverage/default/1.usbdev_phy_pins_sense.1936105390 May 02 03:44:43 PM PDT 24 May 02 03:44:45 PM PDT 24 136684567 ps
T1355 /workspace/coverage/default/31.min_length_in_transaction.3509843401 May 02 03:47:30 PM PDT 24 May 02 03:47:41 PM PDT 24 8378717024 ps
T1356 /workspace/coverage/default/33.usbdev_out_trans_nak.1636340107 May 02 03:47:39 PM PDT 24 May 02 03:47:48 PM PDT 24 8411918731 ps
T1357 /workspace/coverage/default/49.usbdev_pending_in_trans.2706928884 May 02 03:48:35 PM PDT 24 May 02 03:48:45 PM PDT 24 8386110144 ps
T1358 /workspace/coverage/default/4.random_length_in_trans.2149365761 May 02 03:44:51 PM PDT 24 May 02 03:45:01 PM PDT 24 8446888860 ps
T1359 /workspace/coverage/default/8.usbdev_smoke.3557682417 May 02 03:45:05 PM PDT 24 May 02 03:45:16 PM PDT 24 8411093739 ps
T1360 /workspace/coverage/default/23.usbdev_smoke.3547694945 May 02 03:46:22 PM PDT 24 May 02 03:46:33 PM PDT 24 8416765713 ps
T1361 /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1279131867 May 02 03:45:07 PM PDT 24 May 02 03:45:16 PM PDT 24 8362351862 ps
T1362 /workspace/coverage/default/38.max_length_in_transaction.525484556 May 02 03:47:51 PM PDT 24 May 02 03:48:03 PM PDT 24 8467270185 ps
T1363 /workspace/coverage/default/4.usbdev_in_iso.877606225 May 02 03:44:53 PM PDT 24 May 02 03:45:03 PM PDT 24 8425479691 ps
T1364 /workspace/coverage/default/10.random_length_in_trans.3865728380 May 02 03:45:27 PM PDT 24 May 02 03:45:37 PM PDT 24 8456788836 ps
T1365 /workspace/coverage/default/5.random_length_in_trans.1045223640 May 02 03:45:00 PM PDT 24 May 02 03:45:10 PM PDT 24 8459447989 ps
T1366 /workspace/coverage/default/33.usbdev_pkt_sent.3807620633 May 02 03:47:27 PM PDT 24 May 02 03:47:37 PM PDT 24 8444651056 ps
T1367 /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2402657505 May 02 03:44:34 PM PDT 24 May 02 03:44:43 PM PDT 24 8391467318 ps
T1368 /workspace/coverage/default/6.usbdev_in_stall.1157914563 May 02 03:44:59 PM PDT 24 May 02 03:45:09 PM PDT 24 8370608310 ps
T1369 /workspace/coverage/default/28.usbdev_pkt_received.1391193969 May 02 03:46:31 PM PDT 24 May 02 03:46:40 PM PDT 24 8403068851 ps
T1370 /workspace/coverage/default/49.usbdev_nak_trans.475100218 May 02 03:48:39 PM PDT 24 May 02 03:48:51 PM PDT 24 8411250947 ps
T1371 /workspace/coverage/default/44.random_length_in_trans.2075647031 May 02 03:48:21 PM PDT 24 May 02 03:48:30 PM PDT 24 8470665185 ps
T1372 /workspace/coverage/default/29.usbdev_setup_stage.2236659286 May 02 03:46:50 PM PDT 24 May 02 03:47:01 PM PDT 24 8379191766 ps
T1373 /workspace/coverage/default/8.usbdev_fifo_rst.3598631011 May 02 03:45:03 PM PDT 24 May 02 03:45:06 PM PDT 24 60341921 ps
T1374 /workspace/coverage/default/42.max_length_in_transaction.2612368270 May 02 03:48:02 PM PDT 24 May 02 03:48:13 PM PDT 24 8468082594 ps
T1375 /workspace/coverage/default/37.usbdev_setup_stage.3706522113 May 02 03:47:47 PM PDT 24 May 02 03:47:59 PM PDT 24 8372361363 ps
T1376 /workspace/coverage/default/13.usbdev_pkt_received.2412279819 May 02 03:45:37 PM PDT 24 May 02 03:45:48 PM PDT 24 8409555059 ps
T1377 /workspace/coverage/default/23.usbdev_pkt_sent.2255957149 May 02 03:46:24 PM PDT 24 May 02 03:46:35 PM PDT 24 8488402075 ps
T1378 /workspace/coverage/default/9.usbdev_out_trans_nak.3189193828 May 02 03:45:07 PM PDT 24 May 02 03:45:16 PM PDT 24 8394826147 ps
T1379 /workspace/coverage/default/36.usbdev_pkt_received.3857848025 May 02 03:47:44 PM PDT 24 May 02 03:47:55 PM PDT 24 8423096181 ps
T1380 /workspace/coverage/default/39.usbdev_stall_trans.2198004063 May 02 03:47:50 PM PDT 24 May 02 03:48:02 PM PDT 24 8409330053 ps
T1381 /workspace/coverage/default/20.usbdev_pkt_buffer.1498201822 May 02 03:46:01 PM PDT 24 May 02 03:47:03 PM PDT 24 27642053945 ps
T1382 /workspace/coverage/default/33.usbdev_fifo_rst.1552092976 May 02 03:47:40 PM PDT 24 May 02 03:47:44 PM PDT 24 188128392 ps
T1383 /workspace/coverage/default/27.usbdev_pkt_sent.1114303491 May 02 03:46:49 PM PDT 24 May 02 03:47:01 PM PDT 24 8436170889 ps
T1384 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1844382933 May 02 03:53:55 PM PDT 24 May 02 03:54:00 PM PDT 24 368077059 ps
T68 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3266201865 May 02 03:54:01 PM PDT 24 May 02 03:54:07 PM PDT 24 132739496 ps
T69 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3710356116 May 02 03:54:03 PM PDT 24 May 02 03:54:08 PM PDT 24 82719230 ps
T70 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2210346814 May 02 03:54:06 PM PDT 24 May 02 03:54:11 PM PDT 24 298466804 ps
T1385 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2310936948 May 02 03:54:06 PM PDT 24 May 02 03:54:12 PM PDT 24 267501594 ps
T71 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.922706459 May 02 03:54:02 PM PDT 24 May 02 03:54:07 PM PDT 24 141356662 ps
T72 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.599547382 May 02 03:54:17 PM PDT 24 May 02 03:54:18 PM PDT 24 36698638 ps
T205 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2837781240 May 02 03:55:13 PM PDT 24 May 02 03:55:16 PM PDT 24 30428739 ps
T73 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2696493570 May 02 03:54:06 PM PDT 24 May 02 03:54:10 PM PDT 24 33659757 ps
T206 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2916113685 May 02 03:53:51 PM PDT 24 May 02 03:53:57 PM PDT 24 291183107 ps
T207 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2023879095 May 02 03:55:15 PM PDT 24 May 02 03:55:18 PM PDT 24 50070546 ps
T62 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3706599142 May 02 03:54:00 PM PDT 24 May 02 03:54:06 PM PDT 24 186344068 ps
T74 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3885425346 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 32253878 ps
T63 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2504770923 May 02 03:53:59 PM PDT 24 May 02 03:54:02 PM PDT 24 54080499 ps
T64 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2384044023 May 02 03:54:01 PM PDT 24 May 02 03:54:07 PM PDT 24 164780813 ps
T75 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3260671431 May 02 03:53:51 PM PDT 24 May 02 03:53:54 PM PDT 24 61515361 ps
T76 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2002677427 May 02 03:54:29 PM PDT 24 May 02 03:54:31 PM PDT 24 44604100 ps
T209 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.9133375 May 02 03:55:15 PM PDT 24 May 02 03:55:19 PM PDT 24 150102078 ps
T208 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2153633875 May 02 03:53:59 PM PDT 24 May 02 03:54:03 PM PDT 24 76581760 ps
T80 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.462098962 May 02 03:53:54 PM PDT 24 May 02 03:53:57 PM PDT 24 30342549 ps
T212 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4070606043 May 02 03:54:08 PM PDT 24 May 02 03:54:14 PM PDT 24 252146857 ps
T213 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.611486815 May 02 03:53:53 PM PDT 24 May 02 03:53:57 PM PDT 24 51137588 ps
T1386 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2104453050 May 02 03:53:56 PM PDT 24 May 02 03:54:03 PM PDT 24 475954260 ps
T214 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3429813976 May 02 03:54:02 PM PDT 24 May 02 03:54:09 PM PDT 24 310574032 ps
T272 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.395620072 May 02 03:53:53 PM PDT 24 May 02 03:53:58 PM PDT 24 192428489 ps
T265 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.342846609 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 43414270 ps
T77 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2281449590 May 02 03:53:58 PM PDT 24 May 02 03:54:00 PM PDT 24 37670762 ps
T78 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1184159198 May 02 03:54:04 PM PDT 24 May 02 03:54:08 PM PDT 24 34209652 ps
T79 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4007738640 May 02 03:54:05 PM PDT 24 May 02 03:54:09 PM PDT 24 30000279 ps
T258 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.258804353 May 02 03:53:53 PM PDT 24 May 02 03:53:58 PM PDT 24 159667553 ps
T1387 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3434595414 May 02 03:54:02 PM PDT 24 May 02 03:54:13 PM PDT 24 164940773 ps
T259 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3653782482 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 83864050 ps
T210 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1788207982 May 02 03:53:52 PM PDT 24 May 02 03:53:59 PM PDT 24 281204876 ps
T231 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2896069492 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 48419803 ps
T290 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.695957943 May 02 03:54:04 PM PDT 24 May 02 03:54:09 PM PDT 24 33107610 ps
T273 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4276961404 May 02 03:53:59 PM PDT 24 May 02 03:54:04 PM PDT 24 128937526 ps
T1388 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.362754096 May 02 03:53:58 PM PDT 24 May 02 03:54:01 PM PDT 24 256540777 ps
T260 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.813570659 May 02 03:55:15 PM PDT 24 May 02 03:55:19 PM PDT 24 194104281 ps
T238 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1037726091 May 02 03:54:00 PM PDT 24 May 02 03:54:09 PM PDT 24 856464673 ps
T284 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3959110737 May 02 03:53:53 PM PDT 24 May 02 03:53:57 PM PDT 24 34775947 ps
T239 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3466096978 May 02 03:54:00 PM PDT 24 May 02 03:54:05 PM PDT 24 86634799 ps
T233 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3878986711 May 02 03:54:01 PM PDT 24 May 02 03:54:08 PM PDT 24 265945789 ps
T240 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1824405033 May 02 03:54:06 PM PDT 24 May 02 03:54:12 PM PDT 24 551444399 ps
T295 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.534778666 May 02 03:54:04 PM PDT 24 May 02 03:54:08 PM PDT 24 27755413 ps
T241 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3028951138 May 02 03:53:54 PM PDT 24 May 02 03:53:59 PM PDT 24 142383516 ps
T235 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1372670727 May 02 03:53:51 PM PDT 24 May 02 03:53:55 PM PDT 24 51565329 ps
T285 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2207880408 May 02 03:54:04 PM PDT 24 May 02 03:54:09 PM PDT 24 23841048 ps
T1389 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1058045054 May 02 03:54:08 PM PDT 24 May 02 03:54:13 PM PDT 24 63786992 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3432577530 May 02 03:53:56 PM PDT 24 May 02 03:54:01 PM PDT 24 190093371 ps
T262 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.471154234 May 02 03:54:07 PM PDT 24 May 02 03:54:12 PM PDT 24 183949480 ps
T286 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.149728410 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 30607196 ps
T263 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.563546392 May 02 03:55:15 PM PDT 24 May 02 03:55:21 PM PDT 24 658610417 ps
T264 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.394858109 May 02 03:54:02 PM PDT 24 May 02 03:54:07 PM PDT 24 32571052 ps
T296 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2892928983 May 02 03:54:05 PM PDT 24 May 02 03:54:10 PM PDT 24 35386483 ps
T279 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4136879081 May 02 03:53:51 PM PDT 24 May 02 03:53:56 PM PDT 24 333968214 ps
T1390 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2157880620 May 02 03:54:00 PM PDT 24 May 02 03:54:07 PM PDT 24 393490886 ps
T292 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2688292709 May 02 03:54:16 PM PDT 24 May 02 03:54:28 PM PDT 24 27365212 ps
T1391 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1050688454 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 36386611 ps
T266 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.398366798 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 34950960 ps
T280 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.275472594 May 02 03:53:59 PM PDT 24 May 02 03:54:07 PM PDT 24 607845148 ps
T281 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2784308344 May 02 03:54:07 PM PDT 24 May 02 03:54:12 PM PDT 24 172805226 ps
T211 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1684895098 May 02 03:53:59 PM PDT 24 May 02 03:54:04 PM PDT 24 164497008 ps
T237 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1438821384 May 02 03:53:51 PM PDT 24 May 02 03:53:57 PM PDT 24 685697641 ps
T1392 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.892321880 May 02 03:54:04 PM PDT 24 May 02 03:54:10 PM PDT 24 157392169 ps
T232 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1903462447 May 02 03:53:54 PM PDT 24 May 02 03:53:59 PM PDT 24 92041667 ps
T291 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3799495026 May 02 03:54:02 PM PDT 24 May 02 03:54:07 PM PDT 24 36673351 ps
T282 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1888510362 May 02 03:53:52 PM PDT 24 May 02 03:54:00 PM PDT 24 719212318 ps
T283 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2509555789 May 02 03:54:06 PM PDT 24 May 02 03:54:11 PM PDT 24 95059460 ps
T293 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.962282388 May 02 03:54:03 PM PDT 24 May 02 03:54:08 PM PDT 24 29232832 ps
T1393 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3944775268 May 02 03:53:59 PM PDT 24 May 02 03:54:04 PM PDT 24 267711858 ps
T287 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1925984346 May 02 03:54:09 PM PDT 24 May 02 03:54:12 PM PDT 24 60588579 ps
T1394 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.679413735 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 94421095 ps
T1395 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.442873012 May 02 03:53:58 PM PDT 24 May 02 03:54:00 PM PDT 24 29249335 ps
T1396 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3355356845 May 02 03:54:07 PM PDT 24 May 02 03:54:11 PM PDT 24 66419070 ps
T234 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.825212847 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 55563495 ps
T1397 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1703630010 May 02 03:54:04 PM PDT 24 May 02 03:54:08 PM PDT 24 45406167 ps
T298 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3138479661 May 02 03:53:59 PM PDT 24 May 02 03:54:05 PM PDT 24 1281881717 ps
T267 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.504300254 May 02 03:54:02 PM PDT 24 May 02 03:54:06 PM PDT 24 54173896 ps
T288 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.581076712 May 02 03:54:05 PM PDT 24 May 02 03:54:09 PM PDT 24 32557666 ps
T1398 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.703711088 May 02 03:53:59 PM PDT 24 May 02 03:54:02 PM PDT 24 71170514 ps
T1399 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.360168730 May 02 03:54:01 PM PDT 24 May 02 03:54:09 PM PDT 24 667666166 ps
T1400 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4006937145 May 02 03:54:08 PM PDT 24 May 02 03:54:12 PM PDT 24 131022474 ps
T1401 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.240511092 May 02 03:54:02 PM PDT 24 May 02 03:54:13 PM PDT 24 2282832298 ps
T300 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2339018661 May 02 03:53:57 PM PDT 24 May 02 03:54:03 PM PDT 24 619573695 ps
T270 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3094290371 May 02 03:54:04 PM PDT 24 May 02 03:54:09 PM PDT 24 80125110 ps
T289 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1638864025 May 02 03:54:00 PM PDT 24 May 02 03:54:04 PM PDT 24 29391827 ps
T1402 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2227247651 May 02 03:54:00 PM PDT 24 May 02 03:54:04 PM PDT 24 71464319 ps
T297 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2069250180 May 02 03:54:09 PM PDT 24 May 02 03:54:12 PM PDT 24 38424531 ps
T271 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2573398698 May 02 03:54:06 PM PDT 24 May 02 03:54:10 PM PDT 24 42627621 ps
T1403 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.198567640 May 02 03:53:59 PM PDT 24 May 02 03:54:04 PM PDT 24 313429772 ps
T1404 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3663871392 May 02 03:54:01 PM PDT 24 May 02 03:54:10 PM PDT 24 28652443 ps
T268 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1806726171 May 02 03:53:55 PM PDT 24 May 02 03:54:06 PM PDT 24 291393448 ps
T236 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2853244148 May 02 03:54:30 PM PDT 24 May 02 03:54:31 PM PDT 24 205165893 ps
T1405 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1121728852 May 02 03:55:15 PM PDT 24 May 02 03:55:19 PM PDT 24 256120147 ps
T1406 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3302758708 May 02 03:54:07 PM PDT 24 May 02 03:54:11 PM PDT 24 83154292 ps
T1407 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3119320065 May 02 03:54:03 PM PDT 24 May 02 03:54:07 PM PDT 24 60635684 ps
T1408 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2389154836 May 02 03:53:58 PM PDT 24 May 02 03:54:02 PM PDT 24 82659508 ps
T1409 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4261477104 May 02 03:54:02 PM PDT 24 May 02 03:54:08 PM PDT 24 139977804 ps
T1410 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3563080237 May 02 03:54:07 PM PDT 24 May 02 03:54:15 PM PDT 24 62748011 ps
T1411 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2202590669 May 02 03:53:59 PM PDT 24 May 02 03:54:03 PM PDT 24 45662785 ps
T1412 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1142230947 May 02 03:54:05 PM PDT 24 May 02 03:54:09 PM PDT 24 33989144 ps
T1413 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1355103538 May 02 03:54:05 PM PDT 24 May 02 03:54:10 PM PDT 24 150854934 ps
T269 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1600706559 May 02 03:53:54 PM PDT 24 May 02 03:53:59 PM PDT 24 190578695 ps
T1414 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1336433371 May 02 03:54:04 PM PDT 24 May 02 03:54:09 PM PDT 24 38368161 ps
T1415 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1005531581 May 02 03:53:53 PM PDT 24 May 02 03:53:58 PM PDT 24 99714194 ps
T1416 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.405068496 May 02 03:54:04 PM PDT 24 May 02 03:54:10 PM PDT 24 270085271 ps
T1417 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3724925187 May 02 03:54:01 PM PDT 24 May 02 03:54:07 PM PDT 24 323815692 ps
T1418 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1519827937 May 02 03:54:01 PM PDT 24 May 02 03:54:07 PM PDT 24 333456279 ps
T1419 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1945317089 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 195364353 ps
T294 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2307491131 May 02 03:54:09 PM PDT 24 May 02 03:54:13 PM PDT 24 33834260 ps
T1420 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1718551855 May 02 03:53:51 PM PDT 24 May 02 03:53:55 PM PDT 24 168175199 ps
T1421 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3465533304 May 02 03:54:07 PM PDT 24 May 02 03:54:12 PM PDT 24 70341741 ps
T1422 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2420969123 May 02 03:54:07 PM PDT 24 May 02 03:54:11 PM PDT 24 26335056 ps
T1423 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1035331640 May 02 03:53:51 PM PDT 24 May 02 03:53:58 PM PDT 24 154598463 ps
T1424 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2535095815 May 02 03:54:15 PM PDT 24 May 02 03:54:17 PM PDT 24 40793896 ps
T1425 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3108528157 May 02 03:54:11 PM PDT 24 May 02 03:54:15 PM PDT 24 75116671 ps
T1426 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.969544757 May 02 03:54:06 PM PDT 24 May 02 03:54:10 PM PDT 24 60958878 ps
T1427 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1837702418 May 02 03:54:02 PM PDT 24 May 02 03:54:07 PM PDT 24 90921202 ps
T1428 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3455594508 May 02 03:54:06 PM PDT 24 May 02 03:54:10 PM PDT 24 31641360 ps
T1429 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1456592629 May 02 03:53:58 PM PDT 24 May 02 03:54:01 PM PDT 24 113731938 ps
T1430 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1559802220 May 02 03:53:59 PM PDT 24 May 02 03:54:02 PM PDT 24 137353421 ps
T1431 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1529524864 May 02 03:53:59 PM PDT 24 May 02 03:54:05 PM PDT 24 933785784 ps
T1432 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1904763314 May 02 03:54:07 PM PDT 24 May 02 03:54:11 PM PDT 24 35671900 ps
T1433 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4013701799 May 02 03:55:14 PM PDT 24 May 02 03:55:17 PM PDT 24 45105394 ps
T1434 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1620800549 May 02 03:53:54 PM PDT 24 May 02 03:53:57 PM PDT 24 27000155 ps
T1435 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2586513975 May 02 03:54:02 PM PDT 24 May 02 03:54:07 PM PDT 24 30889376 ps
T1436 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3837897132 May 02 03:54:00 PM PDT 24 May 02 03:54:05 PM PDT 24 89983277 ps
T1437 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3459495338 May 02 03:55:14 PM PDT 24 May 02 03:55:17 PM PDT 24 90103302 ps
T1438 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1910757283 May 02 03:53:58 PM PDT 24 May 02 03:54:01 PM PDT 24 59351432 ps
T1439 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2750277075 May 02 03:54:00 PM PDT 24 May 02 03:54:04 PM PDT 24 36775274 ps
T1440 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.777430745 May 02 03:54:00 PM PDT 24 May 02 03:54:04 PM PDT 24 206418623 ps
T1441 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3921027740 May 02 03:54:00 PM PDT 24 May 02 03:54:04 PM PDT 24 32256565 ps
T1442 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1817994081 May 02 03:54:00 PM PDT 24 May 02 03:54:05 PM PDT 24 71658157 ps
T1443 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2088607480 May 02 03:54:03 PM PDT 24 May 02 03:54:09 PM PDT 24 135591213 ps
T1444 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1825030427 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 33951122 ps
T1445 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2529341241 May 02 03:53:59 PM PDT 24 May 02 03:54:05 PM PDT 24 104185874 ps
T1446 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3949299452 May 02 03:55:15 PM PDT 24 May 02 03:55:18 PM PDT 24 120558484 ps
T301 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1408596660 May 02 03:53:58 PM PDT 24 May 02 03:54:04 PM PDT 24 1102896950 ps
T1447 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2042954839 May 02 03:53:53 PM PDT 24 May 02 03:54:00 PM PDT 24 840043218 ps
T1448 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2462319084 May 02 03:54:05 PM PDT 24 May 02 03:54:11 PM PDT 24 86649241 ps
T1449 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3384245414 May 02 03:54:06 PM PDT 24 May 02 03:54:10 PM PDT 24 29755154 ps
T1450 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.83644188 May 02 03:54:00 PM PDT 24 May 02 03:54:05 PM PDT 24 83591354 ps
T299 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2174989134 May 02 03:53:59 PM PDT 24 May 02 03:54:06 PM PDT 24 565334758 ps
T1451 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1024382075 May 02 03:54:01 PM PDT 24 May 02 03:54:09 PM PDT 24 912365099 ps
T1452 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3831837715 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 60653322 ps
T1453 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1607074185 May 02 03:54:00 PM PDT 24 May 02 03:54:03 PM PDT 24 51415197 ps
T1454 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3933460004 May 02 03:53:53 PM PDT 24 May 02 03:53:57 PM PDT 24 89406944 ps
T1455 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.416359798 May 02 03:54:01 PM PDT 24 May 02 03:54:05 PM PDT 24 41242251 ps
T1456 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.333469061 May 02 03:54:14 PM PDT 24 May 02 03:54:15 PM PDT 24 85435186 ps
T1457 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3835622871 May 02 03:53:59 PM PDT 24 May 02 03:54:04 PM PDT 24 80347418 ps
T1458 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2972523520 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 60582142 ps
T1459 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.698533477 May 02 03:53:58 PM PDT 24 May 02 03:54:00 PM PDT 24 44678504 ps
T1460 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.460619972 May 02 03:54:04 PM PDT 24 May 02 03:54:11 PM PDT 24 218671114 ps
T1461 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.409199511 May 02 03:54:07 PM PDT 24 May 02 03:54:12 PM PDT 24 66374162 ps
T1462 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1731721796 May 02 03:53:57 PM PDT 24 May 02 03:54:01 PM PDT 24 137486342 ps
T1463 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3498634096 May 02 03:53:53 PM PDT 24 May 02 03:53:57 PM PDT 24 31470349 ps
T1464 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3942163 May 02 03:55:15 PM PDT 24 May 02 03:55:18 PM PDT 24 54283784 ps
T1465 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3481925931 May 02 03:53:59 PM PDT 24 May 02 03:54:02 PM PDT 24 42979287 ps
T1466 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1598656638 May 02 03:54:10 PM PDT 24 May 02 03:54:14 PM PDT 24 150400918 ps
T1467 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1344266611 May 02 03:54:00 PM PDT 24 May 02 03:54:03 PM PDT 24 39162598 ps
T1468 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1718998432 May 02 03:55:15 PM PDT 24 May 02 03:55:20 PM PDT 24 116759085 ps
T1469 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.762657875 May 02 03:54:06 PM PDT 24 May 02 03:54:10 PM PDT 24 159756053 ps
T1470 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2684705098 May 02 03:54:10 PM PDT 24 May 02 03:54:13 PM PDT 24 116687510 ps
T1471 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1503881212 May 02 03:54:01 PM PDT 24 May 02 03:54:07 PM PDT 24 207422635 ps
T1472 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2042787676 May 02 03:54:02 PM PDT 24 May 02 03:54:07 PM PDT 24 27256760 ps
T22 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.278038617 May 02 03:53:51 PM PDT 24 May 02 03:53:54 PM PDT 24 43246869 ps
T1473 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1549940003 May 02 03:54:05 PM PDT 24 May 02 03:54:09 PM PDT 24 33969168 ps
T1474 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3401608510 May 02 03:55:15 PM PDT 24 May 02 03:55:17 PM PDT 24 62549477 ps
T1475 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4027191164 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 99675079 ps
T1476 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3260783584 May 02 03:53:55 PM PDT 24 May 02 03:54:05 PM PDT 24 139452731 ps
T1477 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3546209921 May 02 03:54:01 PM PDT 24 May 02 03:54:06 PM PDT 24 60958244 ps
T1478 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2280738525 May 02 03:54:07 PM PDT 24 May 02 03:54:11 PM PDT 24 34090800 ps
T1479 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1475029846 May 02 03:53:59 PM PDT 24 May 02 03:54:05 PM PDT 24 527624578 ps
T1480 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3718702482 May 02 03:54:00 PM PDT 24 May 02 03:54:05 PM PDT 24 80229644 ps
T1481 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4097202464 May 02 03:54:09 PM PDT 24 May 02 03:54:12 PM PDT 24 40689700 ps

Test location /workspace/coverage/default/46.usbdev_smoke.3425165054
Short name T1
Test name
Test status
Simulation time 8448253136 ps
CPU time 10.36 seconds
Started May 02 03:48:26 PM PDT 24
Finished May 02 03:48:38 PM PDT 24
Peak memory 204144 kb
Host smart-766b9e62-c0dc-4fb1-a0bd-21c358172f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34251
65054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3425165054
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1184159198
Short name T78
Test name
Test status
Simulation time 34209652 ps
CPU time 0.67 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 202956 kb
Host smart-3fea82ce-f40f-4515-b13f-a48acec535c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1184159198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1184159198
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.169547148
Short name T12
Test name
Test status
Simulation time 21028416616 ps
CPU time 38.33 seconds
Started May 02 03:48:09 PM PDT 24
Finished May 02 03:48:48 PM PDT 24
Peak memory 204356 kb
Host smart-83494e53-0f03-4a55-a5f9-21576aafd91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16954
7148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.169547148
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.872595648
Short name T44
Test name
Test status
Simulation time 8412265730 ps
CPU time 9.31 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:38 PM PDT 24
Peak memory 204120 kb
Host smart-8dc05a39-d5e0-4677-89ff-0605ffc841a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87259
5648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.872595648
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2384044023
Short name T64
Test name
Test status
Simulation time 164780813 ps
CPU time 2.29 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203888 kb
Host smart-65572453-d6eb-4199-847c-4d7076e8ed87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2384044023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2384044023
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3885425346
Short name T74
Test name
Test status
Simulation time 32253878 ps
CPU time 0.73 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203236 kb
Host smart-8508c3c5-d221-4231-9352-d541e7fcd728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3885425346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3885425346
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3541222326
Short name T216
Test name
Test status
Simulation time 54344315 ps
CPU time 1.36 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:02 PM PDT 24
Peak memory 204216 kb
Host smart-59c04346-48d0-419b-b425-8c914c60dd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
22326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3541222326
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.4009216268
Short name T39
Test name
Test status
Simulation time 70640965 ps
CPU time 0.71 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:05 PM PDT 24
Peak memory 203920 kb
Host smart-65892cf8-940c-4477-9296-0f02df5daab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40092
16268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.4009216268
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2279775616
Short name T65
Test name
Test status
Simulation time 509655036 ps
CPU time 1.42 seconds
Started May 02 03:44:48 PM PDT 24
Finished May 02 03:44:51 PM PDT 24
Peak memory 221464 kb
Host smart-1ef2a8ad-120b-48b9-9720-015902b0ccbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2279775616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2279775616
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2617011119
Short name T6
Test name
Test status
Simulation time 8373135867 ps
CPU time 7.74 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:50 PM PDT 24
Peak memory 204136 kb
Host smart-94175634-4b2d-4059-8cd7-03018397d201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26170
11119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2617011119
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3219191239
Short name T8
Test name
Test status
Simulation time 8379476504 ps
CPU time 7.48 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204112 kb
Host smart-b7d85cb2-46e6-4881-81b6-6f6ee9ea0489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32191
91239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3219191239
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.9133375
Short name T209
Test name
Test status
Simulation time 150102078 ps
CPU time 1.91 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:19 PM PDT 24
Peak memory 203532 kb
Host smart-54dc2f54-76ea-44e1-a2ac-361c4c0282ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=9133375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.9133375
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.278038617
Short name T22
Test name
Test status
Simulation time 43246869 ps
CPU time 0.79 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:54 PM PDT 24
Peak memory 203768 kb
Host smart-faa1979f-23fe-40e0-8d0a-4416194acac6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=278038617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.278038617
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1703873969
Short name T100
Test name
Test status
Simulation time 8401193654 ps
CPU time 8.77 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204112 kb
Host smart-14b3a1e3-0f32-4d81-904a-e49b6a498e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17038
73969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1703873969
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.563546392
Short name T263
Test name
Test status
Simulation time 658610417 ps
CPU time 4.25 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:21 PM PDT 24
Peak memory 203248 kb
Host smart-f46feb61-c8cd-4712-84fd-849c2493c9d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=563546392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.563546392
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4007738640
Short name T79
Test name
Test status
Simulation time 30000279 ps
CPU time 0.68 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203280 kb
Host smart-c212c976-6786-4df4-b78c-64d2ca98088e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4007738640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.4007738640
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3257847974
Short name T19
Test name
Test status
Simulation time 8451703684 ps
CPU time 8.17 seconds
Started May 02 03:48:41 PM PDT 24
Finished May 02 03:48:52 PM PDT 24
Peak memory 204152 kb
Host smart-b74c5ebe-92dc-472f-a907-612ecb766d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32578
47974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3257847974
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2867185811
Short name T14
Test name
Test status
Simulation time 17782360217 ps
CPU time 30.08 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:23 PM PDT 24
Peak memory 204412 kb
Host smart-5f74cdce-764d-4072-869c-07892f7535c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28671
85811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2867185811
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1607074185
Short name T1453
Test name
Test status
Simulation time 51415197 ps
CPU time 0.69 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:03 PM PDT 24
Peak memory 203252 kb
Host smart-6871156e-03bd-4003-a542-455218369399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1607074185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1607074185
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1888510362
Short name T282
Test name
Test status
Simulation time 719212318 ps
CPU time 4.92 seconds
Started May 02 03:53:52 PM PDT 24
Finished May 02 03:54:00 PM PDT 24
Peak memory 204040 kb
Host smart-a72dfe73-c1c1-4135-ba6b-c1d7b586d611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1888510362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1888510362
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2688292709
Short name T292
Test name
Test status
Simulation time 27365212 ps
CPU time 0.71 seconds
Started May 02 03:54:16 PM PDT 24
Finished May 02 03:54:28 PM PDT 24
Peak memory 203212 kb
Host smart-0dd26465-a865-486f-8f85-5329d18860ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2688292709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2688292709
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1629476260
Short name T339
Test name
Test status
Simulation time 8386193985 ps
CPU time 8.11 seconds
Started May 02 03:44:33 PM PDT 24
Finished May 02 03:44:42 PM PDT 24
Peak memory 204060 kb
Host smart-a4f83624-265a-4b94-89e3-026d2f9ca4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
76260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1629476260
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3266201865
Short name T68
Test name
Test status
Simulation time 132739496 ps
CPU time 1.73 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203948 kb
Host smart-abf83507-f6ff-45b5-b4a1-c28ff2afd17e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3266201865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3266201865
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2281449590
Short name T77
Test name
Test status
Simulation time 37670762 ps
CPU time 0.7 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:00 PM PDT 24
Peak memory 203292 kb
Host smart-85f0e97b-3477-4e64-97a2-231ccaf4d6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281449590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2281449590
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1475029846
Short name T1479
Test name
Test status
Simulation time 527624578 ps
CPU time 4.51 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 204044 kb
Host smart-08bf6240-470a-497f-8ae0-9ebdea547a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1475029846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1475029846
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.924905478
Short name T11
Test name
Test status
Simulation time 5106085148 ps
CPU time 125.97 seconds
Started May 02 03:44:31 PM PDT 24
Finished May 02 03:46:38 PM PDT 24
Peak memory 204316 kb
Host smart-fa285875-6988-4bbf-91d8-312d0aa15a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92490
5478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.924905478
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1527679295
Short name T20
Test name
Test status
Simulation time 8384748289 ps
CPU time 7.59 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204132 kb
Host smart-f50e8b9a-05bc-4817-8939-a346d86a1953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
79295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1527679295
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3323136610
Short name T219
Test name
Test status
Simulation time 25704624539 ps
CPU time 49.49 seconds
Started May 02 03:44:32 PM PDT 24
Finished May 02 03:45:23 PM PDT 24
Peak memory 204344 kb
Host smart-787b121a-c594-4899-8e48-6dd77604e9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33231
36610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3323136610
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3631275466
Short name T27
Test name
Test status
Simulation time 8404539062 ps
CPU time 9.01 seconds
Started May 02 03:45:24 PM PDT 24
Finished May 02 03:45:34 PM PDT 24
Peak memory 204080 kb
Host smart-8088bc0c-4083-4347-91dc-a5c43da33ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36312
75466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3631275466
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1385397069
Short name T46
Test name
Test status
Simulation time 36890098 ps
CPU time 0.64 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 203980 kb
Host smart-296812d6-af87-4cc3-8963-e1f37544693c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13853
97069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1385397069
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3260445887
Short name T335
Test name
Test status
Simulation time 8459962969 ps
CPU time 8.1 seconds
Started May 02 03:44:40 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204068 kb
Host smart-69d1bb50-4cb8-47db-8d56-bc37be596ee1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3260445887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3260445887
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2267677774
Short name T702
Test name
Test status
Simulation time 8422408960 ps
CPU time 7.64 seconds
Started May 02 03:44:37 PM PDT 24
Finished May 02 03:44:45 PM PDT 24
Peak memory 204056 kb
Host smart-8a39d886-277c-4422-b41e-e92fdbbb0198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22676
77774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2267677774
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_smoke.743677874
Short name T132
Test name
Test status
Simulation time 8479711911 ps
CPU time 8.04 seconds
Started May 02 03:44:28 PM PDT 24
Finished May 02 03:44:37 PM PDT 24
Peak memory 204132 kb
Host smart-b366ed9d-d0e3-43f8-a4ae-5d7c7baed31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74367
7874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.743677874
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4034491758
Short name T162
Test name
Test status
Simulation time 8450375679 ps
CPU time 9.07 seconds
Started May 02 03:44:40 PM PDT 24
Finished May 02 03:44:50 PM PDT 24
Peak memory 204036 kb
Host smart-86ec6a7d-4616-4e08-9c32-9d4110e2b82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40344
91758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4034491758
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2538752802
Short name T137
Test name
Test status
Simulation time 8467449908 ps
CPU time 8.84 seconds
Started May 02 03:45:33 PM PDT 24
Finished May 02 03:45:43 PM PDT 24
Peak memory 204092 kb
Host smart-07444ddb-c2cf-4863-b216-ffafecd441f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25387
52802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2538752802
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3916712572
Short name T29
Test name
Test status
Simulation time 8434572243 ps
CPU time 8.27 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204108 kb
Host smart-47b6a4fc-217d-47fc-8af3-752f47acc5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39167
12572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3916712572
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1913969956
Short name T200
Test name
Test status
Simulation time 8398133412 ps
CPU time 8.32 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204140 kb
Host smart-93bf954c-b01b-4a81-bad0-746cdfb400bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139
69956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1913969956
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3214872126
Short name T179
Test name
Test status
Simulation time 8394794697 ps
CPU time 7.89 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:55 PM PDT 24
Peak memory 204112 kb
Host smart-837c4817-aa44-4cb3-a7af-ba9925084166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32148
72126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3214872126
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1695706005
Short name T182
Test name
Test status
Simulation time 8372442356 ps
CPU time 8.02 seconds
Started May 02 03:46:21 PM PDT 24
Finished May 02 03:46:30 PM PDT 24
Peak memory 204060 kb
Host smart-f6b41407-12ff-4d67-b40b-bfee15c8b220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
06005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1695706005
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2208002710
Short name T143
Test name
Test status
Simulation time 8449963519 ps
CPU time 7.96 seconds
Started May 02 03:47:35 PM PDT 24
Finished May 02 03:47:44 PM PDT 24
Peak memory 204136 kb
Host smart-d3cae16d-b7ef-4663-a44a-82ff1007dbc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22080
02710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2208002710
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.4090915442
Short name T7
Test name
Test status
Simulation time 8407486009 ps
CPU time 7.65 seconds
Started May 02 03:47:38 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204128 kb
Host smart-b044e0fd-4bf2-4d4b-b8e8-b2c180684d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40909
15442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.4090915442
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.766982937
Short name T37
Test name
Test status
Simulation time 8373223926 ps
CPU time 8.57 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204044 kb
Host smart-0fe7e878-a4ab-474d-a263-e0e90fe33b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76698
2937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.766982937
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2504770923
Short name T63
Test name
Test status
Simulation time 54080499 ps
CPU time 1.61 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:02 PM PDT 24
Peak memory 204056 kb
Host smart-15ab6beb-121c-4171-ac13-79e3bb0f575f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504770923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2504770923
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/15.usbdev_smoke.962361435
Short name T171
Test name
Test status
Simulation time 8477908902 ps
CPU time 8.83 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204064 kb
Host smart-4bdd3715-8032-4c5a-91f4-d7ab68cdd743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96236
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.962361435
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3319799976
Short name T305
Test name
Test status
Simulation time 8361768985 ps
CPU time 7.73 seconds
Started May 02 03:46:37 PM PDT 24
Finished May 02 03:46:46 PM PDT 24
Peak memory 204124 kb
Host smart-d866a413-11b6-44d6-86fd-711bc65b3772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
99976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3319799976
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1438821384
Short name T237
Test name
Test status
Simulation time 685697641 ps
CPU time 3.28 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203984 kb
Host smart-b3afbdfa-fbdd-4099-905c-afdbad929edc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1438821384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1438821384
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2461546528
Short name T822
Test name
Test status
Simulation time 8365787364 ps
CPU time 8.91 seconds
Started May 02 03:44:31 PM PDT 24
Finished May 02 03:44:40 PM PDT 24
Peak memory 204076 kb
Host smart-bcf60097-44e5-4427-8c36-567d6c13a37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24615
46528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2461546528
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1544941891
Short name T108
Test name
Test status
Simulation time 8384765505 ps
CPU time 8.33 seconds
Started May 02 03:44:33 PM PDT 24
Finished May 02 03:44:42 PM PDT 24
Peak memory 204088 kb
Host smart-ba868a84-3cf5-458d-9034-3319ca9b581d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
41891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1544941891
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1230817092
Short name T122
Test name
Test status
Simulation time 8455414036 ps
CPU time 8.87 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204076 kb
Host smart-76a56880-eba5-49f3-bf79-6ea21aa7956c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12308
17092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1230817092
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.730608616
Short name T1346
Test name
Test status
Simulation time 8455663985 ps
CPU time 9.41 seconds
Started May 02 03:45:27 PM PDT 24
Finished May 02 03:45:38 PM PDT 24
Peak memory 204012 kb
Host smart-e5cac870-6215-4b2e-947d-3f808e99e96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73060
8616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.730608616
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1193308641
Short name T443
Test name
Test status
Simulation time 8420638220 ps
CPU time 7.79 seconds
Started May 02 03:45:26 PM PDT 24
Finished May 02 03:45:35 PM PDT 24
Peak memory 204148 kb
Host smart-3241b619-155b-4570-b6df-b1e64299fe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11933
08641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1193308641
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2323970602
Short name T38
Test name
Test status
Simulation time 89469486 ps
CPU time 0.75 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:25 PM PDT 24
Peak memory 203948 kb
Host smart-f40d8217-d03c-4c0e-a092-55dc3942e635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
70602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2323970602
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1443474642
Short name T146
Test name
Test status
Simulation time 8399128844 ps
CPU time 8.85 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204076 kb
Host smart-5b1ae7c0-85d9-43d4-a4f1-908018e8319c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
74642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1443474642
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1521166017
Short name T101
Test name
Test status
Simulation time 8428186834 ps
CPU time 7.98 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204120 kb
Host smart-2f6645df-38b5-465c-bdbb-c6489f1e5c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15211
66017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1521166017
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1835450299
Short name T937
Test name
Test status
Simulation time 8395934445 ps
CPU time 7.75 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204068 kb
Host smart-64df9778-b225-4635-988b-0d2ac5b5de7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18354
50299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1835450299
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.982384247
Short name T685
Test name
Test status
Simulation time 8469264187 ps
CPU time 8.05 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204072 kb
Host smart-659f2548-2dad-4462-9700-1ae1466c2875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98238
4247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.982384247
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2185093175
Short name T129
Test name
Test status
Simulation time 8461901801 ps
CPU time 8.69 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204156 kb
Host smart-394bc620-fb05-4ed4-a57f-f547dbdbe4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850
93175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2185093175
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2208652252
Short name T924
Test name
Test status
Simulation time 8417949437 ps
CPU time 10.56 seconds
Started May 02 03:45:38 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204004 kb
Host smart-9ba577e9-b60b-4af3-8a35-d3270c5f8a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086
52252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2208652252
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1921758341
Short name T111
Test name
Test status
Simulation time 8415778466 ps
CPU time 9.83 seconds
Started May 02 03:45:43 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204104 kb
Host smart-55232dc3-16a2-4b4a-849d-b40a09244c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
58341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1921758341
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.817769203
Short name T636
Test name
Test status
Simulation time 8447770231 ps
CPU time 8.01 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204072 kb
Host smart-a54ecb6c-3276-4b5d-9602-2f37295214cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81776
9203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.817769203
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.307630220
Short name T116
Test name
Test status
Simulation time 8399561262 ps
CPU time 10.82 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204048 kb
Host smart-d8f6b67b-f3d0-44fc-9297-f3e8f9db4a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
0220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.307630220
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2552891597
Short name T196
Test name
Test status
Simulation time 8364632470 ps
CPU time 7.75 seconds
Started May 02 03:45:51 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204056 kb
Host smart-c5e1134d-074c-414d-a953-476f1dd7a5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25528
91597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2552891597
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3454660623
Short name T102
Test name
Test status
Simulation time 8435171396 ps
CPU time 8.87 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204112 kb
Host smart-6418e32c-18da-4227-b39e-9d2777bc3df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34546
60623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3454660623
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2737391430
Short name T987
Test name
Test status
Simulation time 8372148903 ps
CPU time 7.55 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204056 kb
Host smart-cd9efbd5-6e1d-4964-ae8a-64bcb8de0135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27373
91430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2737391430
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.101338503
Short name T127
Test name
Test status
Simulation time 8469178486 ps
CPU time 8.78 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204068 kb
Host smart-1ef80cfd-c704-4104-82bb-2c1870dc042d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
8503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.101338503
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.151987807
Short name T117
Test name
Test status
Simulation time 8455021941 ps
CPU time 9.6 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204096 kb
Host smart-96c40f1e-aacd-419d-8aa9-c8bea48298a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15198
7807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.151987807
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1900379679
Short name T163
Test name
Test status
Simulation time 8398862593 ps
CPU time 8.16 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204100 kb
Host smart-cd5d0485-3911-464c-be2f-74086f2a3b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19003
79679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1900379679
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2298507439
Short name T1173
Test name
Test status
Simulation time 8419164975 ps
CPU time 9.72 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:21 PM PDT 24
Peak memory 204136 kb
Host smart-8d96a101-2c59-4ba3-aa6c-c35b918bf244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
07439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2298507439
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3592122684
Short name T98
Test name
Test status
Simulation time 21902932504 ps
CPU time 45.31 seconds
Started May 02 03:44:51 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204368 kb
Host smart-0ac8504f-7931-48be-81df-ca9e2aaa24e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35921
22684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3592122684
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.579515905
Short name T105
Test name
Test status
Simulation time 8395384030 ps
CPU time 8.7 seconds
Started May 02 03:48:27 PM PDT 24
Finished May 02 03:48:37 PM PDT 24
Peak memory 204104 kb
Host smart-3183423a-2e4a-4ef0-8019-72b038931203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57951
5905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.579515905
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3724925187
Short name T1417
Test name
Test status
Simulation time 323815692 ps
CPU time 3.56 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203820 kb
Host smart-7b5f3bfe-da9e-4a05-b395-1d5c66768b1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3724925187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3724925187
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2042954839
Short name T1447
Test name
Test status
Simulation time 840043218 ps
CPU time 4.38 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:54:00 PM PDT 24
Peak memory 203964 kb
Host smart-059ef7f6-130c-482b-beb2-876413af4363
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2042954839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2042954839
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3260671431
Short name T75
Test name
Test status
Simulation time 61515361 ps
CPU time 0.79 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:54 PM PDT 24
Peak memory 203704 kb
Host smart-60c547c2-7513-4254-be3b-fc7b1827f97e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3260671431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3260671431
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2153633875
Short name T208
Test name
Test status
Simulation time 76581760 ps
CPU time 1.5 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:03 PM PDT 24
Peak memory 212220 kb
Host smart-4d1a33fd-339c-471a-8b73-fa958edb3553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153633875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2153633875
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.698533477
Short name T1459
Test name
Test status
Simulation time 44678504 ps
CPU time 0.81 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:00 PM PDT 24
Peak memory 203656 kb
Host smart-4faf3d11-e5fb-4cc5-a272-8bb19aaa289c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=698533477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.698533477
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3498634096
Short name T1463
Test name
Test status
Simulation time 31470349 ps
CPU time 0.64 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203176 kb
Host smart-5dd18b33-d7d0-4a00-8051-11061379feaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3498634096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3498634096
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.258804353
Short name T258
Test name
Test status
Simulation time 159667553 ps
CPU time 2.23 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:58 PM PDT 24
Peak memory 204008 kb
Host smart-515e85cd-593f-402c-9423-4a8210aa9bde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=258804353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.258804353
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1035331640
Short name T1423
Test name
Test status
Simulation time 154598463 ps
CPU time 3.94 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:58 PM PDT 24
Peak memory 203940 kb
Host smart-feaaff2a-b5df-4200-983a-270f8c9ec316
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1035331640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1035331640
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.362754096
Short name T1388
Test name
Test status
Simulation time 256540777 ps
CPU time 1.54 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:01 PM PDT 24
Peak memory 203884 kb
Host smart-e2de19d6-434b-468b-a05d-dc218bc670a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362754096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.362754096
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.611486815
Short name T213
Test name
Test status
Simulation time 51137588 ps
CPU time 1.31 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203920 kb
Host smart-3419c5fe-3f92-4da0-a2bc-4b140da878f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=611486815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.611486815
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2339018661
Short name T300
Test name
Test status
Simulation time 619573695 ps
CPU time 4.24 seconds
Started May 02 03:53:57 PM PDT 24
Finished May 02 03:54:03 PM PDT 24
Peak memory 203936 kb
Host smart-0e82728f-008c-40ac-b88f-915613a92240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2339018661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2339018661
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.471154234
Short name T262
Test name
Test status
Simulation time 183949480 ps
CPU time 2.14 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203880 kb
Host smart-efd3c76b-53ec-4342-92e5-fd534860e5ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=471154234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.471154234
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2157880620
Short name T1390
Test name
Test status
Simulation time 393490886 ps
CPU time 3.78 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203900 kb
Host smart-f5711e0c-43a9-49cd-a7c7-10c64d7c9205
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2157880620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2157880620
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3028951138
Short name T241
Test name
Test status
Simulation time 142383516 ps
CPU time 1.89 seconds
Started May 02 03:53:54 PM PDT 24
Finished May 02 03:53:59 PM PDT 24
Peak memory 212204 kb
Host smart-39955202-6529-40fa-98d8-e35511dedc29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028951138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3028951138
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.342846609
Short name T265
Test name
Test status
Simulation time 43414270 ps
CPU time 0.76 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203796 kb
Host smart-6561b957-d81a-47b0-afb6-e9f938267deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=342846609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.342846609
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3921027740
Short name T1441
Test name
Test status
Simulation time 32256565 ps
CPU time 0.68 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 203308 kb
Host smart-028d3d31-9f6a-46b4-bae4-c5f271efd0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3921027740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3921027740
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3949299452
Short name T1446
Test name
Test status
Simulation time 120558484 ps
CPU time 1.37 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:18 PM PDT 24
Peak memory 211576 kb
Host smart-5ca637ae-4b08-43ed-82a7-58940725eca8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3949299452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3949299452
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3434595414
Short name T1387
Test name
Test status
Simulation time 164940773 ps
CPU time 2.3 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:13 PM PDT 24
Peak memory 203772 kb
Host smart-e4678216-800a-492c-a5ce-b2ec1c7ad87e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3434595414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3434595414
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.777430745
Short name T1440
Test name
Test status
Simulation time 206418623 ps
CPU time 1.56 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 203952 kb
Host smart-74c7ef4a-a91d-4ac2-82bc-6f0060395c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=777430745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.777430745
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.892321880
Short name T1392
Test name
Test status
Simulation time 157392169 ps
CPU time 2.55 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 212228 kb
Host smart-2c71892c-6c3f-4943-b3b3-5b40577e1d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892321880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.892321880
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3302758708
Short name T1406
Test name
Test status
Simulation time 83154292 ps
CPU time 1.03 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203952 kb
Host smart-0593bb19-2bb4-4c1e-b62d-9dca3568199b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3302758708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3302758708
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1142230947
Short name T1412
Test name
Test status
Simulation time 33989144 ps
CPU time 0.67 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203516 kb
Host smart-e66d3177-a6a4-4c6e-8131-0eb3ec7a5e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1142230947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1142230947
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1559802220
Short name T1430
Test name
Test status
Simulation time 137353421 ps
CPU time 1.73 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:02 PM PDT 24
Peak memory 203976 kb
Host smart-325cfe85-3018-4d77-b3dc-bed8f1af893b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1559802220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1559802220
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1355103538
Short name T1413
Test name
Test status
Simulation time 150854934 ps
CPU time 1.61 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 204096 kb
Host smart-95e7d8da-af74-41dc-9e81-e8892c6f1b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355103538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1355103538
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3944775268
Short name T1393
Test name
Test status
Simulation time 267711858 ps
CPU time 2.69 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 204004 kb
Host smart-0c90279f-c4a9-4dab-9181-a1bfebfe24b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3944775268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3944775268
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3108528157
Short name T1425
Test name
Test status
Simulation time 75116671 ps
CPU time 2.04 seconds
Started May 02 03:54:11 PM PDT 24
Finished May 02 03:54:15 PM PDT 24
Peak memory 212244 kb
Host smart-e7c6249f-2bdc-472d-b6a5-573584245d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108528157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3108528157
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2227247651
Short name T1402
Test name
Test status
Simulation time 71464319 ps
CPU time 0.83 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 203772 kb
Host smart-95757000-5357-474d-85bb-16fbfd6673c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2227247651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2227247651
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.416359798
Short name T1455
Test name
Test status
Simulation time 41242251 ps
CPU time 0.68 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203248 kb
Host smart-26f84f48-5a2d-466a-80e2-1b8642c6f300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=416359798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.416359798
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4276961404
Short name T273
Test name
Test status
Simulation time 128937526 ps
CPU time 1.22 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 204028 kb
Host smart-d19f7a70-28ac-432d-a159-cb8d216489b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4276961404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.4276961404
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3835622871
Short name T1457
Test name
Test status
Simulation time 80347418 ps
CPU time 2.44 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 204064 kb
Host smart-d02fab5c-d711-4cf4-b73a-e752610bc98d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3835622871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3835622871
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1684895098
Short name T211
Test name
Test status
Simulation time 164497008 ps
CPU time 2.45 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 204036 kb
Host smart-ce2423ed-96eb-4628-82da-d6c1b82f0880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1684895098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1684895098
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4027191164
Short name T1475
Test name
Test status
Simulation time 99675079 ps
CPU time 1.36 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 212264 kb
Host smart-01c53cd5-3c45-41b2-9582-c503c95d1c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027191164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4027191164
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.703711088
Short name T1398
Test name
Test status
Simulation time 71170514 ps
CPU time 0.84 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:02 PM PDT 24
Peak memory 203776 kb
Host smart-9b9ca070-7847-4999-ba75-efc0afea75be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=703711088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.703711088
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2280738525
Short name T1478
Test name
Test status
Simulation time 34090800 ps
CPU time 0.77 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203300 kb
Host smart-ec215c35-9a10-44ac-adef-22401117e239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2280738525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2280738525
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.762657875
Short name T1469
Test name
Test status
Simulation time 159756053 ps
CPU time 1.27 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203976 kb
Host smart-ab433f9e-8ce5-4de7-b51b-4c03d5202b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=762657875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.762657875
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.825212847
Short name T234
Test name
Test status
Simulation time 55563495 ps
CPU time 1.56 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203944 kb
Host smart-46d80e75-57c9-4d79-a7bb-80da7a389d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=825212847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.825212847
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2174989134
Short name T299
Test name
Test status
Simulation time 565334758 ps
CPU time 4.52 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 202776 kb
Host smart-9b6bb3e9-8772-42a8-bb92-26c9381107e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2174989134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2174989134
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3837897132
Short name T1436
Test name
Test status
Simulation time 89983277 ps
CPU time 2.66 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 212296 kb
Host smart-e44f49e8-2af5-4269-90c1-4965ce8107a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837897132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3837897132
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.398366798
Short name T266
Test name
Test status
Simulation time 34950960 ps
CPU time 0.78 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203748 kb
Host smart-9e457286-c00b-44d1-b8e9-e051e99a4442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=398366798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.398366798
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3718702482
Short name T1480
Test name
Test status
Simulation time 80229644 ps
CPU time 1.07 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 204008 kb
Host smart-24e578e3-81d0-4e50-9700-24537a3a25e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3718702482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3718702482
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4070606043
Short name T212
Test name
Test status
Simulation time 252146857 ps
CPU time 3.21 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:14 PM PDT 24
Peak memory 204032 kb
Host smart-8057e78d-ad64-4754-911c-5303d9a262b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4070606043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4070606043
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2784308344
Short name T281
Test name
Test status
Simulation time 172805226 ps
CPU time 2.13 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 215836 kb
Host smart-5898bea0-dc87-466c-9073-793aac50cb49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784308344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2784308344
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3355356845
Short name T1396
Test name
Test status
Simulation time 66419070 ps
CPU time 0.88 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203720 kb
Host smart-063fcfea-345a-4a84-89d6-6eeca9a93a11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3355356845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3355356845
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2696493570
Short name T73
Test name
Test status
Simulation time 33659757 ps
CPU time 0.65 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203208 kb
Host smart-5be42bc7-a91b-4477-b199-41a92936b8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2696493570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2696493570
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1519827937
Short name T1418
Test name
Test status
Simulation time 333456279 ps
CPU time 1.9 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 204000 kb
Host smart-ecf9aa76-17d0-4588-8f21-46cb46a456da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1519827937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1519827937
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2529341241
Short name T1445
Test name
Test status
Simulation time 104185874 ps
CPU time 3.35 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203088 kb
Host smart-c3c9462c-c4e2-446e-ae5d-8cf416e2b60b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529341241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2529341241
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1824405033
Short name T240
Test name
Test status
Simulation time 551444399 ps
CPU time 3.41 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203980 kb
Host smart-919456ae-c537-48b7-b990-f2687d94d249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1824405033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1824405033
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3546209921
Short name T1477
Test name
Test status
Simulation time 60958244 ps
CPU time 1.75 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 212188 kb
Host smart-19f0bb17-9dac-4bcb-8845-e83e9cf9808f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546209921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3546209921
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.394858109
Short name T264
Test name
Test status
Simulation time 32571052 ps
CPU time 0.76 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203516 kb
Host smart-267eedcd-b838-4c6c-8b1f-f6782035898f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=394858109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.394858109
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1503881212
Short name T1471
Test name
Test status
Simulation time 207422635 ps
CPU time 1.66 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 204060 kb
Host smart-18df94fa-3e66-47fa-916d-e5ae045b06cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1503881212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1503881212
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1598656638
Short name T1466
Test name
Test status
Simulation time 150400918 ps
CPU time 1.58 seconds
Started May 02 03:54:10 PM PDT 24
Finished May 02 03:54:14 PM PDT 24
Peak memory 203992 kb
Host smart-0051fd0b-a211-4067-9bde-9d128d13cbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1598656638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1598656638
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3429813976
Short name T214
Test name
Test status
Simulation time 310574032 ps
CPU time 2.53 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203940 kb
Host smart-467482d3-d8a0-494f-9505-8251b71869ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3429813976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3429813976
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2088607480
Short name T1443
Test name
Test status
Simulation time 135591213 ps
CPU time 1.87 seconds
Started May 02 03:54:03 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 215256 kb
Host smart-f238afef-dda6-4ba3-95c4-94aea16607ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088607480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2088607480
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3094290371
Short name T270
Test name
Test status
Simulation time 80125110 ps
CPU time 1.01 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203932 kb
Host smart-115912b3-8ded-4817-bc8d-7c0f49d72c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3094290371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3094290371
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1904763314
Short name T1432
Test name
Test status
Simulation time 35671900 ps
CPU time 0.68 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203236 kb
Host smart-c4f3053c-eaae-4bba-8a09-69042cc6edfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1904763314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1904763314
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.922706459
Short name T71
Test name
Test status
Simulation time 141356662 ps
CPU time 1.78 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 204000 kb
Host smart-1eda5e01-565f-4b4b-89ec-87b6c5652002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=922706459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.922706459
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2896069492
Short name T231
Test name
Test status
Simulation time 48419803 ps
CPU time 1.19 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 204092 kb
Host smart-d3a6242b-3be3-455e-a3df-9520e6ae2bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2896069492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2896069492
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1408596660
Short name T301
Test name
Test status
Simulation time 1102896950 ps
CPU time 4.73 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 204016 kb
Host smart-3756221c-8ded-428d-b944-d359f1a269e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1408596660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1408596660
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4261477104
Short name T1409
Test name
Test status
Simulation time 139977804 ps
CPU time 1.76 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 215156 kb
Host smart-515b40fd-7318-4077-92cd-d6c5b76b34f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261477104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.4261477104
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.969544757
Short name T1426
Test name
Test status
Simulation time 60958878 ps
CPU time 0.99 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203904 kb
Host smart-6cf32462-bbd2-4f16-9d3c-a6d03561685b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=969544757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.969544757
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1050688454
Short name T1391
Test name
Test status
Simulation time 36386611 ps
CPU time 0.65 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203188 kb
Host smart-d7840ff0-2ffe-4b0b-b1a5-2fe3d1742dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1050688454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1050688454
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4006937145
Short name T1400
Test name
Test status
Simulation time 131022474 ps
CPU time 1.18 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203972 kb
Host smart-fe57db37-1e8f-46c9-9577-66f85c5128ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4006937145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4006937145
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3878986711
Short name T233
Test name
Test status
Simulation time 265945789 ps
CPU time 3.31 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 204036 kb
Host smart-54d9f36d-19d5-4f31-9ae9-076f54f92bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3878986711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3878986711
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.198567640
Short name T1403
Test name
Test status
Simulation time 313429772 ps
CPU time 2.69 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 203980 kb
Host smart-50675a0c-db55-41d3-a370-aa741f251d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=198567640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.198567640
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2389154836
Short name T1408
Test name
Test status
Simulation time 82659508 ps
CPU time 1.3 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:02 PM PDT 24
Peak memory 212220 kb
Host smart-1349cf45-26d0-4fbd-a5f0-9882dfefe03b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389154836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2389154836
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.504300254
Short name T267
Test name
Test status
Simulation time 54173896 ps
CPU time 0.97 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203916 kb
Host smart-20693543-25d7-4a02-ae88-977cfd2bbfff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=504300254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.504300254
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.442873012
Short name T1395
Test name
Test status
Simulation time 29249335 ps
CPU time 0.61 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:00 PM PDT 24
Peak memory 203268 kb
Host smart-03518da7-635d-454f-831e-bfe6f134bd2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=442873012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.442873012
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3710356116
Short name T69
Test name
Test status
Simulation time 82719230 ps
CPU time 1.07 seconds
Started May 02 03:54:03 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 203956 kb
Host smart-8346ec3b-00f4-4288-9235-a2db4d7fb5f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3710356116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3710356116
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1058045054
Short name T1389
Test name
Test status
Simulation time 63786992 ps
CPU time 1.92 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:13 PM PDT 24
Peak memory 204024 kb
Host smart-e4bae4c4-80cd-4c63-b65c-b8a8d61780f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1058045054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1058045054
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.240511092
Short name T1401
Test name
Test status
Simulation time 2282832298 ps
CPU time 6.56 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:13 PM PDT 24
Peak memory 204100 kb
Host smart-336d525a-99fe-4057-aaa7-1599871b5fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=240511092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.240511092
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1817994081
Short name T1442
Test name
Test status
Simulation time 71658157 ps
CPU time 1.34 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 212184 kb
Host smart-b549ea10-3d91-4a5d-aaed-626b46cb9e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817994081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1817994081
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3653782482
Short name T259
Test name
Test status
Simulation time 83864050 ps
CPU time 1.03 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 204016 kb
Host smart-6e26586f-9f82-4454-bdd9-d7a0c4c4cf1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3653782482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3653782482
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1825030427
Short name T1444
Test name
Test status
Simulation time 33951122 ps
CPU time 0.72 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203296 kb
Host smart-eecf122d-c4d3-460e-afea-721a9ae2adbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825030427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1825030427
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.405068496
Short name T1416
Test name
Test status
Simulation time 270085271 ps
CPU time 2.88 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203832 kb
Host smart-4a86c8d7-6539-4a63-acc3-cfa6a25a9064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=405068496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.405068496
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3138479661
Short name T298
Test name
Test status
Simulation time 1281881717 ps
CPU time 4.27 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203988 kb
Host smart-d495f7b2-45dc-4191-aa73-7479f0555f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3138479661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3138479661
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3465533304
Short name T1421
Test name
Test status
Simulation time 70341741 ps
CPU time 2.01 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203888 kb
Host smart-5ae640ce-9913-43f1-a385-8ee487be00ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3465533304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3465533304
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.360168730
Short name T1399
Test name
Test status
Simulation time 667666166 ps
CPU time 4.58 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203904 kb
Host smart-7d239e78-b0bb-40ec-acd0-ca481268b70d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=360168730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.360168730
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1549940003
Short name T1473
Test name
Test status
Simulation time 33969168 ps
CPU time 0.82 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203704 kb
Host smart-1df6fe04-3cb1-40a9-b9f9-bd4fcee67972
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1549940003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1549940003
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1456592629
Short name T1429
Test name
Test status
Simulation time 113731938 ps
CPU time 1.37 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:01 PM PDT 24
Peak memory 212160 kb
Host smart-a969823b-6805-4a90-ab23-59e5dbb39f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456592629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1456592629
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2837781240
Short name T205
Test name
Test status
Simulation time 30428739 ps
CPU time 0.73 seconds
Started May 02 03:55:13 PM PDT 24
Finished May 02 03:55:16 PM PDT 24
Peak memory 202636 kb
Host smart-746592ff-0a16-4717-8d4f-e47e90d157fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2837781240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2837781240
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.462098962
Short name T80
Test name
Test status
Simulation time 30342549 ps
CPU time 0.64 seconds
Started May 02 03:53:54 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203200 kb
Host smart-38d0cf6c-8857-4c70-83c6-2022752f47cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=462098962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.462098962
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1600706559
Short name T269
Test name
Test status
Simulation time 190578695 ps
CPU time 2.33 seconds
Started May 02 03:53:54 PM PDT 24
Finished May 02 03:53:59 PM PDT 24
Peak memory 212184 kb
Host smart-2d85e5ff-9195-461f-990d-029ab52d0286
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1600706559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1600706559
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1844382933
Short name T1384
Test name
Test status
Simulation time 368077059 ps
CPU time 2.61 seconds
Started May 02 03:53:55 PM PDT 24
Finished May 02 03:54:00 PM PDT 24
Peak memory 203820 kb
Host smart-5adc5443-43aa-47f6-835c-07ef2ab0e32f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1844382933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1844382933
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2210346814
Short name T70
Test name
Test status
Simulation time 298466804 ps
CPU time 1.82 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203988 kb
Host smart-38f62105-8358-436d-9566-1ac1d0bd12ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2210346814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2210346814
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.460619972
Short name T1460
Test name
Test status
Simulation time 218671114 ps
CPU time 2.67 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 204116 kb
Host smart-2a831907-170a-448a-8b29-26e12d5f1be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=460619972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.460619972
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4136879081
Short name T279
Test name
Test status
Simulation time 333968214 ps
CPU time 2.76 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:56 PM PDT 24
Peak memory 204040 kb
Host smart-cde46d8c-16b8-4f70-8708-0606bc45f1dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4136879081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4136879081
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.149728410
Short name T286
Test name
Test status
Simulation time 30607196 ps
CPU time 0.65 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203320 kb
Host smart-c57b277b-f910-4b9f-82da-b0dd85498dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=149728410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.149728410
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1344266611
Short name T1467
Test name
Test status
Simulation time 39162598 ps
CPU time 0.67 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:03 PM PDT 24
Peak memory 203252 kb
Host smart-f8cd0902-bd10-42e6-a09c-9fb3c9f8110f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1344266611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1344266611
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2750277075
Short name T1439
Test name
Test status
Simulation time 36775274 ps
CPU time 0.66 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 203284 kb
Host smart-f522d06d-15d4-4d79-9552-c18b27179a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2750277075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2750277075
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.962282388
Short name T293
Test name
Test status
Simulation time 29232832 ps
CPU time 0.65 seconds
Started May 02 03:54:03 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 203252 kb
Host smart-3a75c2be-bd33-41dc-a29c-a805491ba361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=962282388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.962282388
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3831837715
Short name T1452
Test name
Test status
Simulation time 60653322 ps
CPU time 0.7 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203252 kb
Host smart-f737fa8a-2203-4c47-9d45-3f759037cb81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3831837715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3831837715
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2586513975
Short name T1435
Test name
Test status
Simulation time 30889376 ps
CPU time 0.66 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203284 kb
Host smart-d7cb116b-8b29-4fcb-9099-ce4b1b7c56b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2586513975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2586513975
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1638864025
Short name T289
Test name
Test status
Simulation time 29391827 ps
CPU time 0.69 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:04 PM PDT 24
Peak memory 203296 kb
Host smart-a070b787-cfaf-423a-9499-38280da89401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1638864025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1638864025
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3663871392
Short name T1404
Test name
Test status
Simulation time 28652443 ps
CPU time 0.65 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203316 kb
Host smart-b9c62b59-1ca5-4c20-9b09-9199c6e386e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3663871392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3663871392
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1806726171
Short name T268
Test name
Test status
Simulation time 291393448 ps
CPU time 3.4 seconds
Started May 02 03:53:55 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203912 kb
Host smart-cd081ee6-2f65-4af2-8037-412ed6a78e8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1806726171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1806726171
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2853244148
Short name T236
Test name
Test status
Simulation time 205165893 ps
CPU time 1.03 seconds
Started May 02 03:54:30 PM PDT 24
Finished May 02 03:54:31 PM PDT 24
Peak memory 203764 kb
Host smart-92b6b57a-efa8-471f-aebe-160b4fc3c8a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2853244148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2853244148
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1005531581
Short name T1415
Test name
Test status
Simulation time 99714194 ps
CPU time 1.27 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:58 PM PDT 24
Peak memory 212256 kb
Host smart-e7e23fb2-72f9-43f2-a4a6-e19490f40ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005531581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1005531581
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3401608510
Short name T1474
Test name
Test status
Simulation time 62549477 ps
CPU time 0.96 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:17 PM PDT 24
Peak memory 203020 kb
Host smart-0cece99f-bf5e-483f-91c2-d6077d95a22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3401608510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3401608510
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3959110737
Short name T284
Test name
Test status
Simulation time 34775947 ps
CPU time 0.69 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203320 kb
Host smart-923766b7-586c-4a3b-bef9-0da08fafc14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3959110737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3959110737
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3432577530
Short name T261
Test name
Test status
Simulation time 190093371 ps
CPU time 2.33 seconds
Started May 02 03:53:56 PM PDT 24
Finished May 02 03:54:01 PM PDT 24
Peak memory 212176 kb
Host smart-04532ebf-7dfa-4a39-9331-12a671908937
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3432577530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3432577530
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2104453050
Short name T1386
Test name
Test status
Simulation time 475954260 ps
CPU time 4.45 seconds
Started May 02 03:53:56 PM PDT 24
Finished May 02 03:54:03 PM PDT 24
Peak memory 203844 kb
Host smart-ca2e0912-00d4-4b10-8045-2c7b76f21681
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2104453050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2104453050
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3933460004
Short name T1454
Test name
Test status
Simulation time 89406944 ps
CPU time 1.04 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203960 kb
Host smart-8f09c6eb-a063-489f-b865-d5ef49ae9ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3933460004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3933460004
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1910757283
Short name T1438
Test name
Test status
Simulation time 59351432 ps
CPU time 1.42 seconds
Started May 02 03:53:58 PM PDT 24
Finished May 02 03:54:01 PM PDT 24
Peak memory 203940 kb
Host smart-cd6d11b9-a30d-4a14-adc7-0f0b8258a8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1910757283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1910757283
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4097202464
Short name T1481
Test name
Test status
Simulation time 40689700 ps
CPU time 0.65 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203212 kb
Host smart-02f3947a-49c0-415e-a1b2-b42627fe7b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097202464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4097202464
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2307491131
Short name T294
Test name
Test status
Simulation time 33834260 ps
CPU time 0.73 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:13 PM PDT 24
Peak memory 203204 kb
Host smart-ab6ad212-1a95-4af2-87a1-777cb233986a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2307491131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2307491131
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2684705098
Short name T1470
Test name
Test status
Simulation time 116687510 ps
CPU time 0.73 seconds
Started May 02 03:54:10 PM PDT 24
Finished May 02 03:54:13 PM PDT 24
Peak memory 203292 kb
Host smart-44875b2e-d187-44b6-a222-fbf0711a83c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2684705098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2684705098
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.581076712
Short name T288
Test name
Test status
Simulation time 32557666 ps
CPU time 0.66 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203200 kb
Host smart-dc71510d-883e-4a2d-9048-81450112de85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=581076712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.581076712
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1925984346
Short name T287
Test name
Test status
Simulation time 60588579 ps
CPU time 0.67 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203232 kb
Host smart-646c8ce0-bf2a-4434-91af-f3a36e9bc8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1925984346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1925984346
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2892928983
Short name T296
Test name
Test status
Simulation time 35386483 ps
CPU time 0.67 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203316 kb
Host smart-9a6eb3e0-a9ad-4c2c-91f8-b5108d2fe193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2892928983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2892928983
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3384245414
Short name T1449
Test name
Test status
Simulation time 29755154 ps
CPU time 0.67 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203308 kb
Host smart-4e864b77-1dd7-4f7e-ad4b-eb921ff90303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3384245414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3384245414
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2069250180
Short name T297
Test name
Test status
Simulation time 38424531 ps
CPU time 0.76 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203212 kb
Host smart-848708bf-e630-49d3-a40d-f67fbd94fa1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2069250180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2069250180
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2916113685
Short name T206
Test name
Test status
Simulation time 291183107 ps
CPU time 3.64 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203940 kb
Host smart-e07b67a8-4459-480f-b4c5-b4191bd69ffe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2916113685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2916113685
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1024382075
Short name T1451
Test name
Test status
Simulation time 912365099 ps
CPU time 5.16 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203836 kb
Host smart-f7160296-8f19-41be-b45a-fa56605cc966
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1024382075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1024382075
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1372670727
Short name T235
Test name
Test status
Simulation time 51565329 ps
CPU time 0.83 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:55 PM PDT 24
Peak memory 203688 kb
Host smart-fcaf60f9-61f3-4ad0-b9c6-18923a6c3a56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1372670727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1372670727
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1731721796
Short name T1462
Test name
Test status
Simulation time 137486342 ps
CPU time 1.78 seconds
Started May 02 03:53:57 PM PDT 24
Finished May 02 03:54:01 PM PDT 24
Peak memory 214976 kb
Host smart-6f813733-d1df-4779-bbcc-b00a37408c71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731721796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1731721796
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2573398698
Short name T271
Test name
Test status
Simulation time 42627621 ps
CPU time 1.01 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203924 kb
Host smart-d4935394-7e00-4f3f-b30c-c10f19f81e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2573398698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2573398698
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3481925931
Short name T1465
Test name
Test status
Simulation time 42979287 ps
CPU time 0.69 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:02 PM PDT 24
Peak memory 203224 kb
Host smart-08f24547-a3a5-4caa-9d3f-50603420e9e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3481925931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3481925931
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.813570659
Short name T260
Test name
Test status
Simulation time 194104281 ps
CPU time 2.21 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:19 PM PDT 24
Peak memory 211576 kb
Host smart-7f4b840d-ea7e-4c0b-834f-92b3cb34a3ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=813570659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.813570659
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2310936948
Short name T1385
Test name
Test status
Simulation time 267501594 ps
CPU time 2.48 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 203876 kb
Host smart-b5251a91-f31e-4fdb-a974-6c1638978f0d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2310936948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2310936948
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.409199511
Short name T1461
Test name
Test status
Simulation time 66374162 ps
CPU time 1.09 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 204028 kb
Host smart-fc02d4f8-4c57-416b-8011-157e8f16b730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=409199511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.409199511
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1903462447
Short name T232
Test name
Test status
Simulation time 92041667 ps
CPU time 2.4 seconds
Started May 02 03:53:54 PM PDT 24
Finished May 02 03:53:59 PM PDT 24
Peak memory 203980 kb
Host smart-b2a86dba-b6e4-4890-819c-bc6f400bf331
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1903462447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1903462447
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1788207982
Short name T210
Test name
Test status
Simulation time 281204876 ps
CPU time 3.65 seconds
Started May 02 03:53:52 PM PDT 24
Finished May 02 03:53:59 PM PDT 24
Peak memory 203956 kb
Host smart-6a33cbfd-24a3-4c89-96a3-443015cc452c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1788207982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1788207982
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2002677427
Short name T76
Test name
Test status
Simulation time 44604100 ps
CPU time 0.74 seconds
Started May 02 03:54:29 PM PDT 24
Finished May 02 03:54:31 PM PDT 24
Peak memory 203272 kb
Host smart-6b517a80-2763-44c3-a536-39040924e051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2002677427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2002677427
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2535095815
Short name T1424
Test name
Test status
Simulation time 40793896 ps
CPU time 0.66 seconds
Started May 02 03:54:15 PM PDT 24
Finished May 02 03:54:17 PM PDT 24
Peak memory 203264 kb
Host smart-48827af4-a749-403a-b935-6645015da862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2535095815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2535095815
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.695957943
Short name T290
Test name
Test status
Simulation time 33107610 ps
CPU time 0.65 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203200 kb
Host smart-90cb2e9f-cc96-4ee2-bb87-eca6d111b6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=695957943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.695957943
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1703630010
Short name T1397
Test name
Test status
Simulation time 45406167 ps
CPU time 0.69 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 203176 kb
Host smart-390b43a9-3e5b-4b4f-8888-d21a026024b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1703630010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1703630010
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.599547382
Short name T72
Test name
Test status
Simulation time 36698638 ps
CPU time 0.69 seconds
Started May 02 03:54:17 PM PDT 24
Finished May 02 03:54:18 PM PDT 24
Peak memory 203244 kb
Host smart-8b73eaf5-df31-4ebc-8e6d-f965df85a73b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=599547382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.599547382
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2420969123
Short name T1422
Test name
Test status
Simulation time 26335056 ps
CPU time 0.63 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203224 kb
Host smart-dcc3fc7c-8a27-40ee-b616-6371ec44f8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2420969123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2420969123
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.534778666
Short name T295
Test name
Test status
Simulation time 27755413 ps
CPU time 0.66 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:08 PM PDT 24
Peak memory 203244 kb
Host smart-be660e09-62bf-4980-b6c3-84bd2bbd0c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=534778666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.534778666
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.333469061
Short name T1456
Test name
Test status
Simulation time 85435186 ps
CPU time 0.76 seconds
Started May 02 03:54:14 PM PDT 24
Finished May 02 03:54:15 PM PDT 24
Peak memory 203312 kb
Host smart-f0fd45c2-6a1f-4ab3-b781-049cd8d0adc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=333469061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.333469061
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2207880408
Short name T285
Test name
Test status
Simulation time 23841048 ps
CPU time 0.65 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 203320 kb
Host smart-8d9f4014-d88f-498c-a46c-6ab6fe4426e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2207880408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2207880408
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3563080237
Short name T1410
Test name
Test status
Simulation time 62748011 ps
CPU time 0.68 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:15 PM PDT 24
Peak memory 203232 kb
Host smart-78c0a7ce-e8c2-457e-998f-b271a5eae5c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3563080237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3563080237
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1121728852
Short name T1405
Test name
Test status
Simulation time 256120147 ps
CPU time 1.94 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:19 PM PDT 24
Peak memory 211720 kb
Host smart-300f5c6c-6e20-40e1-8f64-db65b6e78396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121728852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1121728852
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2972523520
Short name T1458
Test name
Test status
Simulation time 60582142 ps
CPU time 0.87 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203744 kb
Host smart-ad4befe3-d797-4003-8a45-fb6e7f1489b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2972523520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2972523520
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3119320065
Short name T1407
Test name
Test status
Simulation time 60635684 ps
CPU time 0.68 seconds
Started May 02 03:54:03 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203288 kb
Host smart-db545c61-19f0-4a94-8994-283e2e7556a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3119320065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3119320065
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.395620072
Short name T272
Test name
Test status
Simulation time 192428489 ps
CPU time 1.58 seconds
Started May 02 03:53:53 PM PDT 24
Finished May 02 03:53:58 PM PDT 24
Peak memory 204000 kb
Host smart-1b95b4d0-5d0e-4b8b-a52b-7f384e1769a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395620072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.395620072
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.83644188
Short name T1450
Test name
Test status
Simulation time 83591354 ps
CPU time 1.66 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 204004 kb
Host smart-51d039f9-a7a8-410a-a49c-3d9ce101fe2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=83644188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.83644188
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1037726091
Short name T238
Test name
Test status
Simulation time 856464673 ps
CPU time 4.76 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 204024 kb
Host smart-d7fa68b2-1466-4790-8e4d-701dcd25337c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1037726091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1037726091
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3466096978
Short name T239
Test name
Test status
Simulation time 86634799 ps
CPU time 1.3 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 212264 kb
Host smart-de505721-fe16-4423-ab4c-0bf43a689be5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466096978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3466096978
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3455594508
Short name T1428
Test name
Test status
Simulation time 31641360 ps
CPU time 0.84 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:10 PM PDT 24
Peak memory 203240 kb
Host smart-d80d748e-7597-4710-83a1-51edcd4d93b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3455594508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3455594508
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1620800549
Short name T1434
Test name
Test status
Simulation time 27000155 ps
CPU time 0.63 seconds
Started May 02 03:53:54 PM PDT 24
Finished May 02 03:53:57 PM PDT 24
Peak memory 203100 kb
Host smart-a7930413-b8ac-4757-9185-485270578448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1620800549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1620800549
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1945317089
Short name T1419
Test name
Test status
Simulation time 195364353 ps
CPU time 1.66 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203964 kb
Host smart-bb181bde-4881-4f15-8827-5d93264dc94e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1945317089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1945317089
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3260783584
Short name T1476
Test name
Test status
Simulation time 139452731 ps
CPU time 1.81 seconds
Started May 02 03:53:55 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 212248 kb
Host smart-585bbc33-3074-4272-b052-b6de88453a5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260783584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3260783584
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.679413735
Short name T1394
Test name
Test status
Simulation time 94421095 ps
CPU time 0.85 seconds
Started May 02 03:54:01 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203796 kb
Host smart-54e36eb7-2d59-4463-9a24-caa6d447380f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=679413735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.679413735
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2202590669
Short name T1411
Test name
Test status
Simulation time 45662785 ps
CPU time 0.63 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:03 PM PDT 24
Peak memory 203188 kb
Host smart-b2d372a6-f716-49d9-9ec4-892bf58e08dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2202590669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2202590669
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3459495338
Short name T1437
Test name
Test status
Simulation time 90103302 ps
CPU time 1.08 seconds
Started May 02 03:55:14 PM PDT 24
Finished May 02 03:55:17 PM PDT 24
Peak memory 202224 kb
Host smart-47225463-129b-4b12-bc12-4447d05486eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3459495338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3459495338
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1336433371
Short name T1414
Test name
Test status
Simulation time 38368161 ps
CPU time 1.2 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:09 PM PDT 24
Peak memory 204048 kb
Host smart-f751cb11-0936-4e85-bc69-ed1ee98c826a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1336433371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1336433371
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3706599142
Short name T62
Test name
Test status
Simulation time 186344068 ps
CPU time 2.3 seconds
Started May 02 03:54:00 PM PDT 24
Finished May 02 03:54:06 PM PDT 24
Peak memory 203920 kb
Host smart-cafc82bf-90e3-4b61-95cd-63e453b1741c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3706599142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3706599142
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3942163
Short name T1464
Test name
Test status
Simulation time 54283784 ps
CPU time 1.51 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:18 PM PDT 24
Peak memory 211464 kb
Host smart-7caf1ea4-96ff-4ec9-b08f-04f321aebe3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us
bdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_c
sr_mem_rw_with_rand_reset.3942163
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1837702418
Short name T1427
Test name
Test status
Simulation time 90921202 ps
CPU time 1.02 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203976 kb
Host smart-ea610018-15c1-4f51-a94f-df8666562c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1837702418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1837702418
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4013701799
Short name T1433
Test name
Test status
Simulation time 45105394 ps
CPU time 0.69 seconds
Started May 02 03:55:14 PM PDT 24
Finished May 02 03:55:17 PM PDT 24
Peak memory 201488 kb
Host smart-b4be9426-4330-4fbc-9094-e5e6e30d8fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4013701799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4013701799
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2023879095
Short name T207
Test name
Test status
Simulation time 50070546 ps
CPU time 1.01 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:18 PM PDT 24
Peak memory 203408 kb
Host smart-45b70cf1-147a-4a24-af9b-e6776dbb37c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2023879095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2023879095
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1718998432
Short name T1468
Test name
Test status
Simulation time 116759085 ps
CPU time 2.47 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 03:55:20 PM PDT 24
Peak memory 203532 kb
Host smart-b1ba9f3a-4a69-4caf-99a6-e0848c1e42a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1718998432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1718998432
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.275472594
Short name T280
Test name
Test status
Simulation time 607845148 ps
CPU time 4.92 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 204028 kb
Host smart-bdaa282d-e76c-4e0f-ae18-1de2b9280279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=275472594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.275472594
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2462319084
Short name T1448
Test name
Test status
Simulation time 86649241 ps
CPU time 1.47 seconds
Started May 02 03:54:05 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 212772 kb
Host smart-d58901a4-6d3f-4ef0-8022-ce6fdb332cd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462319084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2462319084
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2042787676
Short name T1472
Test name
Test status
Simulation time 27256760 ps
CPU time 0.84 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203728 kb
Host smart-1a37775a-76d4-43dc-9357-69e60c09b684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2042787676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2042787676
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3799495026
Short name T291
Test name
Test status
Simulation time 36673351 ps
CPU time 0.66 seconds
Started May 02 03:54:02 PM PDT 24
Finished May 02 03:54:07 PM PDT 24
Peak memory 203276 kb
Host smart-06282a91-d300-45cd-a91a-06597cfa7f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3799495026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3799495026
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2509555789
Short name T283
Test name
Test status
Simulation time 95059460 ps
CPU time 1.15 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 203976 kb
Host smart-a6d88e5c-d56a-441f-8a5b-f82e149b5e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509555789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2509555789
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1718551855
Short name T1420
Test name
Test status
Simulation time 168175199 ps
CPU time 1.95 seconds
Started May 02 03:53:51 PM PDT 24
Finished May 02 03:53:55 PM PDT 24
Peak memory 204032 kb
Host smart-998b9088-1f9c-4a6d-923c-5c724bf20da9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1718551855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1718551855
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1529524864
Short name T1431
Test name
Test status
Simulation time 933785784 ps
CPU time 3.51 seconds
Started May 02 03:53:59 PM PDT 24
Finished May 02 03:54:05 PM PDT 24
Peak memory 203984 kb
Host smart-8157bba0-a71b-4ed2-ab6f-c8cbe480b43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1529524864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1529524864
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.3231291551
Short name T1055
Test name
Test status
Simulation time 8385638675 ps
CPU time 10.04 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204140 kb
Host smart-e357bb52-f62c-492e-babb-f4345089c09c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3231291551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.3231291551
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.2359723308
Short name T518
Test name
Test status
Simulation time 8428890942 ps
CPU time 7.91 seconds
Started May 02 03:44:41 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204144 kb
Host smart-6df4d4f0-e221-49e7-8843-e75d00dd363f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23597
23308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.2359723308
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3504139186
Short name T1191
Test name
Test status
Simulation time 8443528021 ps
CPU time 9.61 seconds
Started May 02 03:44:26 PM PDT 24
Finished May 02 03:44:36 PM PDT 24
Peak memory 204120 kb
Host smart-8fc30a54-3f31-4e16-9a91-0f86ab415060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35041
39186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3504139186
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.1728970106
Short name T506
Test name
Test status
Simulation time 8374394151 ps
CPU time 8.89 seconds
Started May 02 03:44:28 PM PDT 24
Finished May 02 03:44:38 PM PDT 24
Peak memory 204132 kb
Host smart-57b42aff-40b8-482c-a958-0173f304e615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
70106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1728970106
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3409650464
Short name T303
Test name
Test status
Simulation time 51056775 ps
CPU time 1.14 seconds
Started May 02 03:44:27 PM PDT 24
Finished May 02 03:44:29 PM PDT 24
Peak memory 204136 kb
Host smart-1cd54d3e-921d-46c6-a9cb-1402df067385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34096
50464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3409650464
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.349625361
Short name T1061
Test name
Test status
Simulation time 8406122237 ps
CPU time 9.71 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:50 PM PDT 24
Peak memory 204152 kb
Host smart-c416769a-373a-48f4-b99c-885e2be08496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34962
5361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.349625361
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4115541746
Short name T1095
Test name
Test status
Simulation time 8445701266 ps
CPU time 8.03 seconds
Started May 02 03:44:32 PM PDT 24
Finished May 02 03:44:41 PM PDT 24
Peak memory 204048 kb
Host smart-e9681ac9-3788-4cf9-93c9-193417ba7118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41155
41746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4115541746
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2224466785
Short name T509
Test name
Test status
Simulation time 8443640959 ps
CPU time 7.53 seconds
Started May 02 03:44:36 PM PDT 24
Finished May 02 03:44:45 PM PDT 24
Peak memory 204136 kb
Host smart-acf8960d-aebe-41ff-8455-615eb6e1b096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22244
66785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2224466785
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2043312324
Short name T1088
Test name
Test status
Simulation time 8374416239 ps
CPU time 7.97 seconds
Started May 02 03:44:32 PM PDT 24
Finished May 02 03:44:41 PM PDT 24
Peak memory 204080 kb
Host smart-bc1ca7d2-f9d5-4642-b4ec-923908d05433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20433
12324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2043312324
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3972495512
Short name T705
Test name
Test status
Simulation time 8408809928 ps
CPU time 8.02 seconds
Started May 02 03:44:32 PM PDT 24
Finished May 02 03:44:41 PM PDT 24
Peak memory 204156 kb
Host smart-7ee885f1-8a85-46f7-a300-765c5ebd2eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39724
95512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3972495512
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2548566287
Short name T1131
Test name
Test status
Simulation time 8373854074 ps
CPU time 7.99 seconds
Started May 02 03:44:29 PM PDT 24
Finished May 02 03:44:38 PM PDT 24
Peak memory 204076 kb
Host smart-97b76319-6686-4a8a-b1b9-8c83c637a8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25485
66287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2548566287
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2402657505
Short name T1367
Test name
Test status
Simulation time 8391467318 ps
CPU time 8.16 seconds
Started May 02 03:44:34 PM PDT 24
Finished May 02 03:44:43 PM PDT 24
Peak memory 204060 kb
Host smart-303eaf8e-26f3-49ef-81a6-74ba5202adad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24026
57505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2402657505
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.443852807
Short name T951
Test name
Test status
Simulation time 45888466 ps
CPU time 0.68 seconds
Started May 02 03:44:35 PM PDT 24
Finished May 02 03:44:36 PM PDT 24
Peak memory 203960 kb
Host smart-16677fb2-0d74-4ba2-8126-91f0d5473198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44385
2807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.443852807
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.722465698
Short name T386
Test name
Test status
Simulation time 8463354345 ps
CPU time 7.66 seconds
Started May 02 03:44:31 PM PDT 24
Finished May 02 03:44:40 PM PDT 24
Peak memory 204100 kb
Host smart-261b7a99-1f8d-4d74-a550-26f6f2b4d0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72246
5698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.722465698
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1032255359
Short name T418
Test name
Test status
Simulation time 8412878558 ps
CPU time 9.16 seconds
Started May 02 03:44:32 PM PDT 24
Finished May 02 03:44:42 PM PDT 24
Peak memory 204104 kb
Host smart-3a1fb9d6-f907-437b-a5e5-67474e036201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322
55359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1032255359
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1012245933
Short name T67
Test name
Test status
Simulation time 366810390 ps
CPU time 1.27 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 221504 kb
Host smart-50212291-f3d7-4731-9c15-2a39b2082f75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1012245933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1012245933
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.325973296
Short name T574
Test name
Test status
Simulation time 8378423562 ps
CPU time 7.67 seconds
Started May 02 03:44:34 PM PDT 24
Finished May 02 03:44:42 PM PDT 24
Peak memory 204068 kb
Host smart-b85e56e4-1209-4158-82fd-81cd44b3d2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
3296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.325973296
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.418295628
Short name T430
Test name
Test status
Simulation time 8387775404 ps
CPU time 7.49 seconds
Started May 02 03:44:31 PM PDT 24
Finished May 02 03:44:40 PM PDT 24
Peak memory 204136 kb
Host smart-aaed0cbf-7402-42d0-9357-7b4dff46b464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41829
5628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.418295628
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2648929274
Short name T1299
Test name
Test status
Simulation time 8398375738 ps
CPU time 7.82 seconds
Started May 02 03:44:36 PM PDT 24
Finished May 02 03:44:45 PM PDT 24
Peak memory 204132 kb
Host smart-696db0ad-7d59-4c91-b074-c67a9637736a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489
29274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2648929274
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.870740859
Short name T380
Test name
Test status
Simulation time 8382681223 ps
CPU time 7.96 seconds
Started May 02 03:44:31 PM PDT 24
Finished May 02 03:44:39 PM PDT 24
Peak memory 204100 kb
Host smart-7b4b5230-6bc3-4a48-a677-e5f70eb29b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87074
0859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.870740859
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3756440303
Short name T333
Test name
Test status
Simulation time 8507531150 ps
CPU time 7.69 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:47 PM PDT 24
Peak memory 204048 kb
Host smart-21721add-5851-4a42-b892-883e75849ac3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3756440303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3756440303
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.1569031708
Short name T491
Test name
Test status
Simulation time 8384566717 ps
CPU time 7.72 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:52 PM PDT 24
Peak memory 204128 kb
Host smart-f03b23c4-6efd-4f50-b713-0cbee45b8070
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1569031708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.1569031708
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1307082937
Short name T662
Test name
Test status
Simulation time 8437755679 ps
CPU time 8.51 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204140 kb
Host smart-6e3eb8ab-6d83-438d-93e0-d2bad02ea929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
82937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1307082937
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2163765226
Short name T1157
Test name
Test status
Simulation time 8391727809 ps
CPU time 8.67 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204088 kb
Host smart-914fc6fa-3925-455f-b123-d1ed3063672a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21637
65226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2163765226
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.3884496704
Short name T1218
Test name
Test status
Simulation time 8418194366 ps
CPU time 10.77 seconds
Started May 02 03:44:41 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204136 kb
Host smart-256fdbbb-dd3d-42ab-8a63-65b1c0fb5f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38844
96704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3884496704
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.4077146201
Short name T226
Test name
Test status
Simulation time 200914892 ps
CPU time 2.12 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:45 PM PDT 24
Peak memory 204264 kb
Host smart-af9f557e-785d-4808-b4e1-1ecd02b065af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40771
46201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.4077146201
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.281202787
Short name T707
Test name
Test status
Simulation time 8441037123 ps
CPU time 8.92 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204064 kb
Host smart-479d09fe-68e6-4418-b353-94f6e2149899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
2787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.281202787
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2191733566
Short name T994
Test name
Test status
Simulation time 8383329427 ps
CPU time 7.94 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:47 PM PDT 24
Peak memory 203468 kb
Host smart-c21dd124-3707-47da-9c42-669f9c0b6a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21917
33566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2191733566
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.682462693
Short name T1179
Test name
Test status
Simulation time 8429820949 ps
CPU time 7.75 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:47 PM PDT 24
Peak memory 204068 kb
Host smart-7373a003-4738-4bea-bbf4-c696b09a430f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68246
2693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.682462693
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.522449522
Short name T349
Test name
Test status
Simulation time 8414895792 ps
CPU time 8.69 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:47 PM PDT 24
Peak memory 203464 kb
Host smart-84328fd8-58c4-4ae9-a4c3-8edcb7125f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52244
9522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.522449522
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2957319058
Short name T733
Test name
Test status
Simulation time 8366447692 ps
CPU time 7.76 seconds
Started May 02 03:44:40 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204020 kb
Host smart-e692105e-7b91-4da0-bb7a-c7721f544b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
19058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2957319058
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2757881289
Short name T319
Test name
Test status
Simulation time 8410393223 ps
CPU time 8.58 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204128 kb
Host smart-558f18a3-141c-4a16-979b-d61fa2d18f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
81289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2757881289
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.406190431
Short name T435
Test name
Test status
Simulation time 8388751749 ps
CPU time 9.03 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:52 PM PDT 24
Peak memory 204140 kb
Host smart-ca64aafb-af8d-4a63-a2b3-374e9194cd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40619
0431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.406190431
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1883457565
Short name T1309
Test name
Test status
Simulation time 8395187456 ps
CPU time 7.61 seconds
Started May 02 03:44:40 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204004 kb
Host smart-52712f28-3cb0-43c8-af3d-72d706db72d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
57565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1883457565
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1554766163
Short name T918
Test name
Test status
Simulation time 8377666459 ps
CPU time 8.63 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:47 PM PDT 24
Peak memory 204120 kb
Host smart-a6729efb-cbe5-4922-9209-c5fd722f23c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15547
66163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1554766163
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1936105390
Short name T1354
Test name
Test status
Simulation time 136684567 ps
CPU time 0.84 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:45 PM PDT 24
Peak memory 203996 kb
Host smart-e681ee43-ea54-4f3f-a2ff-32cc5f5b03fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19361
05390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1936105390
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.885550007
Short name T1271
Test name
Test status
Simulation time 22553921320 ps
CPU time 38.13 seconds
Started May 02 03:44:37 PM PDT 24
Finished May 02 03:45:15 PM PDT 24
Peak memory 204396 kb
Host smart-88ded6bd-e644-49cc-bbe3-66565dff64b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88555
0007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.885550007
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.165233441
Short name T791
Test name
Test status
Simulation time 8421183987 ps
CPU time 7.97 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:51 PM PDT 24
Peak memory 204076 kb
Host smart-fe8f07f5-ee1b-47a0-9597-6717d7bc42dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
3441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.165233441
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.4214068804
Short name T1162
Test name
Test status
Simulation time 8412089258 ps
CPU time 10.19 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:49 PM PDT 24
Peak memory 204140 kb
Host smart-2bc6162e-e76a-4d1d-90b2-fb6a246737af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42140
68804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.4214068804
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1372839823
Short name T657
Test name
Test status
Simulation time 8389295370 ps
CPU time 7.68 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204112 kb
Host smart-61a7107a-2a4a-440c-932b-1e7796c2a90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13728
39823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1372839823
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.956763161
Short name T81
Test name
Test status
Simulation time 306609229 ps
CPU time 1.24 seconds
Started May 02 03:44:41 PM PDT 24
Finished May 02 03:44:43 PM PDT 24
Peak memory 221420 kb
Host smart-bf48e73c-12fe-49b4-9e4f-9661bdf8aea1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=956763161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.956763161
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2787710067
Short name T1318
Test name
Test status
Simulation time 8393681917 ps
CPU time 7.84 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204160 kb
Host smart-c658185c-59a0-4daa-850e-283dd2f57d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
10067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2787710067
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1663955726
Short name T837
Test name
Test status
Simulation time 8376977360 ps
CPU time 7.21 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:46 PM PDT 24
Peak memory 204072 kb
Host smart-51e285a9-3e73-4017-9133-315b3c61ae82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
55726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1663955726
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1047814902
Short name T623
Test name
Test status
Simulation time 8369317021 ps
CPU time 10.14 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204072 kb
Host smart-4ac4d17d-9ee8-4df9-a3f3-94f1d1b2c0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
14902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1047814902
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1060440946
Short name T931
Test name
Test status
Simulation time 8517115994 ps
CPU time 7.55 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204136 kb
Host smart-91fa5f62-5177-48d7-8be9-94d4144f31c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10604
40946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1060440946
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.1620195379
Short name T1290
Test name
Test status
Simulation time 8472445678 ps
CPU time 8.86 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:33 PM PDT 24
Peak memory 204144 kb
Host smart-602a9b04-0682-4dac-8ec1-0f7c655d2458
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1620195379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.1620195379
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2508388147
Short name T1152
Test name
Test status
Simulation time 8385770820 ps
CPU time 10 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:34 PM PDT 24
Peak memory 204144 kb
Host smart-29da82b5-5a3c-4697-8647-525c0b6aefcb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2508388147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2508388147
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.3865728380
Short name T1364
Test name
Test status
Simulation time 8456788836 ps
CPU time 8.62 seconds
Started May 02 03:45:27 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204120 kb
Host smart-df2671bf-c14c-4d03-93c7-352b6fec0a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
28380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.3865728380
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2041106047
Short name T1129
Test name
Test status
Simulation time 8373001546 ps
CPU time 8.26 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:33 PM PDT 24
Peak memory 204048 kb
Host smart-63ebc1a0-ef56-46da-8dd7-cfbf1c1cd209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411
06047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2041106047
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.3491615750
Short name T93
Test name
Test status
Simulation time 8378753467 ps
CPU time 8.07 seconds
Started May 02 03:45:25 PM PDT 24
Finished May 02 03:45:34 PM PDT 24
Peak memory 204112 kb
Host smart-eb0acf0b-5c4c-4fdc-a0ad-8c6f63c40f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
15750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3491615750
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3688110504
Short name T1229
Test name
Test status
Simulation time 115749974 ps
CPU time 1.48 seconds
Started May 02 03:45:22 PM PDT 24
Finished May 02 03:45:24 PM PDT 24
Peak memory 204252 kb
Host smart-2a9a6205-d89a-490b-b1f5-90c17f780b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36881
10504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3688110504
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3852358953
Short name T199
Test name
Test status
Simulation time 8364967837 ps
CPU time 7.96 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204084 kb
Host smart-98f1c6d0-10b1-446a-bc88-1cbeb08c5da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
58953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3852358953
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2403156697
Short name T1156
Test name
Test status
Simulation time 8452635468 ps
CPU time 9.84 seconds
Started May 02 03:45:25 PM PDT 24
Finished May 02 03:45:35 PM PDT 24
Peak memory 204076 kb
Host smart-cf21222a-b914-46de-ab93-5558f1791d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24031
56697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2403156697
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3838649175
Short name T534
Test name
Test status
Simulation time 8411222643 ps
CPU time 7.7 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204128 kb
Host smart-84736c43-bcbf-4979-9760-b28e92a9054e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
49175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3838649175
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3472834147
Short name T1320
Test name
Test status
Simulation time 8366991219 ps
CPU time 7.49 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:31 PM PDT 24
Peak memory 204100 kb
Host smart-2b5e478a-119b-48d4-a2ba-f0d83471cde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34728
34147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3472834147
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3981123406
Short name T1241
Test name
Test status
Simulation time 8418373223 ps
CPU time 10.44 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204140 kb
Host smart-c40c422f-3ffd-428c-8ee0-000ad21acdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39811
23406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3981123406
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1917481239
Short name T352
Test name
Test status
Simulation time 8393157974 ps
CPU time 9.72 seconds
Started May 02 03:45:30 PM PDT 24
Finished May 02 03:45:41 PM PDT 24
Peak memory 204096 kb
Host smart-244ec413-ec34-45ec-8fee-2090e8ffd4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19174
81239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1917481239
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.475491440
Short name T159
Test name
Test status
Simulation time 8450738338 ps
CPU time 9.44 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:39 PM PDT 24
Peak memory 204084 kb
Host smart-c6acdafe-c34d-420d-add8-7f6c96dc1c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47549
1440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.475491440
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.618527336
Short name T923
Test name
Test status
Simulation time 8430971958 ps
CPU time 7.75 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204124 kb
Host smart-5bf062e1-05f7-43ec-9c84-e1e267784f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61852
7336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.618527336
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3099030444
Short name T1056
Test name
Test status
Simulation time 70427611 ps
CPU time 0.7 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204024 kb
Host smart-45c65b60-b437-45bd-b277-c9c6c807833f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30990
30444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3099030444
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1817440255
Short name T230
Test name
Test status
Simulation time 29584421533 ps
CPU time 65.42 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:46:43 PM PDT 24
Peak memory 204436 kb
Host smart-63f454a9-c44f-4de8-adf3-46525fdb120c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18174
40255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1817440255
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.420465593
Short name T1215
Test name
Test status
Simulation time 8427075655 ps
CPU time 8.37 seconds
Started May 02 03:45:24 PM PDT 24
Finished May 02 03:45:33 PM PDT 24
Peak memory 204092 kb
Host smart-1f463aa5-6f04-4306-a88d-b35e36e06a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42046
5593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.420465593
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1961357280
Short name T852
Test name
Test status
Simulation time 8475851724 ps
CPU time 9.63 seconds
Started May 02 03:45:22 PM PDT 24
Finished May 02 03:45:33 PM PDT 24
Peak memory 204116 kb
Host smart-3354d73c-2902-44f8-8a94-005b77b6ecee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
57280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1961357280
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.525503986
Short name T1284
Test name
Test status
Simulation time 8417655081 ps
CPU time 9.24 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:33 PM PDT 24
Peak memory 204124 kb
Host smart-5b958d07-8980-4a18-bfe3-c6a6733642b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52550
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.525503986
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1261610224
Short name T1312
Test name
Test status
Simulation time 8392877769 ps
CPU time 8.31 seconds
Started May 02 03:45:22 PM PDT 24
Finished May 02 03:45:31 PM PDT 24
Peak memory 204068 kb
Host smart-f949c164-de45-4c4c-8476-ed05f1993ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12616
10224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1261610224
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2592655294
Short name T634
Test name
Test status
Simulation time 8399334515 ps
CPU time 7.26 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204092 kb
Host smart-4972acfe-04b6-42d4-b4fc-8aec6acf2547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25926
55294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2592655294
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.66677280
Short name T865
Test name
Test status
Simulation time 8479036142 ps
CPU time 9.52 seconds
Started May 02 03:45:18 PM PDT 24
Finished May 02 03:45:28 PM PDT 24
Peak memory 204120 kb
Host smart-d594f690-4d95-4d4f-b499-2480492b41f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66677
280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.66677280
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3827434879
Short name T538
Test name
Test status
Simulation time 8438785083 ps
CPU time 8.83 seconds
Started May 02 03:45:27 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204072 kb
Host smart-2bf5f21d-39af-42df-80f6-bab7343b62ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38274
34879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3827434879
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2594527166
Short name T1024
Test name
Test status
Simulation time 8426662338 ps
CPU time 10.25 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204152 kb
Host smart-bccbdd4f-d965-435c-b5d3-65e7c6da16ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25945
27166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2594527166
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.2663516076
Short name T329
Test name
Test status
Simulation time 8474967347 ps
CPU time 7.54 seconds
Started May 02 03:45:38 PM PDT 24
Finished May 02 03:45:48 PM PDT 24
Peak memory 204088 kb
Host smart-016bf354-2379-4b8f-bb4d-b75d83a451c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2663516076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.2663516076
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.2411922060
Short name T1189
Test name
Test status
Simulation time 8375412898 ps
CPU time 7.41 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204144 kb
Host smart-cce165d7-3c06-48cd-a32f-e220692cba9a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2411922060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.2411922060
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.247495887
Short name T99
Test name
Test status
Simulation time 8470180293 ps
CPU time 7.91 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204064 kb
Host smart-83c98211-f997-4fd0-8180-1784b96497ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
5887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.247495887
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3127869339
Short name T809
Test name
Test status
Simulation time 8426357892 ps
CPU time 7.65 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:36 PM PDT 24
Peak memory 204096 kb
Host smart-2a727500-091e-4a42-97a2-eac7f4c0e8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
69339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3127869339
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3399657658
Short name T425
Test name
Test status
Simulation time 8374241370 ps
CPU time 8.06 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204144 kb
Host smart-aacc2375-cfc2-4e35-bf96-5c6d42a4e23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
57658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3399657658
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3449761044
Short name T648
Test name
Test status
Simulation time 47690381 ps
CPU time 1.31 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204212 kb
Host smart-142548e3-3110-41e8-8776-6f7f1ce74ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34497
61044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3449761044
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.374215918
Short name T814
Test name
Test status
Simulation time 8411941008 ps
CPU time 7.84 seconds
Started May 02 03:45:27 PM PDT 24
Finished May 02 03:45:36 PM PDT 24
Peak memory 204028 kb
Host smart-985fe646-8ba5-4f0a-a8c5-713d76acd47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
5918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.374215918
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1034145846
Short name T945
Test name
Test status
Simulation time 8457013190 ps
CPU time 8.66 seconds
Started May 02 03:45:25 PM PDT 24
Finished May 02 03:45:34 PM PDT 24
Peak memory 204080 kb
Host smart-3bb0ef7d-9864-4c5b-85d5-ec84a87dcd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10341
45846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1034145846
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3633348899
Short name T1105
Test name
Test status
Simulation time 8373276052 ps
CPU time 7.29 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 203884 kb
Host smart-5c68acf8-4bd7-440c-9b12-5f76a76a1f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36333
48899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3633348899
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3746600270
Short name T597
Test name
Test status
Simulation time 8443379612 ps
CPU time 7.85 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204068 kb
Host smart-ab87ef31-41be-4ece-8811-ff94492ceb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37466
00270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3746600270
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3667973722
Short name T484
Test name
Test status
Simulation time 8393980037 ps
CPU time 10.23 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204168 kb
Host smart-cbe29d50-3b7b-4eb0-827b-d4f42e67294d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36679
73722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3667973722
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.791500002
Short name T1090
Test name
Test status
Simulation time 8391100097 ps
CPU time 9.33 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204148 kb
Host smart-67350035-088f-4cb5-8ba0-f338e50b712b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79150
0002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.791500002
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1316889245
Short name T1046
Test name
Test status
Simulation time 8393901903 ps
CPU time 8.07 seconds
Started May 02 03:45:22 PM PDT 24
Finished May 02 03:45:31 PM PDT 24
Peak memory 204112 kb
Host smart-b5fa8f33-ea17-4e05-a4a6-d8dfb24d6464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
89245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1316889245
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1213975463
Short name T13
Test name
Test status
Simulation time 29605400428 ps
CPU time 62.11 seconds
Started May 02 03:45:26 PM PDT 24
Finished May 02 03:46:29 PM PDT 24
Peak memory 204360 kb
Host smart-46cecb00-4574-40b2-bd5b-cfa4fc190d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12139
75463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1213975463
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.797977857
Short name T1138
Test name
Test status
Simulation time 8415943413 ps
CPU time 8.58 seconds
Started May 02 03:45:27 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204016 kb
Host smart-3b5f65c0-2557-482f-83f9-f2927c1aa837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79797
7857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.797977857
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.4099367854
Short name T1111
Test name
Test status
Simulation time 8390373856 ps
CPU time 7.86 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:38 PM PDT 24
Peak memory 203920 kb
Host smart-402ab104-e33b-4c7c-aa1e-b14bc1142a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993
67854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.4099367854
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1980077245
Short name T1209
Test name
Test status
Simulation time 8386131255 ps
CPU time 7.71 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:43 PM PDT 24
Peak memory 204048 kb
Host smart-5de83ece-4f5c-4e15-ae2c-23033c8e1ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
77245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1980077245
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3518452694
Short name T1269
Test name
Test status
Simulation time 8436021856 ps
CPU time 7.78 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204096 kb
Host smart-22aee68d-6284-472e-b429-5eb5327b22e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35184
52694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3518452694
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.4154786111
Short name T475
Test name
Test status
Simulation time 8417253854 ps
CPU time 7.68 seconds
Started May 02 03:45:25 PM PDT 24
Finished May 02 03:45:34 PM PDT 24
Peak memory 204036 kb
Host smart-28fc343b-7f35-40a6-94bc-a200d8bb2c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41547
86111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4154786111
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1864766389
Short name T1035
Test name
Test status
Simulation time 8401140923 ps
CPU time 8.17 seconds
Started May 02 03:45:28 PM PDT 24
Finished May 02 03:45:38 PM PDT 24
Peak memory 204032 kb
Host smart-3f90452e-187c-467e-bc29-762404975679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18647
66389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1864766389
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2201980180
Short name T901
Test name
Test status
Simulation time 8395695988 ps
CPU time 7.3 seconds
Started May 02 03:45:23 PM PDT 24
Finished May 02 03:45:32 PM PDT 24
Peak memory 204068 kb
Host smart-42ee84c2-4cc8-4409-a596-2379ffde0de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22019
80180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2201980180
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.3478998441
Short name T781
Test name
Test status
Simulation time 8460972018 ps
CPU time 7.94 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204128 kb
Host smart-6fa49643-14a0-4107-ba5c-17ee2dffa385
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3478998441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.3478998441
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.1699284975
Short name T1110
Test name
Test status
Simulation time 8388997682 ps
CPU time 9.48 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:48 PM PDT 24
Peak memory 204100 kb
Host smart-251da0ab-4fa2-40bf-9f10-091bcd18d6aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699284975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.1699284975
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.2986318654
Short name T763
Test name
Test status
Simulation time 8404554048 ps
CPU time 8.22 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:13 PM PDT 24
Peak memory 203572 kb
Host smart-788b8718-3a4d-4ebe-97b0-1d871deead56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29863
18654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.2986318654
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3684684082
Short name T350
Test name
Test status
Simulation time 8374626174 ps
CPU time 8.97 seconds
Started May 02 03:45:38 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204088 kb
Host smart-92e9253d-2008-41dd-a865-d4cf913c1a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
84082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3684684082
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.1932842555
Short name T218
Test name
Test status
Simulation time 8368935997 ps
CPU time 8.88 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:48 PM PDT 24
Peak memory 204088 kb
Host smart-55b904f5-84b6-4072-912d-b93bd5c40bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19328
42555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1932842555
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.4222369540
Short name T601
Test name
Test status
Simulation time 165460043 ps
CPU time 1.9 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:41 PM PDT 24
Peak memory 204256 kb
Host smart-bfd3f8bc-73b4-4704-89fb-8d85c8501fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
69540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.4222369540
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.4056775601
Short name T828
Test name
Test status
Simulation time 8400117273 ps
CPU time 9.8 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204084 kb
Host smart-ae5a8859-b4c0-4876-841c-26bfb960da8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40567
75601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.4056775601
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2962021606
Short name T954
Test name
Test status
Simulation time 8386314049 ps
CPU time 8.42 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204116 kb
Host smart-82dff243-534b-4b7f-bb82-8843ed4d23fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29620
21606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2962021606
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3100983657
Short name T752
Test name
Test status
Simulation time 8444696800 ps
CPU time 8.71 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:48 PM PDT 24
Peak memory 204080 kb
Host smart-a93225bd-dead-495b-bcb1-00c18fb00725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31009
83657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3100983657
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.713801769
Short name T527
Test name
Test status
Simulation time 8410328672 ps
CPU time 8.66 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204016 kb
Host smart-f669680a-c027-4c3d-b135-85647b97c48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71380
1769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.713801769
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1622144470
Short name T801
Test name
Test status
Simulation time 8380705096 ps
CPU time 7.41 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204140 kb
Host smart-32520893-e809-4e85-89a8-558aea9a3e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16221
44470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1622144470
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.798818176
Short name T788
Test name
Test status
Simulation time 8412839506 ps
CPU time 7.92 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:48 PM PDT 24
Peak memory 204136 kb
Host smart-f337f44b-c980-43ee-8b4d-7f82be1b7fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79881
8176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.798818176
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1509639227
Short name T410
Test name
Test status
Simulation time 8449185479 ps
CPU time 8.25 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204060 kb
Host smart-a20d87fe-1e3b-45bf-b6e3-a00477f1a221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
39227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1509639227
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.774951400
Short name T851
Test name
Test status
Simulation time 8378378112 ps
CPU time 7.69 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204132 kb
Host smart-d24b994d-a4bb-4609-bbf1-860519995b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77495
1400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.774951400
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2949833263
Short name T613
Test name
Test status
Simulation time 172613720 ps
CPU time 0.84 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:41 PM PDT 24
Peak memory 204020 kb
Host smart-f4b6fde3-2a08-4bc0-8314-48c031a250d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
33263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2949833263
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.896066563
Short name T254
Test name
Test status
Simulation time 26803510232 ps
CPU time 50.92 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:46:30 PM PDT 24
Peak memory 204404 kb
Host smart-bd270bd7-f3ff-4266-b8a5-b8255fe93722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89606
6563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.896066563
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.443603265
Short name T544
Test name
Test status
Simulation time 8408930502 ps
CPU time 8.02 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204104 kb
Host smart-bb1356d4-4abe-47f7-9912-689106376cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44360
3265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.443603265
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3747681079
Short name T413
Test name
Test status
Simulation time 8396582528 ps
CPU time 7.75 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204116 kb
Host smart-4a849f27-ba2b-4b9c-a41d-b8481155cf54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37476
81079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3747681079
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2666755665
Short name T318
Test name
Test status
Simulation time 8378908412 ps
CPU time 8.63 seconds
Started May 02 03:45:38 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204136 kb
Host smart-a700bd0c-837f-425e-8c20-f20c47acd3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
55665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2666755665
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.650359855
Short name T535
Test name
Test status
Simulation time 8386458136 ps
CPU time 7.91 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:43 PM PDT 24
Peak memory 204092 kb
Host smart-86367fbe-9b70-4683-a663-0b62c03b92b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65035
9855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.650359855
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.4087225055
Short name T354
Test name
Test status
Simulation time 8382273053 ps
CPU time 7.74 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204112 kb
Host smart-94383625-3429-482a-bc6e-bb91740451f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40872
25055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.4087225055
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2140822510
Short name T306
Test name
Test status
Simulation time 8408420480 ps
CPU time 8.24 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:43 PM PDT 24
Peak memory 204076 kb
Host smart-85b44183-b5e2-4450-81c7-25d41cfff238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21408
22510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2140822510
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1026946801
Short name T739
Test name
Test status
Simulation time 8399536519 ps
CPU time 8.22 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204108 kb
Host smart-31148789-e1c6-4ef5-a597-688658858b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10269
46801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1026946801
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.501643438
Short name T525
Test name
Test status
Simulation time 8464104558 ps
CPU time 8.46 seconds
Started May 02 03:45:40 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204136 kb
Host smart-76b4272e-95e2-43e7-bc05-18a3c2af5324
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=501643438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.501643438
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.387236555
Short name T310
Test name
Test status
Simulation time 8379210425 ps
CPU time 9.28 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204088 kb
Host smart-a29da10d-94c6-4d9e-8088-b4b11ff90498
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=387236555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.387236555
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1819535021
Short name T719
Test name
Test status
Simulation time 8467759165 ps
CPU time 8.09 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204096 kb
Host smart-f190c483-6636-4c3d-8b2a-e20d62d21538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
35021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1819535021
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.824027595
Short name T922
Test name
Test status
Simulation time 8374840622 ps
CPU time 9.55 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204136 kb
Host smart-7d21d3f3-dfa1-44af-a349-20c1cd724a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82402
7595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.824027595
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.3661244131
Short name T1108
Test name
Test status
Simulation time 8378530646 ps
CPU time 9.13 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204128 kb
Host smart-d272dd30-b518-4fdc-b967-96f5e7c2a792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36612
44131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3661244131
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.655844458
Short name T1231
Test name
Test status
Simulation time 178298605 ps
CPU time 2.16 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:42 PM PDT 24
Peak memory 204204 kb
Host smart-12350b8c-3733-40e2-8ae7-04ce4da4d9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65584
4458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.655844458
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3646172199
Short name T972
Test name
Test status
Simulation time 8390114453 ps
CPU time 7.89 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204152 kb
Host smart-1ddf11b8-cf1e-442e-b400-edff3f2b59ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
72199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3646172199
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.348156225
Short name T874
Test name
Test status
Simulation time 8379088203 ps
CPU time 7.46 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204128 kb
Host smart-8ddc7ec7-3326-49b1-ad08-9f3d478eb048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34815
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.348156225
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2141561969
Short name T550
Test name
Test status
Simulation time 8443474763 ps
CPU time 7.76 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204124 kb
Host smart-376aff63-7b19-40ed-9d5a-fc597017eb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21415
61969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2141561969
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.409951137
Short name T755
Test name
Test status
Simulation time 8375867838 ps
CPU time 8.35 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204132 kb
Host smart-485b3164-a1f5-4571-bbe9-02d82ba08d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40995
1137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.409951137
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3210777739
Short name T908
Test name
Test status
Simulation time 8406509179 ps
CPU time 7.72 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204124 kb
Host smart-26ed7dc9-c69a-4610-828f-bf5903b9c98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32107
77739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3210777739
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1302679915
Short name T706
Test name
Test status
Simulation time 8413698205 ps
CPU time 8.74 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204136 kb
Host smart-daa81d36-a361-4dc1-ae08-6975c8d43b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13026
79915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1302679915
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1148327212
Short name T23
Test name
Test status
Simulation time 8366989858 ps
CPU time 7.56 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204136 kb
Host smart-be779bef-ab00-40a9-b9e1-c88d29376857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
27212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1148327212
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3465603499
Short name T742
Test name
Test status
Simulation time 50303587 ps
CPU time 0.66 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:37 PM PDT 24
Peak memory 204036 kb
Host smart-16674536-1033-43da-ab0c-269ae6cc3003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656
03499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3465603499
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.4280449790
Short name T847
Test name
Test status
Simulation time 14924092797 ps
CPU time 27.28 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:46:03 PM PDT 24
Peak memory 204356 kb
Host smart-4897d07d-0798-413a-b48e-d6f104d9a119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42804
49790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.4280449790
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2412279819
Short name T1376
Test name
Test status
Simulation time 8409555059 ps
CPU time 8.41 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:48 PM PDT 24
Peak memory 204128 kb
Host smart-eeade066-dc11-4cf7-94fa-02ad971723a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24122
79819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2412279819
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2288712872
Short name T322
Test name
Test status
Simulation time 8426226413 ps
CPU time 7.47 seconds
Started May 02 03:45:34 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204060 kb
Host smart-06ecaaba-57dd-401d-811d-980cc820563d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
12872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2288712872
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1615714226
Short name T562
Test name
Test status
Simulation time 8407580824 ps
CPU time 7.97 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204084 kb
Host smart-5056f396-f9b6-426a-a37e-24117135b9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16157
14226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1615714226
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4082421499
Short name T1177
Test name
Test status
Simulation time 8384585727 ps
CPU time 10.35 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204076 kb
Host smart-b5a8ea26-29de-4033-8175-6c239217718d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40824
21499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4082421499
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.378617621
Short name T1307
Test name
Test status
Simulation time 8367151291 ps
CPU time 8.31 seconds
Started May 02 03:45:39 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204128 kb
Host smart-aaa46a88-62c2-4275-939c-d8a7cebf70a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
7621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.378617621
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1772632742
Short name T603
Test name
Test status
Simulation time 8452980248 ps
CPU time 9.25 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204112 kb
Host smart-edcd7090-08ec-4cb7-b558-881c48cbfb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
32742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1772632742
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.996443836
Short name T753
Test name
Test status
Simulation time 8416220578 ps
CPU time 7.74 seconds
Started May 02 03:45:33 PM PDT 24
Finished May 02 03:45:42 PM PDT 24
Peak memory 204072 kb
Host smart-c6074ce0-040f-4872-822a-e783e1cc631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99644
3836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.996443836
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.952249958
Short name T1107
Test name
Test status
Simulation time 8381192266 ps
CPU time 7.48 seconds
Started May 02 03:45:40 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204072 kb
Host smart-c3c49ffc-1cd3-4399-a66f-89467cd745a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95224
9958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.952249958
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.3460445800
Short name T504
Test name
Test status
Simulation time 8490923118 ps
CPU time 8.08 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204128 kb
Host smart-7744efef-48e3-4990-b512-8cbeb8dacf0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3460445800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.3460445800
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.1974499622
Short name T449
Test name
Test status
Simulation time 8394015741 ps
CPU time 9.84 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:52 PM PDT 24
Peak memory 204076 kb
Host smart-129add58-ab4f-49eb-904a-742e7911eca8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1974499622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.1974499622
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.3970543291
Short name T1341
Test name
Test status
Simulation time 8420108484 ps
CPU time 8.22 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204124 kb
Host smart-383446a3-bd21-4d7e-98b2-9033966ad527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
43291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.3970543291
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.527105949
Short name T1347
Test name
Test status
Simulation time 8401744496 ps
CPU time 8 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204128 kb
Host smart-32d5b020-6171-497a-a79c-9c4a33db5453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52710
5949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.527105949
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.3613519454
Short name T907
Test name
Test status
Simulation time 8404915030 ps
CPU time 7.87 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204128 kb
Host smart-d2976727-c1a6-499f-9192-1a5fa51572fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36135
19454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3613519454
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3601557012
Short name T465
Test name
Test status
Simulation time 72568941 ps
CPU time 1.32 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204132 kb
Host smart-8ee4c0f4-9b17-4d21-b64f-b9b8211e5855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36015
57012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3601557012
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3183476661
Short name T580
Test name
Test status
Simulation time 8382127118 ps
CPU time 9.68 seconds
Started May 02 03:45:43 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204112 kb
Host smart-19504139-0e69-4c3e-a818-b5e4d9fbf276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31834
76661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3183476661
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2970882124
Short name T192
Test name
Test status
Simulation time 8368356207 ps
CPU time 7.63 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204020 kb
Host smart-a9168ea8-bfed-4a9b-9a3c-189b89d56554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29708
82124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2970882124
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2168044425
Short name T543
Test name
Test status
Simulation time 8404037704 ps
CPU time 8.47 seconds
Started May 02 03:45:45 PM PDT 24
Finished May 02 03:45:55 PM PDT 24
Peak memory 204136 kb
Host smart-830b30cd-def8-4f23-b4f4-505a95e88ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21680
44425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2168044425
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3402946235
Short name T826
Test name
Test status
Simulation time 8442842541 ps
CPU time 8.24 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204128 kb
Host smart-f7972602-dd30-4cc6-8018-0b06adfc98c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34029
46235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3402946235
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1834089840
Short name T1050
Test name
Test status
Simulation time 8374128913 ps
CPU time 7.63 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204120 kb
Host smart-a2db97c8-b6e2-4e88-a2b5-8065485e2def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
89840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1834089840
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2053587702
Short name T106
Test name
Test status
Simulation time 8424899907 ps
CPU time 9.75 seconds
Started May 02 03:45:37 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204136 kb
Host smart-d8a6ede2-6de3-4745-bce7-0d9f0b57ca54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20535
87702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2053587702
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3370090372
Short name T1032
Test name
Test status
Simulation time 8442668775 ps
CPU time 7.49 seconds
Started May 02 03:45:35 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204128 kb
Host smart-eecc436b-9ccc-4d4d-b404-10404280f2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33700
90372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3370090372
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2122419570
Short name T778
Test name
Test status
Simulation time 8409614689 ps
CPU time 7.72 seconds
Started May 02 03:45:40 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204128 kb
Host smart-84f820d7-f9c1-477b-a241-0415c250b031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21224
19570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2122419570
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3797828982
Short name T96
Test name
Test status
Simulation time 8400106927 ps
CPU time 7.82 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204116 kb
Host smart-2329c8bd-9670-43c7-85bd-b3fa39acf892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
28982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3797828982
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.171359701
Short name T10
Test name
Test status
Simulation time 8374465864 ps
CPU time 8.31 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204128 kb
Host smart-747455a1-80a9-4e43-bc0a-7f6b9e418d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17135
9701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.171359701
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1768795843
Short name T389
Test name
Test status
Simulation time 48819933 ps
CPU time 0.64 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 203996 kb
Host smart-3afe3cc9-d431-4614-9587-914fe0c58768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17687
95843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1768795843
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2042214369
Short name T1297
Test name
Test status
Simulation time 17414582818 ps
CPU time 33.53 seconds
Started May 02 03:45:45 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204420 kb
Host smart-36c7995a-141c-42d4-91af-6e81b933a418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20422
14369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2042214369
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.431234997
Short name T654
Test name
Test status
Simulation time 8406570192 ps
CPU time 7.72 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204020 kb
Host smart-2cace232-3ac5-43e8-b24b-8d7be312f8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43123
4997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.431234997
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1322122866
Short name T1193
Test name
Test status
Simulation time 8386125623 ps
CPU time 9.62 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:55 PM PDT 24
Peak memory 204140 kb
Host smart-fb0894e0-2676-48fb-8687-38bf1a54221b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13221
22866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1322122866
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3047648576
Short name T1201
Test name
Test status
Simulation time 8397805975 ps
CPU time 9.9 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204104 kb
Host smart-b523b5ff-11ba-4036-9a22-f909f2e66878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476
48576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3047648576
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1026854226
Short name T540
Test name
Test status
Simulation time 8376374419 ps
CPU time 8.66 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204128 kb
Host smart-7522f472-38b1-4835-a37f-bfa7ad27572c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10268
54226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1026854226
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.578731514
Short name T584
Test name
Test status
Simulation time 8366419676 ps
CPU time 7.6 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204052 kb
Host smart-5f180dd2-cfc3-4eaf-8a5f-510bd59307c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57873
1514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.578731514
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4021625579
Short name T1314
Test name
Test status
Simulation time 8406471914 ps
CPU time 7.75 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204028 kb
Host smart-a074fc96-ca55-47d3-a7a2-6f4ac2317e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40216
25579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4021625579
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.698349626
Short name T554
Test name
Test status
Simulation time 8402025542 ps
CPU time 8.07 seconds
Started May 02 03:45:45 PM PDT 24
Finished May 02 03:45:55 PM PDT 24
Peak memory 204124 kb
Host smart-7c49413f-2454-40b2-bbb7-e21a33866017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69834
9626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.698349626
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.149886251
Short name T384
Test name
Test status
Simulation time 8397627837 ps
CPU time 9.81 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:49 PM PDT 24
Peak memory 204140 kb
Host smart-e501f8c9-e4fe-4e99-9e07-52265dd90103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14988
6251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.149886251
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.7767052
Short name T925
Test name
Test status
Simulation time 8462977602 ps
CPU time 8.83 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204084 kb
Host smart-bce0fad9-8bb7-439b-a9a8-a45edd5eb18d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=7767052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.7767052
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.4245460857
Short name T446
Test name
Test status
Simulation time 8380372551 ps
CPU time 8.22 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:53 PM PDT 24
Peak memory 204076 kb
Host smart-5d0a570b-7212-4446-afdf-f9d9238e27ca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4245460857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.4245460857
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.3014348412
Short name T633
Test name
Test status
Simulation time 8390919676 ps
CPU time 7.54 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 204056 kb
Host smart-f967bdd7-35e3-4e63-8481-b5b3b2bd5b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143
48412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.3014348412
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.4169308339
Short name T1169
Test name
Test status
Simulation time 8401728292 ps
CPU time 7.91 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204140 kb
Host smart-73f00ffd-631c-4e6e-8af1-b72a0760cd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693
08339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.4169308339
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.2858273345
Short name T545
Test name
Test status
Simulation time 8376183121 ps
CPU time 7.42 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 204072 kb
Host smart-beb1bf60-3c76-4448-bc0a-d11eb9dfe6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28582
73345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2858273345
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1944167361
Short name T1011
Test name
Test status
Simulation time 111527441 ps
CPU time 1.37 seconds
Started May 02 03:45:40 PM PDT 24
Finished May 02 03:45:43 PM PDT 24
Peak memory 204188 kb
Host smart-845802cc-3991-46dc-aff5-9504f259744d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19441
67361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1944167361
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3785052238
Short name T45
Test name
Test status
Simulation time 8459696845 ps
CPU time 7.94 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:59 PM PDT 24
Peak memory 204048 kb
Host smart-76e601c1-ab8b-42ba-ac04-dd9028009414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
52238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3785052238
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1895848533
Short name T203
Test name
Test status
Simulation time 8364188043 ps
CPU time 7.66 seconds
Started May 02 03:45:43 PM PDT 24
Finished May 02 03:45:52 PM PDT 24
Peak memory 204156 kb
Host smart-dbdc72c7-fdc5-4beb-844c-14ac65864bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18958
48533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1895848533
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.845341019
Short name T134
Test name
Test status
Simulation time 8434707247 ps
CPU time 7.85 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:53 PM PDT 24
Peak memory 204132 kb
Host smart-70c660a8-5eb9-4239-acf4-201798c33f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84534
1019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.845341019
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2329130782
Short name T997
Test name
Test status
Simulation time 8424052241 ps
CPU time 8.48 seconds
Started May 02 03:45:36 PM PDT 24
Finished May 02 03:45:47 PM PDT 24
Peak memory 204100 kb
Host smart-df8b5f92-2c3e-4b1f-a1c4-f5f6e06d946c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23291
30782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2329130782
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.644560845
Short name T949
Test name
Test status
Simulation time 8373294280 ps
CPU time 7.43 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:52 PM PDT 24
Peak memory 204124 kb
Host smart-df488eff-28e0-47fd-bc10-4c1283f85a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64456
0845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.644560845
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2625550626
Short name T1261
Test name
Test status
Simulation time 8394504774 ps
CPU time 9.78 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204068 kb
Host smart-6697c24b-fe99-4ed2-b876-081f92f73f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
50626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2625550626
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2792918685
Short name T754
Test name
Test status
Simulation time 8408094939 ps
CPU time 7.55 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204116 kb
Host smart-c467b6cd-b404-408d-b916-7255d8f9b4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27929
18685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2792918685
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2025267068
Short name T658
Test name
Test status
Simulation time 8406090704 ps
CPU time 8.16 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204044 kb
Host smart-55235544-9889-4504-868e-6fd3e37c2ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252
67068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2025267068
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2068614873
Short name T751
Test name
Test status
Simulation time 8376585340 ps
CPU time 8.34 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204112 kb
Host smart-17cdd776-aa86-4d66-a80c-7f4decf132b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20686
14873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2068614873
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1182858920
Short name T1264
Test name
Test status
Simulation time 8384676627 ps
CPU time 8.14 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204084 kb
Host smart-14ba4fec-d034-4b08-9e84-d72810fdd93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828
58920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1182858920
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.656506718
Short name T861
Test name
Test status
Simulation time 37082681 ps
CPU time 0.65 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:46 PM PDT 24
Peak memory 203988 kb
Host smart-6b8cc79b-ca38-42ab-9606-d8517e5d4180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65650
6718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.656506718
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.76478338
Short name T998
Test name
Test status
Simulation time 25665682131 ps
CPU time 49.41 seconds
Started May 02 03:45:46 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204344 kb
Host smart-71fedf23-4ee4-45f6-a7eb-fc0839ade34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76478
338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.76478338
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.925192897
Short name T433
Test name
Test status
Simulation time 8430719702 ps
CPU time 8.1 seconds
Started May 02 03:45:40 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204016 kb
Host smart-b3ba2b7b-f72c-43a7-9742-3f3978ee6b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92519
2897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.925192897
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2473573266
Short name T464
Test name
Test status
Simulation time 8408778080 ps
CPU time 8.37 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204124 kb
Host smart-a0d61b9f-9fa2-4332-97e2-c53a74ee6675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24735
73266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2473573266
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.4092416420
Short name T561
Test name
Test status
Simulation time 8407569122 ps
CPU time 8.89 seconds
Started May 02 03:45:46 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 204044 kb
Host smart-1afdff27-bd6d-4bce-a384-457bdbb1925c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
16420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.4092416420
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1610146991
Short name T170
Test name
Test status
Simulation time 8393034940 ps
CPU time 8.45 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:52 PM PDT 24
Peak memory 204072 kb
Host smart-72f38cda-bb23-42a7-9ab3-7434084750b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
46991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1610146991
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1146181879
Short name T401
Test name
Test status
Simulation time 8364286441 ps
CPU time 7.9 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204108 kb
Host smart-92ae7ba9-8550-4f10-a656-74ee337edd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461
81879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1146181879
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2987065678
Short name T686
Test name
Test status
Simulation time 8451273088 ps
CPU time 7.9 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:53 PM PDT 24
Peak memory 204068 kb
Host smart-1f244d38-a86d-47c8-bb82-46a7aa3784c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29870
65678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2987065678
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.479924570
Short name T546
Test name
Test status
Simulation time 8382832979 ps
CPU time 7.29 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:45:59 PM PDT 24
Peak memory 204040 kb
Host smart-1afdb687-a78c-4a42-ac98-10d8b5dbca49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47992
4570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.479924570
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3563174426
Short name T1283
Test name
Test status
Simulation time 8532279178 ps
CPU time 8.23 seconds
Started May 02 03:45:46 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 204096 kb
Host smart-b96c2691-9218-4a8c-8440-0c9540b895d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3563174426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3563174426
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2028952849
Short name T1289
Test name
Test status
Simulation time 8392844404 ps
CPU time 7.85 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204112 kb
Host smart-e9fb1a7f-55e4-4e82-80ee-524f55c67f0a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2028952849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2028952849
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.3596811374
Short name T328
Test name
Test status
Simulation time 8419311745 ps
CPU time 7.72 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204112 kb
Host smart-c1a03a36-faa6-4750-a520-47309b1c6d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35968
11374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.3596811374
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2889886107
Short name T730
Test name
Test status
Simulation time 8370406675 ps
CPU time 7.69 seconds
Started May 02 03:45:46 PM PDT 24
Finished May 02 03:45:55 PM PDT 24
Peak memory 204068 kb
Host smart-094f984a-a979-4f04-aa85-7ee897bd9c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
86107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2889886107
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.369885012
Short name T94
Test name
Test status
Simulation time 8373125197 ps
CPU time 7.76 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204112 kb
Host smart-f55a7f40-7e9f-42db-be47-e4729e4175f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36988
5012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.369885012
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4283751296
Short name T1047
Test name
Test status
Simulation time 143518320 ps
CPU time 1.59 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:53 PM PDT 24
Peak memory 204264 kb
Host smart-7d125524-5e40-4700-ae3f-3c121c4bb033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42837
51296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4283751296
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.927220322
Short name T1313
Test name
Test status
Simulation time 8428404015 ps
CPU time 7.54 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:45:59 PM PDT 24
Peak memory 204044 kb
Host smart-502e7a1d-2f00-4d16-93b8-4e315f58af6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92722
0322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.927220322
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1152400459
Short name T964
Test name
Test status
Simulation time 8368914701 ps
CPU time 8.07 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204040 kb
Host smart-d68a8233-99bd-48b9-a0f5-59fb467acf1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524
00459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1152400459
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.456026799
Short name T947
Test name
Test status
Simulation time 8452864138 ps
CPU time 8.22 seconds
Started May 02 03:45:43 PM PDT 24
Finished May 02 03:45:53 PM PDT 24
Peak memory 204128 kb
Host smart-65c43749-7d38-4450-a0c8-1ac89e875774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45602
6799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.456026799
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3971865697
Short name T1005
Test name
Test status
Simulation time 8414210703 ps
CPU time 9 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204116 kb
Host smart-a12ce1e7-d717-412b-82c1-68d5b50edaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
65697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3971865697
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1531109463
Short name T1154
Test name
Test status
Simulation time 8370467371 ps
CPU time 9.63 seconds
Started May 02 03:45:45 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 204116 kb
Host smart-115281ee-4bf6-4e3b-b7b8-e77ab42230a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15311
09463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1531109463
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3443645133
Short name T834
Test name
Test status
Simulation time 8383124888 ps
CPU time 8.51 seconds
Started May 02 03:45:56 PM PDT 24
Finished May 02 03:46:06 PM PDT 24
Peak memory 204124 kb
Host smart-d8c90a37-421e-416c-a6f3-dcaa58f7d37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34436
45133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3443645133
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3361389470
Short name T758
Test name
Test status
Simulation time 8379771520 ps
CPU time 8.18 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204060 kb
Host smart-efe999f2-6811-41fb-8ba1-8c6a469a0c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613
89470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3361389470
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1941860356
Short name T194
Test name
Test status
Simulation time 8453346461 ps
CPU time 7.49 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 204136 kb
Host smart-f6c15b5a-f826-4ede-b528-3032abb09e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19418
60356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1941860356
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3702119900
Short name T856
Test name
Test status
Simulation time 8369724294 ps
CPU time 7.69 seconds
Started May 02 03:45:41 PM PDT 24
Finished May 02 03:45:50 PM PDT 24
Peak memory 204092 kb
Host smart-5bd38910-3a8b-4b50-8c9e-9a0e77712c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021
19900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3702119900
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2841300432
Short name T52
Test name
Test status
Simulation time 111193508 ps
CPU time 0.72 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:52 PM PDT 24
Peak memory 203992 kb
Host smart-098b2ba0-4231-4880-8d9a-0080df99edd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28413
00432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2841300432
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1365020067
Short name T1280
Test name
Test status
Simulation time 14960696702 ps
CPU time 25.22 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204376 kb
Host smart-ce2ccab4-b540-4b80-99f2-1f36cc42934d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13650
20067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1365020067
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1882658776
Short name T1266
Test name
Test status
Simulation time 8394363583 ps
CPU time 7.64 seconds
Started May 02 03:45:43 PM PDT 24
Finished May 02 03:45:52 PM PDT 24
Peak memory 204128 kb
Host smart-a66ce225-8383-4828-b7e1-8666f802d7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18826
58776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1882658776
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2617959907
Short name T42
Test name
Test status
Simulation time 8411122818 ps
CPU time 7.84 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:57 PM PDT 24
Peak memory 204140 kb
Host smart-cb3d7cc2-fffb-4fb6-8f31-844959f547a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
59907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2617959907
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.572097464
Short name T1163
Test name
Test status
Simulation time 8386384605 ps
CPU time 8.13 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:57 PM PDT 24
Peak memory 204136 kb
Host smart-dc0044e8-d04a-4dad-8ea6-38c34906df33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57209
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.572097464
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1818758233
Short name T1071
Test name
Test status
Simulation time 8380099689 ps
CPU time 7.79 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204048 kb
Host smart-cb7c79c3-c969-44f6-a3ea-e9ca0da4f834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18187
58233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1818758233
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1720615700
Short name T926
Test name
Test status
Simulation time 8378582675 ps
CPU time 7.84 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204048 kb
Host smart-1f1aa25e-1446-4a9e-b54a-268267889d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
15700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1720615700
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2899996616
Short name T589
Test name
Test status
Simulation time 8407945444 ps
CPU time 9.22 seconds
Started May 02 03:45:44 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 204128 kb
Host smart-27d52b52-ba63-4c39-92ba-0a6392a860f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999
96616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2899996616
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2020563363
Short name T1159
Test name
Test status
Simulation time 8514921334 ps
CPU time 8.67 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204100 kb
Host smart-e187d72a-1075-400a-b562-deabcb597da1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2020563363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2020563363
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1521656397
Short name T427
Test name
Test status
Simulation time 8377808095 ps
CPU time 7.57 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204108 kb
Host smart-e047a04c-c02a-497e-ba11-67231e5cda41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1521656397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1521656397
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.2058687783
Short name T667
Test name
Test status
Simulation time 8455948114 ps
CPU time 7.65 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204116 kb
Host smart-1dcccd2e-3db5-451f-a29c-4fe25962cebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
87783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.2058687783
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4100303850
Short name T309
Test name
Test status
Simulation time 8428428995 ps
CPU time 10.46 seconds
Started May 02 03:45:46 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204060 kb
Host smart-7561c2e4-fa49-4688-9184-0fb95fe2597b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41003
03850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4100303850
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.1856590103
Short name T405
Test name
Test status
Simulation time 8388447084 ps
CPU time 8.73 seconds
Started May 02 03:45:43 PM PDT 24
Finished May 02 03:45:53 PM PDT 24
Peak memory 204088 kb
Host smart-a6c2486e-dac1-4a12-9f97-a24ccdb657e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
90103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1856590103
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.272442956
Short name T652
Test name
Test status
Simulation time 50538740 ps
CPU time 1.34 seconds
Started May 02 03:45:42 PM PDT 24
Finished May 02 03:45:45 PM PDT 24
Peak memory 204152 kb
Host smart-35f494a7-d6ef-426c-9c57-a2294ed636d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
2956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.272442956
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3773847765
Short name T204
Test name
Test status
Simulation time 8366816597 ps
CPU time 9.18 seconds
Started May 02 03:45:56 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204148 kb
Host smart-015a72f5-5e63-49ee-91ad-5384ccd9302d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37738
47765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3773847765
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1571838065
Short name T703
Test name
Test status
Simulation time 8452828018 ps
CPU time 7.59 seconds
Started May 02 03:45:46 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 204076 kb
Host smart-23a7e125-41b8-4fb5-8e31-643106feb160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
38065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1571838065
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2243695988
Short name T698
Test name
Test status
Simulation time 8416011223 ps
CPU time 9.97 seconds
Started May 02 03:45:56 PM PDT 24
Finished May 02 03:46:07 PM PDT 24
Peak memory 204120 kb
Host smart-da052dad-aa53-4538-b521-fc2fd7a2f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
95988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2243695988
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3632474526
Short name T85
Test name
Test status
Simulation time 8381889741 ps
CPU time 9.21 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204112 kb
Host smart-0a09c08b-ceab-4294-b79e-34869bc71116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36324
74526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3632474526
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.980620465
Short name T88
Test name
Test status
Simulation time 8400688023 ps
CPU time 8.07 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204068 kb
Host smart-1b700aef-c08a-4a9d-8175-a68a454bc7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98062
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.980620465
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2476919240
Short name T246
Test name
Test status
Simulation time 8391003578 ps
CPU time 9.16 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204132 kb
Host smart-55265a0f-4b46-4d30-81d2-cf8a407a6839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24769
19240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2476919240
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3975098624
Short name T493
Test name
Test status
Simulation time 8385601001 ps
CPU time 7.61 seconds
Started May 02 03:45:51 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204144 kb
Host smart-f49b7e43-73f8-421e-bf00-a21e6aec52ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39750
98624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3975098624
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3555127358
Short name T902
Test name
Test status
Simulation time 100934913 ps
CPU time 0.76 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204024 kb
Host smart-e519a58e-d6df-4647-8b9b-48f98da4bc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
27358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3555127358
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1917938006
Short name T810
Test name
Test status
Simulation time 21285412776 ps
CPU time 48.3 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:40 PM PDT 24
Peak memory 204404 kb
Host smart-bcdc29c0-0296-4b06-867c-72d610edf35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19179
38006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1917938006
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2356412820
Short name T244
Test name
Test status
Simulation time 8399074471 ps
CPU time 7.81 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204080 kb
Host smart-766e80c2-8c57-4042-9708-45359b643dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23564
12820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2356412820
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2542424452
Short name T1222
Test name
Test status
Simulation time 8395387239 ps
CPU time 8.44 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204132 kb
Host smart-0e89e016-8515-4124-8806-2cb71b0e2cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
24452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2542424452
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.244381591
Short name T459
Test name
Test status
Simulation time 8430310300 ps
CPU time 9.52 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204140 kb
Host smart-848d9e60-f53b-4315-a353-b43cae77c5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
1591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.244381591
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3839128802
Short name T336
Test name
Test status
Simulation time 8386119641 ps
CPU time 10.4 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:59 PM PDT 24
Peak memory 204128 kb
Host smart-4572f843-eba2-476b-bf94-957abbee8730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38391
28802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3839128802
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.361109877
Short name T704
Test name
Test status
Simulation time 8368398453 ps
CPU time 10.2 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 203592 kb
Host smart-0ee81d64-fd8d-42c4-86b3-5a0e7b512fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36110
9877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.361109877
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3780875284
Short name T1148
Test name
Test status
Simulation time 8422085151 ps
CPU time 9.13 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204112 kb
Host smart-30ad9d03-9d1c-4314-83b7-97adaf796704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808
75284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3780875284
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2426387399
Short name T1291
Test name
Test status
Simulation time 8404069802 ps
CPU time 9.67 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204148 kb
Host smart-3cabb9b4-c718-444c-b126-af1b2494f988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24263
87399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2426387399
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2738663284
Short name T86
Test name
Test status
Simulation time 8408992505 ps
CPU time 8.77 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:02 PM PDT 24
Peak memory 204168 kb
Host smart-a9789feb-e1b1-4965-86ac-044a60121e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27386
63284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2738663284
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2582674196
Short name T1248
Test name
Test status
Simulation time 8468259815 ps
CPU time 9.15 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204148 kb
Host smart-58c60a10-a781-4cfa-ad77-d139e0c6efca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2582674196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2582674196
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.1240864535
Short name T249
Test name
Test status
Simulation time 8392781899 ps
CPU time 8.27 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204148 kb
Host smart-e7df7644-1b19-42bc-be07-f3ee4442e342
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1240864535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.1240864535
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.317432422
Short name T1187
Test name
Test status
Simulation time 8394475892 ps
CPU time 8.13 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204056 kb
Host smart-9d3cd51a-fa2c-4f77-afba-4bceafa7e112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
2422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.317432422
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_enable.2919626770
Short name T582
Test name
Test status
Simulation time 8370691073 ps
CPU time 8.25 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204076 kb
Host smart-0f8ce0c5-386d-4559-a858-0f2ae0ab5410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29196
26770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2919626770
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2338371152
Short name T903
Test name
Test status
Simulation time 109558313 ps
CPU time 1.26 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204232 kb
Host smart-899f44e7-18f7-41b5-8905-fe80d20f13aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23383
71152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2338371152
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3859479925
Short name T1351
Test name
Test status
Simulation time 8446975800 ps
CPU time 8.98 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204088 kb
Host smart-fafc71b1-f262-4c35-9f04-b09169c7b04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
79925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3859479925
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2678824657
Short name T1192
Test name
Test status
Simulation time 8440329765 ps
CPU time 7.96 seconds
Started May 02 03:45:51 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204072 kb
Host smart-b36d73f0-e468-451e-94ef-2c4e53b90293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26788
24657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2678824657
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2569665164
Short name T1142
Test name
Test status
Simulation time 8429179553 ps
CPU time 8.78 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204132 kb
Host smart-1403e89e-d95a-4b8e-94c2-cf3694f50914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
65164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2569665164
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2419184819
Short name T1232
Test name
Test status
Simulation time 8371001515 ps
CPU time 10.88 seconds
Started May 02 03:45:50 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204048 kb
Host smart-db6d8e14-8d54-44bf-96f7-43f73f1d99d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24191
84819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2419184819
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2110881886
Short name T1214
Test name
Test status
Simulation time 8418030765 ps
CPU time 8.45 seconds
Started May 02 03:45:48 PM PDT 24
Finished May 02 03:45:59 PM PDT 24
Peak memory 203528 kb
Host smart-a402e79a-414e-477b-8b99-81879c128c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
81886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2110881886
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2494740683
Short name T1259
Test name
Test status
Simulation time 8396360283 ps
CPU time 9.95 seconds
Started May 02 03:45:49 PM PDT 24
Finished May 02 03:46:02 PM PDT 24
Peak memory 204104 kb
Host smart-080a8a32-da07-4cef-84bc-183ee8fb8479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
40683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2494740683
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3482856744
Short name T717
Test name
Test status
Simulation time 8364655591 ps
CPU time 9.66 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:03 PM PDT 24
Peak memory 204140 kb
Host smart-4bbcb975-9a24-41a1-ba9d-6129b5c1f6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34828
56744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3482856744
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2904343587
Short name T760
Test name
Test status
Simulation time 41872324 ps
CPU time 0.66 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:45:54 PM PDT 24
Peak memory 203964 kb
Host smart-7bfd51d1-5f43-409a-a832-d45439c47411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
43587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2904343587
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3593931606
Short name T255
Test name
Test status
Simulation time 14635094319 ps
CPU time 29.44 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204420 kb
Host smart-c8a56548-6644-428d-87d7-f9d0c3b8ff76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35939
31606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3593931606
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4138238029
Short name T89
Test name
Test status
Simulation time 8373821634 ps
CPU time 8.14 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204164 kb
Host smart-0c020cef-05b8-4429-a75e-f66090c0884b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
38029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4138238029
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.400771339
Short name T131
Test name
Test status
Simulation time 8477416681 ps
CPU time 9.21 seconds
Started May 02 03:45:53 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204088 kb
Host smart-e8bc9820-2721-46d2-8074-9cc37b45bc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.400771339
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1190443801
Short name T516
Test name
Test status
Simulation time 8409751134 ps
CPU time 8.52 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204148 kb
Host smart-8f4e8cb1-06e8-421d-9605-22ba6d3f6be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11904
43801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1190443801
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3073162371
Short name T166
Test name
Test status
Simulation time 8373636423 ps
CPU time 9.62 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:05 PM PDT 24
Peak memory 204096 kb
Host smart-2fb40e06-24f8-4c3a-9399-cbf376ef63ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30731
62371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3073162371
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2181468795
Short name T470
Test name
Test status
Simulation time 8366850451 ps
CPU time 8.38 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:57 PM PDT 24
Peak memory 204068 kb
Host smart-637ec148-7c0c-4f82-816f-ac7ed8968e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21814
68795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2181468795
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2575083413
Short name T172
Test name
Test status
Simulation time 8429825478 ps
CPU time 8.08 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:02 PM PDT 24
Peak memory 204128 kb
Host smart-654896eb-d750-4127-af65-68b96e6de879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
83413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2575083413
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3523632458
Short name T474
Test name
Test status
Simulation time 8417043409 ps
CPU time 7.81 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:03 PM PDT 24
Peak memory 204096 kb
Host smart-f0b10361-641a-4e3d-8c6e-7ada3b29e996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35236
32458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3523632458
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1957109244
Short name T1172
Test name
Test status
Simulation time 8454871874 ps
CPU time 10.06 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204132 kb
Host smart-1cd4b16e-de31-4eaf-9c45-4d049482cefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19571
09244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1957109244
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.618757694
Short name T549
Test name
Test status
Simulation time 8542225614 ps
CPU time 10.87 seconds
Started May 02 03:46:00 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204160 kb
Host smart-2d9d5aed-69b7-42f6-b27d-8a4d3f75b04e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=618757694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.618757694
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2567579491
Short name T1081
Test name
Test status
Simulation time 8373449157 ps
CPU time 8.26 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:11 PM PDT 24
Peak memory 204144 kb
Host smart-7e8fa084-18bd-4733-bf1e-3d063a4bdc2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2567579491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2567579491
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.179318092
Short name T315
Test name
Test status
Simulation time 8418065969 ps
CPU time 7.69 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204084 kb
Host smart-0cfd0aa7-db50-4747-b3d5-df5d10033edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17931
8092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.179318092
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.500959209
Short name T1334
Test name
Test status
Simulation time 8376146333 ps
CPU time 7.56 seconds
Started May 02 03:45:53 PM PDT 24
Finished May 02 03:46:02 PM PDT 24
Peak memory 204136 kb
Host smart-ff331c06-a10a-4829-a4a8-c34c010b33b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50095
9209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.500959209
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.2684334898
Short name T494
Test name
Test status
Simulation time 8375133216 ps
CPU time 9.72 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:05 PM PDT 24
Peak memory 204076 kb
Host smart-bc5588a5-5dd2-419d-8169-a6eaa3841fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26843
34898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2684334898
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1803168875
Short name T890
Test name
Test status
Simulation time 77519905 ps
CPU time 1.03 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204184 kb
Host smart-bb54a1bd-0710-4220-9ec6-e96b3a5836bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
68875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1803168875
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3300163443
Short name T147
Test name
Test status
Simulation time 8376299302 ps
CPU time 7.35 seconds
Started May 02 03:45:51 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 204080 kb
Host smart-9f285337-9eb0-4074-a982-1877fffebc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33001
63443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3300163443
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1103649709
Short name T610
Test name
Test status
Simulation time 8366994745 ps
CPU time 8.2 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204132 kb
Host smart-e31bc757-f924-4b5d-8264-adf2343ada30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036
49709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1103649709
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1625653156
Short name T1226
Test name
Test status
Simulation time 8396496078 ps
CPU time 8.49 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:07 PM PDT 24
Peak memory 204076 kb
Host smart-0c4e82ec-cbae-4585-92f2-a3a0830db4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
53156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1625653156
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1862937091
Short name T555
Test name
Test status
Simulation time 8448076015 ps
CPU time 8.93 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:03 PM PDT 24
Peak memory 204092 kb
Host smart-bdea2778-099c-4d44-be21-07c528ba43d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18629
37091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1862937091
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3370263694
Short name T560
Test name
Test status
Simulation time 8374696474 ps
CPU time 7.96 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:46:05 PM PDT 24
Peak memory 204100 kb
Host smart-620e1b7b-3e07-4df3-8881-12a9e5d6f029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33702
63694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3370263694
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3237710628
Short name T1339
Test name
Test status
Simulation time 8389900622 ps
CPU time 7.62 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204112 kb
Host smart-a511c272-7163-410d-a666-22308b74a992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32377
10628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3237710628
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2615146755
Short name T1049
Test name
Test status
Simulation time 8402089195 ps
CPU time 8.07 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:46:05 PM PDT 24
Peak memory 204100 kb
Host smart-579670fc-060e-40b8-95d0-dd7540c28ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26151
46755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2615146755
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.256203736
Short name T673
Test name
Test status
Simulation time 8396198390 ps
CPU time 8.3 seconds
Started May 02 03:45:55 PM PDT 24
Finished May 02 03:46:05 PM PDT 24
Peak memory 204068 kb
Host smart-dd4cd853-2edb-44bc-9cb5-f7c3c2f11686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
3736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.256203736
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2455171471
Short name T24
Test name
Test status
Simulation time 8381941611 ps
CPU time 7.75 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:03 PM PDT 24
Peak memory 204116 kb
Host smart-0036a24f-eb75-4b3b-ad49-7249171ac8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24551
71471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2455171471
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3850303181
Short name T770
Test name
Test status
Simulation time 50438877 ps
CPU time 0.67 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:45:56 PM PDT 24
Peak memory 203996 kb
Host smart-5f660377-5a08-44fa-8f20-a3341b454629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
03181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3850303181
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3345897652
Short name T629
Test name
Test status
Simulation time 13838982350 ps
CPU time 27.06 seconds
Started May 02 03:45:56 PM PDT 24
Finished May 02 03:46:25 PM PDT 24
Peak memory 204456 kb
Host smart-34826925-6937-4471-b01a-34342b02e15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
97652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3345897652
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.823922535
Short name T1203
Test name
Test status
Simulation time 8383956365 ps
CPU time 7.69 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:12 PM PDT 24
Peak memory 204132 kb
Host smart-fe2aad16-ce66-49c7-9b1e-e20ab6e03f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82392
2535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.823922535
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.642648476
Short name T1207
Test name
Test status
Simulation time 8380820322 ps
CPU time 8.26 seconds
Started May 02 03:46:02 PM PDT 24
Finished May 02 03:46:12 PM PDT 24
Peak memory 204052 kb
Host smart-31c0e0e6-8af6-45ff-b627-881f393fc789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64264
8476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.642648476
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.312255039
Short name T345
Test name
Test status
Simulation time 8403630039 ps
CPU time 9.13 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:03 PM PDT 24
Peak memory 204140 kb
Host smart-14c787d1-5cd5-4cde-b8ba-dc5b92a87d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31225
5039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.312255039
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2194804050
Short name T842
Test name
Test status
Simulation time 8371473773 ps
CPU time 7.92 seconds
Started May 02 03:45:52 PM PDT 24
Finished May 02 03:46:02 PM PDT 24
Peak memory 204108 kb
Host smart-117e4c53-bac2-46ea-bf61-2aba9bfc3474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21948
04050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2194804050
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1061237970
Short name T883
Test name
Test status
Simulation time 8374342645 ps
CPU time 8.15 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204136 kb
Host smart-2d2ffe77-b56c-437d-a527-87cc584dcaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10612
37970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1061237970
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.248670753
Short name T515
Test name
Test status
Simulation time 8472484344 ps
CPU time 8.37 seconds
Started May 02 03:45:47 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204136 kb
Host smart-b4640903-f5f6-4bd8-acc9-c3b72572fff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24867
0753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.248670753
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.4091711887
Short name T1008
Test name
Test status
Simulation time 8382625002 ps
CPU time 8.01 seconds
Started May 02 03:46:05 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204112 kb
Host smart-cbc866cc-74f8-4816-a745-254322c19edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
11887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.4091711887
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.497229060
Short name T687
Test name
Test status
Simulation time 8422531071 ps
CPU time 8.18 seconds
Started May 02 03:45:56 PM PDT 24
Finished May 02 03:46:06 PM PDT 24
Peak memory 204140 kb
Host smart-f25a57e5-982f-4259-ab08-5c53e7053d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49722
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.497229060
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.79430031
Short name T966
Test name
Test status
Simulation time 8479479732 ps
CPU time 8.25 seconds
Started May 02 03:44:47 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204084 kb
Host smart-8c1c8960-6b8a-423f-960c-9a78ad07d7a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=79430031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.79430031
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1648672019
Short name T539
Test name
Test status
Simulation time 8379991510 ps
CPU time 10.44 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204076 kb
Host smart-b7fcd9de-a3de-421e-87c6-2b3720db7551
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1648672019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1648672019
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.3753817909
Short name T1144
Test name
Test status
Simulation time 8401452874 ps
CPU time 7.65 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204124 kb
Host smart-e1c53edf-942d-4b36-8a1e-8cecf35f6869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37538
17909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.3753817909
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3961258187
Short name T709
Test name
Test status
Simulation time 8376730868 ps
CPU time 7.68 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204116 kb
Host smart-0c2ce162-1549-4676-9692-e2a6f5599160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612
58187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3961258187
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.1616340954
Short name T1007
Test name
Test status
Simulation time 8381100341 ps
CPU time 7.51 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:47 PM PDT 24
Peak memory 204100 kb
Host smart-31710162-5b9a-479f-8a0a-824e8a7d0e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
40954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1616340954
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2452493630
Short name T503
Test name
Test status
Simulation time 80853532 ps
CPU time 1.06 seconds
Started May 02 03:44:37 PM PDT 24
Finished May 02 03:44:39 PM PDT 24
Peak memory 204112 kb
Host smart-6f7154fc-de8c-45d9-8532-65f4c6289bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24524
93630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2452493630
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3066910978
Short name T914
Test name
Test status
Simulation time 8502651398 ps
CPU time 8.39 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204132 kb
Host smart-c33e4da3-a28b-4fbe-bb4a-03352883ca80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30669
10978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3066910978
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.519076148
Short name T1311
Test name
Test status
Simulation time 8387497749 ps
CPU time 7.88 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204128 kb
Host smart-7c289b9c-c71e-420c-aff1-2ccb4b7215fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51907
6148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.519076148
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3540985602
Short name T1205
Test name
Test status
Simulation time 8503462286 ps
CPU time 8.23 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204028 kb
Host smart-3ff43326-1d3b-4286-b4ab-5ac61639f54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35409
85602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3540985602
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2076801739
Short name T772
Test name
Test status
Simulation time 8417381972 ps
CPU time 8.18 seconds
Started May 02 03:44:39 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204132 kb
Host smart-22c5bd61-d7fb-4c35-8333-bf0af7a7c16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20768
01739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2076801739
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.60045369
Short name T1217
Test name
Test status
Simulation time 8388464963 ps
CPU time 8.4 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:51 PM PDT 24
Peak memory 204144 kb
Host smart-e20b3b12-ad6d-44c6-b4ea-0e3ea25f72dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60045
369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.60045369
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.735861683
Short name T463
Test name
Test status
Simulation time 8387127869 ps
CPU time 9.25 seconds
Started May 02 03:44:38 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204136 kb
Host smart-7b3b8d62-b27e-4a74-9620-7f9d54a06d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73586
1683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.735861683
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2289177107
Short name T514
Test name
Test status
Simulation time 8381759603 ps
CPU time 7.77 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204108 kb
Host smart-a83d80d6-8278-47ff-9963-4319c9d9650f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22891
77107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2289177107
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.4109340073
Short name T664
Test name
Test status
Simulation time 8400650439 ps
CPU time 8 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204128 kb
Host smart-3ebe249a-975c-4446-b12a-11597c6bf1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
40073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.4109340073
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3579578482
Short name T586
Test name
Test status
Simulation time 8366728215 ps
CPU time 7.61 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:52 PM PDT 24
Peak memory 204076 kb
Host smart-8f54e876-be73-43c7-8b55-5050c925716e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
78482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3579578482
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2439586943
Short name T1234
Test name
Test status
Simulation time 88483299 ps
CPU time 0.73 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:48 PM PDT 24
Peak memory 204028 kb
Host smart-b2094c58-8db4-45a8-92a6-a53331c5aead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395
86943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2439586943
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1470958969
Short name T253
Test name
Test status
Simulation time 16122320860 ps
CPU time 28.52 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:45:12 PM PDT 24
Peak memory 204436 kb
Host smart-47c12072-c406-4580-b2b0-f4ba408daf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14709
58969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1470958969
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.84439702
Short name T1348
Test name
Test status
Simulation time 8391858396 ps
CPU time 9.09 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204096 kb
Host smart-393be2c4-f8df-42b0-a424-256e2a8ec417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84439
702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.84439702
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.929284608
Short name T144
Test name
Test status
Simulation time 8423413701 ps
CPU time 9.81 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:55 PM PDT 24
Peak memory 204076 kb
Host smart-809ac147-816f-4fcd-9ac2-a9aebb3c134f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92928
4608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.929284608
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.570319583
Short name T620
Test name
Test status
Simulation time 8376093116 ps
CPU time 8.53 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204060 kb
Host smart-d1853664-d991-4c49-bf1c-bab5f986990a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57031
9583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.570319583
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.4133435604
Short name T1331
Test name
Test status
Simulation time 8375634646 ps
CPU time 7.49 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204136 kb
Host smart-9bbe45db-47fb-44b0-8f3a-5b8dc7c32884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41334
35604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.4133435604
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.135382212
Short name T784
Test name
Test status
Simulation time 8370254822 ps
CPU time 8.49 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204124 kb
Host smart-2489870f-38a8-4229-a702-147424cdf408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13538
2212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.135382212
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.749013350
Short name T630
Test name
Test status
Simulation time 8392517037 ps
CPU time 8.44 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204068 kb
Host smart-e0d5f48f-b309-4f8f-a0cc-6b08fcace3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74901
3350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.749013350
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3048979096
Short name T374
Test name
Test status
Simulation time 8389178254 ps
CPU time 8.07 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204120 kb
Host smart-b7bccd53-8eff-4840-94f0-ddaba4c16850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489
79096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3048979096
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.660357142
Short name T830
Test name
Test status
Simulation time 8469743653 ps
CPU time 7.92 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204112 kb
Host smart-8edf70b0-a96c-4dd1-99bb-051773691a4b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=660357142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.660357142
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1085321101
Short name T1285
Test name
Test status
Simulation time 8381130360 ps
CPU time 7.8 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204108 kb
Host smart-f7cc774c-8751-42a0-a3c5-4d6320c43c60
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1085321101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1085321101
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.2829975613
Short name T595
Test name
Test status
Simulation time 8396042979 ps
CPU time 8.92 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204112 kb
Host smart-53997557-e479-49cc-8778-9ae4550092c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28299
75613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.2829975613
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3782737909
Short name T1016
Test name
Test status
Simulation time 8373531842 ps
CPU time 7.54 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204128 kb
Host smart-6f13ec79-2bdf-43fe-9078-36b0ed57ead1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37827
37909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3782737909
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.1641011474
Short name T732
Test name
Test status
Simulation time 8372725317 ps
CPU time 8.04 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204140 kb
Host smart-0a02910d-90db-4026-8e25-1291e6f77781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16410
11474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1641011474
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2010841538
Short name T740
Test name
Test status
Simulation time 96983761 ps
CPU time 1.83 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:02 PM PDT 24
Peak memory 204216 kb
Host smart-6fa02340-8421-4b9e-a54d-8ed12eb328c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
41538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2010841538
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.4200832257
Short name T528
Test name
Test status
Simulation time 8462913286 ps
CPU time 8.08 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204100 kb
Host smart-831d1cc3-241d-4ea6-b099-735f3620c2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42008
32257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.4200832257
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1625496323
Short name T197
Test name
Test status
Simulation time 8373515623 ps
CPU time 7.73 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204048 kb
Host smart-65dc991c-adf3-4d7a-b98e-c7e21be80833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
96323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1625496323
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3844572827
Short name T895
Test name
Test status
Simulation time 8427094185 ps
CPU time 9.12 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:11 PM PDT 24
Peak memory 204128 kb
Host smart-52b927b7-1116-48f4-8f92-1ceb5fdd89d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445
72827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3844572827
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.160424929
Short name T1078
Test name
Test status
Simulation time 8420926848 ps
CPU time 10.04 seconds
Started May 02 03:46:01 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204132 kb
Host smart-f705e620-c1c1-4e35-91e9-b7f3287fdd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16042
4929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.160424929
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1891885576
Short name T953
Test name
Test status
Simulation time 8382999660 ps
CPU time 7.73 seconds
Started May 02 03:46:01 PM PDT 24
Finished May 02 03:46:11 PM PDT 24
Peak memory 204060 kb
Host smart-7d456e4b-fc33-468a-abb9-3c4c0442e7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18918
85576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1891885576
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2580704460
Short name T1101
Test name
Test status
Simulation time 8422433284 ps
CPU time 7.81 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204136 kb
Host smart-8a3ec789-e77c-40e3-bc8f-96369835e171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25807
04460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2580704460
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1928218825
Short name T832
Test name
Test status
Simulation time 8421076953 ps
CPU time 8.42 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204096 kb
Host smart-f07f018a-5236-435b-acf2-a8e5958d487f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
18825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1928218825
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.394967046
Short name T957
Test name
Test status
Simulation time 8431222036 ps
CPU time 9.06 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 203532 kb
Host smart-9a5aa969-4197-4af6-a54a-dece4e06e68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.394967046
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2755088350
Short name T897
Test name
Test status
Simulation time 8391807856 ps
CPU time 7.69 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 204096 kb
Host smart-ef1214c0-5ae0-4242-bced-557781c58ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27550
88350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2755088350
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1961267215
Short name T476
Test name
Test status
Simulation time 8368099811 ps
CPU time 8.62 seconds
Started May 02 03:46:01 PM PDT 24
Finished May 02 03:46:12 PM PDT 24
Peak memory 204060 kb
Host smart-44278463-4cbf-4761-93ec-ae87478a2326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19612
67215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1961267215
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.799063258
Short name T663
Test name
Test status
Simulation time 33915949 ps
CPU time 0.66 seconds
Started May 02 03:45:57 PM PDT 24
Finished May 02 03:46:00 PM PDT 24
Peak memory 203968 kb
Host smart-acf24b5f-890b-4e04-9b5f-bcf2dc6a0aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79906
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.799063258
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1498201822
Short name T1381
Test name
Test status
Simulation time 27642053945 ps
CPU time 58.86 seconds
Started May 02 03:46:01 PM PDT 24
Finished May 02 03:47:03 PM PDT 24
Peak memory 204352 kb
Host smart-cc673202-2116-46e0-b28e-f9318a7cb0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14982
01822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1498201822
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1942598858
Short name T1068
Test name
Test status
Simulation time 8414547795 ps
CPU time 7.83 seconds
Started May 02 03:46:01 PM PDT 24
Finished May 02 03:46:11 PM PDT 24
Peak memory 204060 kb
Host smart-d5711382-2ddc-4531-8432-59d57b5706fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19425
98858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1942598858
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1939637481
Short name T1060
Test name
Test status
Simulation time 8451402692 ps
CPU time 8.75 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:04 PM PDT 24
Peak memory 204088 kb
Host smart-2a9bba8c-396c-406d-8e65-0c9b4013f4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
37481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1939637481
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.1066259768
Short name T1195
Test name
Test status
Simulation time 8381058805 ps
CPU time 9.78 seconds
Started May 02 03:45:59 PM PDT 24
Finished May 02 03:46:12 PM PDT 24
Peak memory 204108 kb
Host smart-77c57a11-e6dd-4c2c-a99c-ae605373b6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10662
59768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.1066259768
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1539178640
Short name T169
Test name
Test status
Simulation time 8381938051 ps
CPU time 7.78 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204144 kb
Host smart-e8674914-a2f9-4a12-a618-310ca0bd76b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15391
78640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1539178640
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2910283342
Short name T665
Test name
Test status
Simulation time 8368560444 ps
CPU time 7.75 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:08 PM PDT 24
Peak memory 204048 kb
Host smart-442990fb-e229-4860-92c6-50393ce3a591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29102
83342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2910283342
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1397594229
Short name T859
Test name
Test status
Simulation time 8454947847 ps
CPU time 9.62 seconds
Started May 02 03:45:54 PM PDT 24
Finished May 02 03:46:05 PM PDT 24
Peak memory 204064 kb
Host smart-efedcaf8-925c-4bfd-99e0-c8bea0157cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13975
94229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1397594229
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1351967303
Short name T1265
Test name
Test status
Simulation time 8387407852 ps
CPU time 9.44 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:15 PM PDT 24
Peak memory 204152 kb
Host smart-9d2437c1-e92f-47ed-bd14-302238d0e46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
67303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1351967303
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2899575156
Short name T460
Test name
Test status
Simulation time 8401014700 ps
CPU time 8.97 seconds
Started May 02 03:45:58 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204128 kb
Host smart-4ab594a9-001f-4cf4-ab0e-a245e8863bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
75156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2899575156
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3078279822
Short name T737
Test name
Test status
Simulation time 8505094490 ps
CPU time 8 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204108 kb
Host smart-b4f13a8a-c49f-4299-abcb-417306f95c11
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3078279822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3078279822
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2016540291
Short name T975
Test name
Test status
Simulation time 8399509654 ps
CPU time 7.96 seconds
Started May 02 03:46:11 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204076 kb
Host smart-00941a45-85b9-4b4e-9252-cd9db785f59f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2016540291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2016540291
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3276234676
Short name T692
Test name
Test status
Simulation time 8429763510 ps
CPU time 10.25 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:22 PM PDT 24
Peak memory 204060 kb
Host smart-ef0247ae-20bd-424c-8e70-3bfd76fb4d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
34676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3276234676
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3695269581
Short name T1228
Test name
Test status
Simulation time 8379508954 ps
CPU time 7.86 seconds
Started May 02 03:46:05 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204072 kb
Host smart-d306308a-4807-4478-8c72-b87e62c60a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36952
69581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3695269581
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.3370938915
Short name T756
Test name
Test status
Simulation time 8382640593 ps
CPU time 9.14 seconds
Started May 02 03:46:09 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204148 kb
Host smart-4d209733-c246-4575-997c-7f27f2bb72a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33709
38915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3370938915
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3301085236
Short name T831
Test name
Test status
Simulation time 146424385 ps
CPU time 1.6 seconds
Started May 02 03:46:06 PM PDT 24
Finished May 02 03:46:09 PM PDT 24
Peak memory 204220 kb
Host smart-42acaaae-e080-45a5-a6ef-30718d8f459b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33010
85236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3301085236
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.261004923
Short name T408
Test name
Test status
Simulation time 8441329797 ps
CPU time 7.67 seconds
Started May 02 03:46:11 PM PDT 24
Finished May 02 03:46:19 PM PDT 24
Peak memory 204140 kb
Host smart-03e661ee-d714-4ee4-b996-18cbeff1d762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100
4923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.261004923
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1360082707
Short name T969
Test name
Test status
Simulation time 8368048714 ps
CPU time 8.35 seconds
Started May 02 03:46:13 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204104 kb
Host smart-4777e995-81a9-42d6-b74c-22ee6e6be1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600
82707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1360082707
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3284139689
Short name T149
Test name
Test status
Simulation time 8444387184 ps
CPU time 8.15 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:13 PM PDT 24
Peak memory 204168 kb
Host smart-be352440-8486-4ce2-960b-52f9ba937223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32841
39689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3284139689
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1947008041
Short name T985
Test name
Test status
Simulation time 8425463467 ps
CPU time 9.08 seconds
Started May 02 03:46:02 PM PDT 24
Finished May 02 03:46:13 PM PDT 24
Peak memory 204072 kb
Host smart-150d4bdb-2532-45f4-bff0-8ac3fced2adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19470
08041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1947008041
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3856821163
Short name T1073
Test name
Test status
Simulation time 8372327992 ps
CPU time 9.66 seconds
Started May 02 03:46:02 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204144 kb
Host smart-9713201a-a6b0-4ebe-9921-2ef1d5207ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3856821163
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3262400264
Short name T929
Test name
Test status
Simulation time 8433549842 ps
CPU time 9.31 seconds
Started May 02 03:46:09 PM PDT 24
Finished May 02 03:46:19 PM PDT 24
Peak memory 204144 kb
Host smart-5275caec-f6b6-4d84-a0e2-d4ffb0230800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32624
00264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3262400264
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1678410819
Short name T683
Test name
Test status
Simulation time 8468482057 ps
CPU time 8.38 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204084 kb
Host smart-faeca77f-3d29-41ca-8c12-beabc8f12f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16784
10819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1678410819
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1308393102
Short name T798
Test name
Test status
Simulation time 8398205432 ps
CPU time 8.33 seconds
Started May 02 03:46:06 PM PDT 24
Finished May 02 03:46:15 PM PDT 24
Peak memory 204100 kb
Host smart-8d833881-36d2-4529-b830-05cb41e04c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
93102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1308393102
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3886649161
Short name T1194
Test name
Test status
Simulation time 8390548420 ps
CPU time 8 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204148 kb
Host smart-b1a1c550-f1d6-4721-af23-b6f93e43019f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38866
49161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3886649161
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.120695306
Short name T1084
Test name
Test status
Simulation time 87704770 ps
CPU time 0.72 seconds
Started May 02 03:46:08 PM PDT 24
Finished May 02 03:46:10 PM PDT 24
Peak memory 203928 kb
Host smart-ebae3a2e-5a8d-46a4-8721-80be47318bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
5306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.120695306
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2918053205
Short name T1246
Test name
Test status
Simulation time 23883918246 ps
CPU time 45.96 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:51 PM PDT 24
Peak memory 204424 kb
Host smart-d86c5d2d-7e3a-43b8-9a25-f338b1df9427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
53205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2918053205
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.295077342
Short name T341
Test name
Test status
Simulation time 8404977633 ps
CPU time 8.25 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204068 kb
Host smart-6537865f-2830-41fd-9e12-ae2d0c703512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
7342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.295077342
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3961622264
Short name T135
Test name
Test status
Simulation time 8435423810 ps
CPU time 7.8 seconds
Started May 02 03:46:05 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204120 kb
Host smart-b4ac687c-8f92-4816-a3b8-0f48f963fb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
22264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3961622264
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1835617553
Short name T609
Test name
Test status
Simulation time 8378123225 ps
CPU time 9.37 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204132 kb
Host smart-b3e88d72-69c5-41e2-9013-d48624a29e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18356
17553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1835617553
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2193868931
Short name T1258
Test name
Test status
Simulation time 8377210398 ps
CPU time 8.74 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204080 kb
Host smart-b9d68b0e-7514-43cc-b5b3-cc10f1fdb44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21938
68931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2193868931
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1611798001
Short name T370
Test name
Test status
Simulation time 8380730543 ps
CPU time 8.07 seconds
Started May 02 03:46:04 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204060 kb
Host smart-db1e1e3b-85c9-4db9-9563-5678bc799aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16117
98001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1611798001
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3120202534
Short name T181
Test name
Test status
Simulation time 8418188774 ps
CPU time 8.27 seconds
Started May 02 03:46:03 PM PDT 24
Finished May 02 03:46:13 PM PDT 24
Peak memory 204068 kb
Host smart-3daca817-99da-439b-a889-1b5d2f4a5518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31202
02534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3120202534
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3658647080
Short name T447
Test name
Test status
Simulation time 8380212025 ps
CPU time 8.24 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204140 kb
Host smart-4ac88ff2-d676-4de7-8b34-3aa0ce6b3e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36586
47080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3658647080
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4035356641
Short name T1143
Test name
Test status
Simulation time 8388540424 ps
CPU time 8.01 seconds
Started May 02 03:46:04 PM PDT 24
Finished May 02 03:46:14 PM PDT 24
Peak memory 204060 kb
Host smart-dca3c2c1-8e72-49b5-843a-07c0caaaf608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353
56641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4035356641
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.3217967392
Short name T1089
Test name
Test status
Simulation time 8465376061 ps
CPU time 10.02 seconds
Started May 02 03:46:13 PM PDT 24
Finished May 02 03:46:29 PM PDT 24
Peak memory 204116 kb
Host smart-913b0143-807e-47de-a974-6e5a1f8b0930
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3217967392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.3217967392
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3752276114
Short name T1279
Test name
Test status
Simulation time 8408231031 ps
CPU time 8.72 seconds
Started May 02 03:46:13 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204096 kb
Host smart-17e5e630-1fdb-488f-bf4b-1b1ac08c36f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3752276114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3752276114
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.1542402353
Short name T1086
Test name
Test status
Simulation time 8453096132 ps
CPU time 8.77 seconds
Started May 02 03:46:13 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204084 kb
Host smart-c4552bcf-22d6-4251-b531-755949cf5716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
02353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.1542402353
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2357738301
Short name T343
Test name
Test status
Simulation time 8381002611 ps
CPU time 7.98 seconds
Started May 02 03:46:12 PM PDT 24
Finished May 02 03:46:21 PM PDT 24
Peak memory 204144 kb
Host smart-61a6f6bf-12ff-450d-a767-1e2fdae391b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23577
38301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2357738301
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.3179520786
Short name T1115
Test name
Test status
Simulation time 8400561045 ps
CPU time 8.91 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:24 PM PDT 24
Peak memory 204068 kb
Host smart-1384a5d1-d697-4565-8a5c-0f4b33631e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31795
20786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3179520786
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1648678840
Short name T385
Test name
Test status
Simulation time 128943165 ps
CPU time 1.78 seconds
Started May 02 03:46:18 PM PDT 24
Finished May 02 03:46:21 PM PDT 24
Peak memory 204120 kb
Host smart-a17887f5-d237-4430-85b8-7467931e36e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
78840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1648678840
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3868319203
Short name T505
Test name
Test status
Simulation time 8454786873 ps
CPU time 7.76 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204100 kb
Host smart-4c2cfa9b-eea0-4975-8fa1-48831677fd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38683
19203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3868319203
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1286146856
Short name T1292
Test name
Test status
Simulation time 8424198964 ps
CPU time 8.15 seconds
Started May 02 03:46:22 PM PDT 24
Finished May 02 03:46:32 PM PDT 24
Peak memory 203468 kb
Host smart-6394085b-7e05-469d-9583-ed75bc09a7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12861
46856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1286146856
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3247129320
Short name T697
Test name
Test status
Simulation time 8401795443 ps
CPU time 8.17 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204096 kb
Host smart-bbf741d6-5836-4830-9d9a-798959544312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32471
29320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3247129320
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3265344437
Short name T980
Test name
Test status
Simulation time 8417986189 ps
CPU time 7.88 seconds
Started May 02 03:46:09 PM PDT 24
Finished May 02 03:46:18 PM PDT 24
Peak memory 204056 kb
Host smart-846ac6b2-a94e-463c-9820-1c2fe97d6c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653
44437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3265344437
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3545522817
Short name T691
Test name
Test status
Simulation time 8374194825 ps
CPU time 7.82 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204096 kb
Host smart-e99c1fbe-8411-449b-b9db-206b176cdf16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35455
22817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3545522817
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3003397341
Short name T915
Test name
Test status
Simulation time 8409565637 ps
CPU time 7.88 seconds
Started May 02 03:46:11 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204152 kb
Host smart-2284c170-c111-4611-93fd-bdbc67665415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30033
97341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3003397341
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2559401686
Short name T559
Test name
Test status
Simulation time 8420845110 ps
CPU time 7.86 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:19 PM PDT 24
Peak memory 204120 kb
Host smart-2fe6cf11-cf68-4e92-9329-95ce17a47be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594
01686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2559401686
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.844535789
Short name T777
Test name
Test status
Simulation time 8432525766 ps
CPU time 7.48 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:22 PM PDT 24
Peak memory 204084 kb
Host smart-3ae3a320-ee74-4ce6-b6c5-4b19c6817667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84453
5789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.844535789
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.400689971
Short name T866
Test name
Test status
Simulation time 8391887844 ps
CPU time 8.54 seconds
Started May 02 03:46:16 PM PDT 24
Finished May 02 03:46:25 PM PDT 24
Peak memory 204136 kb
Host smart-c5adb528-e91c-4c80-a045-5331276db17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40068
9971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.400689971
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.628955868
Short name T920
Test name
Test status
Simulation time 33364951 ps
CPU time 0.7 seconds
Started May 02 03:46:15 PM PDT 24
Finished May 02 03:46:17 PM PDT 24
Peak memory 204024 kb
Host smart-e5b1b894-5d32-4c55-9058-78ae4b258473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62895
5868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.628955868
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1740309137
Short name T1001
Test name
Test status
Simulation time 28617650145 ps
CPU time 54.03 seconds
Started May 02 03:46:12 PM PDT 24
Finished May 02 03:47:07 PM PDT 24
Peak memory 204336 kb
Host smart-333816f5-720e-4c7d-88b7-fe82cde76141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17403
09137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1740309137
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3867394289
Short name T368
Test name
Test status
Simulation time 8398008684 ps
CPU time 8.19 seconds
Started May 02 03:46:12 PM PDT 24
Finished May 02 03:46:21 PM PDT 24
Peak memory 204152 kb
Host smart-9f8c554f-0177-46e4-b686-c6c9381d3b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38673
94289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3867394289
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1304970393
Short name T789
Test name
Test status
Simulation time 8426200938 ps
CPU time 7.68 seconds
Started May 02 03:46:10 PM PDT 24
Finished May 02 03:46:19 PM PDT 24
Peak memory 204116 kb
Host smart-9fe3ad0b-cbf7-47cd-890c-8d05c756fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
70393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1304970393
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2861646415
Short name T825
Test name
Test status
Simulation time 8430663210 ps
CPU time 8.17 seconds
Started May 02 03:46:11 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204060 kb
Host smart-892b67dd-012c-431a-b1a1-5d4b7a56af73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28616
46415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2861646415
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3396233612
Short name T894
Test name
Test status
Simulation time 8373684900 ps
CPU time 8.35 seconds
Started May 02 03:46:29 PM PDT 24
Finished May 02 03:46:38 PM PDT 24
Peak memory 203464 kb
Host smart-a9cf49bb-bc61-4321-8fc5-e29e155d5703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33962
33612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3396233612
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1821380780
Short name T340
Test name
Test status
Simulation time 8373277904 ps
CPU time 8.09 seconds
Started May 02 03:46:20 PM PDT 24
Finished May 02 03:46:29 PM PDT 24
Peak memory 204096 kb
Host smart-79936500-a4a1-49cc-b586-b7f720f0af96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213
80780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1821380780
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1709603264
Short name T161
Test name
Test status
Simulation time 8448719290 ps
CPU time 9.49 seconds
Started May 02 03:46:12 PM PDT 24
Finished May 02 03:46:22 PM PDT 24
Peak memory 204092 kb
Host smart-2dec0751-e5f4-4014-a605-bf9e3722a924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17096
03264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1709603264
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1662874169
Short name T1328
Test name
Test status
Simulation time 8380190292 ps
CPU time 7.55 seconds
Started May 02 03:46:16 PM PDT 24
Finished May 02 03:46:24 PM PDT 24
Peak memory 204096 kb
Host smart-d2e79423-1f88-412e-a082-9de7a235cdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
74169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1662874169
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2392403011
Short name T1075
Test name
Test status
Simulation time 8410049849 ps
CPU time 7.62 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:22 PM PDT 24
Peak memory 204088 kb
Host smart-00964d3e-e8e8-4681-9344-37cdfacffe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23924
03011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2392403011
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.111128601
Short name T440
Test name
Test status
Simulation time 8497417018 ps
CPU time 7.66 seconds
Started May 02 03:46:27 PM PDT 24
Finished May 02 03:46:36 PM PDT 24
Peak memory 204088 kb
Host smart-eceb6fdb-71af-437d-a1ca-491b76475af5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=111128601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.111128601
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.419846899
Short name T813
Test name
Test status
Simulation time 8439774549 ps
CPU time 8.11 seconds
Started May 02 03:46:21 PM PDT 24
Finished May 02 03:46:31 PM PDT 24
Peak memory 204024 kb
Host smart-3019763d-37a0-4052-a6c6-22e29af5c2e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=419846899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.419846899
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.395255875
Short name T661
Test name
Test status
Simulation time 8424819521 ps
CPU time 8.81 seconds
Started May 02 03:46:22 PM PDT 24
Finished May 02 03:46:33 PM PDT 24
Peak memory 204056 kb
Host smart-8ee7c86d-de9e-4946-81bc-8615e09578f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
5875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.395255875
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1205911826
Short name T495
Test name
Test status
Simulation time 8387285563 ps
CPU time 7.56 seconds
Started May 02 03:46:18 PM PDT 24
Finished May 02 03:46:27 PM PDT 24
Peak memory 204148 kb
Host smart-c94ca2e3-117c-47a4-9a37-8c350a22008f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
11826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1205911826
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.1682021876
Short name T635
Test name
Test status
Simulation time 8380201418 ps
CPU time 8.42 seconds
Started May 02 03:46:14 PM PDT 24
Finished May 02 03:46:24 PM PDT 24
Peak memory 204060 kb
Host smart-d69bffe2-3478-4966-9e24-dd48cc2f3398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
21876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1682021876
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2780398006
Short name T500
Test name
Test status
Simulation time 313505866 ps
CPU time 2.53 seconds
Started May 02 03:46:17 PM PDT 24
Finished May 02 03:46:20 PM PDT 24
Peak memory 204240 kb
Host smart-c72b9250-0a2e-4254-9c06-febdd51b2c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27803
98006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2780398006
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2461488412
Short name T681
Test name
Test status
Simulation time 8417977352 ps
CPU time 8.12 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:46 PM PDT 24
Peak memory 204068 kb
Host smart-2ab9ddd3-33dc-44e4-9e84-bdf18cd93be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24614
88412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2461488412
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.653949644
Short name T201
Test name
Test status
Simulation time 8406702722 ps
CPU time 8.41 seconds
Started May 02 03:46:20 PM PDT 24
Finished May 02 03:46:30 PM PDT 24
Peak memory 204104 kb
Host smart-7b6bd688-cf9a-4548-b716-90fb6297b00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65394
9644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.653949644
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2038300348
Short name T548
Test name
Test status
Simulation time 8407131218 ps
CPU time 10.29 seconds
Started May 02 03:46:13 PM PDT 24
Finished May 02 03:46:24 PM PDT 24
Peak memory 204072 kb
Host smart-bea4b534-2c18-457f-acfc-ea6f90a8f1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
00348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2038300348
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2502430400
Short name T889
Test name
Test status
Simulation time 8413707571 ps
CPU time 8.34 seconds
Started May 02 03:46:15 PM PDT 24
Finished May 02 03:46:24 PM PDT 24
Peak memory 204136 kb
Host smart-09529b24-550f-496a-9e8d-596b3f59ccf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25024
30400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2502430400
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2866728879
Short name T1323
Test name
Test status
Simulation time 8400480014 ps
CPU time 7.87 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:34 PM PDT 24
Peak memory 203456 kb
Host smart-6549ac49-6f34-44a5-9cc3-df1e2ea185f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28667
28879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2866728879
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3355144343
Short name T688
Test name
Test status
Simulation time 8465354013 ps
CPU time 10.14 seconds
Started May 02 03:46:13 PM PDT 24
Finished May 02 03:46:25 PM PDT 24
Peak memory 204104 kb
Host smart-3ba43c19-4b88-40a3-a05b-9c870b4a4523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33551
44343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3355144343
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.925491927
Short name T245
Test name
Test status
Simulation time 8408607070 ps
CPU time 8.25 seconds
Started May 02 03:46:17 PM PDT 24
Finished May 02 03:46:26 PM PDT 24
Peak memory 204076 kb
Host smart-01c5ce84-08df-4ff6-b3c7-b6b9ad84a677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92549
1927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.925491927
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.724752088
Short name T360
Test name
Test status
Simulation time 8374408287 ps
CPU time 10.35 seconds
Started May 02 03:46:16 PM PDT 24
Finished May 02 03:46:27 PM PDT 24
Peak memory 204064 kb
Host smart-b5f51ebb-ce3e-4c45-b48f-010b2bd7d8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72475
2088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.724752088
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1537699908
Short name T803
Test name
Test status
Simulation time 8391090494 ps
CPU time 9.75 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:41 PM PDT 24
Peak memory 204124 kb
Host smart-a6529622-5626-4c73-9a01-43a81029a407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
99908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1537699908
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2372211714
Short name T646
Test name
Test status
Simulation time 8387020077 ps
CPU time 7.56 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204068 kb
Host smart-a5f59ab2-4423-43f1-a51d-c2e081be9182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23722
11714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2372211714
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.264631450
Short name T971
Test name
Test status
Simulation time 31404654 ps
CPU time 0.64 seconds
Started May 02 03:46:18 PM PDT 24
Finished May 02 03:46:19 PM PDT 24
Peak memory 203984 kb
Host smart-ef4c03f0-f394-4b21-bf6a-7626b6651112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26463
1450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.264631450
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.444313177
Short name T1020
Test name
Test status
Simulation time 22194402510 ps
CPU time 40 seconds
Started May 02 03:46:23 PM PDT 24
Finished May 02 03:47:05 PM PDT 24
Peak memory 204440 kb
Host smart-9e2bd71e-8e0a-4bf0-9fac-c78f0d86bc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44431
3177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.444313177
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3168537222
Short name T407
Test name
Test status
Simulation time 8402233166 ps
CPU time 9.15 seconds
Started May 02 03:46:21 PM PDT 24
Finished May 02 03:46:31 PM PDT 24
Peak memory 204060 kb
Host smart-9b476dd0-4896-4c10-8c4a-245203d4b41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31685
37222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3168537222
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2255957149
Short name T1377
Test name
Test status
Simulation time 8488402075 ps
CPU time 8.26 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204128 kb
Host smart-29143988-9889-4d3c-bc03-e11626e4e0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22559
57149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2255957149
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.1491536217
Short name T529
Test name
Test status
Simulation time 8395358663 ps
CPU time 8.29 seconds
Started May 02 03:46:19 PM PDT 24
Finished May 02 03:46:29 PM PDT 24
Peak memory 204140 kb
Host smart-6c550956-fbce-4cef-be94-3b8cf6ff41aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14915
36217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.1491536217
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.550265250
Short name T167
Test name
Test status
Simulation time 8378325470 ps
CPU time 10 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:52 PM PDT 24
Peak memory 204072 kb
Host smart-183d6f86-dd82-4b55-87af-72185705e949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55026
5250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.550265250
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1290157136
Short name T637
Test name
Test status
Simulation time 8369013900 ps
CPU time 8.22 seconds
Started May 02 03:46:22 PM PDT 24
Finished May 02 03:46:31 PM PDT 24
Peak memory 204032 kb
Host smart-f3c6bb9d-0ab4-4198-9d76-5eb4c8a5d6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12901
57136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1290157136
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3547694945
Short name T1360
Test name
Test status
Simulation time 8416765713 ps
CPU time 9.4 seconds
Started May 02 03:46:22 PM PDT 24
Finished May 02 03:46:33 PM PDT 24
Peak memory 204140 kb
Host smart-2c668e6f-8188-461d-8750-06588c90d4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35476
94945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3547694945
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1378404158
Short name T607
Test name
Test status
Simulation time 8389607225 ps
CPU time 8.39 seconds
Started May 02 03:46:19 PM PDT 24
Finished May 02 03:46:28 PM PDT 24
Peak memory 204128 kb
Host smart-e3b3fa02-d10c-4031-91f2-1b61a3cb6941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
04158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1378404158
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.892211915
Short name T492
Test name
Test status
Simulation time 8415552045 ps
CPU time 9.72 seconds
Started May 02 03:46:21 PM PDT 24
Finished May 02 03:46:32 PM PDT 24
Peak memory 204072 kb
Host smart-4c378b68-8268-4709-8225-d0e55d8d5146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89221
1915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.892211915
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.286939421
Short name T877
Test name
Test status
Simulation time 8461467385 ps
CPU time 9.75 seconds
Started May 02 03:46:27 PM PDT 24
Finished May 02 03:46:38 PM PDT 24
Peak memory 204120 kb
Host smart-9964af6c-a615-49c9-9f1e-e395cdb67776
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=286939421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.286939421
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3776831775
Short name T363
Test name
Test status
Simulation time 8375179750 ps
CPU time 8.27 seconds
Started May 02 03:46:51 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204068 kb
Host smart-2a8a8388-9e72-48e3-8fd3-61c22a079972
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3776831775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3776831775
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.2842597788
Short name T572
Test name
Test status
Simulation time 8470335911 ps
CPU time 9.99 seconds
Started May 02 03:46:25 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204092 kb
Host smart-c578ab20-8d43-4c0a-8273-8bdfeac226ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
97788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.2842597788
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.23086483
Short name T477
Test name
Test status
Simulation time 8371429395 ps
CPU time 7.78 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204128 kb
Host smart-cb7f82e3-7de8-4d65-9586-2d2f7ac4db23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.23086483
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.3647224692
Short name T437
Test name
Test status
Simulation time 8430883360 ps
CPU time 8.24 seconds
Started May 02 03:46:28 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204052 kb
Host smart-43968d63-01cc-4655-85ac-42a6dd5ad698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36472
24692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3647224692
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1630890138
Short name T331
Test name
Test status
Simulation time 164398851 ps
CPU time 1.56 seconds
Started May 02 03:46:20 PM PDT 24
Finished May 02 03:46:23 PM PDT 24
Peak memory 204228 kb
Host smart-835a4efb-8317-4c3e-aae6-bd530c634f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16308
90138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1630890138
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3110737049
Short name T450
Test name
Test status
Simulation time 8436785404 ps
CPU time 8.98 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:41 PM PDT 24
Peak memory 204076 kb
Host smart-9e8b9438-0e0d-4c8a-b8e8-7227b02f4a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31107
37049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3110737049
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3248373652
Short name T962
Test name
Test status
Simulation time 8363227165 ps
CPU time 7.91 seconds
Started May 02 03:46:33 PM PDT 24
Finished May 02 03:46:42 PM PDT 24
Peak memory 204100 kb
Host smart-f32f97ba-70b4-4180-8202-bfee5abe0a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32483
73652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3248373652
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2060875774
Short name T645
Test name
Test status
Simulation time 8447781828 ps
CPU time 7.48 seconds
Started May 02 03:46:20 PM PDT 24
Finished May 02 03:46:30 PM PDT 24
Peak memory 204060 kb
Host smart-b7c84e71-016a-4fba-a6d1-dbcf3d6c06e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
75774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2060875774
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.4145186723
Short name T388
Test name
Test status
Simulation time 8424005143 ps
CPU time 7.82 seconds
Started May 02 03:46:23 PM PDT 24
Finished May 02 03:46:32 PM PDT 24
Peak memory 204040 kb
Host smart-666995f8-9fab-4a26-bcc7-2caad605636b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41451
86723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.4145186723
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2699621759
Short name T1174
Test name
Test status
Simulation time 8374141648 ps
CPU time 7.65 seconds
Started May 02 03:46:23 PM PDT 24
Finished May 02 03:46:32 PM PDT 24
Peak memory 204144 kb
Host smart-d061c5a6-2607-4b29-8d6d-440cc79980ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26996
21759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2699621759
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2940333297
Short name T118
Test name
Test status
Simulation time 8454961891 ps
CPU time 7.55 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:33 PM PDT 24
Peak memory 204084 kb
Host smart-8958db0e-5f35-492e-b674-07a035a143c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
33297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2940333297
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.575342025
Short name T1344
Test name
Test status
Simulation time 8453138326 ps
CPU time 8.9 seconds
Started May 02 03:46:23 PM PDT 24
Finished May 02 03:46:34 PM PDT 24
Peak memory 204072 kb
Host smart-c00910ee-a39e-4fca-af3b-2d4f7a9de30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57534
2025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.575342025
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1719625980
Short name T32
Test name
Test status
Simulation time 8372937287 ps
CPU time 7.44 seconds
Started May 02 03:46:34 PM PDT 24
Finished May 02 03:46:43 PM PDT 24
Peak memory 204132 kb
Host smart-d44c339e-9a53-4d42-b461-3c589978ebac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
25980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1719625980
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3704707590
Short name T716
Test name
Test status
Simulation time 8370026592 ps
CPU time 10.19 seconds
Started May 02 03:46:22 PM PDT 24
Finished May 02 03:46:33 PM PDT 24
Peak memory 204068 kb
Host smart-c6a96159-a087-42d7-81c8-4139210f382a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37047
07590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3704707590
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1638874351
Short name T1042
Test name
Test status
Simulation time 43849483 ps
CPU time 0.64 seconds
Started May 02 03:46:29 PM PDT 24
Finished May 02 03:46:30 PM PDT 24
Peak memory 203972 kb
Host smart-671627b9-9fee-4e3d-9a26-ef307d72c2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
74351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1638874351
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2203492087
Short name T1338
Test name
Test status
Simulation time 16399220806 ps
CPU time 30.88 seconds
Started May 02 03:46:21 PM PDT 24
Finished May 02 03:46:54 PM PDT 24
Peak memory 204364 kb
Host smart-3e856c63-456a-45e5-937f-33a806c7b642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22034
92087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2203492087
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4204957407
Short name T768
Test name
Test status
Simulation time 8418852605 ps
CPU time 7.67 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:36 PM PDT 24
Peak memory 204068 kb
Host smart-0bf92898-7764-43da-8e39-74f93033e7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
57407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4204957407
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2965931005
Short name T690
Test name
Test status
Simulation time 8486043467 ps
CPU time 9.64 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:52 PM PDT 24
Peak memory 203468 kb
Host smart-c4f1f2f0-bfc7-427b-aa45-1719911608e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
31005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2965931005
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.749780459
Short name T1023
Test name
Test status
Simulation time 8396955161 ps
CPU time 8.2 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:34 PM PDT 24
Peak memory 204132 kb
Host smart-547dfe37-2e9f-4927-82de-25841298a925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74978
0459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.749780459
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.4291706730
Short name T587
Test name
Test status
Simulation time 8377359012 ps
CPU time 7.62 seconds
Started May 02 03:46:20 PM PDT 24
Finished May 02 03:46:29 PM PDT 24
Peak memory 204076 kb
Host smart-9b46762b-b676-4f5a-b12e-37eb9ac48f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
06730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.4291706730
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3257034680
Short name T891
Test name
Test status
Simulation time 8363792171 ps
CPU time 10.46 seconds
Started May 02 03:46:21 PM PDT 24
Finished May 02 03:46:33 PM PDT 24
Peak memory 204068 kb
Host smart-321e0f93-e35d-4d8c-be7f-e8cc98c32161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
34680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3257034680
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.279012203
Short name T734
Test name
Test status
Simulation time 8428328754 ps
CPU time 8.36 seconds
Started May 02 03:46:19 PM PDT 24
Finished May 02 03:46:28 PM PDT 24
Peak memory 204064 kb
Host smart-8fbe4538-5e4f-462a-b726-00f37515a30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
2203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.279012203
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1864313113
Short name T699
Test name
Test status
Simulation time 8416528351 ps
CPU time 7.96 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:39 PM PDT 24
Peak memory 203456 kb
Host smart-eac30ae1-9f22-423f-b818-3c6590b8ee1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18643
13113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1864313113
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3509951339
Short name T382
Test name
Test status
Simulation time 8399576580 ps
CPU time 8.08 seconds
Started May 02 03:46:35 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204152 kb
Host smart-514fd5c2-c1ef-4ef9-b10b-9def0b064890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35099
51339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3509951339
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.4113124480
Short name T1213
Test name
Test status
Simulation time 8527951799 ps
CPU time 7.67 seconds
Started May 02 03:46:44 PM PDT 24
Finished May 02 03:46:53 PM PDT 24
Peak memory 204088 kb
Host smart-e522a29b-fb62-45cf-a935-f33d0a1624ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4113124480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.4113124480
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.1820422968
Short name T583
Test name
Test status
Simulation time 8377241459 ps
CPU time 7.46 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204140 kb
Host smart-6d08664a-26e7-4642-9417-5b8fc20bdabb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1820422968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.1820422968
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.3984324794
Short name T1124
Test name
Test status
Simulation time 8439529823 ps
CPU time 8.29 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:46 PM PDT 24
Peak memory 204116 kb
Host smart-9b9055c9-f69a-489a-aae3-87485332c7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39843
24794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.3984324794
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2600804367
Short name T1026
Test name
Test status
Simulation time 8378159935 ps
CPU time 8.74 seconds
Started May 02 03:46:22 PM PDT 24
Finished May 02 03:46:33 PM PDT 24
Peak memory 204140 kb
Host smart-78314fc9-7db0-4a55-baa3-ff79141ddd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26008
04367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2600804367
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.398982251
Short name T927
Test name
Test status
Simulation time 8373645375 ps
CPU time 7.49 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204008 kb
Host smart-062628d6-321b-436a-855f-f8fd8bc5ee21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.398982251
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.4230739329
Short name T217
Test name
Test status
Simulation time 106518347 ps
CPU time 1.29 seconds
Started May 02 03:46:35 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204208 kb
Host smart-06fa77fe-97fa-4f0f-a9f1-80497a66b381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
39329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.4230739329
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3285725382
Short name T150
Test name
Test status
Simulation time 8466654958 ps
CPU time 8.35 seconds
Started May 02 03:46:25 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204096 kb
Host smart-7f4a03e9-f769-47f6-b255-5b4ffe985aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32857
25382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3285725382
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1911058352
Short name T1030
Test name
Test status
Simulation time 8394520374 ps
CPU time 7.52 seconds
Started May 02 03:46:42 PM PDT 24
Finished May 02 03:46:51 PM PDT 24
Peak memory 204088 kb
Host smart-b4f1eddd-7945-4481-b266-e45ff380196f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
58352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1911058352
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3124497010
Short name T1010
Test name
Test status
Simulation time 8390011091 ps
CPU time 8.77 seconds
Started May 02 03:46:40 PM PDT 24
Finished May 02 03:46:50 PM PDT 24
Peak memory 204132 kb
Host smart-d4579075-9eec-4f61-a085-de80708e52bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244
97010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3124497010
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3592135809
Short name T453
Test name
Test status
Simulation time 8419382462 ps
CPU time 8.1 seconds
Started May 02 03:46:32 PM PDT 24
Finished May 02 03:46:42 PM PDT 24
Peak memory 204108 kb
Host smart-0204f059-6954-44c0-b036-149a261859b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35921
35809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3592135809
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.13380894
Short name T1037
Test name
Test status
Simulation time 8379732713 ps
CPU time 7.99 seconds
Started May 02 03:46:44 PM PDT 24
Finished May 02 03:46:53 PM PDT 24
Peak memory 204132 kb
Host smart-dbcb843a-5f7e-4c47-8634-7b9bd0369050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.13380894
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2271358281
Short name T124
Test name
Test status
Simulation time 8434356695 ps
CPU time 9.03 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204148 kb
Host smart-a3bfd803-aafb-4d49-b608-139de79aca81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
58281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2271358281
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2669826176
Short name T274
Test name
Test status
Simulation time 8374636314 ps
CPU time 9.21 seconds
Started May 02 03:46:25 PM PDT 24
Finished May 02 03:46:36 PM PDT 24
Peak memory 204088 kb
Host smart-d84b0f8b-8831-40e9-8250-7f08d0d3fef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26698
26176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2669826176
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.980797452
Short name T1054
Test name
Test status
Simulation time 8411536700 ps
CPU time 7.75 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:50 PM PDT 24
Peak memory 204128 kb
Host smart-02dcb916-907f-4fcc-acd0-96a63bbff597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98079
7452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.980797452
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3525176500
Short name T60
Test name
Test status
Simulation time 8415801230 ps
CPU time 7.83 seconds
Started May 02 03:46:35 PM PDT 24
Finished May 02 03:46:44 PM PDT 24
Peak memory 204132 kb
Host smart-45852768-b87b-4f10-ba1f-43c106881a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35251
76500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3525176500
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2379312188
Short name T1018
Test name
Test status
Simulation time 8368270955 ps
CPU time 8.24 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:36 PM PDT 24
Peak memory 204092 kb
Host smart-68c4a0f0-94d0-4a51-91da-7b77b0ad57f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
12188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2379312188
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1089469309
Short name T1294
Test name
Test status
Simulation time 36314214 ps
CPU time 0.65 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:28 PM PDT 24
Peak memory 204012 kb
Host smart-5405c91b-4f20-459b-969b-6d901bcaeb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
69309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1089469309
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2349752675
Short name T225
Test name
Test status
Simulation time 21926099720 ps
CPU time 43.31 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:47:14 PM PDT 24
Peak memory 204364 kb
Host smart-2f5c9640-d780-43d9-8bda-db617ace93ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23497
52675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2349752675
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1496173591
Short name T507
Test name
Test status
Simulation time 8419901284 ps
CPU time 8.77 seconds
Started May 02 03:46:32 PM PDT 24
Finished May 02 03:46:42 PM PDT 24
Peak memory 204064 kb
Host smart-fd99c295-2ca0-47f1-ae03-91aec06cb690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14961
73591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1496173591
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1594446449
Short name T138
Test name
Test status
Simulation time 8434399295 ps
CPU time 9.9 seconds
Started May 02 03:46:25 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204148 kb
Host smart-dff0946a-6c9a-45b6-a3b8-6905c2c4720c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
46449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1594446449
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.220511941
Short name T593
Test name
Test status
Simulation time 8390348164 ps
CPU time 10.5 seconds
Started May 02 03:46:42 PM PDT 24
Finished May 02 03:46:54 PM PDT 24
Peak memory 204144 kb
Host smart-5a05fa2d-9f66-47a6-aed4-5fd5c9c1a964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22051
1941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.220511941
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.729735624
Short name T1235
Test name
Test status
Simulation time 8401838935 ps
CPU time 9.28 seconds
Started May 02 03:46:44 PM PDT 24
Finished May 02 03:46:54 PM PDT 24
Peak memory 204088 kb
Host smart-864c789d-8f15-4c72-9f81-ddfb52f3a52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72973
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.729735624
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3551421463
Short name T480
Test name
Test status
Simulation time 8378265572 ps
CPU time 9.39 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204128 kb
Host smart-01b3892f-8954-4f95-bc90-4ab76c8e951e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
21463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3551421463
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1957630567
Short name T1337
Test name
Test status
Simulation time 8459753429 ps
CPU time 8.25 seconds
Started May 02 03:46:32 PM PDT 24
Finished May 02 03:46:41 PM PDT 24
Peak memory 204056 kb
Host smart-eba587ea-5cdd-4f34-91dc-7bda57d4d76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
30567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1957630567
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1657814240
Short name T591
Test name
Test status
Simulation time 8396536589 ps
CPU time 7.76 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:46:57 PM PDT 24
Peak memory 204080 kb
Host smart-5f291d0b-28d7-4690-846c-429b85db512d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16578
14240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1657814240
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3208732008
Short name T838
Test name
Test status
Simulation time 8372009875 ps
CPU time 8.28 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204104 kb
Host smart-44d12b48-0fa4-4fe8-a837-d797e90ebfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32087
32008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3208732008
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.828034456
Short name T250
Test name
Test status
Simulation time 8489669469 ps
CPU time 7.98 seconds
Started May 02 03:46:43 PM PDT 24
Finished May 02 03:46:52 PM PDT 24
Peak memory 204136 kb
Host smart-a540342c-1393-48e4-920a-7a89c9e68ad4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=828034456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.828034456
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.3487506975
Short name T936
Test name
Test status
Simulation time 8380752963 ps
CPU time 8.12 seconds
Started May 02 03:46:34 PM PDT 24
Finished May 02 03:46:44 PM PDT 24
Peak memory 204128 kb
Host smart-a4b4f063-00d9-45f0-b144-efe4da3ba8b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3487506975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.3487506975
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.2823744338
Short name T1212
Test name
Test status
Simulation time 8381598503 ps
CPU time 10.52 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:39 PM PDT 24
Peak memory 204108 kb
Host smart-18bb14bc-9840-452f-93da-a7eeb420bc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
44338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.2823744338
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1361594718
Short name T1012
Test name
Test status
Simulation time 8377853361 ps
CPU time 7.92 seconds
Started May 02 03:46:39 PM PDT 24
Finished May 02 03:46:48 PM PDT 24
Peak memory 204080 kb
Host smart-d743bbb4-59ee-415b-9cc5-7cb4ab0d0086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
94718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1361594718
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.2879210999
Short name T1013
Test name
Test status
Simulation time 8375996194 ps
CPU time 8.41 seconds
Started May 02 03:46:28 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204088 kb
Host smart-f3ebb97f-b85d-4b33-bd20-750d3fc2090c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28792
10999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2879210999
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.975218869
Short name T402
Test name
Test status
Simulation time 100157992 ps
CPU time 1.59 seconds
Started May 02 03:46:25 PM PDT 24
Finished May 02 03:46:28 PM PDT 24
Peak memory 204096 kb
Host smart-4d0e0974-4e5f-4bcc-8009-63ddda998acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97521
8869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.975218869
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2093731224
Short name T795
Test name
Test status
Simulation time 8434362075 ps
CPU time 9.86 seconds
Started May 02 03:46:55 PM PDT 24
Finished May 02 03:47:06 PM PDT 24
Peak memory 204144 kb
Host smart-712aff5d-bdda-4bc3-847b-1acb378a4835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
31224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2093731224
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2603053777
Short name T578
Test name
Test status
Simulation time 8367197188 ps
CPU time 7.87 seconds
Started May 02 03:46:27 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204096 kb
Host smart-0f47cf96-01b2-4975-b0db-0ef7451a2524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26030
53777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2603053777
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3442995579
Short name T1128
Test name
Test status
Simulation time 8444578122 ps
CPU time 8.77 seconds
Started May 02 03:46:32 PM PDT 24
Finished May 02 03:46:42 PM PDT 24
Peak memory 204108 kb
Host smart-1948132b-29ec-4987-ba24-c23566bc6a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34429
95579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3442995579
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1574674486
Short name T579
Test name
Test status
Simulation time 8420591259 ps
CPU time 8.61 seconds
Started May 02 03:46:25 PM PDT 24
Finished May 02 03:46:36 PM PDT 24
Peak memory 204044 kb
Host smart-4ecf80c6-7b30-4f6e-8aeb-4729b42a7da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15746
74486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1574674486
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1650817057
Short name T1104
Test name
Test status
Simulation time 8375279901 ps
CPU time 9.12 seconds
Started May 02 03:46:33 PM PDT 24
Finished May 02 03:46:43 PM PDT 24
Peak memory 204128 kb
Host smart-0d0c357b-3ab8-42f6-adcf-8fe7cb9a617a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
17057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1650817057
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.479527359
Short name T103
Test name
Test status
Simulation time 8433795423 ps
CPU time 8.12 seconds
Started May 02 03:46:43 PM PDT 24
Finished May 02 03:46:52 PM PDT 24
Peak memory 204144 kb
Host smart-5f8cf9a0-b15a-430c-873b-45beb64f51df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47952
7359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.479527359
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.4267946980
Short name T1244
Test name
Test status
Simulation time 8396596412 ps
CPU time 7.61 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:39 PM PDT 24
Peak memory 204148 kb
Host smart-4b5891c6-34f2-4ed5-9a81-1c74d84d729d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
46980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.4267946980
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3276029642
Short name T481
Test name
Test status
Simulation time 8389871995 ps
CPU time 7.91 seconds
Started May 02 03:46:47 PM PDT 24
Finished May 02 03:46:56 PM PDT 24
Peak memory 204080 kb
Host smart-96f64598-8ece-4da2-b946-cb0730814f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
29642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3276029642
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2539391740
Short name T631
Test name
Test status
Simulation time 8416591072 ps
CPU time 7.77 seconds
Started May 02 03:46:51 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204116 kb
Host smart-b46b7b5f-3990-434e-9ba7-7ab5aa08f162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25393
91740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2539391740
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2947770468
Short name T9
Test name
Test status
Simulation time 8408222245 ps
CPU time 8.95 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204080 kb
Host smart-fac22edd-c887-42c6-a188-5c9bb8749d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29477
70468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2947770468
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3910527234
Short name T378
Test name
Test status
Simulation time 66801049 ps
CPU time 0.7 seconds
Started May 02 03:46:44 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204012 kb
Host smart-0a209239-cc29-471e-bc5f-ea8272f28bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39105
27234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3910527234
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2123097202
Short name T1014
Test name
Test status
Simulation time 23025830998 ps
CPU time 49.08 seconds
Started May 02 03:46:29 PM PDT 24
Finished May 02 03:47:19 PM PDT 24
Peak memory 204456 kb
Host smart-3e413d70-98f3-4db5-b03c-93325497a2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
97202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2123097202
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1733071429
Short name T416
Test name
Test status
Simulation time 8402513227 ps
CPU time 7.88 seconds
Started May 02 03:46:27 PM PDT 24
Finished May 02 03:46:36 PM PDT 24
Peak memory 204104 kb
Host smart-da7995c4-7caf-428c-aba4-f0063b0e45ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
71429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1733071429
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3356572747
Short name T786
Test name
Test status
Simulation time 8439368077 ps
CPU time 7.65 seconds
Started May 02 03:46:34 PM PDT 24
Finished May 02 03:46:43 PM PDT 24
Peak memory 204108 kb
Host smart-fe47bca1-95e6-4387-a8ff-78ed65a12409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
72747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3356572747
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.341448515
Short name T765
Test name
Test status
Simulation time 8379305988 ps
CPU time 8.38 seconds
Started May 02 03:46:27 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204100 kb
Host smart-44c49ca8-1abf-4d85-8279-c6bac6d91e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34144
8515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.341448515
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2072230036
Short name T948
Test name
Test status
Simulation time 8374002421 ps
CPU time 9.26 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204072 kb
Host smart-c80999a4-d187-431f-96af-8e60f3a9d916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722
30036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2072230036
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3147772227
Short name T164
Test name
Test status
Simulation time 8470276174 ps
CPU time 10.08 seconds
Started May 02 03:46:24 PM PDT 24
Finished May 02 03:46:37 PM PDT 24
Peak memory 204144 kb
Host smart-91c3eb70-1007-4bca-a79e-9ae9eb324f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
72227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3147772227
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.20892994
Short name T1296
Test name
Test status
Simulation time 8397294305 ps
CPU time 8.23 seconds
Started May 02 03:46:31 PM PDT 24
Finished May 02 03:46:40 PM PDT 24
Peak memory 204060 kb
Host smart-66f2eea7-3d77-4b46-8738-b730a66eca0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20892
994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.20892994
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.92387298
Short name T1029
Test name
Test status
Simulation time 8435768161 ps
CPU time 7.53 seconds
Started May 02 03:46:26 PM PDT 24
Finished May 02 03:46:35 PM PDT 24
Peak memory 204132 kb
Host smart-308f4a99-cddc-4bd5-bc49-a83e8984df2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92387
298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.92387298
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.27108004
Short name T986
Test name
Test status
Simulation time 8463724519 ps
CPU time 7.96 seconds
Started May 02 03:46:31 PM PDT 24
Finished May 02 03:46:40 PM PDT 24
Peak memory 204080 kb
Host smart-c355446b-f664-4a0b-bd66-9609561e915e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=27108004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.27108004
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.801445771
Short name T1227
Test name
Test status
Simulation time 8378327734 ps
CPU time 7.87 seconds
Started May 02 03:46:47 PM PDT 24
Finished May 02 03:46:56 PM PDT 24
Peak memory 204132 kb
Host smart-33ff4550-ddf4-4620-b0a2-33dacaf4244c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=801445771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.801445771
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.1324017714
Short name T942
Test name
Test status
Simulation time 8457823882 ps
CPU time 8.52 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204120 kb
Host smart-d32fb5a1-a3ae-48f5-bc10-036c6de578f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13240
17714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.1324017714
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.370283018
Short name T1059
Test name
Test status
Simulation time 8392718460 ps
CPU time 7.71 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:39 PM PDT 24
Peak memory 204112 kb
Host smart-1cc3d9e6-6188-49d0-b10b-f6893e5ee9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37028
3018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.370283018
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.2391416746
Short name T1025
Test name
Test status
Simulation time 8378609328 ps
CPU time 7.64 seconds
Started May 02 03:46:29 PM PDT 24
Finished May 02 03:46:38 PM PDT 24
Peak memory 204116 kb
Host smart-76cadcbc-061d-4803-a984-2d64951e26b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23914
16746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2391416746
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2322095105
Short name T773
Test name
Test status
Simulation time 58998551 ps
CPU time 1.62 seconds
Started May 02 03:46:29 PM PDT 24
Finished May 02 03:46:32 PM PDT 24
Peak memory 204144 kb
Host smart-3f640855-3728-4f9e-bab9-36515102ed1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23220
95105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2322095105
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1415427460
Short name T724
Test name
Test status
Simulation time 8408560230 ps
CPU time 7.86 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204132 kb
Host smart-3a46440d-0bd5-4e88-ba99-be6235d89a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
27460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1415427460
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2947557560
Short name T921
Test name
Test status
Simulation time 8387957809 ps
CPU time 9.33 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:40 PM PDT 24
Peak memory 204096 kb
Host smart-e4f1f30f-6af7-46e8-a671-f00ad727b423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29475
57560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2947557560
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2457318090
Short name T1130
Test name
Test status
Simulation time 8460204706 ps
CPU time 7.96 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204140 kb
Host smart-9cd75729-1eba-4b57-a10b-09edb56bdd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
18090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2457318090
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1172234582
Short name T347
Test name
Test status
Simulation time 8423745538 ps
CPU time 8.21 seconds
Started May 02 03:46:38 PM PDT 24
Finished May 02 03:46:47 PM PDT 24
Peak memory 204080 kb
Host smart-38b58d69-c3f8-4202-91db-eaed22bd108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
34582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1172234582
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2477134791
Short name T776
Test name
Test status
Simulation time 8373528483 ps
CPU time 7.77 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204132 kb
Host smart-055ce617-bba7-44ad-879d-75f345accf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24771
34791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2477134791
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3251230054
Short name T812
Test name
Test status
Simulation time 8476112458 ps
CPU time 7.59 seconds
Started May 02 03:46:37 PM PDT 24
Finished May 02 03:46:46 PM PDT 24
Peak memory 204016 kb
Host smart-11f3ac68-dbbe-46c8-b13a-1f6e5e51f967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
30054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3251230054
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2143093136
Short name T594
Test name
Test status
Simulation time 8447348813 ps
CPU time 7.83 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204136 kb
Host smart-c3df2917-9611-4f1d-ae8e-567dac5bbec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21430
93136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2143093136
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1306986889
Short name T735
Test name
Test status
Simulation time 8385275289 ps
CPU time 8 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:50 PM PDT 24
Peak memory 204148 kb
Host smart-eb245aac-06a1-452c-8513-0487b8ddfbb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13069
86889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1306986889
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.19736911
Short name T1224
Test name
Test status
Simulation time 8414972281 ps
CPU time 9.63 seconds
Started May 02 03:46:33 PM PDT 24
Finished May 02 03:46:43 PM PDT 24
Peak memory 204096 kb
Host smart-2f0df22b-71f4-4fca-aa05-0df1202610b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19736
911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.19736911
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.445957788
Short name T532
Test name
Test status
Simulation time 8394966656 ps
CPU time 7.97 seconds
Started May 02 03:46:32 PM PDT 24
Finished May 02 03:46:41 PM PDT 24
Peak memory 204112 kb
Host smart-839de6ae-f781-4c05-9675-d36411c796c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44595
7788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.445957788
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.4089118489
Short name T51
Test name
Test status
Simulation time 82328105 ps
CPU time 0.69 seconds
Started May 02 03:46:44 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204024 kb
Host smart-f9068410-624f-471a-921d-20e1735ca95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40891
18489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.4089118489
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3143437877
Short name T1146
Test name
Test status
Simulation time 17380358268 ps
CPU time 30.76 seconds
Started May 02 03:46:34 PM PDT 24
Finished May 02 03:47:06 PM PDT 24
Peak memory 204384 kb
Host smart-666c2b31-a1a9-4ad7-9750-c1c141c14a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31434
37877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3143437877
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.531186607
Short name T222
Test name
Test status
Simulation time 8393831326 ps
CPU time 7.64 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204108 kb
Host smart-5ac80c1c-e0b3-49a8-ac94-61a3067097ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53118
6607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.531186607
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1114303491
Short name T1383
Test name
Test status
Simulation time 8436170889 ps
CPU time 8.1 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204140 kb
Host smart-ef8a21fc-ce94-48eb-bc21-6af1e739bfa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11143
03491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1114303491
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.3795350585
Short name T467
Test name
Test status
Simulation time 8378575714 ps
CPU time 7.56 seconds
Started May 02 03:46:47 PM PDT 24
Finished May 02 03:46:56 PM PDT 24
Peak memory 204132 kb
Host smart-a5cd2607-8d7a-436d-a320-40495fc4e9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37953
50585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.3795350585
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.133301033
Short name T173
Test name
Test status
Simulation time 8377104361 ps
CPU time 8.03 seconds
Started May 02 03:46:31 PM PDT 24
Finished May 02 03:46:40 PM PDT 24
Peak memory 204112 kb
Host smart-ca87c190-8939-48de-b7b3-819663b4146f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13330
1033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.133301033
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2489077613
Short name T1137
Test name
Test status
Simulation time 8370143751 ps
CPU time 8.05 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204128 kb
Host smart-772a4828-ecdc-411f-805e-69d3e87ae5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890
77613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2489077613
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.520779032
Short name T576
Test name
Test status
Simulation time 8429078844 ps
CPU time 10.51 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204132 kb
Host smart-342ec445-b451-474d-8f12-7757bf535472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52077
9032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.520779032
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.258466280
Short name T1102
Test name
Test status
Simulation time 8390309089 ps
CPU time 8.31 seconds
Started May 02 03:46:35 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204068 kb
Host smart-be358e6b-1f89-48c4-a97b-e30386edcadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25846
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.258466280
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2804991952
Short name T1106
Test name
Test status
Simulation time 8387327619 ps
CPU time 10.45 seconds
Started May 02 03:46:38 PM PDT 24
Finished May 02 03:46:49 PM PDT 24
Peak memory 204072 kb
Host smart-5c5afd10-1fbb-4f25-9d65-9424e935a77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28049
91952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2804991952
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2141384850
Short name T824
Test name
Test status
Simulation time 8466868193 ps
CPU time 7.57 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204156 kb
Host smart-1dfd557c-ff62-432e-833c-e4b77baf068a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2141384850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2141384850
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3547836444
Short name T950
Test name
Test status
Simulation time 8407067513 ps
CPU time 8.41 seconds
Started May 02 03:46:44 PM PDT 24
Finished May 02 03:46:53 PM PDT 24
Peak memory 204048 kb
Host smart-46b92efc-e34f-4417-b627-8c228106680e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3547836444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3547836444
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.1801780781
Short name T248
Test name
Test status
Simulation time 8441869019 ps
CPU time 8.49 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:00 PM PDT 24
Peak memory 204128 kb
Host smart-2c3b67ab-f3dc-4416-bee1-66dc0fc5a1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18017
80781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.1801780781
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1905236158
Short name T880
Test name
Test status
Simulation time 8374727077 ps
CPU time 7.65 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204076 kb
Host smart-a5201673-542b-41bb-9f68-e786eed23d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19052
36158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1905236158
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.3380304536
Short name T324
Test name
Test status
Simulation time 8379284018 ps
CPU time 10.21 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204132 kb
Host smart-b9888d57-baa2-4ab1-a963-67485022777b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803
04536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3380304536
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2416993771
Short name T57
Test name
Test status
Simulation time 95264617 ps
CPU time 1.15 seconds
Started May 02 03:46:51 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204200 kb
Host smart-c6aa5e6c-cb54-45ea-b9d8-64a444a0797e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24169
93771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2416993771
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3937597260
Short name T1141
Test name
Test status
Simulation time 8437318477 ps
CPU time 8.04 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:56 PM PDT 24
Peak memory 204128 kb
Host smart-a47d7e92-c055-4ee2-ad66-647f8a8767ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375
97260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3937597260
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.180743248
Short name T1004
Test name
Test status
Simulation time 8404764443 ps
CPU time 7.32 seconds
Started May 02 03:46:40 PM PDT 24
Finished May 02 03:46:48 PM PDT 24
Peak memory 204100 kb
Host smart-b73a7cc5-25d6-49bf-8d3b-daa8086cddd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18074
3248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.180743248
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1702509388
Short name T816
Test name
Test status
Simulation time 8480983808 ps
CPU time 8.55 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204128 kb
Host smart-3a6d8a6d-0a90-4530-ba82-69b7bc6956ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17025
09388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1702509388
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3753232089
Short name T599
Test name
Test status
Simulation time 8414874871 ps
CPU time 8.26 seconds
Started May 02 03:46:45 PM PDT 24
Finished May 02 03:46:54 PM PDT 24
Peak memory 204140 kb
Host smart-13c7459b-7095-45c1-8efd-676ea95c858c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37532
32089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3753232089
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.137360208
Short name T833
Test name
Test status
Simulation time 8367984618 ps
CPU time 8.11 seconds
Started May 02 03:46:46 PM PDT 24
Finished May 02 03:46:55 PM PDT 24
Peak memory 204124 kb
Host smart-7485c5be-a8d2-49cd-bf28-9a098cb9543f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736
0208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.137360208
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2548819519
Short name T1053
Test name
Test status
Simulation time 8429630867 ps
CPU time 8.69 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:00 PM PDT 24
Peak memory 204140 kb
Host smart-c0b82fac-18fb-474a-be89-dd0b195f2dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25488
19519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2548819519
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1029628967
Short name T220
Test name
Test status
Simulation time 8411798091 ps
CPU time 9.76 seconds
Started May 02 03:46:37 PM PDT 24
Finished May 02 03:46:48 PM PDT 24
Peak memory 204016 kb
Host smart-34761d01-dff0-4ec3-8238-22bd32e776cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10296
28967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1029628967
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.941762767
Short name T469
Test name
Test status
Simulation time 8411591831 ps
CPU time 8.04 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:00 PM PDT 24
Peak memory 204068 kb
Host smart-0e440b6d-c395-4ac6-8559-e29661cd71b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94176
2767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.941762767
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1746441312
Short name T1281
Test name
Test status
Simulation time 8498891650 ps
CPU time 8.96 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:47 PM PDT 24
Peak memory 204048 kb
Host smart-bb7ea9ad-7609-41d6-ab65-411c01b48cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17464
41312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1746441312
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.424313987
Short name T1293
Test name
Test status
Simulation time 33115219 ps
CPU time 0.67 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:38 PM PDT 24
Peak memory 203964 kb
Host smart-bae1be1c-047f-4d9f-b98c-473838308a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42431
3987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.424313987
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2683615222
Short name T952
Test name
Test status
Simulation time 28373290664 ps
CPU time 54.5 seconds
Started May 02 03:46:31 PM PDT 24
Finished May 02 03:47:26 PM PDT 24
Peak memory 204396 kb
Host smart-992d3565-61cc-4f2d-92c3-3f5326f1c464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
15222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2683615222
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1391193969
Short name T1369
Test name
Test status
Simulation time 8403068851 ps
CPU time 7.45 seconds
Started May 02 03:46:31 PM PDT 24
Finished May 02 03:46:40 PM PDT 24
Peak memory 204088 kb
Host smart-6674a06d-4f97-434d-8b3a-8d0002dce4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
93969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1391193969
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2852685969
Short name T811
Test name
Test status
Simulation time 8393398574 ps
CPU time 7.67 seconds
Started May 02 03:46:30 PM PDT 24
Finished May 02 03:46:39 PM PDT 24
Peak memory 204036 kb
Host smart-d9a2fd53-752b-414d-ac56-8ba2ed8cf11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28526
85969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2852685969
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2484905338
Short name T355
Test name
Test status
Simulation time 8402893203 ps
CPU time 9.11 seconds
Started May 02 03:46:39 PM PDT 24
Finished May 02 03:46:49 PM PDT 24
Peak memory 204096 kb
Host smart-a191f0c0-d4f0-4ce5-909f-beb6edef986d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24849
05338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2484905338
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2625712501
Short name T917
Test name
Test status
Simulation time 8375117801 ps
CPU time 7.85 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:00 PM PDT 24
Peak memory 204136 kb
Host smart-2bb6d0fd-2592-476e-a17f-99f5fced8460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26257
12501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2625712501
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.324167311
Short name T1239
Test name
Test status
Simulation time 8367982263 ps
CPU time 8.66 seconds
Started May 02 03:46:45 PM PDT 24
Finished May 02 03:46:54 PM PDT 24
Peak memory 204132 kb
Host smart-ef6633a0-9c3a-4f84-8913-b020498c9fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32416
7311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.324167311
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3893481985
Short name T1340
Test name
Test status
Simulation time 8459635683 ps
CPU time 10.49 seconds
Started May 02 03:46:34 PM PDT 24
Finished May 02 03:46:46 PM PDT 24
Peak memory 204092 kb
Host smart-7d131c28-36ab-4c47-9b73-e91d155b8468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934
81985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3893481985
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1635926888
Short name T436
Test name
Test status
Simulation time 8411413525 ps
CPU time 9.3 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:47:00 PM PDT 24
Peak memory 204132 kb
Host smart-a1556eff-6c8e-4ec5-80c5-96b203273b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16359
26888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1635926888
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.583777592
Short name T1330
Test name
Test status
Simulation time 8394860966 ps
CPU time 7.57 seconds
Started May 02 03:46:38 PM PDT 24
Finished May 02 03:46:46 PM PDT 24
Peak memory 204100 kb
Host smart-0ba0f522-6170-44fa-8260-e65758fff9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58377
7592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.583777592
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3613575230
Short name T510
Test name
Test status
Simulation time 8468636877 ps
CPU time 8.35 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204088 kb
Host smart-1779b300-3c2e-481f-918a-ad39607b5227
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3613575230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3613575230
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2666960569
Short name T727
Test name
Test status
Simulation time 8380942719 ps
CPU time 8.56 seconds
Started May 02 03:46:55 PM PDT 24
Finished May 02 03:47:05 PM PDT 24
Peak memory 204168 kb
Host smart-730fc52a-04e8-406b-965b-391e34ae2c83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2666960569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2666960569
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2164788009
Short name T779
Test name
Test status
Simulation time 8404546768 ps
CPU time 7.68 seconds
Started May 02 03:46:54 PM PDT 24
Finished May 02 03:47:04 PM PDT 24
Peak memory 204032 kb
Host smart-a6d2564b-22f0-4bb1-8be3-1b3b7d22c4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647
88009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2164788009
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2167849474
Short name T731
Test name
Test status
Simulation time 8381077137 ps
CPU time 7.84 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204156 kb
Host smart-0cdd152f-9e3f-4adc-95ca-1f710d2b3a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21678
49474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2167849474
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.3061011772
Short name T521
Test name
Test status
Simulation time 8385453007 ps
CPU time 8.17 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:50 PM PDT 24
Peak memory 204072 kb
Host smart-5a0ba79f-cbb6-4c50-99fe-0605d890d553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30610
11772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3061011772
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.299111087
Short name T1267
Test name
Test status
Simulation time 155786459 ps
CPU time 1.52 seconds
Started May 02 03:46:43 PM PDT 24
Finished May 02 03:46:45 PM PDT 24
Peak memory 204256 kb
Host smart-72101576-a918-4a7a-b01b-6a31622b7151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29911
1087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.299111087
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.712472943
Short name T478
Test name
Test status
Simulation time 8453525965 ps
CPU time 8.4 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204092 kb
Host smart-b68d3ee9-8f94-4214-b79c-82f0842aa23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71247
2943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.712472943
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1956973976
Short name T871
Test name
Test status
Simulation time 8444594250 ps
CPU time 8.2 seconds
Started May 02 03:46:39 PM PDT 24
Finished May 02 03:46:48 PM PDT 24
Peak memory 204124 kb
Host smart-0180a85b-b4ec-43f6-a37d-da4569fb4e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569
73976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1956973976
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2611633872
Short name T617
Test name
Test status
Simulation time 8426403319 ps
CPU time 9.97 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204040 kb
Host smart-c9bee565-442e-4c0b-bdf1-81aba85575e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
33872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2611633872
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2035610584
Short name T743
Test name
Test status
Simulation time 8377126166 ps
CPU time 9.03 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204140 kb
Host smart-da22100d-15b5-4e5b-96a6-3dd3321ff83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20356
10584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2035610584
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2491705857
Short name T125
Test name
Test status
Simulation time 8440842616 ps
CPU time 7.46 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204136 kb
Host smart-34ab519e-86c7-42dc-9567-0dc29fbbdc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24917
05857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2491705857
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2629798420
Short name T15
Test name
Test status
Simulation time 8409093983 ps
CPU time 9.24 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:47 PM PDT 24
Peak memory 204112 kb
Host smart-cf21f8e5-bd9f-4383-a175-d9ed11a0c757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26297
98420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2629798420
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2856622122
Short name T961
Test name
Test status
Simulation time 8393290542 ps
CPU time 8.58 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:47 PM PDT 24
Peak memory 204132 kb
Host smart-02bcae2a-7622-4f5b-aa54-d69fda35c5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
22122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2856622122
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.840275568
Short name T708
Test name
Test status
Simulation time 8408190157 ps
CPU time 9.51 seconds
Started May 02 03:46:33 PM PDT 24
Finished May 02 03:46:44 PM PDT 24
Peak memory 204084 kb
Host smart-4408e22d-34ce-4546-83e9-f223730da5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84027
5568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.840275568
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2182260764
Short name T1079
Test name
Test status
Simulation time 8367576960 ps
CPU time 9.78 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204120 kb
Host smart-8f3ab3a7-7896-4a40-963a-b22ecf8a5e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21822
60764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2182260764
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3643351086
Short name T790
Test name
Test status
Simulation time 44156848 ps
CPU time 0.67 seconds
Started May 02 03:46:53 PM PDT 24
Finished May 02 03:46:57 PM PDT 24
Peak memory 204012 kb
Host smart-a58dcb6a-a9d2-4f40-bb61-80007555ce7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36433
51086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3643351086
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3552572531
Short name T229
Test name
Test status
Simulation time 28062960775 ps
CPU time 52.84 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:47:31 PM PDT 24
Peak memory 204424 kb
Host smart-266ba4c4-bc5e-47c5-ab01-a7f6a5e5938f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525
72531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3552572531
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1590445632
Short name T999
Test name
Test status
Simulation time 8393252068 ps
CPU time 8.44 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204128 kb
Host smart-adcb7e1e-c9fe-40fe-ac6b-ac522f16d07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15904
45632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1590445632
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3823413061
Short name T745
Test name
Test status
Simulation time 8408367555 ps
CPU time 7.49 seconds
Started May 02 03:46:51 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204068 kb
Host smart-4319a259-4c92-432c-a076-5321ff9307ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38234
13061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3823413061
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2388694643
Short name T1027
Test name
Test status
Simulation time 8392439487 ps
CPU time 8.4 seconds
Started May 02 03:46:36 PM PDT 24
Finished May 02 03:46:47 PM PDT 24
Peak memory 204072 kb
Host smart-5ef6f8d1-a3a8-42b2-8c13-732f49251be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23886
94643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2388694643
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2236659286
Short name T1372
Test name
Test status
Simulation time 8379191766 ps
CPU time 7.71 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204140 kb
Host smart-36ead823-73b4-4981-8abf-924104f866d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
59286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2236659286
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.105132120
Short name T1186
Test name
Test status
Simulation time 8437106022 ps
CPU time 7.88 seconds
Started May 02 03:46:34 PM PDT 24
Finished May 02 03:46:44 PM PDT 24
Peak memory 204132 kb
Host smart-c9b7ee14-2620-4ca4-b7bb-52b4f9ad5c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10513
2120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.105132120
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2367652663
Short name T577
Test name
Test status
Simulation time 8475575160 ps
CPU time 10 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:47:00 PM PDT 24
Peak memory 204136 kb
Host smart-6194333b-0b53-404e-80e5-14ef5baab2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676
52663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2367652663
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.4163925572
Short name T626
Test name
Test status
Simulation time 8405259265 ps
CPU time 8.29 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204032 kb
Host smart-5957d0f6-4f30-415f-af13-22d30599850b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41639
25572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.4163925572
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.85783591
Short name T1310
Test name
Test status
Simulation time 8393212910 ps
CPU time 10.17 seconds
Started May 02 03:46:48 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204076 kb
Host smart-744e46a4-fc5f-4d29-8714-40b076c53027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85783
591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.85783591
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.4003491873
Short name T369
Test name
Test status
Simulation time 8472022311 ps
CPU time 7.47 seconds
Started May 02 03:44:54 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204068 kb
Host smart-eca6082d-def7-4068-9e2e-6a63929999a8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4003491873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.4003491873
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.796978759
Short name T721
Test name
Test status
Simulation time 8383960292 ps
CPU time 7.97 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:02 PM PDT 24
Peak memory 204116 kb
Host smart-1fde937f-0947-4178-b20f-b004c3e8b841
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=796978759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.796978759
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.4285761517
Short name T154
Test name
Test status
Simulation time 8449805034 ps
CPU time 7.71 seconds
Started May 02 03:44:51 PM PDT 24
Finished May 02 03:45:00 PM PDT 24
Peak memory 204120 kb
Host smart-4a36e3ff-6bff-47b4-a04a-3e3090efec69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42857
61517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.4285761517
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3800126903
Short name T618
Test name
Test status
Simulation time 8377632979 ps
CPU time 9.4 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204136 kb
Host smart-bac0f86d-bbb4-4746-875d-e2c1052f8068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
26903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3800126903
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.359740182
Short name T656
Test name
Test status
Simulation time 8382958617 ps
CPU time 8.86 seconds
Started May 02 03:44:41 PM PDT 24
Finished May 02 03:44:51 PM PDT 24
Peak memory 204100 kb
Host smart-2087c84e-49a2-45a3-bd6c-d9359b457103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35974
0182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.359740182
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.4021739670
Short name T468
Test name
Test status
Simulation time 133420568 ps
CPU time 1.63 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:44:57 PM PDT 24
Peak memory 204196 kb
Host smart-657de37d-2166-4ea3-925b-071dc9a445f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40217
39670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.4021739670
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.4242748778
Short name T452
Test name
Test status
Simulation time 8435450817 ps
CPU time 10.21 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204028 kb
Host smart-d85a896a-6789-4665-9163-02e87cf2c214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
48778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.4242748778
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.380693569
Short name T186
Test name
Test status
Simulation time 8369305688 ps
CPU time 9.79 seconds
Started May 02 03:44:48 PM PDT 24
Finished May 02 03:44:59 PM PDT 24
Peak memory 204060 kb
Host smart-159756c8-3e3e-46ff-87c3-931446916521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38069
3569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.380693569
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3115461687
Short name T155
Test name
Test status
Simulation time 8435107950 ps
CPU time 7.58 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204004 kb
Host smart-f09daa53-9cfb-4faa-9d24-b3235a0b127b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31154
61687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3115461687
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3938050081
Short name T605
Test name
Test status
Simulation time 8418171485 ps
CPU time 7.38 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204128 kb
Host smart-8df717da-50f4-474b-8114-e166a012cbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
50081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3938050081
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2337448338
Short name T651
Test name
Test status
Simulation time 8379572171 ps
CPU time 8.43 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:52 PM PDT 24
Peak memory 204060 kb
Host smart-62afdc21-6279-494e-876c-1e0c52a24fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374
48338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2337448338
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1280206442
Short name T115
Test name
Test status
Simulation time 8396140317 ps
CPU time 10.16 seconds
Started May 02 03:44:42 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204076 kb
Host smart-54be93e3-2164-444a-9c6e-b13e2b02b2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
06442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1280206442
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.553730392
Short name T399
Test name
Test status
Simulation time 8420463419 ps
CPU time 8.94 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:55 PM PDT 24
Peak memory 204120 kb
Host smart-e1cd6550-5c0a-4cc8-b67b-08f0cdd3f1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55373
0392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.553730392
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.971748879
Short name T1327
Test name
Test status
Simulation time 8404605452 ps
CPU time 8.78 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204064 kb
Host smart-b7d7b5bc-fa86-4885-9140-2ad91be7748a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97174
8879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.971748879
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1259662132
Short name T807
Test name
Test status
Simulation time 8430505612 ps
CPU time 9.74 seconds
Started May 02 03:44:47 PM PDT 24
Finished May 02 03:44:58 PM PDT 24
Peak memory 204076 kb
Host smart-e62039d8-15fc-42d3-9b74-728cbba78299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12596
62132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1259662132
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3576604403
Short name T473
Test name
Test status
Simulation time 8376286802 ps
CPU time 8.45 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204128 kb
Host smart-0ddababb-af3e-4194-a54b-fb060bc24388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
04403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3576604403
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3085570012
Short name T714
Test name
Test status
Simulation time 70988911 ps
CPU time 0.75 seconds
Started May 02 03:44:51 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204032 kb
Host smart-6cad87e4-25ba-443c-8fc7-c29229c79494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30855
70012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3085570012
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2843999392
Short name T944
Test name
Test status
Simulation time 24144735278 ps
CPU time 46.84 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:45:32 PM PDT 24
Peak memory 204316 kb
Host smart-751ac7b1-97bb-4569-9bbd-663d44649e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28439
99392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2843999392
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2682869501
Short name T56
Test name
Test status
Simulation time 8416501624 ps
CPU time 7.65 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204100 kb
Host smart-03eec46a-42f1-43d3-a9df-0c36d82e7df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26828
69501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2682869501
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2330948861
Short name T694
Test name
Test status
Simulation time 8427997562 ps
CPU time 7.73 seconds
Started May 02 03:44:46 PM PDT 24
Finished May 02 03:44:55 PM PDT 24
Peak memory 204060 kb
Host smart-7a7130a2-15de-45f4-b828-d4eebc798832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
48861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2330948861
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2915708065
Short name T729
Test name
Test status
Simulation time 8403713956 ps
CPU time 7.56 seconds
Started May 02 03:44:45 PM PDT 24
Finished May 02 03:44:53 PM PDT 24
Peak memory 204072 kb
Host smart-c6a1713b-ac14-4a2e-b81c-8d6c1e5f2d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29157
08065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2915708065
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2896494175
Short name T82
Test name
Test status
Simulation time 331078323 ps
CPU time 1.17 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:44:58 PM PDT 24
Peak memory 220308 kb
Host smart-3e700639-eb2d-4884-9c67-63fa7b15166f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2896494175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2896494175
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2976576977
Short name T823
Test name
Test status
Simulation time 8373384544 ps
CPU time 9.06 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204088 kb
Host smart-168b6623-2e07-43f2-af3c-e81fb141ba9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29765
76977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2976576977
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2944181782
Short name T302
Test name
Test status
Simulation time 8364543930 ps
CPU time 8.55 seconds
Started May 02 03:44:44 PM PDT 24
Finished May 02 03:44:54 PM PDT 24
Peak memory 204120 kb
Host smart-7c0cac2c-5864-4c47-871e-937cad9b9ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
81782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2944181782
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1858995057
Short name T519
Test name
Test status
Simulation time 8428155419 ps
CPU time 8.7 seconds
Started May 02 03:44:47 PM PDT 24
Finished May 02 03:44:57 PM PDT 24
Peak memory 204108 kb
Host smart-41a9278f-4fb9-4eda-b973-04650951ffa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18589
95057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1858995057
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3627870785
Short name T878
Test name
Test status
Simulation time 8384509383 ps
CPU time 8.31 seconds
Started May 02 03:44:47 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204140 kb
Host smart-31bf0e86-c217-4459-a635-60ad8dfcc4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
70785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3627870785
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2141023718
Short name T596
Test name
Test status
Simulation time 8398597997 ps
CPU time 7.63 seconds
Started May 02 03:44:43 PM PDT 24
Finished May 02 03:44:51 PM PDT 24
Peak memory 204168 kb
Host smart-50ceae77-4d97-437a-9782-abb644853daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21410
23718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2141023718
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1128708184
Short name T1022
Test name
Test status
Simulation time 8468404052 ps
CPU time 7.9 seconds
Started May 02 03:47:03 PM PDT 24
Finished May 02 03:47:13 PM PDT 24
Peak memory 204124 kb
Host smart-21a2eb75-f8af-4ea4-91d7-2ec4867419df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1128708184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1128708184
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3637449423
Short name T21
Test name
Test status
Simulation time 8373995774 ps
CPU time 7.6 seconds
Started May 02 03:47:01 PM PDT 24
Finished May 02 03:47:10 PM PDT 24
Peak memory 204140 kb
Host smart-b0734f4f-075b-4f76-bcbe-5702ac8e013b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3637449423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3637449423
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3720109293
Short name T323
Test name
Test status
Simulation time 8410454876 ps
CPU time 7.54 seconds
Started May 02 03:46:57 PM PDT 24
Finished May 02 03:47:06 PM PDT 24
Peak memory 204108 kb
Host smart-7cd2cfb7-a556-469f-952a-b9356d490ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37201
09293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3720109293
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3560267566
Short name T958
Test name
Test status
Simulation time 8374363687 ps
CPU time 8.75 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204088 kb
Host smart-6dd2cb45-5333-4682-8e71-3c9d6687d345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35602
67566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3560267566
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.2514738088
Short name T461
Test name
Test status
Simulation time 8400234090 ps
CPU time 7.44 seconds
Started May 02 03:46:40 PM PDT 24
Finished May 02 03:46:49 PM PDT 24
Peak memory 204092 kb
Host smart-a573c0d6-8e77-4ad4-a101-ba80cbf9236a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25147
38088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2514738088
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4070933309
Short name T614
Test name
Test status
Simulation time 193051413 ps
CPU time 2.07 seconds
Started May 02 03:46:41 PM PDT 24
Finished May 02 03:46:44 PM PDT 24
Peak memory 204232 kb
Host smart-2855436a-2128-47d3-bd0c-2ffd5e475f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40709
33309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4070933309
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3306149808
Short name T720
Test name
Test status
Simulation time 8400568107 ps
CPU time 8.12 seconds
Started May 02 03:46:53 PM PDT 24
Finished May 02 03:47:03 PM PDT 24
Peak memory 204100 kb
Host smart-7f959b6a-20c5-46d9-8198-35650f00a329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33061
49808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3306149808
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1499221227
Short name T4
Test name
Test status
Simulation time 8369367146 ps
CPU time 9.39 seconds
Started May 02 03:46:57 PM PDT 24
Finished May 02 03:47:08 PM PDT 24
Peak memory 204060 kb
Host smart-1558c180-cb17-469d-ae62-9b07b05ed460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14992
21227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1499221227
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2512885758
Short name T1343
Test name
Test status
Simulation time 8443251100 ps
CPU time 8.53 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204128 kb
Host smart-422c8d5b-1a57-4151-9824-e649d06c4da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25128
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2512885758
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.880739664
Short name T1093
Test name
Test status
Simulation time 8419039658 ps
CPU time 8.1 seconds
Started May 02 03:46:52 PM PDT 24
Finished May 02 03:47:03 PM PDT 24
Peak memory 204108 kb
Host smart-f512d576-4f3a-425f-8466-7bda39a4e35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88073
9664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.880739664
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1938582302
Short name T693
Test name
Test status
Simulation time 8369940832 ps
CPU time 8.45 seconds
Started May 02 03:46:55 PM PDT 24
Finished May 02 03:47:05 PM PDT 24
Peak memory 204044 kb
Host smart-edf914db-567b-4575-af57-77d66524c4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19385
82302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1938582302
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.984281721
Short name T120
Test name
Test status
Simulation time 8443605129 ps
CPU time 9.84 seconds
Started May 02 03:46:57 PM PDT 24
Finished May 02 03:47:08 PM PDT 24
Peak memory 204132 kb
Host smart-08977cca-4de5-4234-a290-412f76877720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98428
1721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.984281721
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2622243730
Short name T1132
Test name
Test status
Simulation time 8408695493 ps
CPU time 8.22 seconds
Started May 02 03:46:58 PM PDT 24
Finished May 02 03:47:08 PM PDT 24
Peak memory 204136 kb
Host smart-17a5903b-d351-4188-8c4d-fe9e0aa9d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
43730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2622243730
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3661692517
Short name T1270
Test name
Test status
Simulation time 8388969707 ps
CPU time 9.02 seconds
Started May 02 03:47:03 PM PDT 24
Finished May 02 03:47:14 PM PDT 24
Peak memory 204132 kb
Host smart-4f93ce78-fbe8-4c08-af8a-2987cfc1f2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36616
92517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3661692517
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2926578532
Short name T1322
Test name
Test status
Simulation time 8496104473 ps
CPU time 9.63 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204096 kb
Host smart-3b475381-c558-4de1-bf53-9d0d5cbecd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29265
78532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2926578532
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2354904133
Short name T1069
Test name
Test status
Simulation time 8370281349 ps
CPU time 7.54 seconds
Started May 02 03:46:55 PM PDT 24
Finished May 02 03:47:05 PM PDT 24
Peak memory 204120 kb
Host smart-378afd73-f96a-48a9-9785-e034fd9028bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
04133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2354904133
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1101160944
Short name T40
Test name
Test status
Simulation time 40797756 ps
CPU time 0.67 seconds
Started May 02 03:46:59 PM PDT 24
Finished May 02 03:47:01 PM PDT 24
Peak memory 204000 kb
Host smart-5c155126-02ac-475d-a269-1e1835327c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
60944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1101160944
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1913021926
Short name T976
Test name
Test status
Simulation time 8425227542 ps
CPU time 9.65 seconds
Started May 02 03:47:01 PM PDT 24
Finished May 02 03:47:13 PM PDT 24
Peak memory 204132 kb
Host smart-71eb2d56-9cfd-4daa-b1f8-f1a46fc7827b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19130
21926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1913021926
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2308860459
Short name T1236
Test name
Test status
Simulation time 8444858440 ps
CPU time 7.59 seconds
Started May 02 03:46:49 PM PDT 24
Finished May 02 03:46:59 PM PDT 24
Peak memory 204100 kb
Host smart-45fa1b61-3935-4df7-8d85-3c86146dcbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23088
60459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2308860459
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1238251518
Short name T1113
Test name
Test status
Simulation time 8393776123 ps
CPU time 8.31 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204060 kb
Host smart-5837f94d-32b7-48f8-8879-5e9a34dab983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
51518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1238251518
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1778360819
Short name T353
Test name
Test status
Simulation time 8375343439 ps
CPU time 8.74 seconds
Started May 02 03:46:54 PM PDT 24
Finished May 02 03:47:05 PM PDT 24
Peak memory 204104 kb
Host smart-83705b43-9f22-4a64-9aab-7ae15838a6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17783
60819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1778360819
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1418497604
Short name T451
Test name
Test status
Simulation time 8376903873 ps
CPU time 7.47 seconds
Started May 02 03:46:56 PM PDT 24
Finished May 02 03:47:05 PM PDT 24
Peak memory 204144 kb
Host smart-213ee0a1-1c7c-4282-a1f1-0bc1bbba07f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14184
97604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1418497604
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1667788942
Short name T867
Test name
Test status
Simulation time 8449045906 ps
CPU time 10.2 seconds
Started May 02 03:46:50 PM PDT 24
Finished May 02 03:47:03 PM PDT 24
Peak memory 204040 kb
Host smart-3f84127d-c69f-4b57-9b29-5efc41a78cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
88942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1667788942
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3887201044
Short name T678
Test name
Test status
Simulation time 8438556260 ps
CPU time 9.81 seconds
Started May 02 03:46:51 PM PDT 24
Finished May 02 03:47:04 PM PDT 24
Peak memory 204104 kb
Host smart-833e3939-f9d4-42f3-998f-aad9b57264c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38872
01044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3887201044
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1717385291
Short name T412
Test name
Test status
Simulation time 8388125164 ps
CPU time 8.26 seconds
Started May 02 03:46:53 PM PDT 24
Finished May 02 03:47:04 PM PDT 24
Peak memory 204168 kb
Host smart-5784dde2-b495-4d39-949e-92f07aeb056d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17173
85291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1717385291
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.4175389559
Short name T815
Test name
Test status
Simulation time 8464642714 ps
CPU time 8.1 seconds
Started May 02 03:47:10 PM PDT 24
Finished May 02 03:47:19 PM PDT 24
Peak memory 204132 kb
Host smart-81bed24e-7bbb-49af-bc0a-475a87587c74
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4175389559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.4175389559
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.3509843401
Short name T1355
Test name
Test status
Simulation time 8378717024 ps
CPU time 10.35 seconds
Started May 02 03:47:30 PM PDT 24
Finished May 02 03:47:41 PM PDT 24
Peak memory 204160 kb
Host smart-04e0165e-b694-465c-9c25-ad3a58c1f057
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3509843401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.3509843401
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2740569279
Short name T787
Test name
Test status
Simulation time 8442415161 ps
CPU time 8.18 seconds
Started May 02 03:47:08 PM PDT 24
Finished May 02 03:47:17 PM PDT 24
Peak memory 204144 kb
Host smart-4ec458a0-d77e-4ad7-8acb-c74763b4e5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27405
69279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2740569279
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1280526736
Short name T696
Test name
Test status
Simulation time 8389853800 ps
CPU time 9.33 seconds
Started May 02 03:47:02 PM PDT 24
Finished May 02 03:47:13 PM PDT 24
Peak memory 204068 kb
Host smart-19797779-cd6f-499e-955f-71d28457e75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
26736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1280526736
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.2485708890
Short name T829
Test name
Test status
Simulation time 8393698565 ps
CPU time 8.76 seconds
Started May 02 03:47:00 PM PDT 24
Finished May 02 03:47:11 PM PDT 24
Peak memory 204076 kb
Host smart-24e92ac5-5b52-4b68-863d-8cae8a9a35e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
08890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2485708890
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1853576323
Short name T928
Test name
Test status
Simulation time 52417376 ps
CPU time 1.43 seconds
Started May 02 03:46:59 PM PDT 24
Finished May 02 03:47:02 PM PDT 24
Peak memory 204228 kb
Host smart-73bafa92-7724-4a8d-9113-973b40ab2b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18535
76323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1853576323
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1473285556
Short name T536
Test name
Test status
Simulation time 8421825112 ps
CPU time 10.3 seconds
Started May 02 03:47:07 PM PDT 24
Finished May 02 03:47:19 PM PDT 24
Peak memory 204092 kb
Host smart-6646256d-2513-4684-b152-7646d0d6d3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
85556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1473285556
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4084428275
Short name T1066
Test name
Test status
Simulation time 8377425717 ps
CPU time 7.36 seconds
Started May 02 03:47:18 PM PDT 24
Finished May 02 03:47:26 PM PDT 24
Peak memory 204144 kb
Host smart-b74f156d-a951-4585-bbd8-d388e3ec9401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40844
28275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4084428275
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1446095626
Short name T156
Test name
Test status
Simulation time 8388507590 ps
CPU time 10.15 seconds
Started May 02 03:47:02 PM PDT 24
Finished May 02 03:47:14 PM PDT 24
Peak memory 204104 kb
Host smart-cefecb63-52b0-446a-a479-5ccf16549367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
95626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1446095626
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2941866243
Short name T1099
Test name
Test status
Simulation time 8473478732 ps
CPU time 8.35 seconds
Started May 02 03:47:02 PM PDT 24
Finished May 02 03:47:12 PM PDT 24
Peak memory 204060 kb
Host smart-fdc4db52-ede6-4de2-b944-c7391bb96b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
66243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2941866243
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1732608051
Short name T989
Test name
Test status
Simulation time 8374875428 ps
CPU time 10.52 seconds
Started May 02 03:47:03 PM PDT 24
Finished May 02 03:47:15 PM PDT 24
Peak memory 204076 kb
Host smart-c0ee3ec7-7fa7-4e64-9f6b-238fffbb4df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17326
08051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1732608051
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1108738351
Short name T1202
Test name
Test status
Simulation time 8407764657 ps
CPU time 8.27 seconds
Started May 02 03:46:59 PM PDT 24
Finished May 02 03:47:09 PM PDT 24
Peak memory 204104 kb
Host smart-6c193ff6-5a4b-45f6-9a21-062ee2d1ad2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
38351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1108738351
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3790295102
Short name T317
Test name
Test status
Simulation time 8396395529 ps
CPU time 7.99 seconds
Started May 02 03:47:00 PM PDT 24
Finished May 02 03:47:10 PM PDT 24
Peak memory 204128 kb
Host smart-b5242863-09f0-43f2-b951-487bcad4c54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37902
95102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3790295102
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.613314093
Short name T457
Test name
Test status
Simulation time 8382130903 ps
CPU time 8.59 seconds
Started May 02 03:47:03 PM PDT 24
Finished May 02 03:47:13 PM PDT 24
Peak memory 204088 kb
Host smart-111791d2-b8a7-4f66-8860-5ad1f472a5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61331
4093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.613314093
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.562352426
Short name T571
Test name
Test status
Simulation time 8413960939 ps
CPU time 7.64 seconds
Started May 02 03:47:17 PM PDT 24
Finished May 02 03:47:26 PM PDT 24
Peak memory 204144 kb
Host smart-07ac94e9-7eeb-4fa9-b9c2-7d577b43447c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56235
2426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.562352426
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1941936044
Short name T563
Test name
Test status
Simulation time 8391403162 ps
CPU time 9.38 seconds
Started May 02 03:47:08 PM PDT 24
Finished May 02 03:47:18 PM PDT 24
Peak memory 204128 kb
Host smart-dcae59be-aee6-4ce6-86c8-8620b0daf925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19419
36044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1941936044
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3508798262
Short name T934
Test name
Test status
Simulation time 39212182 ps
CPU time 0.66 seconds
Started May 02 03:47:12 PM PDT 24
Finished May 02 03:47:14 PM PDT 24
Peak memory 204012 kb
Host smart-ada28933-a4ab-46c2-9fc9-a13850beec0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35087
98262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3508798262
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.703259791
Short name T277
Test name
Test status
Simulation time 27392845075 ps
CPU time 50.7 seconds
Started May 02 03:47:03 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204360 kb
Host smart-21b328c3-c7b4-47e1-8042-edfad0e83f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70325
9791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.703259791
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2461927342
Short name T1255
Test name
Test status
Simulation time 8415907684 ps
CPU time 7.47 seconds
Started May 02 03:47:02 PM PDT 24
Finished May 02 03:47:11 PM PDT 24
Peak memory 204148 kb
Host smart-9a1c15d2-e72f-47f6-a590-defdd378ee17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24619
27342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2461927342
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4108757176
Short name T1160
Test name
Test status
Simulation time 8388069473 ps
CPU time 9.77 seconds
Started May 02 03:47:01 PM PDT 24
Finished May 02 03:47:13 PM PDT 24
Peak memory 204160 kb
Host smart-a1b0b214-43d5-4ced-8431-fb885fe6b25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
57176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4108757176
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.1802915422
Short name T400
Test name
Test status
Simulation time 8388066383 ps
CPU time 7.86 seconds
Started May 02 03:47:01 PM PDT 24
Finished May 02 03:47:11 PM PDT 24
Peak memory 204108 kb
Host smart-a0316fcc-4d17-4b6b-8bac-66dd0fbaa4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029
15422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.1802915422
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2332589728
Short name T332
Test name
Test status
Simulation time 8387762607 ps
CPU time 8.07 seconds
Started May 02 03:47:10 PM PDT 24
Finished May 02 03:47:19 PM PDT 24
Peak memory 204016 kb
Host smart-292d7ae8-21c4-42ad-a22c-1677660aafe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325
89728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2332589728
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.262308673
Short name T1308
Test name
Test status
Simulation time 8371788968 ps
CPU time 9.67 seconds
Started May 02 03:47:11 PM PDT 24
Finished May 02 03:47:21 PM PDT 24
Peak memory 204092 kb
Host smart-2682b978-73d8-4bb3-ad1e-6d72dbf1311e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
8673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.262308673
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.4070805452
Short name T1182
Test name
Test status
Simulation time 8466157548 ps
CPU time 7.8 seconds
Started May 02 03:47:02 PM PDT 24
Finished May 02 03:47:11 PM PDT 24
Peak memory 204136 kb
Host smart-31c7e81f-96a4-453a-9da6-3eceeed83a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40708
05452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.4070805452
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2208313360
Short name T320
Test name
Test status
Simulation time 8420387154 ps
CPU time 8.36 seconds
Started May 02 03:47:12 PM PDT 24
Finished May 02 03:47:21 PM PDT 24
Peak memory 204072 kb
Host smart-adea8a73-f4b1-4ef7-b885-efd0ffa342d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22083
13360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2208313360
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2107505024
Short name T804
Test name
Test status
Simulation time 8380115782 ps
CPU time 7.82 seconds
Started May 02 03:47:04 PM PDT 24
Finished May 02 03:47:13 PM PDT 24
Peak memory 204060 kb
Host smart-6a14ffea-1575-4147-b0aa-09119a0de2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
05024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2107505024
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.3320200286
Short name T531
Test name
Test status
Simulation time 8467834512 ps
CPU time 7.58 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:36 PM PDT 24
Peak memory 204148 kb
Host smart-f9d5dad1-fe12-4bb0-a962-96e9e56fba6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3320200286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.3320200286
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1132647319
Short name T575
Test name
Test status
Simulation time 8378229557 ps
CPU time 7.67 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:48 PM PDT 24
Peak memory 203488 kb
Host smart-3c990d85-03bd-4a97-8964-06a3a78ec657
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1132647319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1132647319
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.4178524401
Short name T827
Test name
Test status
Simulation time 8453909548 ps
CPU time 8.08 seconds
Started May 02 03:47:32 PM PDT 24
Finished May 02 03:47:40 PM PDT 24
Peak memory 204124 kb
Host smart-5b154bf1-7a2c-4d53-b368-006eacecca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41785
24401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.4178524401
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1842154427
Short name T325
Test name
Test status
Simulation time 8390625165 ps
CPU time 7.35 seconds
Started May 02 03:47:36 PM PDT 24
Finished May 02 03:47:45 PM PDT 24
Peak memory 204116 kb
Host smart-f7449754-e85b-46d4-b8ad-17b786ea0c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18421
54427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1842154427
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.325772461
Short name T857
Test name
Test status
Simulation time 8378236888 ps
CPU time 9.1 seconds
Started May 02 03:47:32 PM PDT 24
Finished May 02 03:47:42 PM PDT 24
Peak memory 204048 kb
Host smart-db388ca6-0e9c-4ed7-8fd3-a3a04c149183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32577
2461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.325772461
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.4256860161
Short name T659
Test name
Test status
Simulation time 82165307 ps
CPU time 2.21 seconds
Started May 02 03:47:12 PM PDT 24
Finished May 02 03:47:16 PM PDT 24
Peak memory 204220 kb
Host smart-29218d68-0651-4337-be2b-41f02a9364f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42568
60161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.4256860161
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3081257890
Short name T1298
Test name
Test status
Simulation time 8390546084 ps
CPU time 8.91 seconds
Started May 02 03:47:24 PM PDT 24
Finished May 02 03:47:34 PM PDT 24
Peak memory 204144 kb
Host smart-39a1c1fe-c396-40f4-9ff9-6d2ee2d2376b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30812
57890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3081257890
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2565187664
Short name T5
Test name
Test status
Simulation time 8368445672 ps
CPU time 7.72 seconds
Started May 02 03:47:35 PM PDT 24
Finished May 02 03:47:44 PM PDT 24
Peak memory 204104 kb
Host smart-a0c1b6bc-21c4-401e-adc9-325dc2be7d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25651
87664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2565187664
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.465491761
Short name T141
Test name
Test status
Simulation time 8420557227 ps
CPU time 7.98 seconds
Started May 02 03:47:15 PM PDT 24
Finished May 02 03:47:24 PM PDT 24
Peak memory 204024 kb
Host smart-64960330-84a0-4131-8bdf-c37b39284f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46549
1761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.465491761
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2891582019
Short name T1286
Test name
Test status
Simulation time 8444756863 ps
CPU time 8.16 seconds
Started May 02 03:47:12 PM PDT 24
Finished May 02 03:47:21 PM PDT 24
Peak memory 204080 kb
Host smart-0c691862-e589-4b17-bb16-398e809e8f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28915
82019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2891582019
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.904882147
Short name T420
Test name
Test status
Simulation time 8386938427 ps
CPU time 8.92 seconds
Started May 02 03:47:13 PM PDT 24
Finished May 02 03:47:23 PM PDT 24
Peak memory 204108 kb
Host smart-86ba4886-a7ef-4ed9-8a0c-cbe4f4d649f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90488
2147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.904882147
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.489214366
Short name T738
Test name
Test status
Simulation time 8421050774 ps
CPU time 9.48 seconds
Started May 02 03:47:28 PM PDT 24
Finished May 02 03:47:38 PM PDT 24
Peak memory 204076 kb
Host smart-7534193d-3869-42f7-a6c3-94a96d25ce81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48921
4366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.489214366
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2411120068
Short name T366
Test name
Test status
Simulation time 8386953118 ps
CPU time 7.34 seconds
Started May 02 03:47:13 PM PDT 24
Finished May 02 03:47:22 PM PDT 24
Peak memory 204016 kb
Host smart-e4ef7c4f-1a95-4ffe-91a2-536785d73ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24111
20068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2411120068
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.602143452
Short name T982
Test name
Test status
Simulation time 8418920821 ps
CPU time 8.24 seconds
Started May 02 03:47:17 PM PDT 24
Finished May 02 03:47:26 PM PDT 24
Peak memory 204076 kb
Host smart-b6b17b88-94ac-4d08-941b-17d0f8ed64c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60214
3452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.602143452
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1832705790
Short name T59
Test name
Test status
Simulation time 8403776853 ps
CPU time 9.44 seconds
Started May 02 03:47:16 PM PDT 24
Finished May 02 03:47:26 PM PDT 24
Peak memory 204116 kb
Host smart-b7e09481-ddfd-4fb1-8325-0c427abc031f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18327
05790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1832705790
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.183929876
Short name T1003
Test name
Test status
Simulation time 8367358374 ps
CPU time 9.1 seconds
Started May 02 03:47:30 PM PDT 24
Finished May 02 03:47:40 PM PDT 24
Peak memory 204128 kb
Host smart-8d4f612d-538a-457f-a4e0-52acf00517f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18392
9876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.183929876
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3236328463
Short name T869
Test name
Test status
Simulation time 78980014 ps
CPU time 0.67 seconds
Started May 02 03:47:23 PM PDT 24
Finished May 02 03:47:24 PM PDT 24
Peak memory 203972 kb
Host smart-42bec7c9-aa2a-454f-a11a-9a39ec9ea0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
28463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3236328463
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2201190255
Short name T935
Test name
Test status
Simulation time 26821853029 ps
CPU time 52.9 seconds
Started May 02 03:47:13 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204336 kb
Host smart-5ce56a35-ba1c-4b83-94db-0e321cab8c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22011
90255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2201190255
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2666075970
Short name T392
Test name
Test status
Simulation time 8405920451 ps
CPU time 7.65 seconds
Started May 02 03:47:14 PM PDT 24
Finished May 02 03:47:23 PM PDT 24
Peak memory 204080 kb
Host smart-9fccbf44-d573-4a47-800d-5efac37ba91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
75970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2666075970
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3592517994
Short name T419
Test name
Test status
Simulation time 8421738419 ps
CPU time 10.21 seconds
Started May 02 03:47:13 PM PDT 24
Finished May 02 03:47:24 PM PDT 24
Peak memory 204136 kb
Host smart-b4555cc7-b869-41b1-a441-4f4ea895ac6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
17994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3592517994
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3807239421
Short name T643
Test name
Test status
Simulation time 8394219106 ps
CPU time 7.71 seconds
Started May 02 03:47:15 PM PDT 24
Finished May 02 03:47:23 PM PDT 24
Peak memory 204032 kb
Host smart-a90701b6-659e-42c6-8d92-ca3bb5407f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
39421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3807239421
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1050826120
Short name T611
Test name
Test status
Simulation time 8375563158 ps
CPU time 8.06 seconds
Started May 02 03:47:17 PM PDT 24
Finished May 02 03:47:26 PM PDT 24
Peak memory 204084 kb
Host smart-1e20de61-389e-4221-9807-2ed912159b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
26120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1050826120
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2229248155
Short name T429
Test name
Test status
Simulation time 8381226541 ps
CPU time 10.98 seconds
Started May 02 03:47:13 PM PDT 24
Finished May 02 03:47:25 PM PDT 24
Peak memory 204072 kb
Host smart-faf0de15-0903-486d-b268-2eaaa09089ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
48155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2229248155
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.4215017117
Short name T1140
Test name
Test status
Simulation time 8437395351 ps
CPU time 8.43 seconds
Started May 02 03:47:20 PM PDT 24
Finished May 02 03:47:29 PM PDT 24
Peak memory 204072 kb
Host smart-4a56ad4b-acf2-468f-9a53-8127d949e187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42150
17117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.4215017117
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1715037175
Short name T541
Test name
Test status
Simulation time 8371652408 ps
CPU time 7.53 seconds
Started May 02 03:47:28 PM PDT 24
Finished May 02 03:47:37 PM PDT 24
Peak memory 204116 kb
Host smart-1301c78d-3a10-4033-b4d0-ff2251de465f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
37175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1715037175
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1858923619
Short name T1288
Test name
Test status
Simulation time 8404099267 ps
CPU time 7.53 seconds
Started May 02 03:47:16 PM PDT 24
Finished May 02 03:47:24 PM PDT 24
Peak memory 204128 kb
Host smart-93e8af69-0d06-45ed-8234-f4fe020a34a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18589
23619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1858923619
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.127475641
Short name T1329
Test name
Test status
Simulation time 8486818955 ps
CPU time 8.19 seconds
Started May 02 03:47:28 PM PDT 24
Finished May 02 03:47:37 PM PDT 24
Peak memory 204076 kb
Host smart-65b535cc-08fb-4537-bcd5-5e47be138efb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=127475641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.127475641
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.34128798
Short name T387
Test name
Test status
Simulation time 8379980752 ps
CPU time 7.53 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:48 PM PDT 24
Peak memory 204084 kb
Host smart-7606e4c1-4a2c-47db-b04a-5ed56b354a22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=34128798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.34128798
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.3596863887
Short name T1009
Test name
Test status
Simulation time 8397064247 ps
CPU time 8.94 seconds
Started May 02 03:47:37 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204124 kb
Host smart-6bd8c4a1-8bbc-4a1d-8fab-ac45d10c8a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35968
63887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.3596863887
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3468301262
Short name T448
Test name
Test status
Simulation time 8383329574 ps
CPU time 9 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204108 kb
Host smart-7634a118-369e-4e18-80a7-9b0e83e98246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34683
01262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3468301262
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1655608148
Short name T308
Test name
Test status
Simulation time 8380388964 ps
CPU time 8.12 seconds
Started May 02 03:47:24 PM PDT 24
Finished May 02 03:47:33 PM PDT 24
Peak memory 204052 kb
Host smart-1206b514-4f4c-4234-a41b-8d5cf20421ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16556
08148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1655608148
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1552092976
Short name T1382
Test name
Test status
Simulation time 188128392 ps
CPU time 2.12 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:44 PM PDT 24
Peak memory 204280 kb
Host smart-6f269058-843a-4b7f-8b0c-e99334999767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15520
92976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1552092976
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4026585433
Short name T139
Test name
Test status
Simulation time 8386463826 ps
CPU time 7.8 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:49 PM PDT 24
Peak memory 204152 kb
Host smart-681f00ab-2382-4b29-a5e4-9023bea6567e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40265
85433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4026585433
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.4083309134
Short name T187
Test name
Test status
Simulation time 8369571027 ps
CPU time 8.23 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204040 kb
Host smart-2e385d03-e699-4e3d-83da-9c57da1b00c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40833
09134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.4083309134
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.4068278193
Short name T876
Test name
Test status
Simulation time 8401160151 ps
CPU time 9.48 seconds
Started May 02 03:47:33 PM PDT 24
Finished May 02 03:47:44 PM PDT 24
Peak memory 204144 kb
Host smart-7d0f6c1f-2dd2-43fb-8fcf-99f96cf6e375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40682
78193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4068278193
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3896902683
Short name T938
Test name
Test status
Simulation time 8449132537 ps
CPU time 7.6 seconds
Started May 02 03:47:36 PM PDT 24
Finished May 02 03:47:45 PM PDT 24
Peak memory 204068 kb
Host smart-f621a64f-9ccb-4ff8-8cee-ac8fcc48d8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969
02683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3896902683
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2680851905
Short name T1126
Test name
Test status
Simulation time 8381620822 ps
CPU time 10.26 seconds
Started May 02 03:47:25 PM PDT 24
Finished May 02 03:47:36 PM PDT 24
Peak memory 204076 kb
Host smart-099ee186-d695-4c42-872b-e671e7d3b64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808
51905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2680851905
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3710561253
Short name T1127
Test name
Test status
Simulation time 8426464827 ps
CPU time 10.02 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204068 kb
Host smart-cf38917c-de20-4535-8ec6-578138c4f2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105
61253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3710561253
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.615620052
Short name T321
Test name
Test status
Simulation time 8415732014 ps
CPU time 8.06 seconds
Started May 02 03:47:24 PM PDT 24
Finished May 02 03:47:33 PM PDT 24
Peak memory 204084 kb
Host smart-cdd0c240-e7d4-4d1a-adc7-a1636265a09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61562
0052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.615620052
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1636340107
Short name T1356
Test name
Test status
Simulation time 8411918731 ps
CPU time 7.93 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:48 PM PDT 24
Peak memory 203464 kb
Host smart-06852dbf-6a7b-4f58-80fe-ef36f0f755ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16363
40107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1636340107
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1179728949
Short name T1176
Test name
Test status
Simulation time 8420612131 ps
CPU time 10.15 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204124 kb
Host smart-e788f242-f52a-437a-9145-c3179bf59a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11797
28949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1179728949
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1254011169
Short name T1216
Test name
Test status
Simulation time 8376197134 ps
CPU time 7.85 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:36 PM PDT 24
Peak memory 204080 kb
Host smart-a0a9ed14-00ee-44f9-9edf-db18958beb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12540
11169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1254011169
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1810867238
Short name T1134
Test name
Test status
Simulation time 127317960 ps
CPU time 0.71 seconds
Started May 02 03:47:37 PM PDT 24
Finished May 02 03:47:39 PM PDT 24
Peak memory 203960 kb
Host smart-e99ae376-2ef5-4457-a125-8385760e9c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108
67238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1810867238
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.740601628
Short name T1305
Test name
Test status
Simulation time 31185689130 ps
CPU time 62.86 seconds
Started May 02 03:47:37 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 204392 kb
Host smart-dae46495-52a7-4555-aa5a-24ca06099f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74060
1628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.740601628
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2951252676
Short name T1170
Test name
Test status
Simulation time 8394130440 ps
CPU time 9.25 seconds
Started May 02 03:47:31 PM PDT 24
Finished May 02 03:47:42 PM PDT 24
Peak memory 204124 kb
Host smart-5e66af82-fa1e-4fb7-8fde-a6b650d4ab84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29512
52676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2951252676
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3807620633
Short name T1366
Test name
Test status
Simulation time 8444651056 ps
CPU time 9.3 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:37 PM PDT 24
Peak memory 204116 kb
Host smart-54f9922e-8a35-452f-b235-1219a4bbbc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38076
20633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3807620633
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3495466076
Short name T537
Test name
Test status
Simulation time 8401066352 ps
CPU time 8.49 seconds
Started May 02 03:47:35 PM PDT 24
Finished May 02 03:47:44 PM PDT 24
Peak memory 204064 kb
Host smart-706f87b4-40ec-49aa-9d85-5eb2103a65d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34954
66076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3495466076
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2917032665
Short name T970
Test name
Test status
Simulation time 8371862364 ps
CPU time 7.62 seconds
Started May 02 03:47:33 PM PDT 24
Finished May 02 03:47:42 PM PDT 24
Peak memory 203464 kb
Host smart-3be7da4a-29e1-47f3-8501-4387245022b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29170
32665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2917032665
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3667615654
Short name T835
Test name
Test status
Simulation time 8370379525 ps
CPU time 7.67 seconds
Started May 02 03:47:36 PM PDT 24
Finished May 02 03:47:45 PM PDT 24
Peak memory 204128 kb
Host smart-dc2d6e34-a45e-4570-9c87-c96f5cce3850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
15654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3667615654
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1071130164
Short name T1247
Test name
Test status
Simulation time 8431092630 ps
CPU time 9.5 seconds
Started May 02 03:47:26 PM PDT 24
Finished May 02 03:47:37 PM PDT 24
Peak memory 204096 kb
Host smart-5e762173-c607-40bc-a2bc-1e53c618c680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10711
30164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1071130164
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2784515836
Short name T1317
Test name
Test status
Simulation time 8409581105 ps
CPU time 7.86 seconds
Started May 02 03:47:38 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204152 kb
Host smart-a9eca739-ae40-4a09-b5f1-592224702d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27845
15836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2784515836
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2262822895
Short name T1002
Test name
Test status
Simulation time 8467713832 ps
CPU time 7.55 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204076 kb
Host smart-ba3e9b23-e7b2-479a-84fd-24e5bb6a8cf1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2262822895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2262822895
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.1728311990
Short name T864
Test name
Test status
Simulation time 8375088618 ps
CPU time 10.02 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204068 kb
Host smart-5cfa717b-e73b-425a-ad4b-37088f44a5d4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1728311990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.1728311990
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1208590066
Short name T1324
Test name
Test status
Simulation time 8387050582 ps
CPU time 7.6 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204028 kb
Host smart-1632473a-8c79-4856-b341-97aee3c0da7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
90066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1208590066
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2292919903
Short name T588
Test name
Test status
Simulation time 8370720154 ps
CPU time 7.86 seconds
Started May 02 03:47:28 PM PDT 24
Finished May 02 03:47:37 PM PDT 24
Peak memory 204108 kb
Host smart-e39d4ac7-dc3e-4a02-b011-a15e8fe8855b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
19903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2292919903
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.3903517844
Short name T1306
Test name
Test status
Simulation time 8372559948 ps
CPU time 8.08 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204004 kb
Host smart-7758466d-f708-4d85-a89c-39d7c403303f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
17844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3903517844
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.839873583
Short name T1168
Test name
Test status
Simulation time 71797704 ps
CPU time 1.61 seconds
Started May 02 03:47:38 PM PDT 24
Finished May 02 03:47:41 PM PDT 24
Peak memory 204200 kb
Host smart-4603d63a-5d5c-49dd-a7c3-21235b8d6e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83987
3583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.839873583
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3870272604
Short name T551
Test name
Test status
Simulation time 8440923005 ps
CPU time 8.19 seconds
Started May 02 03:47:29 PM PDT 24
Finished May 02 03:47:38 PM PDT 24
Peak memory 204100 kb
Host smart-8f5f94fe-a44a-460c-9b1d-d68fc8f297db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38702
72604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3870272604
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3398712674
Short name T846
Test name
Test status
Simulation time 8368531445 ps
CPU time 7.65 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204160 kb
Host smart-0e6ffeef-2237-476a-9a90-fc2f144a3fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
12674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3398712674
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3043897523
Short name T158
Test name
Test status
Simulation time 8432810924 ps
CPU time 7.56 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204140 kb
Host smart-91741b70-1f32-4728-8737-53977f22d29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438
97523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3043897523
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1931241576
Short name T501
Test name
Test status
Simulation time 8443443312 ps
CPU time 7.67 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204040 kb
Host smart-c073965d-cb6c-4692-9316-36e9bdab36a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
41576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1931241576
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1833323483
Short name T390
Test name
Test status
Simulation time 8380117597 ps
CPU time 8.18 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204124 kb
Host smart-fd3d85be-33aa-4f73-ba86-06d345a59c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
23483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1833323483
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2729383075
Short name T114
Test name
Test status
Simulation time 8445664326 ps
CPU time 7.59 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:35 PM PDT 24
Peak memory 204032 kb
Host smart-a540f479-60dc-413f-9be7-545a9341b198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27293
83075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2729383075
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2793986020
Short name T650
Test name
Test status
Simulation time 8372653725 ps
CPU time 9.4 seconds
Started May 02 03:47:29 PM PDT 24
Finished May 02 03:47:39 PM PDT 24
Peak memory 204112 kb
Host smart-93857dc5-c088-46b3-a291-49142f3cc6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27939
86020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2793986020
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.723274928
Short name T1175
Test name
Test status
Simulation time 8402730250 ps
CPU time 7.68 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204148 kb
Host smart-00725e36-a9a2-4e68-853f-1d1fc449ef97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72327
4928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.723274928
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2941136591
Short name T671
Test name
Test status
Simulation time 8395279253 ps
CPU time 9.53 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:37 PM PDT 24
Peak memory 204064 kb
Host smart-e515fd4a-7c5f-4e80-8971-b605df4fe1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
36591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2941136591
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.571601047
Short name T965
Test name
Test status
Simulation time 77648153 ps
CPU time 0.7 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:28 PM PDT 24
Peak memory 203916 kb
Host smart-97788758-d393-4517-b72a-7cd3cef12bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57160
1047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.571601047
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3649520812
Short name T276
Test name
Test status
Simulation time 28365668567 ps
CPU time 55.52 seconds
Started May 02 03:47:28 PM PDT 24
Finished May 02 03:48:24 PM PDT 24
Peak memory 204396 kb
Host smart-d33f2204-3159-4d93-ae57-19f7ee41bd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
20812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3649520812
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1343664099
Short name T1139
Test name
Test status
Simulation time 8419832133 ps
CPU time 7.42 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:35 PM PDT 24
Peak memory 204104 kb
Host smart-2c8b2fa6-8f3e-4035-9d77-42946c443024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13436
64099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1343664099
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3407889558
Short name T1038
Test name
Test status
Simulation time 8425240203 ps
CPU time 8.16 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204124 kb
Host smart-4144302d-eb8f-4fdd-aabc-939dc825f53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34078
89558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3407889558
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.145225728
Short name T1065
Test name
Test status
Simulation time 8405639385 ps
CPU time 7.95 seconds
Started May 02 03:47:27 PM PDT 24
Finished May 02 03:47:36 PM PDT 24
Peak memory 204076 kb
Host smart-4e6bd77d-2511-49c4-8044-b67f68c21610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14522
5728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.145225728
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3397174023
Short name T767
Test name
Test status
Simulation time 8371918434 ps
CPU time 7.68 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204048 kb
Host smart-7a1ef1ce-79cd-4c6f-9d5a-74a711a0e2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
74023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3397174023
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.747057421
Short name T482
Test name
Test status
Simulation time 8367304479 ps
CPU time 8.33 seconds
Started May 02 03:47:31 PM PDT 24
Finished May 02 03:47:40 PM PDT 24
Peak memory 204092 kb
Host smart-d7c1d080-656c-4249-a92a-995a067f8322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74705
7421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.747057421
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1475654941
Short name T133
Test name
Test status
Simulation time 8480295550 ps
CPU time 7.92 seconds
Started May 02 03:47:29 PM PDT 24
Finished May 02 03:47:38 PM PDT 24
Peak memory 204124 kb
Host smart-75e3a268-4ef0-4962-acf6-8363c515c5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14756
54941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1475654941
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.87802876
Short name T608
Test name
Test status
Simulation time 8397804974 ps
CPU time 9.43 seconds
Started May 02 03:47:37 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204004 kb
Host smart-999b7a10-a00a-48d7-bcb8-836752616b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87802
876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.87802876
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.554909372
Short name T1272
Test name
Test status
Simulation time 8385487890 ps
CPU time 8.17 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204040 kb
Host smart-12685aa3-1514-4b20-a64c-f565698a0d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55490
9372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.554909372
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2713337672
Short name T54
Test name
Test status
Simulation time 8484266144 ps
CPU time 8.48 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204060 kb
Host smart-f5c692da-8123-43c9-9aa8-fb2a20dcccff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2713337672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2713337672
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.3021770954
Short name T1033
Test name
Test status
Simulation time 8389079942 ps
CPU time 9.95 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204112 kb
Host smart-e28c16c4-622c-4f18-a765-3752efc17bcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3021770954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.3021770954
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.901581226
Short name T1208
Test name
Test status
Simulation time 8423852960 ps
CPU time 7.44 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204136 kb
Host smart-ab96f3dd-6c36-4783-9c30-9f3b946549b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90158
1226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.901581226
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3871972837
Short name T632
Test name
Test status
Simulation time 8371917031 ps
CPU time 9.71 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 203060 kb
Host smart-654ec543-9e8b-433e-a650-d6568f0b35bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719
72837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3871972837
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.2437045729
Short name T1097
Test name
Test status
Simulation time 8374861925 ps
CPU time 7.85 seconds
Started May 02 03:47:48 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204072 kb
Host smart-1552e163-4396-46d3-bced-ad359e2add6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24370
45729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2437045729
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2536076802
Short name T1325
Test name
Test status
Simulation time 185951775 ps
CPU time 1.66 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204168 kb
Host smart-2408240a-1b84-4343-8427-1399b8b98bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25360
76802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2536076802
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.286477043
Short name T750
Test name
Test status
Simulation time 8424528656 ps
CPU time 7.9 seconds
Started May 02 03:47:38 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204136 kb
Host smart-ed100128-b20d-44ca-83c1-f0c46b73a311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28647
7043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.286477043
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1670541343
Short name T713
Test name
Test status
Simulation time 8369915757 ps
CPU time 8.25 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204084 kb
Host smart-04ae4408-5efa-4816-b029-6fc7ee682022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16705
41343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1670541343
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2558316085
Short name T796
Test name
Test status
Simulation time 8461215056 ps
CPU time 7.56 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204136 kb
Host smart-789d52d0-a006-4d5a-9bc7-66dd7dff86fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25583
16085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2558316085
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1226597476
Short name T221
Test name
Test status
Simulation time 8418230760 ps
CPU time 10.24 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204036 kb
Host smart-dcc7c39f-13cf-4e77-bec5-20796ddfd0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12265
97476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1226597476
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2113134324
Short name T875
Test name
Test status
Simulation time 8370538019 ps
CPU time 9.08 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204120 kb
Host smart-7906da91-e80f-497b-9604-3b6dd480e73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
34324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2113134324
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2205735575
Short name T1349
Test name
Test status
Simulation time 8417261952 ps
CPU time 7.9 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204124 kb
Host smart-0f1311b6-04b1-45ef-8e9d-8276d81d5871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22057
35575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2205735575
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2267908483
Short name T351
Test name
Test status
Simulation time 8410612915 ps
CPU time 8.05 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:49 PM PDT 24
Peak memory 204136 kb
Host smart-71708636-36a5-4a09-9975-62dd8831ffc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22679
08483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2267908483
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1533668827
Short name T426
Test name
Test status
Simulation time 8419896434 ps
CPU time 7.78 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204140 kb
Host smart-41f960e9-b978-4a31-8ff8-97c87e447811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336
68827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1533668827
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2521809202
Short name T675
Test name
Test status
Simulation time 8390475368 ps
CPU time 8.31 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204080 kb
Host smart-28bb5879-18a1-4596-bc1b-23f5122aa7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25218
09202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2521809202
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3010086175
Short name T649
Test name
Test status
Simulation time 8374034067 ps
CPU time 7.61 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204104 kb
Host smart-22e15bfa-f744-4121-99c0-c5b3ab7a718d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30100
86175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3010086175
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3331818353
Short name T1315
Test name
Test status
Simulation time 74471708 ps
CPU time 0.74 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:43 PM PDT 24
Peak memory 203992 kb
Host smart-e40acd31-5c36-417b-b616-e3edf5cb19e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
18353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3331818353
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2872303956
Short name T228
Test name
Test status
Simulation time 25636223007 ps
CPU time 48.14 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:48:32 PM PDT 24
Peak memory 204396 kb
Host smart-a25aca3f-12a6-466a-9976-d77a6f1e35e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723
03956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2872303956
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3195500391
Short name T1155
Test name
Test status
Simulation time 8443698394 ps
CPU time 8.49 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:49 PM PDT 24
Peak memory 204108 kb
Host smart-64e72571-56a9-42d9-a665-dff38037121f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
00391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3195500391
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.58402394
Short name T458
Test name
Test status
Simulation time 8466586521 ps
CPU time 7.82 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:48 PM PDT 24
Peak memory 204080 kb
Host smart-da3c3b3a-b7f4-419b-a582-a8dc2d9eb938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58402
394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.58402394
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2532288445
Short name T362
Test name
Test status
Simulation time 8471136099 ps
CPU time 9.23 seconds
Started May 02 03:47:32 PM PDT 24
Finished May 02 03:47:42 PM PDT 24
Peak memory 204108 kb
Host smart-62832eb2-6cf9-4178-89d5-5efb112395ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25322
88445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2532288445
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3340725301
Short name T1091
Test name
Test status
Simulation time 8386201787 ps
CPU time 7.6 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204124 kb
Host smart-8047292a-6050-4b97-92cd-ba5da3043eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
25301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3340725301
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2640328822
Short name T955
Test name
Test status
Simulation time 8369857027 ps
CPU time 9.23 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204116 kb
Host smart-c443647c-c01f-4601-a6b2-88ba7820cd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26403
28822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2640328822
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.4176503487
Short name T175
Test name
Test status
Simulation time 8451114187 ps
CPU time 7.63 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204128 kb
Host smart-e4921963-ebca-4114-b7ac-0916f85710ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41765
03487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.4176503487
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.4271926600
Short name T1178
Test name
Test status
Simulation time 8468244099 ps
CPU time 9.03 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204072 kb
Host smart-e4eb4c47-985b-4776-9990-f91651b2401f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42719
26600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.4271926600
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.752039513
Short name T1087
Test name
Test status
Simulation time 8407701155 ps
CPU time 10.42 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204136 kb
Host smart-0f24f26a-0dfd-4e24-bb8b-f0ac3d4c0ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75203
9513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.752039513
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3396796007
Short name T381
Test name
Test status
Simulation time 8463589315 ps
CPU time 8.35 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204076 kb
Host smart-7be93064-0cc2-4ee9-a7ec-a8a31b619c3d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3396796007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3396796007
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.707007076
Short name T992
Test name
Test status
Simulation time 8379644017 ps
CPU time 10.23 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204116 kb
Host smart-3b3bab05-2e03-4f3e-8cf8-3d9d59a17fa0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=707007076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.707007076
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.1162445936
Short name T517
Test name
Test status
Simulation time 8469518566 ps
CPU time 10.24 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204060 kb
Host smart-406c7283-66bb-417e-8d42-5409478eced3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11624
45936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.1162445936
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2806732923
Short name T1301
Test name
Test status
Simulation time 8388238699 ps
CPU time 7.42 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204140 kb
Host smart-1ef14c61-d3d4-45df-aaf6-d48987ae829d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28067
32923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2806732923
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.1104471650
Short name T886
Test name
Test status
Simulation time 8373742986 ps
CPU time 8.61 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204140 kb
Host smart-5a01ac6f-5dd0-48e6-b02b-5208505a8ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
71650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1104471650
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.393813877
Short name T1197
Test name
Test status
Simulation time 148013777 ps
CPU time 1.4 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:44 PM PDT 24
Peak memory 204152 kb
Host smart-63188807-0b14-44af-a4df-5d163f4a14f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39381
3877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.393813877
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3050497609
Short name T679
Test name
Test status
Simulation time 8395390889 ps
CPU time 9.38 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204088 kb
Host smart-48f464e3-2e4c-4580-bf29-3b1b6d3f51a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30504
97609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3050497609
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3002302086
Short name T565
Test name
Test status
Simulation time 8381839561 ps
CPU time 7.84 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204136 kb
Host smart-f6d1e56d-b5a0-4b21-9a3d-7ef89fbabf49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
02086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3002302086
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2476068782
Short name T1220
Test name
Test status
Simulation time 8424533885 ps
CPU time 8.23 seconds
Started May 02 03:47:48 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204156 kb
Host smart-839fa78a-eaa3-48f7-811d-de3ca2e5a54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760
68782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2476068782
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2336724131
Short name T1043
Test name
Test status
Simulation time 8420918798 ps
CPU time 8.05 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204132 kb
Host smart-4d4835fa-80ad-4908-8611-fa9de0fcd5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23367
24131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2336724131
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3440303891
Short name T855
Test name
Test status
Simulation time 8370906642 ps
CPU time 9.55 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204144 kb
Host smart-27d6cb4c-33e0-43fd-ac13-502d727cc4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34403
03891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3440303891
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1056726173
Short name T128
Test name
Test status
Simulation time 8438601345 ps
CPU time 9.19 seconds
Started May 02 03:47:32 PM PDT 24
Finished May 02 03:47:42 PM PDT 24
Peak memory 204064 kb
Host smart-90be74b4-d998-49da-8d9b-d9c326815019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
26173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1056726173
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1099299776
Short name T1225
Test name
Test status
Simulation time 8389571188 ps
CPU time 7.98 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204116 kb
Host smart-68a46276-bc34-43bf-bbd3-95d07b55e14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10992
99776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1099299776
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3230859494
Short name T346
Test name
Test status
Simulation time 8393493050 ps
CPU time 7.66 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204060 kb
Host smart-c38b89f5-ac81-4bd1-81db-b938ad549cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32308
59494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3230859494
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2175026249
Short name T1184
Test name
Test status
Simulation time 8399370440 ps
CPU time 7.93 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204124 kb
Host smart-48c03e81-abb1-41b3-b716-975dfab3f2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21750
26249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2175026249
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.451322862
Short name T1057
Test name
Test status
Simulation time 8371724839 ps
CPU time 7.97 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204108 kb
Host smart-32a96ae3-28f4-4c49-b937-27c0ed82fddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45132
2862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.451322862
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1594818837
Short name T808
Test name
Test status
Simulation time 47746879 ps
CPU time 0.66 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:49 PM PDT 24
Peak memory 203980 kb
Host smart-538d84e4-3a0b-4a69-8477-db0d22790f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15948
18837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1594818837
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3554207115
Short name T252
Test name
Test status
Simulation time 21443951936 ps
CPU time 39.32 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:48:26 PM PDT 24
Peak memory 204432 kb
Host smart-fc70f347-d57b-4378-97ff-7611b58aac4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
07115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3554207115
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3857848025
Short name T1379
Test name
Test status
Simulation time 8423096181 ps
CPU time 7.48 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204128 kb
Host smart-66737d24-ac71-437a-90ee-423c9780069e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
48025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3857848025
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3897578415
Short name T905
Test name
Test status
Simulation time 8474064945 ps
CPU time 7.99 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204132 kb
Host smart-fc571b24-3163-4662-833f-5de756618035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38975
78415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3897578415
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1845873986
Short name T403
Test name
Test status
Simulation time 8379957713 ps
CPU time 7.79 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204084 kb
Host smart-9e46b288-4824-40b1-919b-549c5263dc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18458
73986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1845873986
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3423055482
Short name T1300
Test name
Test status
Simulation time 8385230312 ps
CPU time 7.53 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204096 kb
Host smart-fbec329f-b38e-4296-b384-eaf85a17fd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34230
55482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3423055482
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3650077166
Short name T968
Test name
Test status
Simulation time 8367881409 ps
CPU time 8.24 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204072 kb
Host smart-b838f69b-9c0d-4719-8e24-ecc02c96f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500
77166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3650077166
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1283739657
Short name T174
Test name
Test status
Simulation time 8464686784 ps
CPU time 7.52 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204056 kb
Host smart-59b24212-1ce4-47a0-ba6c-5c8da1e7deef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12837
39657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1283739657
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2632074900
Short name T330
Test name
Test status
Simulation time 8414747850 ps
CPU time 8.47 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204112 kb
Host smart-40a3452c-392e-4b18-ab97-dfdefaf499a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26320
74900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2632074900
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.4292417575
Short name T223
Test name
Test status
Simulation time 8397445088 ps
CPU time 7.86 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204112 kb
Host smart-2180820a-3282-43ad-afb2-3321466e77f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924
17575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.4292417575
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.1219585463
Short name T841
Test name
Test status
Simulation time 8466729511 ps
CPU time 8.61 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204100 kb
Host smart-0d894a68-a379-474a-aa56-1d01e22cfa04
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1219585463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.1219585463
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.1003701606
Short name T553
Test name
Test status
Simulation time 8382304980 ps
CPU time 7.56 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204020 kb
Host smart-5bf7c0bb-e8f7-4637-956c-747b91eb1c37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1003701606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.1003701606
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.3256888319
Short name T840
Test name
Test status
Simulation time 8421794049 ps
CPU time 8.55 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204064 kb
Host smart-fcc4f9ec-4034-4dab-8546-5cef2e13c111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32568
88319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.3256888319
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3865818173
Short name T533
Test name
Test status
Simulation time 8382296280 ps
CPU time 8.09 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204072 kb
Host smart-18157e48-0887-49b1-b310-8f68cd9343a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38658
18173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3865818173
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.1733378584
Short name T444
Test name
Test status
Simulation time 8372354078 ps
CPU time 10.16 seconds
Started May 02 03:47:38 PM PDT 24
Finished May 02 03:47:49 PM PDT 24
Peak memory 204064 kb
Host smart-427c3783-ac81-482f-ba7c-d33c8de699cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17333
78584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1733378584
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1810643258
Short name T227
Test name
Test status
Simulation time 71517290 ps
CPU time 1.85 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204180 kb
Host smart-082db94c-27c0-4a84-96e4-e48de1758c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
43258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1810643258
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2525193007
Short name T326
Test name
Test status
Simulation time 8433406680 ps
CPU time 7.57 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:47 PM PDT 24
Peak memory 204052 kb
Host smart-af7ed612-087d-4f45-8248-0499707c5865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25251
93007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2525193007
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1710622169
Short name T198
Test name
Test status
Simulation time 8373845898 ps
CPU time 7.83 seconds
Started May 02 03:47:48 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204140 kb
Host smart-5f565fbf-93f0-4b1a-a007-862439436d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
22169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1710622169
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.54102403
Short name T956
Test name
Test status
Simulation time 8453163083 ps
CPU time 8.08 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204144 kb
Host smart-68bdaddc-00fd-41ac-a745-edadd5a007ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54102
403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.54102403
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2721801222
Short name T1064
Test name
Test status
Simulation time 8417857230 ps
CPU time 8.99 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204132 kb
Host smart-3b83ccab-f8fc-417c-9a00-97b7d573a1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27218
01222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2721801222
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2960320865
Short name T723
Test name
Test status
Simulation time 8376467783 ps
CPU time 8.69 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204132 kb
Host smart-2d33fb46-30d4-4b8f-bfa0-37da1087832a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29603
20865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2960320865
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1526379220
Short name T1123
Test name
Test status
Simulation time 8400881353 ps
CPU time 8.13 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204148 kb
Host smart-7965f6c1-418d-491d-9a43-3a00311ef8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15263
79220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1526379220
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.136775000
Short name T376
Test name
Test status
Simulation time 8391051309 ps
CPU time 10.46 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204148 kb
Host smart-d94ea194-8a2d-46ba-b5e6-8525f51022fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13677
5000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.136775000
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.4016854474
Short name T641
Test name
Test status
Simulation time 8377227694 ps
CPU time 8.26 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204140 kb
Host smart-94ab588a-4b82-4fe6-9104-270d5385ee95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40168
54474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.4016854474
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2463500146
Short name T160
Test name
Test status
Simulation time 8402436188 ps
CPU time 7.57 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204112 kb
Host smart-94ff297c-c945-4455-88c6-5df870510b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24635
00146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2463500146
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1150392944
Short name T819
Test name
Test status
Simulation time 8371822287 ps
CPU time 7.93 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204080 kb
Host smart-9632ddcd-e940-4e98-b19e-80187eee64e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
92944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1150392944
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3460156158
Short name T394
Test name
Test status
Simulation time 75057133 ps
CPU time 0.69 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 203988 kb
Host smart-96d75989-74cd-4815-95f6-737b38058501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34601
56158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3460156158
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.758006146
Short name T1041
Test name
Test status
Simulation time 15319623185 ps
CPU time 30.4 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:48:14 PM PDT 24
Peak memory 204300 kb
Host smart-ff7e9032-fa89-4102-a6f5-6cfa4ba15345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75800
6146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.758006146
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1454447297
Short name T598
Test name
Test status
Simulation time 8385391611 ps
CPU time 7.63 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204024 kb
Host smart-61cf4815-dd50-45ff-a8e4-9932f8459e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14544
47297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1454447297
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3304298716
Short name T1282
Test name
Test status
Simulation time 8403883871 ps
CPU time 9.43 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204020 kb
Host smart-937d2926-c643-413e-acac-27e0422e0638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33042
98716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3304298716
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.4140431225
Short name T983
Test name
Test status
Simulation time 8378966100 ps
CPU time 8.02 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204032 kb
Host smart-f55d64c6-8ae2-4d02-9d25-c3284cdc5fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
31225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.4140431225
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3706522113
Short name T1375
Test name
Test status
Simulation time 8372361363 ps
CPU time 8.05 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204048 kb
Host smart-0ef46351-9eec-4748-b623-47d8b041b628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37065
22113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3706522113
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2478419205
Short name T639
Test name
Test status
Simulation time 8366315566 ps
CPU time 10.44 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204148 kb
Host smart-a9341779-6e20-475c-bf11-46af708fc936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
19205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2478419205
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2159492072
Short name T1109
Test name
Test status
Simulation time 8421251128 ps
CPU time 9.19 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204144 kb
Host smart-ca1a89a3-8696-4f77-b43c-732712d57a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21594
92072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2159492072
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3696508967
Short name T612
Test name
Test status
Simulation time 8438656423 ps
CPU time 8.71 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204128 kb
Host smart-254506c5-b270-4dcc-8287-3cc76f39e53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36965
08967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3696508967
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4225994955
Short name T602
Test name
Test status
Simulation time 8378947925 ps
CPU time 8.01 seconds
Started May 02 03:47:58 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204128 kb
Host smart-6f78935e-54fb-4702-9319-625a1a74b3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
94955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4225994955
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.525484556
Short name T1362
Test name
Test status
Simulation time 8467270185 ps
CPU time 7.88 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204136 kb
Host smart-f17cf8b4-753b-41a7-ae60-710bc258e3dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=525484556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.525484556
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.788532143
Short name T604
Test name
Test status
Simulation time 8401363472 ps
CPU time 9.25 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204108 kb
Host smart-e851ce18-6667-43cc-bdca-ce3b16eeb70f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=788532143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.788532143
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.3889371266
Short name T1353
Test name
Test status
Simulation time 8460252364 ps
CPU time 7.8 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204056 kb
Host smart-5bb7e092-288f-49c5-934b-cb92240df3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38893
71266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.3889371266
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1510071404
Short name T92
Test name
Test status
Simulation time 8377590040 ps
CPU time 8.06 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204144 kb
Host smart-c88262b8-b855-4eac-983a-7512a672d3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15100
71404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1510071404
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.919471139
Short name T485
Test name
Test status
Simulation time 8372406824 ps
CPU time 7.58 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204104 kb
Host smart-58df5a7c-a523-4b4f-a12f-d9f74e14a3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91947
1139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.919471139
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2676203962
Short name T1210
Test name
Test status
Simulation time 131184436 ps
CPU time 1.33 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204240 kb
Host smart-4911ca62-c299-4eb7-8fe9-7101e4338328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26762
03962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2676203962
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.975044356
Short name T672
Test name
Test status
Simulation time 8388146282 ps
CPU time 7.65 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204028 kb
Host smart-c9ad5721-896a-4a7b-8d0d-2afebcb95977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97504
4356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.975044356
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.879958533
Short name T680
Test name
Test status
Simulation time 8374046906 ps
CPU time 8.69 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204136 kb
Host smart-04821b06-54b3-48cd-900c-34fd6e982fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87995
8533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.879958533
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.6249267
Short name T1274
Test name
Test status
Simulation time 8521940512 ps
CPU time 8.44 seconds
Started May 02 03:47:42 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204088 kb
Host smart-8ac39ea9-3604-4b85-88f9-4745a439c82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62492
67 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.6249267
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.501235325
Short name T642
Test name
Test status
Simulation time 8414933119 ps
CPU time 8.33 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204132 kb
Host smart-719278da-39a1-4740-82bc-f29f875349e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50123
5325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.501235325
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3337964949
Short name T1164
Test name
Test status
Simulation time 8381744019 ps
CPU time 8.24 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204104 kb
Host smart-d90df9d7-fc9d-47d9-ad68-60e19764e548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
64949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3337964949
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2788583470
Short name T113
Test name
Test status
Simulation time 8430230865 ps
CPU time 8.94 seconds
Started May 02 03:47:39 PM PDT 24
Finished May 02 03:47:50 PM PDT 24
Peak memory 204096 kb
Host smart-c0c97647-f93e-4770-998b-d38fcb71b09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
83470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2788583470
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.573897419
Short name T327
Test name
Test status
Simulation time 8400870422 ps
CPU time 7.91 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204084 kb
Host smart-f3c78544-2488-4e73-b304-ccdc4a44cd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57389
7419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.573897419
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.839482436
Short name T900
Test name
Test status
Simulation time 8410637451 ps
CPU time 8.24 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204104 kb
Host smart-0f9f8198-b309-46a2-b07e-e7cf5721adaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83948
2436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.839482436
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1586568596
Short name T188
Test name
Test status
Simulation time 8410510587 ps
CPU time 8.03 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204020 kb
Host smart-f12eb0c9-58b9-4778-a0e4-35cd6ad0a347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
68596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1586568596
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3266016159
Short name T1119
Test name
Test status
Simulation time 8371428800 ps
CPU time 8.5 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204040 kb
Host smart-a61c104f-e279-4fc5-8793-31d73f2ba37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
16159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3266016159
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3113781637
Short name T48
Test name
Test status
Simulation time 29159131 ps
CPU time 0.67 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:47:54 PM PDT 24
Peak memory 204004 kb
Host smart-b1fb3dad-7bbc-4ac7-a00b-449207100521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31137
81637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3113781637
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1400652854
Short name T1048
Test name
Test status
Simulation time 21929694602 ps
CPU time 43.31 seconds
Started May 02 03:48:10 PM PDT 24
Finished May 02 03:48:54 PM PDT 24
Peak memory 204432 kb
Host smart-852de9ea-2a80-477f-970b-c30dedc73e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14006
52854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1400652854
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.4198209340
Short name T995
Test name
Test status
Simulation time 8400516315 ps
CPU time 8.01 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:50 PM PDT 24
Peak memory 204076 kb
Host smart-5c32d674-b86a-414f-9cd4-8b26e1a4be1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41982
09340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.4198209340
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1082178399
Short name T1120
Test name
Test status
Simulation time 8458194331 ps
CPU time 9.54 seconds
Started May 02 03:47:40 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204048 kb
Host smart-5c6d146b-cd19-4e38-9c94-07edf847e181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10821
78399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1082178399
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2604911893
Short name T668
Test name
Test status
Simulation time 8402028006 ps
CPU time 7.72 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204060 kb
Host smart-53c77151-1d78-4d01-bc4d-1c815e831116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26049
11893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2604911893
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3014440916
Short name T1039
Test name
Test status
Simulation time 8383400644 ps
CPU time 9.78 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204132 kb
Host smart-b4af4b83-54cf-407f-8e0a-30ef573b0bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30144
40916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3014440916
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4000808945
Short name T771
Test name
Test status
Simulation time 8360468672 ps
CPU time 7.78 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204032 kb
Host smart-9049a0a9-06b4-490e-8aa3-c402a76185b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
08945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4000808945
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3356486201
Short name T428
Test name
Test status
Simulation time 8414665338 ps
CPU time 8.74 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204132 kb
Host smart-404eb401-b523-4d6c-81f4-104cb0e94a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33564
86201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3356486201
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3461085678
Short name T130
Test name
Test status
Simulation time 8390310655 ps
CPU time 9.89 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204096 kb
Host smart-a0805ec5-8e48-44c8-9e7b-c2fba4abb834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34610
85678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3461085678
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2114546427
Short name T1171
Test name
Test status
Simulation time 8398091167 ps
CPU time 7.85 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204132 kb
Host smart-be39088c-c521-4478-a8ac-6c8b120d3999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21145
46427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2114546427
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.3896225405
Short name T35
Test name
Test status
Simulation time 8464991776 ps
CPU time 9.1 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204116 kb
Host smart-b729ec83-899b-49dd-9bcc-f479add4319c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3896225405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.3896225405
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.2754248175
Short name T524
Test name
Test status
Simulation time 8396880960 ps
CPU time 9.9 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204152 kb
Host smart-df283eb4-fd22-4273-84ce-59fbdfb5e5c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2754248175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.2754248175
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.3333298340
Short name T375
Test name
Test status
Simulation time 8379656223 ps
CPU time 7.8 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204128 kb
Host smart-9a92bd38-2b61-4e6f-81cf-eacb65f4da56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33332
98340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.3333298340
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3492305712
Short name T916
Test name
Test status
Simulation time 8375945191 ps
CPU time 7.71 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204096 kb
Host smart-bb8d37ad-cd00-4df1-8b4f-b142517af6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34923
05712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3492305712
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.1227485016
Short name T581
Test name
Test status
Simulation time 8373813713 ps
CPU time 7.9 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204132 kb
Host smart-fc99983d-0a9f-431c-84aa-3e596fffa5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274
85016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1227485016
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1412373052
Short name T1252
Test name
Test status
Simulation time 125757672 ps
CPU time 1.34 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204160 kb
Host smart-c9c0d512-b5a2-4c88-a7a3-8cdd9973f857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14123
73052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1412373052
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3157531057
Short name T1242
Test name
Test status
Simulation time 8425472259 ps
CPU time 9.58 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204060 kb
Host smart-d0e3d169-c60a-4f7a-af1d-5687bb54aca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31575
31057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3157531057
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2567778554
Short name T190
Test name
Test status
Simulation time 8368534064 ps
CPU time 8.27 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204048 kb
Host smart-003d1893-c548-43b1-af5c-ff7008bf750d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25677
78554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2567778554
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1292627256
Short name T456
Test name
Test status
Simulation time 8440404807 ps
CPU time 7.38 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204088 kb
Host smart-92ea2d92-3835-400d-9805-03479b670d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926
27256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1292627256
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1623846618
Short name T393
Test name
Test status
Simulation time 8434643123 ps
CPU time 8.28 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204060 kb
Host smart-47e7bce2-87dc-44db-9859-b3b7d59d6480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
46618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1623846618
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.557740450
Short name T348
Test name
Test status
Simulation time 8371058731 ps
CPU time 8.85 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204068 kb
Host smart-6ec49ef4-7412-4c2d-b124-e154505c6774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55774
0450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.557740450
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.217103228
Short name T110
Test name
Test status
Simulation time 8438052977 ps
CPU time 7.46 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204068 kb
Host smart-c7ebd023-48bc-4fa5-ae12-21dee7f24c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21710
3228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.217103228
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1936364641
Short name T439
Test name
Test status
Simulation time 8398466397 ps
CPU time 7.59 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204088 kb
Host smart-69600eb4-1071-433b-a8b9-a26e831269d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
64641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1936364641
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2830550946
Short name T1268
Test name
Test status
Simulation time 8401492933 ps
CPU time 8.56 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204080 kb
Host smart-9f449e3d-de5e-4203-9876-574f4c1b816d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28305
50946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2830550946
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1524139837
Short name T943
Test name
Test status
Simulation time 8403077160 ps
CPU time 8.08 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204144 kb
Host smart-baea1bc9-f8d2-48f2-90d8-59a03d4dbc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241
39837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1524139837
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3862533626
Short name T564
Test name
Test status
Simulation time 8376975753 ps
CPU time 7.59 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204140 kb
Host smart-f2b5554d-3753-4a55-b231-1793c03e4b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38625
33626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3862533626
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1896704877
Short name T49
Test name
Test status
Simulation time 96570087 ps
CPU time 0.67 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 203984 kb
Host smart-cba81622-9752-4f88-94fe-742c00253258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18967
04877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1896704877
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2710182343
Short name T1098
Test name
Test status
Simulation time 25548062854 ps
CPU time 44.07 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:48:34 PM PDT 24
Peak memory 204352 kb
Host smart-ab392918-ec80-424d-ab8f-e30c3421ff01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27101
82343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2710182343
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3280171301
Short name T1145
Test name
Test status
Simulation time 8412555324 ps
CPU time 9.76 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204108 kb
Host smart-26081243-359e-4adf-8b1f-bc9e6faeb521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32801
71301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3280171301
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.4144193015
Short name T1221
Test name
Test status
Simulation time 8379747852 ps
CPU time 8.81 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204068 kb
Host smart-e9d0e676-63ff-4d6f-b706-88f9bc604a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
93015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.4144193015
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3802263596
Short name T1074
Test name
Test status
Simulation time 8451276420 ps
CPU time 8.06 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204096 kb
Host smart-0649b62f-16fb-489c-b8fe-78b6ad26f8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38022
63596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3802263596
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2686559788
Short name T165
Test name
Test status
Simulation time 8382188400 ps
CPU time 7.68 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:48:01 PM PDT 24
Peak memory 204108 kb
Host smart-a699f301-f7c5-4896-917e-cbb9d07142df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26865
59788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2686559788
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.4176508961
Short name T31
Test name
Test status
Simulation time 8366696158 ps
CPU time 7.49 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204080 kb
Host smart-396e5831-5473-40db-b019-9e884e1bf054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41765
08961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4176508961
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.55315573
Short name T1342
Test name
Test status
Simulation time 8452957110 ps
CPU time 7.88 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204088 kb
Host smart-39ef5de2-626d-4119-afcc-52ce7b41ab82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55315
573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.55315573
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4280341612
Short name T83
Test name
Test status
Simulation time 8404623209 ps
CPU time 7.54 seconds
Started May 02 03:48:02 PM PDT 24
Finished May 02 03:48:12 PM PDT 24
Peak memory 204080 kb
Host smart-75f26cac-f58e-461c-a737-12164ebb9f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42803
41612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4280341612
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2198004063
Short name T1380
Test name
Test status
Simulation time 8409330053 ps
CPU time 8.28 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204096 kb
Host smart-d3e0e17e-c085-4130-b042-88e40533f26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
04063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2198004063
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1469032262
Short name T502
Test name
Test status
Simulation time 8471980159 ps
CPU time 9.71 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:04 PM PDT 24
Peak memory 204048 kb
Host smart-efcd9f4b-b8ff-4183-b0b2-1e9e2fa97ac1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1469032262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1469032262
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2488728253
Short name T762
Test name
Test status
Simulation time 8388664165 ps
CPU time 9.57 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204100 kb
Host smart-f06c0877-c141-4357-be4f-724421e332dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2488728253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2488728253
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2149365761
Short name T1358
Test name
Test status
Simulation time 8446888860 ps
CPU time 8.99 seconds
Started May 02 03:44:51 PM PDT 24
Finished May 02 03:45:01 PM PDT 24
Peak memory 204020 kb
Host smart-fc367e95-f0df-4b0e-bed1-62cad567da11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
65761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2149365761
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.231459882
Short name T1295
Test name
Test status
Simulation time 8390263388 ps
CPU time 8.49 seconds
Started May 02 03:44:48 PM PDT 24
Finished May 02 03:44:58 PM PDT 24
Peak memory 204140 kb
Host smart-2321e29b-9c46-4d43-8e6b-1d5a1a3eef49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23145
9882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.231459882
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.494846152
Short name T939
Test name
Test status
Simulation time 8375993193 ps
CPU time 8.34 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:04 PM PDT 24
Peak memory 204028 kb
Host smart-cbc4a90b-23d9-4bbb-b594-078b99541a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49484
6152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.494846152
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3122155227
Short name T1253
Test name
Test status
Simulation time 135325422 ps
CPU time 1.66 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:44:56 PM PDT 24
Peak memory 204200 kb
Host smart-04c8ed95-945f-48bb-aace-cc7cb7baff0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31221
55227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3122155227
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.877606225
Short name T1363
Test name
Test status
Simulation time 8425479691 ps
CPU time 8.63 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204088 kb
Host smart-5915d5e0-ebac-4a91-b90d-c3b27c467c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87760
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.877606225
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1429845328
Short name T183
Test name
Test status
Simulation time 8363991481 ps
CPU time 10.37 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:12 PM PDT 24
Peak memory 204100 kb
Host smart-9ec3da84-1483-429b-b1cf-786a7c0ab765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14298
45328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1429845328
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3105761718
Short name T1031
Test name
Test status
Simulation time 8444842587 ps
CPU time 9.98 seconds
Started May 02 03:44:50 PM PDT 24
Finished May 02 03:45:01 PM PDT 24
Peak memory 204060 kb
Host smart-5a457b83-92a0-4fea-98ca-c10f53c5475e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
61718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3105761718
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1054461124
Short name T973
Test name
Test status
Simulation time 8421767482 ps
CPU time 7.88 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204124 kb
Host smart-e040d078-ac22-4e5d-a72f-03f064d8d1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
61124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1054461124
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3151698368
Short name T1118
Test name
Test status
Simulation time 8374547736 ps
CPU time 8.95 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:02 PM PDT 24
Peak memory 204128 kb
Host smart-7da07a63-ba36-4100-a84d-6600789fc896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31516
98368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3151698368
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3647522480
Short name T933
Test name
Test status
Simulation time 8471454882 ps
CPU time 8.07 seconds
Started May 02 03:44:50 PM PDT 24
Finished May 02 03:44:59 PM PDT 24
Peak memory 204088 kb
Host smart-62df684b-c337-4112-8a11-35c891ed9414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36475
22480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3647522480
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2293631389
Short name T666
Test name
Test status
Simulation time 8387672167 ps
CPU time 8.82 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:04 PM PDT 24
Peak memory 204128 kb
Host smart-03e13652-dc02-4a56-a99e-f2d449e45753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
31389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2293631389
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.611503720
Short name T1006
Test name
Test status
Simulation time 8420541393 ps
CPU time 9.75 seconds
Started May 02 03:44:49 PM PDT 24
Finished May 02 03:45:00 PM PDT 24
Peak memory 204100 kb
Host smart-52ffbbd0-3ae5-452b-a363-6921337b2ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61150
3720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.611503720
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2317840787
Short name T1067
Test name
Test status
Simulation time 8380111078 ps
CPU time 7.77 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204100 kb
Host smart-dab32cb5-f2cb-4e68-b99c-ad8a33a42eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23178
40787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2317840787
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1256567023
Short name T1153
Test name
Test status
Simulation time 8369043768 ps
CPU time 9.02 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:04 PM PDT 24
Peak memory 204100 kb
Host smart-3cc59d92-3d70-4793-a322-9aa61a2eeff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12565
67023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1256567023
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2894927860
Short name T50
Test name
Test status
Simulation time 60491070 ps
CPU time 0.73 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:44:55 PM PDT 24
Peak memory 203996 kb
Host smart-807e5964-95dd-41c3-b4d4-8014ae384b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
27860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2894927860
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1276129296
Short name T912
Test name
Test status
Simulation time 8386342891 ps
CPU time 7.93 seconds
Started May 02 03:44:54 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204120 kb
Host smart-86dc0da4-90bd-4985-9501-9f9d711cfff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12761
29296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1276129296
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3951511889
Short name T152
Test name
Test status
Simulation time 8381753619 ps
CPU time 8.18 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204096 kb
Host smart-b3d8c15b-d268-4f7f-bcfd-00488c11056e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
11889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3951511889
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1759345197
Short name T797
Test name
Test status
Simulation time 8414806919 ps
CPU time 8.24 seconds
Started May 02 03:44:49 PM PDT 24
Finished May 02 03:44:58 PM PDT 24
Peak memory 204156 kb
Host smart-01f17384-d13b-42ac-bcdc-b33084dcf1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17593
45197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1759345197
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1774385902
Short name T66
Test name
Test status
Simulation time 318507137 ps
CPU time 1.14 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:44:55 PM PDT 24
Peak memory 220340 kb
Host smart-fc9a699c-367a-4202-bbe5-da2725d506ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1774385902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1774385902
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.308372970
Short name T168
Test name
Test status
Simulation time 8371373723 ps
CPU time 8.11 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204116 kb
Host smart-6f3705bf-c917-44f1-b560-016c9095a597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30837
2970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.308372970
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2617400804
Short name T930
Test name
Test status
Simulation time 8404316268 ps
CPU time 8.54 seconds
Started May 02 03:44:50 PM PDT 24
Finished May 02 03:44:59 PM PDT 24
Peak memory 204120 kb
Host smart-355f7696-8798-4d27-8bc3-afade390bf7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26174
00804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2617400804
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.83754642
Short name T1185
Test name
Test status
Simulation time 8474021473 ps
CPU time 7.78 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204100 kb
Host smart-016da7b1-da3c-4910-921d-7e708e4d94c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83754
642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.83754642
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4113480656
Short name T684
Test name
Test status
Simulation time 8376364779 ps
CPU time 8.82 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:45:04 PM PDT 24
Peak memory 204124 kb
Host smart-45597e2e-1fca-4068-bccc-9c7562495928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
80656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4113480656
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.279745600
Short name T90
Test name
Test status
Simulation time 8480441201 ps
CPU time 7.66 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:02 PM PDT 24
Peak memory 204144 kb
Host smart-bb923afd-ca3a-41b5-a9ba-77fe2a41db09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
5600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.279745600
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.2640508756
Short name T1332
Test name
Test status
Simulation time 8504233467 ps
CPU time 9.01 seconds
Started May 02 03:48:18 PM PDT 24
Finished May 02 03:48:28 PM PDT 24
Peak memory 204128 kb
Host smart-1feaf12c-98cd-49cc-b82b-26e52ab2aa20
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2640508756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.2640508756
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.4130974516
Short name T471
Test name
Test status
Simulation time 8379349955 ps
CPU time 7.68 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204136 kb
Host smart-3692c621-8c70-4583-9cdf-f86c020917c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4130974516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.4130974516
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.3181675321
Short name T41
Test name
Test status
Simulation time 8389139278 ps
CPU time 8.02 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204156 kb
Host smart-4652cfd3-b207-4d7b-b52c-a7b02803a802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31816
75321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.3181675321
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2344852317
Short name T391
Test name
Test status
Simulation time 8404797122 ps
CPU time 7.88 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204076 kb
Host smart-e9e4344f-269d-401a-aec6-873207f12f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448
52317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2344852317
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.1768529015
Short name T806
Test name
Test status
Simulation time 8430786605 ps
CPU time 8.48 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204072 kb
Host smart-cef132d9-4c88-4864-9883-98ed72cfb916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17685
29015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1768529015
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2622635377
Short name T454
Test name
Test status
Simulation time 139279962 ps
CPU time 1.4 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204212 kb
Host smart-6c88dbed-51f3-4e88-bafa-39a3c6148ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26226
35377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2622635377
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3687850217
Short name T1181
Test name
Test status
Simulation time 8402423110 ps
CPU time 8.61 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204024 kb
Host smart-a65039e2-c5af-4da4-a477-764f75961479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36878
50217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3687850217
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1379945015
Short name T184
Test name
Test status
Simulation time 8388358876 ps
CPU time 8.22 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204068 kb
Host smart-313c7f75-5852-4413-85fd-766ddcb0086a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13799
45015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1379945015
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.387666366
Short name T530
Test name
Test status
Simulation time 8383023891 ps
CPU time 7.57 seconds
Started May 02 03:47:58 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204144 kb
Host smart-1a55cc6d-bda9-4abd-a9c7-1eae7f06a8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38766
6366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.387666366
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2778614956
Short name T638
Test name
Test status
Simulation time 8420478002 ps
CPU time 10.1 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204080 kb
Host smart-f34c0dd8-1981-48ab-aed4-0e168e26acc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
14956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2778614956
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3418321190
Short name T892
Test name
Test status
Simulation time 8393066762 ps
CPU time 8.37 seconds
Started May 02 03:47:48 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204120 kb
Host smart-6e9ce892-99b3-434d-81bf-499daa90b94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
21190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3418321190
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1898935512
Short name T104
Test name
Test status
Simulation time 8451131665 ps
CPU time 8.75 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204108 kb
Host smart-fb60108a-423e-4d9e-85ac-d15621048cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18989
35512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1898935512
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2341801893
Short name T674
Test name
Test status
Simulation time 8373707356 ps
CPU time 8.4 seconds
Started May 02 03:47:44 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 204128 kb
Host smart-b2c53a48-7824-439d-a8a8-f96ec1013d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23418
01893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2341801893
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.515913705
Short name T312
Test name
Test status
Simulation time 8395297124 ps
CPU time 9.59 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204144 kb
Host smart-a15c45ad-9a90-40d5-963f-adef20d604ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51591
3705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.515913705
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.458881601
Short name T748
Test name
Test status
Simulation time 8397723950 ps
CPU time 10.3 seconds
Started May 02 03:47:43 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204096 kb
Host smart-232e4244-8092-440e-9c3d-823a46613af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45888
1601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.458881601
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3760921015
Short name T1243
Test name
Test status
Simulation time 8429959059 ps
CPU time 8.5 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204076 kb
Host smart-d13ccafb-764f-4216-946f-9f61fe0b53e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
21015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3760921015
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3385599631
Short name T570
Test name
Test status
Simulation time 52263530 ps
CPU time 0.7 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:47:55 PM PDT 24
Peak memory 204000 kb
Host smart-f4f78e20-d226-483a-995e-187eac5427a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
99631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3385599631
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3225278412
Short name T97
Test name
Test status
Simulation time 18155236324 ps
CPU time 36.47 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:34 PM PDT 24
Peak memory 204400 kb
Host smart-97085a0a-e863-4ef3-8ebb-28864dbfa90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
78412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3225278412
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2793121472
Short name T1161
Test name
Test status
Simulation time 8392116646 ps
CPU time 8.31 seconds
Started May 02 03:47:46 PM PDT 24
Finished May 02 03:47:58 PM PDT 24
Peak memory 204064 kb
Host smart-1ae34fd6-77b6-402d-b5f3-6c8b111cba05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27931
21472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2793121472
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2408653353
Short name T1277
Test name
Test status
Simulation time 8429127041 ps
CPU time 8.27 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:57 PM PDT 24
Peak memory 204144 kb
Host smart-c60ebc86-29cc-43ed-ba5f-5264843d11aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
53353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2408653353
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3824284958
Short name T728
Test name
Test status
Simulation time 8407241620 ps
CPU time 9.23 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:52 PM PDT 24
Peak memory 204084 kb
Host smart-2a3dded7-45be-44bf-97af-2f7abe4c5155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38242
84958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3824284958
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.76929878
Short name T178
Test name
Test status
Simulation time 8372115046 ps
CPU time 8.29 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204172 kb
Host smart-44067add-4bc4-4d30-9d60-5ee11e15c190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76929
878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.76929878
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1183600342
Short name T30
Test name
Test status
Simulation time 8391264675 ps
CPU time 8.66 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204080 kb
Host smart-15a85396-53f2-4cce-bb21-6ee26917af6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11836
00342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1183600342
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3117498838
Short name T512
Test name
Test status
Simulation time 8443731761 ps
CPU time 7.75 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204128 kb
Host smart-c8420f49-0e86-4701-ac06-8b664a6ffa72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31174
98838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3117498838
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3208276627
Short name T670
Test name
Test status
Simulation time 8389677957 ps
CPU time 8.26 seconds
Started May 02 03:47:45 PM PDT 24
Finished May 02 03:47:56 PM PDT 24
Peak memory 203460 kb
Host smart-6035b7c9-733c-4272-a4d7-728b85ce90a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082
76627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3208276627
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2999149213
Short name T1183
Test name
Test status
Simulation time 8419324721 ps
CPU time 8.81 seconds
Started May 02 03:47:47 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204068 kb
Host smart-7ca4e87f-f96b-4760-9dbf-3926c543d4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29991
49213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2999149213
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.193002357
Short name T423
Test name
Test status
Simulation time 8467267352 ps
CPU time 7.61 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204052 kb
Host smart-4ad93587-0e72-4b58-b2ae-a91c91500dbe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=193002357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.193002357
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.208489431
Short name T625
Test name
Test status
Simulation time 8393915366 ps
CPU time 8.41 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:08 PM PDT 24
Peak memory 204072 kb
Host smart-abf1c77b-81c1-4aff-89d4-69c2cd2072f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=208489431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.208489431
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.164073645
Short name T243
Test name
Test status
Simulation time 8434054517 ps
CPU time 8.7 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204160 kb
Host smart-f2262866-df27-4d9d-8e2c-e2c99d313490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16407
3645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.164073645
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.598206205
Short name T1092
Test name
Test status
Simulation time 8387755276 ps
CPU time 7.48 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204120 kb
Host smart-c4f3c56c-02d7-46e4-a4f1-91e17bf36e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59820
6205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.598206205
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.803532977
Short name T585
Test name
Test status
Simulation time 8397704770 ps
CPU time 8.94 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204132 kb
Host smart-cb311623-4e28-477a-a5b7-7a4f00dde8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80353
2977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.803532977
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2143504828
Short name T224
Test name
Test status
Simulation time 293307788 ps
CPU time 2.15 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204248 kb
Host smart-a1489568-6a82-4095-9999-52523f67ce54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
04828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2143504828
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.110898922
Short name T142
Test name
Test status
Simulation time 8506705809 ps
CPU time 8.43 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204072 kb
Host smart-425a3250-d3ea-4944-a0ed-241e26f246b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
8922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.110898922
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3663459279
Short name T1072
Test name
Test status
Simulation time 8437971490 ps
CPU time 7.74 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204168 kb
Host smart-ac993ad4-5b76-4e95-ad2d-416814019978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
59279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3663459279
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3182420349
Short name T977
Test name
Test status
Simulation time 8397115941 ps
CPU time 8 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204120 kb
Host smart-f5a897b4-6da8-432c-ace8-fec8cc0b2822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31824
20349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3182420349
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2753290402
Short name T1223
Test name
Test status
Simulation time 8413804857 ps
CPU time 8.21 seconds
Started May 02 03:48:00 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204120 kb
Host smart-583e016d-2855-4887-9d4a-b5b50b70f695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
90402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2753290402
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2766563734
Short name T313
Test name
Test status
Simulation time 8369814082 ps
CPU time 7.82 seconds
Started May 02 03:47:58 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204120 kb
Host smart-cd9cd447-79ae-4b2f-8df6-13647f54559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27665
63734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2766563734
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.910204712
Short name T119
Test name
Test status
Simulation time 8448678582 ps
CPU time 7.81 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204116 kb
Host smart-44a408d9-7592-4276-9152-a7365ef5739f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91020
4712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.910204712
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1570440836
Short name T616
Test name
Test status
Simulation time 8450848983 ps
CPU time 8.3 seconds
Started May 02 03:47:57 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204128 kb
Host smart-dbd41d07-9f7e-4602-b04a-a585c6dfc058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
40836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1570440836
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2983228608
Short name T483
Test name
Test status
Simulation time 8410513343 ps
CPU time 7.76 seconds
Started May 02 03:47:41 PM PDT 24
Finished May 02 03:47:51 PM PDT 24
Peak memory 204164 kb
Host smart-a9378d67-5679-4a05-a6cc-e081aad3573d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
28608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2983228608
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1334383974
Short name T862
Test name
Test status
Simulation time 8438347237 ps
CPU time 7.95 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204148 kb
Host smart-d733caa8-4e79-4aee-8af6-68aae812cbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
83974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1334383974
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3706736995
Short name T28
Test name
Test status
Simulation time 8367441735 ps
CPU time 8.99 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204108 kb
Host smart-5ed76f6b-c7e6-469a-85b6-47e2f0fac3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37067
36995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3706736995
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.972393618
Short name T644
Test name
Test status
Simulation time 79483788 ps
CPU time 0.69 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:47:53 PM PDT 24
Peak memory 204008 kb
Host smart-4c85826a-cfe8-45df-b369-be4bd88ed2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97239
3618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.972393618
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3260393860
Short name T1333
Test name
Test status
Simulation time 29331741392 ps
CPU time 57.75 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:56 PM PDT 24
Peak memory 204420 kb
Host smart-c57619a4-6bc6-4bf5-92c5-5d2f70d7f1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32603
93860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3260393860
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.724308949
Short name T725
Test name
Test status
Simulation time 8382013834 ps
CPU time 8.47 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:08 PM PDT 24
Peak memory 204072 kb
Host smart-1ec79e1d-ee19-463b-a757-d7a20acfd3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72430
8949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.724308949
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1171308874
Short name T932
Test name
Test status
Simulation time 8417361005 ps
CPU time 8.93 seconds
Started May 02 03:48:00 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204068 kb
Host smart-0f0b9bae-fa78-44b8-82d1-c79acc887b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11713
08874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1171308874
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1675059164
Short name T1233
Test name
Test status
Simulation time 8412737875 ps
CPU time 8.2 seconds
Started May 02 03:47:48 PM PDT 24
Finished May 02 03:48:00 PM PDT 24
Peak memory 204072 kb
Host smart-6be1c186-c7e4-46c0-8678-e299a97b8f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16750
59164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1675059164
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1096598579
Short name T334
Test name
Test status
Simulation time 8373078841 ps
CPU time 8.06 seconds
Started May 02 03:48:01 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204060 kb
Host smart-47334785-eff3-446f-b8b9-77ef2e282792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10965
98579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1096598579
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4264774678
Short name T682
Test name
Test status
Simulation time 8370675886 ps
CPU time 7.77 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204140 kb
Host smart-11f62f30-9bc1-4fb4-87c9-17980061a90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
74678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4264774678
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1149558149
Short name T882
Test name
Test status
Simulation time 8435864205 ps
CPU time 9.8 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204132 kb
Host smart-35aa60a3-93e9-4ae2-b2e5-3f891d671643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11495
58149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1149558149
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1283365638
Short name T1147
Test name
Test status
Simulation time 8389754110 ps
CPU time 7.35 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204136 kb
Host smart-366ec578-7b2c-41d8-a634-b461a1c8983e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
65638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1283365638
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.806066750
Short name T766
Test name
Test status
Simulation time 8399371245 ps
CPU time 8.09 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204076 kb
Host smart-c1fcf25b-5dbe-44f6-9bd1-44ce02a6cfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80606
6750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.806066750
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2612368270
Short name T1374
Test name
Test status
Simulation time 8468082594 ps
CPU time 8.59 seconds
Started May 02 03:48:02 PM PDT 24
Finished May 02 03:48:13 PM PDT 24
Peak memory 204100 kb
Host smart-0e7cae98-b346-4fa5-88b7-f2012e1e70cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2612368270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2612368270
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.1832044294
Short name T338
Test name
Test status
Simulation time 8385409475 ps
CPU time 7.78 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:08 PM PDT 24
Peak memory 204036 kb
Host smart-1da21690-2be5-4873-950a-3d212aad7a5e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1832044294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.1832044294
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2967549708
Short name T909
Test name
Test status
Simulation time 8435355271 ps
CPU time 7.83 seconds
Started May 02 03:48:22 PM PDT 24
Finished May 02 03:48:31 PM PDT 24
Peak memory 204128 kb
Host smart-94100a84-a9eb-41c5-a666-11d4dd7aa3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29675
49708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2967549708
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2860341022
Short name T342
Test name
Test status
Simulation time 8378078002 ps
CPU time 10.83 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204048 kb
Host smart-31366751-a322-4d13-9e1b-eb07ae8b59b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
41022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2860341022
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.4095182200
Short name T1166
Test name
Test status
Simulation time 8386875921 ps
CPU time 7.86 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204024 kb
Host smart-01548053-166d-47dc-b1ce-7240ab94b047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
82200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.4095182200
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1292864940
Short name T1167
Test name
Test status
Simulation time 259625989 ps
CPU time 2.04 seconds
Started May 02 03:47:59 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204204 kb
Host smart-2e94a8fd-d50c-4f8f-b7f9-b16e738ca593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
64940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1292864940
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1047216825
Short name T1112
Test name
Test status
Simulation time 8383138237 ps
CPU time 9.43 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204008 kb
Host smart-cd86d5cc-e569-415e-9c40-f88ae08c9237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
16825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1047216825
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1266317407
Short name T850
Test name
Test status
Simulation time 8379662316 ps
CPU time 7.95 seconds
Started May 02 03:47:58 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204128 kb
Host smart-e692d771-b9e2-48dd-a64d-343b91b2219a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12663
17407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1266317407
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.881263205
Short name T746
Test name
Test status
Simulation time 8431609886 ps
CPU time 7.91 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:48:01 PM PDT 24
Peak memory 204060 kb
Host smart-cd0da432-4b8c-4909-acab-e4ad41d4451a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88126
3205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.881263205
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.4088571146
Short name T870
Test name
Test status
Simulation time 8420371455 ps
CPU time 8.56 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204092 kb
Host smart-540d1edd-3751-405b-822f-b39e16d02109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40885
71146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.4088571146
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3572978589
Short name T361
Test name
Test status
Simulation time 8376777833 ps
CPU time 8.25 seconds
Started May 02 03:48:20 PM PDT 24
Finished May 02 03:48:30 PM PDT 24
Peak memory 204128 kb
Host smart-4362a916-fa45-4868-b23e-a3a346897488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
78589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3572978589
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2566087878
Short name T123
Test name
Test status
Simulation time 8413641770 ps
CPU time 8.13 seconds
Started May 02 03:47:58 PM PDT 24
Finished May 02 03:48:09 PM PDT 24
Peak memory 204168 kb
Host smart-5bfd8ff7-d669-4f16-8b4c-e2ececfdd58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25660
87878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2566087878
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3425928597
Short name T1103
Test name
Test status
Simulation time 8402764940 ps
CPU time 9.11 seconds
Started May 02 03:47:49 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204072 kb
Host smart-1cb3e831-470e-4d39-80e4-8be4b55b16d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34259
28597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3425928597
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3012715672
Short name T1257
Test name
Test status
Simulation time 8403366113 ps
CPU time 8.18 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204108 kb
Host smart-5101222f-b9a9-41fb-86d6-b47ca12611bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
15672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3012715672
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.770972288
Short name T95
Test name
Test status
Simulation time 8375621282 ps
CPU time 7.85 seconds
Started May 02 03:47:52 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204120 kb
Host smart-2b5077d4-c995-4169-86fe-1557ed666f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77097
2288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.770972288
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.840792284
Short name T913
Test name
Test status
Simulation time 8373203840 ps
CPU time 10.37 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204148 kb
Host smart-b799d787-d445-4182-8b17-63b559539c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84079
2284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.840792284
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1935533134
Short name T715
Test name
Test status
Simulation time 41313759 ps
CPU time 0.64 seconds
Started May 02 03:47:58 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204016 kb
Host smart-a1d891e6-032d-4f7f-9797-fa395b2179b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19355
33134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1935533134
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4130043226
Short name T275
Test name
Test status
Simulation time 27193954170 ps
CPU time 55.02 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:49:15 PM PDT 24
Peak memory 204424 kb
Host smart-ec4322e2-4495-4bf8-9c54-ceec7e1f06f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41300
43226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4130043226
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2686608024
Short name T1278
Test name
Test status
Simulation time 8411922392 ps
CPU time 8.3 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:48:28 PM PDT 24
Peak memory 204132 kb
Host smart-b77c81fa-98e6-41ee-b2f8-c449c7c746b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26866
08024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2686608024
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2208744807
Short name T1254
Test name
Test status
Simulation time 8452079717 ps
CPU time 9.24 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204048 kb
Host smart-72840c4b-14fd-4b52-b990-0b71784c7beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
44807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2208744807
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.4043634766
Short name T792
Test name
Test status
Simulation time 8400214242 ps
CPU time 8.46 seconds
Started May 02 03:47:51 PM PDT 24
Finished May 02 03:48:04 PM PDT 24
Peak memory 204124 kb
Host smart-be7eda47-86fb-44f8-af06-a1a1a1d0b62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
34766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.4043634766
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2548799702
Short name T887
Test name
Test status
Simulation time 8371073153 ps
CPU time 7.63 seconds
Started May 02 03:47:48 PM PDT 24
Finished May 02 03:47:59 PM PDT 24
Peak memory 204128 kb
Host smart-4b8d1cd2-24a2-48a5-8836-e21ce28b4459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25487
99702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2548799702
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2005779371
Short name T441
Test name
Test status
Simulation time 8376023187 ps
CPU time 10.3 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:10 PM PDT 24
Peak memory 204168 kb
Host smart-8591b3f1-9d03-42da-862e-b87b6482035b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
79371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2005779371
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2268569074
Short name T653
Test name
Test status
Simulation time 8422956050 ps
CPU time 9.12 seconds
Started May 02 03:47:50 PM PDT 24
Finished May 02 03:48:03 PM PDT 24
Peak memory 204068 kb
Host smart-9820c592-1b1a-4c22-bfa8-96a51d6b4c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
69074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2268569074
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2163914563
Short name T764
Test name
Test status
Simulation time 8370027303 ps
CPU time 8.13 seconds
Started May 02 03:48:01 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204148 kb
Host smart-2349d92a-125b-46ea-b25b-66d5bf1b4b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21639
14563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2163914563
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2710743263
Short name T316
Test name
Test status
Simulation time 8384640614 ps
CPU time 7.74 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204132 kb
Host smart-2280d7d2-da58-4ff5-b429-9f2991a95617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27107
43263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2710743263
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3584394375
Short name T404
Test name
Test status
Simulation time 8461780310 ps
CPU time 7.76 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:05 PM PDT 24
Peak memory 204112 kb
Host smart-10189200-dd76-4a92-a80a-aaac06198773
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3584394375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3584394375
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.1419195695
Short name T873
Test name
Test status
Simulation time 8415462844 ps
CPU time 9.51 seconds
Started May 02 03:48:13 PM PDT 24
Finished May 02 03:48:23 PM PDT 24
Peak memory 204140 kb
Host smart-f82dac57-16e0-44ae-bf8d-f4756f331412
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1419195695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.1419195695
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.1258820026
Short name T1085
Test name
Test status
Simulation time 8404815728 ps
CPU time 8.07 seconds
Started May 02 03:48:17 PM PDT 24
Finished May 02 03:48:26 PM PDT 24
Peak memory 204056 kb
Host smart-03ff7868-3683-4e61-a125-3155116ffa2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12588
20026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.1258820026
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3035319603
Short name T307
Test name
Test status
Simulation time 8378548083 ps
CPU time 9.03 seconds
Started May 02 03:48:05 PM PDT 24
Finished May 02 03:48:15 PM PDT 24
Peak memory 204136 kb
Host smart-209ab6d9-c889-46c0-a047-672cc5a15093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
19603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3035319603
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.2025106077
Short name T415
Test name
Test status
Simulation time 8406959137 ps
CPU time 8.88 seconds
Started May 02 03:48:00 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204076 kb
Host smart-efa2c9c8-3729-43fe-8b4f-dbb0742c40b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20251
06077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2025106077
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3309792452
Short name T700
Test name
Test status
Simulation time 185282117 ps
CPU time 1.94 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:02 PM PDT 24
Peak memory 204212 kb
Host smart-47a405ab-7461-4ba7-8396-5927795e7970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33097
92452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3309792452
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.267832481
Short name T479
Test name
Test status
Simulation time 8388530459 ps
CPU time 7.86 seconds
Started May 02 03:48:20 PM PDT 24
Finished May 02 03:48:29 PM PDT 24
Peak memory 204136 kb
Host smart-fb98b232-dfd6-4bfd-bd50-d0719fa96bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26783
2481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.267832481
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3939654071
Short name T782
Test name
Test status
Simulation time 8373100698 ps
CPU time 8.17 seconds
Started May 02 03:48:01 PM PDT 24
Finished May 02 03:48:12 PM PDT 24
Peak memory 204128 kb
Host smart-2fdbaf8c-e012-4b32-b773-8a5b93d4d420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39396
54071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3939654071
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1175447298
Short name T148
Test name
Test status
Simulation time 8377075272 ps
CPU time 9.83 seconds
Started May 02 03:47:55 PM PDT 24
Finished May 02 03:48:10 PM PDT 24
Peak memory 204108 kb
Host smart-4e55177b-8e01-4343-a8c1-266942fc9906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11754
47298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1175447298
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3943694072
Short name T34
Test name
Test status
Simulation time 8425277153 ps
CPU time 8.07 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:07 PM PDT 24
Peak memory 204112 kb
Host smart-a4bde0a1-9f59-41d5-8668-c202de9a4afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39436
94072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3943694072
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.513467860
Short name T499
Test name
Test status
Simulation time 8453001319 ps
CPU time 7.78 seconds
Started May 02 03:47:59 PM PDT 24
Finished May 02 03:48:10 PM PDT 24
Peak memory 204128 kb
Host smart-cc156c4b-4d3b-4b53-9d9a-c031c805baee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51346
7860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.513467860
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1350516420
Short name T1149
Test name
Test status
Simulation time 8459789918 ps
CPU time 9.05 seconds
Started May 02 03:47:59 PM PDT 24
Finished May 02 03:48:11 PM PDT 24
Peak memory 204072 kb
Host smart-45f0d3a6-15f8-42e6-ad19-0a22f64a0d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
16420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1350516420
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2683927304
Short name T367
Test name
Test status
Simulation time 8383211544 ps
CPU time 7.57 seconds
Started May 02 03:48:06 PM PDT 24
Finished May 02 03:48:14 PM PDT 24
Peak memory 204068 kb
Host smart-2a5fded3-c74c-4614-a8cd-1e1762c64683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26839
27304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2683927304
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.238986033
Short name T358
Test name
Test status
Simulation time 8460163451 ps
CPU time 7.61 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204060 kb
Host smart-02a0219a-e903-4853-8bf1-db1aeae7cd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
6033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.238986033
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3395671514
Short name T191
Test name
Test status
Simulation time 8451876771 ps
CPU time 8.07 seconds
Started May 02 03:48:20 PM PDT 24
Finished May 02 03:48:29 PM PDT 24
Peak memory 204128 kb
Host smart-3fd4d203-7f3c-417f-97a4-63cc0f445e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956
71514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3395671514
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3087939562
Short name T445
Test name
Test status
Simulation time 8389465429 ps
CPU time 8.55 seconds
Started May 02 03:48:12 PM PDT 24
Finished May 02 03:48:22 PM PDT 24
Peak memory 204116 kb
Host smart-860018d7-f250-4be9-b82b-20b8325d5525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
39562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3087939562
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1192060529
Short name T487
Test name
Test status
Simulation time 8386789284 ps
CPU time 7.88 seconds
Started May 02 03:48:02 PM PDT 24
Finished May 02 03:48:12 PM PDT 24
Peak memory 204088 kb
Host smart-43bc780b-8001-402b-a2fd-303ccceb6c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11920
60529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1192060529
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2250770149
Short name T590
Test name
Test status
Simulation time 8451739837 ps
CPU time 9.82 seconds
Started May 02 03:47:56 PM PDT 24
Finished May 02 03:48:10 PM PDT 24
Peak memory 204136 kb
Host smart-aa5844ef-d1e0-4b18-910b-6f7e0034f336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22507
70149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2250770149
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.568550149
Short name T383
Test name
Test status
Simulation time 8402825947 ps
CPU time 8.19 seconds
Started May 02 03:47:59 PM PDT 24
Finished May 02 03:48:10 PM PDT 24
Peak memory 204088 kb
Host smart-61aa3582-aedb-4993-bb91-04d2f52b7574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56855
0149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.568550149
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1600089230
Short name T820
Test name
Test status
Simulation time 8381189499 ps
CPU time 8.04 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:35 PM PDT 24
Peak memory 204116 kb
Host smart-d558f314-5eed-48c7-9f8b-aaca4d9ea5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16000
89230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1600089230
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.212156255
Short name T940
Test name
Test status
Simulation time 8369686505 ps
CPU time 7.45 seconds
Started May 02 03:48:07 PM PDT 24
Finished May 02 03:48:16 PM PDT 24
Peak memory 204116 kb
Host smart-84441834-1c46-4470-87cb-2477515e2b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
6255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.212156255
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.349819634
Short name T1250
Test name
Test status
Simulation time 8521108660 ps
CPU time 7.68 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204104 kb
Host smart-f7921bda-38f8-451f-876b-bd205d1a6eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34981
9634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.349819634
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2509757232
Short name T91
Test name
Test status
Simulation time 8387767074 ps
CPU time 8 seconds
Started May 02 03:47:53 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204132 kb
Host smart-5bfaa0d1-86be-4e2c-a9d6-584435994862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25097
57232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2509757232
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3997979837
Short name T1000
Test name
Test status
Simulation time 8397867099 ps
CPU time 7.62 seconds
Started May 02 03:47:54 PM PDT 24
Finished May 02 03:48:06 PM PDT 24
Peak memory 204124 kb
Host smart-6fd52574-677e-487a-86b0-563098347c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
79837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3997979837
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.822973925
Short name T619
Test name
Test status
Simulation time 8512179821 ps
CPU time 8.86 seconds
Started May 02 03:48:16 PM PDT 24
Finished May 02 03:48:26 PM PDT 24
Peak memory 204144 kb
Host smart-a8fb5e02-e0e6-4911-a604-4f214aaaded1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=822973925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.822973925
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2737431836
Short name T371
Test name
Test status
Simulation time 8382118282 ps
CPU time 9.16 seconds
Started May 02 03:48:12 PM PDT 24
Finished May 02 03:48:22 PM PDT 24
Peak memory 204072 kb
Host smart-723fcffa-aadb-402a-8dff-3532c0744426
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2737431836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2737431836
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.2075647031
Short name T1371
Test name
Test status
Simulation time 8470665185 ps
CPU time 7.81 seconds
Started May 02 03:48:21 PM PDT 24
Finished May 02 03:48:30 PM PDT 24
Peak memory 204160 kb
Host smart-0f515ef2-89fc-41b7-88b2-87205c4a69ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20756
47031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.2075647031
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3766174532
Short name T677
Test name
Test status
Simulation time 8394920383 ps
CPU time 8.1 seconds
Started May 02 03:48:02 PM PDT 24
Finished May 02 03:48:13 PM PDT 24
Peak memory 204048 kb
Host smart-a515e1be-8595-4a5b-b520-e2491c0e7328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37661
74532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3766174532
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.721123299
Short name T304
Test name
Test status
Simulation time 8373038410 ps
CPU time 8.15 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:35 PM PDT 24
Peak memory 204132 kb
Host smart-4a4bb27a-cf42-493b-9a3a-f9e5d6eff23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72112
3299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.721123299
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1761554106
Short name T1116
Test name
Test status
Simulation time 126432651 ps
CPU time 1.36 seconds
Started May 02 03:48:22 PM PDT 24
Finished May 02 03:48:24 PM PDT 24
Peak memory 204224 kb
Host smart-757a8bce-5426-4718-bd31-6276c3c63b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
54106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1761554106
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3955330990
Short name T18
Test name
Test status
Simulation time 8429009065 ps
CPU time 7.96 seconds
Started May 02 03:48:29 PM PDT 24
Finished May 02 03:48:38 PM PDT 24
Peak memory 204068 kb
Host smart-77a5dc48-1821-4ed0-a6e8-f5d74067a27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
30990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3955330990
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2811277467
Short name T202
Test name
Test status
Simulation time 8378195552 ps
CPU time 8.1 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:31 PM PDT 24
Peak memory 204076 kb
Host smart-2e86e469-574e-4649-af2c-98a6511eb668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
77467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2811277467
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.638592609
Short name T498
Test name
Test status
Simulation time 8421362627 ps
CPU time 7.85 seconds
Started May 02 03:48:14 PM PDT 24
Finished May 02 03:48:23 PM PDT 24
Peak memory 204084 kb
Host smart-d59906aa-4dd7-46ea-8507-f1ffc62322f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63859
2609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.638592609
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1846590999
Short name T215
Test name
Test status
Simulation time 8416498241 ps
CPU time 8.11 seconds
Started May 02 03:48:18 PM PDT 24
Finished May 02 03:48:27 PM PDT 24
Peak memory 204104 kb
Host smart-2bea9fad-aae6-406a-9d97-8aa1040ec895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
90999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1846590999
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3946903205
Short name T710
Test name
Test status
Simulation time 8405097680 ps
CPU time 7.82 seconds
Started May 02 03:48:12 PM PDT 24
Finished May 02 03:48:21 PM PDT 24
Peak memory 204144 kb
Host smart-a6ae618e-7c46-4afb-93bd-e1e7d8599c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39469
03205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3946903205
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.4012137414
Short name T1326
Test name
Test status
Simulation time 8479378866 ps
CPU time 7.98 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:32 PM PDT 24
Peak memory 204136 kb
Host smart-732a3b77-f8f7-41ea-b8d6-24d67c923a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
37414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.4012137414
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3994106481
Short name T411
Test name
Test status
Simulation time 8413682861 ps
CPU time 8.92 seconds
Started May 02 03:48:15 PM PDT 24
Finished May 02 03:48:25 PM PDT 24
Peak memory 204032 kb
Host smart-21974f30-6d75-4718-83a6-ecdf360694ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39941
06481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3994106481
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1797090701
Short name T1240
Test name
Test status
Simulation time 8398213901 ps
CPU time 7.85 seconds
Started May 02 03:48:05 PM PDT 24
Finished May 02 03:48:14 PM PDT 24
Peak memory 204136 kb
Host smart-24cb3ea1-51b1-4335-9373-a145f08d0f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17970
90701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1797090701
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3289441901
Short name T180
Test name
Test status
Simulation time 8372193976 ps
CPU time 8 seconds
Started May 02 03:48:24 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204136 kb
Host smart-4634001a-6906-46a0-ac1b-8f8e294f981e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32894
41901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3289441901
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1563822351
Short name T1275
Test name
Test status
Simulation time 8374759941 ps
CPU time 7.55 seconds
Started May 02 03:48:22 PM PDT 24
Finished May 02 03:48:30 PM PDT 24
Peak memory 204152 kb
Host smart-857af4ba-7142-40ce-82d9-d113079938bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
22351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1563822351
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.4118704585
Short name T47
Test name
Test status
Simulation time 35709408 ps
CPU time 0.66 seconds
Started May 02 03:48:14 PM PDT 24
Finished May 02 03:48:16 PM PDT 24
Peak memory 203968 kb
Host smart-ec9114d4-a32c-4a6a-99fa-cd6820cd660f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
04585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.4118704585
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1523434661
Short name T1304
Test name
Test status
Simulation time 18441511467 ps
CPU time 38.36 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:48:58 PM PDT 24
Peak memory 204352 kb
Host smart-f6b1cb74-3634-4c58-9f45-a461982c49fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15234
34661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1523434661
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.127402857
Short name T1015
Test name
Test status
Simulation time 8415047863 ps
CPU time 8.15 seconds
Started May 02 03:48:11 PM PDT 24
Finished May 02 03:48:21 PM PDT 24
Peak memory 204036 kb
Host smart-5c49134c-411f-4a54-87d9-cd2e8672e9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12740
2857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.127402857
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2303117290
Short name T513
Test name
Test status
Simulation time 8417739754 ps
CPU time 8.65 seconds
Started May 02 03:48:10 PM PDT 24
Finished May 02 03:48:19 PM PDT 24
Peak memory 204004 kb
Host smart-51d5dc4a-39f4-4719-849f-15942c3f6854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23031
17290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2303117290
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3005202747
Short name T701
Test name
Test status
Simulation time 8410591192 ps
CPU time 7.7 seconds
Started May 02 03:48:14 PM PDT 24
Finished May 02 03:48:23 PM PDT 24
Peak memory 204096 kb
Host smart-374b8a36-d077-4d08-a7ef-aec5b0cf3481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
02747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3005202747
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.395823846
Short name T1180
Test name
Test status
Simulation time 8428376859 ps
CPU time 7.87 seconds
Started May 02 03:48:07 PM PDT 24
Finished May 02 03:48:16 PM PDT 24
Peak memory 204088 kb
Host smart-cfdb8a91-25d0-44a1-9904-a3231a8c6d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
3846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.395823846
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1021676563
Short name T898
Test name
Test status
Simulation time 8371530540 ps
CPU time 8.03 seconds
Started May 02 03:48:32 PM PDT 24
Finished May 02 03:48:42 PM PDT 24
Peak memory 204128 kb
Host smart-6c29cd63-783c-4eba-844c-528b6ddd5254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10216
76563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1021676563
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1813971913
Short name T1302
Test name
Test status
Simulation time 8466475160 ps
CPU time 7.81 seconds
Started May 02 03:48:09 PM PDT 24
Finished May 02 03:48:18 PM PDT 24
Peak memory 204096 kb
Host smart-a6a32556-b9bf-40ff-bba0-1cce730de2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
71913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1813971913
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2247229262
Short name T979
Test name
Test status
Simulation time 8401723792 ps
CPU time 8.26 seconds
Started May 02 03:48:15 PM PDT 24
Finished May 02 03:48:24 PM PDT 24
Peak memory 204112 kb
Host smart-19867363-faa9-4571-a7c2-c1b1d189b9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22472
29262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2247229262
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.539741907
Short name T573
Test name
Test status
Simulation time 8367417190 ps
CPU time 7.67 seconds
Started May 02 03:48:12 PM PDT 24
Finished May 02 03:48:21 PM PDT 24
Peak memory 204032 kb
Host smart-dde46106-2979-4e2f-84c8-6b90eb4b7bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53974
1907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.539741907
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.226012242
Short name T655
Test name
Test status
Simulation time 8473141281 ps
CPU time 8.7 seconds
Started May 02 03:48:33 PM PDT 24
Finished May 02 03:48:43 PM PDT 24
Peak memory 204144 kb
Host smart-2b475e58-3883-4968-a754-f50b7cef9672
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=226012242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.226012242
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1574121824
Short name T1034
Test name
Test status
Simulation time 8389401187 ps
CPU time 8.2 seconds
Started May 02 03:48:26 PM PDT 24
Finished May 02 03:48:36 PM PDT 24
Peak memory 204076 kb
Host smart-3f439ff6-8dcc-4cca-8281-253ed4ad47f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1574121824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1574121824
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.1883701450
Short name T839
Test name
Test status
Simulation time 8406580889 ps
CPU time 8.88 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 204132 kb
Host smart-7532ce5d-288d-492d-8518-8b2415dd8b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837
01450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.1883701450
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.894921381
Short name T61
Test name
Test status
Simulation time 8377052034 ps
CPU time 7.85 seconds
Started May 02 03:48:12 PM PDT 24
Finished May 02 03:48:21 PM PDT 24
Peak memory 204136 kb
Host smart-121eeb7c-bdec-4887-94b7-23bfb63a2ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89492
1381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.894921381
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.603107706
Short name T1133
Test name
Test status
Simulation time 8377533253 ps
CPU time 8.3 seconds
Started May 02 03:48:24 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204156 kb
Host smart-cf42eab0-693f-4bc6-a110-acb36e459656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60310
7706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.603107706
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1361775024
Short name T726
Test name
Test status
Simulation time 42576014 ps
CPU time 1.13 seconds
Started May 02 03:48:18 PM PDT 24
Finished May 02 03:48:20 PM PDT 24
Peak memory 204200 kb
Host smart-9235349f-dfe6-4dfa-8905-fcb1f768f954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617
75024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1361775024
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.942120982
Short name T1158
Test name
Test status
Simulation time 8430183318 ps
CPU time 8.95 seconds
Started May 02 03:48:18 PM PDT 24
Finished May 02 03:48:28 PM PDT 24
Peak memory 204024 kb
Host smart-86529d75-552b-44be-9bdc-ce58b12e9f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94212
0982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.942120982
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3278571595
Short name T1276
Test name
Test status
Simulation time 8375678428 ps
CPU time 9.08 seconds
Started May 02 03:48:21 PM PDT 24
Finished May 02 03:48:31 PM PDT 24
Peak memory 204156 kb
Host smart-c875b065-3c0a-49eb-8fb5-d6a75c9ac442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32785
71595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3278571595
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.187563418
Short name T434
Test name
Test status
Simulation time 8457976919 ps
CPU time 8.11 seconds
Started May 02 03:48:12 PM PDT 24
Finished May 02 03:48:21 PM PDT 24
Peak memory 204060 kb
Host smart-d20ba3f9-7a5f-485b-906b-8166df0f75fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18756
3418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.187563418
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2231319491
Short name T993
Test name
Test status
Simulation time 8458306456 ps
CPU time 9.06 seconds
Started May 02 03:48:06 PM PDT 24
Finished May 02 03:48:17 PM PDT 24
Peak memory 204040 kb
Host smart-3cc378b1-2b5c-4178-b024-525ee469890d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
19491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2231319491
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1902272018
Short name T647
Test name
Test status
Simulation time 8381009443 ps
CPU time 7.92 seconds
Started May 02 03:48:15 PM PDT 24
Finished May 02 03:48:24 PM PDT 24
Peak memory 204108 kb
Host smart-adc30d73-5ad2-421a-9125-ecc8cedbe8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19022
72018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1902272018
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.571448071
Short name T1260
Test name
Test status
Simulation time 8515405472 ps
CPU time 9.98 seconds
Started May 02 03:48:29 PM PDT 24
Finished May 02 03:48:40 PM PDT 24
Peak memory 204144 kb
Host smart-0174fcb3-2857-45f9-8a48-0f9aa95a9faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57144
8071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.571448071
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3311284631
Short name T759
Test name
Test status
Simulation time 8398503868 ps
CPU time 8 seconds
Started May 02 03:48:18 PM PDT 24
Finished May 02 03:48:27 PM PDT 24
Peak memory 204108 kb
Host smart-667152dc-ee9c-4c83-9402-56adf9123f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33112
84631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3311284631
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2418549934
Short name T780
Test name
Test status
Simulation time 8394157887 ps
CPU time 7.92 seconds
Started May 02 03:48:17 PM PDT 24
Finished May 02 03:48:26 PM PDT 24
Peak memory 204044 kb
Host smart-3d90cd3c-93c7-4997-b6a7-e29d4692b6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24185
49934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2418549934
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1767309008
Short name T868
Test name
Test status
Simulation time 8401525864 ps
CPU time 8.93 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:48:29 PM PDT 24
Peak memory 204112 kb
Host smart-89231e74-3fa9-41ab-88c0-75ecbfd70cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17673
09008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1767309008
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2152837426
Short name T757
Test name
Test status
Simulation time 8386996650 ps
CPU time 9.78 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:34 PM PDT 24
Peak memory 204152 kb
Host smart-cb5d28dc-9129-4c07-828f-f5b1449b80b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21528
37426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2152837426
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2022233272
Short name T821
Test name
Test status
Simulation time 33699195 ps
CPU time 0.68 seconds
Started May 02 03:48:15 PM PDT 24
Finished May 02 03:48:16 PM PDT 24
Peak memory 204016 kb
Host smart-9d33a9eb-1607-453c-8689-0ce0788cd7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20222
33272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2022233272
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2060552929
Short name T568
Test name
Test status
Simulation time 23235243215 ps
CPU time 45.65 seconds
Started May 02 03:48:22 PM PDT 24
Finished May 02 03:49:09 PM PDT 24
Peak memory 204372 kb
Host smart-716d1e92-01a0-4493-98af-9d7e218ccf76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
52929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2060552929
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2588399419
Short name T640
Test name
Test status
Simulation time 8421453350 ps
CPU time 9.2 seconds
Started May 02 03:48:28 PM PDT 24
Finished May 02 03:48:38 PM PDT 24
Peak memory 204096 kb
Host smart-f5867594-3c94-401a-8fa8-1a6eecc9db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
99419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2588399419
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.4253698899
Short name T1019
Test name
Test status
Simulation time 8414456552 ps
CPU time 8.99 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204128 kb
Host smart-f5baab31-bc22-49ed-8dc9-1954fcec612e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42536
98899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.4253698899
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.401120834
Short name T1345
Test name
Test status
Simulation time 8405124792 ps
CPU time 9.41 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:42 PM PDT 24
Peak memory 204120 kb
Host smart-1573bb38-2afa-42c6-96a9-a9dcf904c529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40112
0834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.401120834
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3342341738
Short name T357
Test name
Test status
Simulation time 8378207761 ps
CPU time 8.41 seconds
Started May 02 03:48:15 PM PDT 24
Finished May 02 03:48:24 PM PDT 24
Peak memory 204096 kb
Host smart-0805f612-fa55-449f-bd9e-5618083540dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
41738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3342341738
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3780992065
Short name T16
Test name
Test status
Simulation time 8368265710 ps
CPU time 7.77 seconds
Started May 02 03:48:22 PM PDT 24
Finished May 02 03:48:31 PM PDT 24
Peak memory 204144 kb
Host smart-2d56845a-847e-41db-989d-3885f220e3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
92065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3780992065
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3364794599
Short name T769
Test name
Test status
Simulation time 8418545185 ps
CPU time 8.83 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:48:29 PM PDT 24
Peak memory 204132 kb
Host smart-4bdd00a6-b56c-4f65-a567-527c041010ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33647
94599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3364794599
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.748090145
Short name T1070
Test name
Test status
Simulation time 8375407194 ps
CPU time 7.92 seconds
Started May 02 03:48:13 PM PDT 24
Finished May 02 03:48:22 PM PDT 24
Peak memory 204096 kb
Host smart-f965fe38-0ee1-40d0-bcdb-d5c1522c40b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74809
0145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.748090145
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1140956818
Short name T490
Test name
Test status
Simulation time 8407539501 ps
CPU time 8.97 seconds
Started May 02 03:48:26 PM PDT 24
Finished May 02 03:48:37 PM PDT 24
Peak memory 204056 kb
Host smart-6a1450b3-f133-4aaa-b2eb-6f37bcf762c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
56818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1140956818
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.756383355
Short name T53
Test name
Test status
Simulation time 8469152269 ps
CPU time 7.64 seconds
Started May 02 03:48:14 PM PDT 24
Finished May 02 03:48:23 PM PDT 24
Peak memory 204136 kb
Host smart-c6c04670-6c4d-474a-a5ec-c65f3061e653
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=756383355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.756383355
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2651654926
Short name T1263
Test name
Test status
Simulation time 8377672912 ps
CPU time 8.08 seconds
Started May 02 03:48:27 PM PDT 24
Finished May 02 03:48:36 PM PDT 24
Peak memory 204076 kb
Host smart-cc9df2b8-5a3b-4fcc-abc4-ce07c7fe92a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2651654926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2651654926
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.3425251898
Short name T344
Test name
Test status
Simulation time 8497407453 ps
CPU time 9.74 seconds
Started May 02 03:48:24 PM PDT 24
Finished May 02 03:48:35 PM PDT 24
Peak memory 204136 kb
Host smart-9a19f3c6-a1cc-4c26-b337-335ca9032d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
51898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.3425251898
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2012547743
Short name T848
Test name
Test status
Simulation time 8375552561 ps
CPU time 8.15 seconds
Started May 02 03:48:17 PM PDT 24
Finished May 02 03:48:26 PM PDT 24
Peak memory 204108 kb
Host smart-fe74dc2d-9b7a-4377-99a6-946cebc8c11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20125
47743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2012547743
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.1958109368
Short name T417
Test name
Test status
Simulation time 8373113860 ps
CPU time 8.22 seconds
Started May 02 03:48:39 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204120 kb
Host smart-764a66c2-c253-4f7d-9d7e-3e8a87c9db78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
09368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1958109368
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1038392098
Short name T1036
Test name
Test status
Simulation time 46332829 ps
CPU time 1.23 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:40 PM PDT 24
Peak memory 204120 kb
Host smart-9f5132fc-1031-43e0-a78c-22175b553a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10383
92098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1038392098
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1549221701
Short name T1199
Test name
Test status
Simulation time 8426629799 ps
CPU time 8.07 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:40 PM PDT 24
Peak memory 204072 kb
Host smart-0dee36e1-14ac-40a9-bdf8-37953644fd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
21701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1549221701
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.815026971
Short name T1206
Test name
Test status
Simulation time 8364372679 ps
CPU time 8.07 seconds
Started May 02 03:48:21 PM PDT 24
Finished May 02 03:48:30 PM PDT 24
Peak memory 204104 kb
Host smart-16bfc319-d2da-4315-bfb8-763fc7ca843e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81502
6971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.815026971
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3698445389
Short name T1350
Test name
Test status
Simulation time 8404863355 ps
CPU time 7.56 seconds
Started May 02 03:48:39 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204136 kb
Host smart-d07ec5af-aaac-42e3-8782-e1e37ff3cdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36984
45389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3698445389
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1463887727
Short name T872
Test name
Test status
Simulation time 8421857894 ps
CPU time 8.18 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:46 PM PDT 24
Peak memory 204124 kb
Host smart-047b7222-f10c-4c97-b36f-f141c223f698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14638
87727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1463887727
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.491212067
Short name T359
Test name
Test status
Simulation time 8371987920 ps
CPU time 9.84 seconds
Started May 02 03:48:30 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 204048 kb
Host smart-9df57ea7-ed35-4d60-9ed3-5db123a11228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49121
2067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.491212067
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1797735978
Short name T36
Test name
Test status
Simulation time 8432319257 ps
CPU time 8.25 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 204124 kb
Host smart-3e6bf0f1-049b-40fe-aed1-fe46faa65102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
35978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1797735978
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2234835291
Short name T1122
Test name
Test status
Simulation time 8399158271 ps
CPU time 9.3 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204120 kb
Host smart-dfc73b28-a590-4473-b29c-11f9c6b3412f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
35291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2234835291
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3499024141
Short name T881
Test name
Test status
Simulation time 8374848705 ps
CPU time 8.88 seconds
Started May 02 03:48:33 PM PDT 24
Finished May 02 03:48:43 PM PDT 24
Peak memory 204124 kb
Host smart-2c515b89-5c6b-4e15-b1a7-7eecb9ad5fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
24141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3499024141
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1260087052
Short name T843
Test name
Test status
Simulation time 8373532166 ps
CPU time 7.46 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:39 PM PDT 24
Peak memory 204140 kb
Host smart-4f1a6ed0-1916-4f8a-889d-244cda434d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12600
87052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1260087052
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.4229039316
Short name T356
Test name
Test status
Simulation time 51028058 ps
CPU time 0.69 seconds
Started May 02 03:48:17 PM PDT 24
Finished May 02 03:48:18 PM PDT 24
Peak memory 203996 kb
Host smart-b614c3e5-9c83-4500-a8ee-94b13b41607c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42290
39316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.4229039316
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1257482695
Short name T1251
Test name
Test status
Simulation time 17268139354 ps
CPU time 29.94 seconds
Started May 02 03:48:18 PM PDT 24
Finished May 02 03:48:49 PM PDT 24
Peak memory 204396 kb
Host smart-2f981054-1669-41e8-8a68-97f4de05a282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12574
82695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1257482695
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.4060849831
Short name T552
Test name
Test status
Simulation time 8409500435 ps
CPU time 9.52 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204088 kb
Host smart-d64e0ed9-4571-43f6-a5b2-1c5269ccd2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40608
49831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4060849831
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4111536103
Short name T145
Test name
Test status
Simulation time 8387820539 ps
CPU time 7.74 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:47 PM PDT 24
Peak memory 204136 kb
Host smart-00f24a91-ca67-4d96-a756-a44eb5e02f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41115
36103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4111536103
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1871823563
Short name T1196
Test name
Test status
Simulation time 8382816430 ps
CPU time 8.3 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:43 PM PDT 24
Peak memory 203456 kb
Host smart-89edb978-5e6e-4401-91e9-1d8b5f5c0f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18718
23563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1871823563
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1438910007
Short name T547
Test name
Test status
Simulation time 8375430307 ps
CPU time 8.24 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 203900 kb
Host smart-9823d081-e375-43d5-934a-88174bcd1b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
10007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1438910007
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2782792669
Short name T1094
Test name
Test status
Simulation time 8371573900 ps
CPU time 7.97 seconds
Started May 02 03:48:20 PM PDT 24
Finished May 02 03:48:29 PM PDT 24
Peak memory 204096 kb
Host smart-71b88c2d-74ae-4c0f-8f76-a8a7f7b0e91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27827
92669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2782792669
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.4083889794
Short name T87
Test name
Test status
Simulation time 8404226035 ps
CPU time 7.9 seconds
Started May 02 03:48:42 PM PDT 24
Finished May 02 03:48:53 PM PDT 24
Peak memory 204124 kb
Host smart-8246595c-c67d-4680-8499-dea577e84ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
89794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.4083889794
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1534523394
Short name T558
Test name
Test status
Simulation time 8427236191 ps
CPU time 8.35 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:48:28 PM PDT 24
Peak memory 204072 kb
Host smart-f2a18f73-a1af-48f9-bdb3-2c6d8a570db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345
23394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1534523394
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.2245891812
Short name T988
Test name
Test status
Simulation time 8476306691 ps
CPU time 7.75 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:34 PM PDT 24
Peak memory 204072 kb
Host smart-ce99e823-911f-4486-8f81-0e7ae365d8b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2245891812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.2245891812
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.1561298295
Short name T919
Test name
Test status
Simulation time 8373803624 ps
CPU time 7.89 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:45 PM PDT 24
Peak memory 204144 kb
Host smart-09cddd63-571a-4fa9-8b45-f261122880be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1561298295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.1561298295
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3028239416
Short name T523
Test name
Test status
Simulation time 8459053975 ps
CPU time 8.13 seconds
Started May 02 03:48:40 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204040 kb
Host smart-5d7b88c1-20a1-4aef-b5f0-52a12e128aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30282
39416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3028239416
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.694851311
Short name T960
Test name
Test status
Simulation time 8371716163 ps
CPU time 8.67 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:46 PM PDT 24
Peak memory 204104 kb
Host smart-d6759181-161b-41ca-b47f-0bae566b0e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69485
1311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.694851311
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.3150800778
Short name T628
Test name
Test status
Simulation time 8375361421 ps
CPU time 9.17 seconds
Started May 02 03:48:41 PM PDT 24
Finished May 02 03:48:54 PM PDT 24
Peak memory 204112 kb
Host smart-d3c52b39-70a2-48eb-a28b-8be76e5b5aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
00778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3150800778
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.506849302
Short name T395
Test name
Test status
Simulation time 77102242 ps
CPU time 1.87 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:28 PM PDT 24
Peak memory 204160 kb
Host smart-800b7a86-72d3-4878-b808-7fae336613ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50684
9302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.506849302
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1316742004
Short name T711
Test name
Test status
Simulation time 8502752758 ps
CPU time 7.74 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:32 PM PDT 24
Peak memory 204064 kb
Host smart-87d12558-0b4e-4d24-b034-528c68bb0708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
42004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1316742004
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1140413537
Short name T398
Test name
Test status
Simulation time 8387135966 ps
CPU time 7.58 seconds
Started May 02 03:48:40 PM PDT 24
Finished May 02 03:48:52 PM PDT 24
Peak memory 204124 kb
Host smart-e34d5fa7-3d49-4b1a-a532-4fc4250bcfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
13537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1140413537
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.91226798
Short name T624
Test name
Test status
Simulation time 8408007539 ps
CPU time 8.76 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:48 PM PDT 24
Peak memory 204068 kb
Host smart-d64064aa-c4bb-4f5a-83c0-d193a6e30d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91226
798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.91226798
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1994970557
Short name T1017
Test name
Test status
Simulation time 8414948155 ps
CPU time 8.54 seconds
Started May 02 03:48:20 PM PDT 24
Finished May 02 03:48:30 PM PDT 24
Peak memory 204112 kb
Host smart-acbbaaf2-4915-4d4c-ad0c-c62e0be7eec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19949
70557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1994970557
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.695078617
Short name T896
Test name
Test status
Simulation time 8370462179 ps
CPU time 8.16 seconds
Started May 02 03:48:19 PM PDT 24
Finished May 02 03:48:28 PM PDT 24
Peak memory 204072 kb
Host smart-a2db5f35-b5d3-4a2f-bef7-3365f0a0a00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69507
8617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.695078617
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.669723835
Short name T799
Test name
Test status
Simulation time 8447884189 ps
CPU time 7.88 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:45 PM PDT 24
Peak memory 203468 kb
Host smart-b70eb626-e727-4d2a-b66b-a1c3f24150d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66972
3835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.669723835
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.877465435
Short name T761
Test name
Test status
Simulation time 8399136148 ps
CPU time 9.08 seconds
Started May 02 03:48:23 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204096 kb
Host smart-e95a3da0-3532-41ec-abce-971b60d94793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87746
5435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.877465435
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1104118167
Short name T941
Test name
Test status
Simulation time 8393337742 ps
CPU time 7.63 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:34 PM PDT 24
Peak memory 204096 kb
Host smart-2e34d854-c20f-460e-8eda-91397c637a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
18167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1104118167
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3936974266
Short name T177
Test name
Test status
Simulation time 8409191970 ps
CPU time 8.92 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204116 kb
Host smart-858ad45b-0d82-466a-939c-e7715b44e07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39369
74266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3936974266
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2082029708
Short name T542
Test name
Test status
Simulation time 8364383067 ps
CPU time 8.43 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:48 PM PDT 24
Peak memory 204096 kb
Host smart-ba199319-a143-4dd5-9687-31aab49601eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20820
29708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2082029708
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.364301092
Short name T379
Test name
Test status
Simulation time 46713983 ps
CPU time 0.65 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:42 PM PDT 24
Peak memory 204024 kb
Host smart-d19a352e-06e6-4bb2-9221-4f416e504d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36430
1092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.364301092
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2430264614
Short name T278
Test name
Test status
Simulation time 27731401157 ps
CPU time 54.7 seconds
Started May 02 03:48:39 PM PDT 24
Finished May 02 03:49:38 PM PDT 24
Peak memory 204444 kb
Host smart-9d4375e2-98a0-406a-bf48-35fd0176723d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
64614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2430264614
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.664747727
Short name T849
Test name
Test status
Simulation time 8410052791 ps
CPU time 10.35 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:38 PM PDT 24
Peak memory 204048 kb
Host smart-f07ab4fd-9919-4c00-8c89-edce8e42bced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66474
7727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.664747727
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1737229928
Short name T963
Test name
Test status
Simulation time 8383972302 ps
CPU time 8.54 seconds
Started May 02 03:48:24 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204048 kb
Host smart-ba67a831-10a0-4179-a859-82ec24be164e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
29928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1737229928
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2670935713
Short name T1062
Test name
Test status
Simulation time 8414398624 ps
CPU time 7.43 seconds
Started May 02 03:48:25 PM PDT 24
Finished May 02 03:48:35 PM PDT 24
Peak memory 204060 kb
Host smart-b258063f-eda5-4e37-89fb-64709009c703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
35713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2670935713
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.4194696897
Short name T488
Test name
Test status
Simulation time 8419453180 ps
CPU time 8.3 seconds
Started May 02 03:48:24 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204104 kb
Host smart-96e31d23-4792-4040-9fe6-02d228c7a240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41946
96897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.4194696897
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2068081633
Short name T466
Test name
Test status
Simulation time 8371376082 ps
CPU time 8.89 seconds
Started May 02 03:48:21 PM PDT 24
Finished May 02 03:48:31 PM PDT 24
Peak memory 204108 kb
Host smart-9c57408f-f6df-40af-9c7f-676fa38260f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
81633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2068081633
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.300522497
Short name T396
Test name
Test status
Simulation time 8443314783 ps
CPU time 8.88 seconds
Started May 02 03:48:29 PM PDT 24
Finished May 02 03:48:38 PM PDT 24
Peak memory 204104 kb
Host smart-939dba71-77d7-4553-98fe-0bb413f7e0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.300522497
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1758756208
Short name T1028
Test name
Test status
Simulation time 8404124966 ps
CPU time 8.15 seconds
Started May 02 03:48:24 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204108 kb
Host smart-9951d0de-e2e0-4cdb-9052-1bff2889038d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17587
56208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1758756208
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.4247597226
Short name T1082
Test name
Test status
Simulation time 8376974726 ps
CPU time 7.31 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:47 PM PDT 24
Peak memory 204096 kb
Host smart-353501de-38b5-4bbb-8ba7-d2e65c015815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42475
97226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.4247597226
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.945365298
Short name T1256
Test name
Test status
Simulation time 8469381468 ps
CPU time 10.19 seconds
Started May 02 03:48:33 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 204100 kb
Host smart-799834c6-97f9-4e2a-83d8-0b35fd1e3ffa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=945365298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.945365298
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.475327470
Short name T817
Test name
Test status
Simulation time 8394162505 ps
CPU time 8.11 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:49 PM PDT 24
Peak memory 204156 kb
Host smart-947f4530-e30e-4ef7-a19e-0ddc56f215db
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=475327470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.475327470
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.828878523
Short name T247
Test name
Test status
Simulation time 8415982586 ps
CPU time 8 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 204040 kb
Host smart-eb9f3a5f-0365-42ca-a552-af7e34c9852c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82887
8523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.828878523
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1616547763
Short name T566
Test name
Test status
Simulation time 8373880303 ps
CPU time 8.38 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 203948 kb
Host smart-dcb193e3-1b45-44da-abca-70109a6e6f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16165
47763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1616547763
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.129121417
Short name T431
Test name
Test status
Simulation time 8382003062 ps
CPU time 10.01 seconds
Started May 02 03:48:39 PM PDT 24
Finished May 02 03:48:52 PM PDT 24
Peak memory 204124 kb
Host smart-db7e3a50-efe2-4d05-b45f-8ce5bfa96f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912
1417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.129121417
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2542049611
Short name T984
Test name
Test status
Simulation time 177997044 ps
CPU time 1.99 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 204200 kb
Host smart-b6413568-5c60-4c42-a58c-459c343e8780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
49611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2542049611
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2774900987
Short name T151
Test name
Test status
Simulation time 8418159035 ps
CPU time 8.02 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204132 kb
Host smart-040eaebe-ae2f-4579-ac25-257a235b588e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27749
00987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2774900987
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1185122568
Short name T1150
Test name
Test status
Simulation time 8369192305 ps
CPU time 7.74 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:47 PM PDT 24
Peak memory 204116 kb
Host smart-94cebb7c-f201-48ae-8c49-5e0a87f44373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
22568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1185122568
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3456595805
Short name T863
Test name
Test status
Simulation time 8467299354 ps
CPU time 8.31 seconds
Started May 02 03:48:39 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204128 kb
Host smart-fc80196e-b598-4732-a5e7-0842d8f15c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
95805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3456595805
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.892164262
Short name T1121
Test name
Test status
Simulation time 8446161548 ps
CPU time 9.69 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:49 PM PDT 24
Peak memory 204140 kb
Host smart-84c42cd7-ce6e-47ed-ad4a-0202e45d0b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89216
4262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.892164262
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3239940015
Short name T1100
Test name
Test status
Simulation time 8382772025 ps
CPU time 7.84 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:45 PM PDT 24
Peak memory 204080 kb
Host smart-14d9c9f0-cdcc-4b60-81be-7c164abec94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32399
40015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3239940015
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.515091704
Short name T107
Test name
Test status
Simulation time 8450535921 ps
CPU time 7.72 seconds
Started May 02 03:48:57 PM PDT 24
Finished May 02 03:49:08 PM PDT 24
Peak memory 204136 kb
Host smart-ee378712-b351-467a-88e3-353b46a3ae2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51509
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.515091704
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3313138388
Short name T1238
Test name
Test status
Simulation time 8382004650 ps
CPU time 8.3 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204128 kb
Host smart-ebe129f2-976a-4979-bf67-dec0a844fb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131
38388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3313138388
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1117691662
Short name T749
Test name
Test status
Simulation time 8383739206 ps
CPU time 9.91 seconds
Started May 02 03:48:40 PM PDT 24
Finished May 02 03:48:54 PM PDT 24
Peak memory 204044 kb
Host smart-96993992-cb32-4bde-b0b0-828fd6e15387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
91662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1117691662
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4198126837
Short name T176
Test name
Test status
Simulation time 8418432041 ps
CPU time 7.45 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 203820 kb
Host smart-3be736dc-1562-438e-a8bd-fabb14419c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41981
26837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4198126837
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.113654372
Short name T1230
Test name
Test status
Simulation time 8374988277 ps
CPU time 8.91 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204108 kb
Host smart-c461107c-fa50-4dec-956c-4384c31d2934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
4372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.113654372
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.194376471
Short name T424
Test name
Test status
Simulation time 46543860 ps
CPU time 0.65 seconds
Started May 02 03:48:32 PM PDT 24
Finished May 02 03:48:33 PM PDT 24
Peak memory 204008 kb
Host smart-eda6e486-5af2-4ef8-abd0-536ff89c0f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
6471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.194376471
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.658029181
Short name T257
Test name
Test status
Simulation time 24649181193 ps
CPU time 44.95 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:49:25 PM PDT 24
Peak memory 203752 kb
Host smart-b0d01608-44bd-4e8d-8c44-83a1e7fb9e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65802
9181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.658029181
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2345428967
Short name T946
Test name
Test status
Simulation time 8393928975 ps
CPU time 10.6 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:48 PM PDT 24
Peak memory 204060 kb
Host smart-ba2edb5c-bacf-4bae-8a26-3ca2dcc6f602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
28967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2345428967
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.1365701619
Short name T794
Test name
Test status
Simulation time 8436417990 ps
CPU time 8.91 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204080 kb
Host smart-6f39a5c0-5f9b-4828-b22e-ebe983534467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
01619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.1365701619
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1262217503
Short name T967
Test name
Test status
Simulation time 8398516579 ps
CPU time 8.56 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204036 kb
Host smart-44920453-f0c7-4794-9fcb-c2455aede414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
17503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1262217503
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1768105133
Short name T1198
Test name
Test status
Simulation time 8375892659 ps
CPU time 9.04 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:45 PM PDT 24
Peak memory 204128 kb
Host smart-d745a020-028a-4c9e-82e4-8c2c56609d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17681
05133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1768105133
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.802115335
Short name T885
Test name
Test status
Simulation time 8471262045 ps
CPU time 8.27 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:49 PM PDT 24
Peak memory 204140 kb
Host smart-14b8a044-8d10-49ac-839a-dda294974fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80211
5335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.802115335
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.164430738
Short name T1096
Test name
Test status
Simulation time 8384243740 ps
CPU time 8.03 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:46 PM PDT 24
Peak memory 204124 kb
Host smart-2373611f-3297-43b0-8777-6e589fc20384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16443
0738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.164430738
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.252258113
Short name T860
Test name
Test status
Simulation time 8453784276 ps
CPU time 9.7 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204076 kb
Host smart-e3040107-0b52-4f5e-ae50-b2a0e70ea258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25225
8113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.252258113
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.4094305553
Short name T1316
Test name
Test status
Simulation time 8470139915 ps
CPU time 10.66 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:46 PM PDT 24
Peak memory 204100 kb
Host smart-2faeb52a-e011-4726-ae54-917bd372c920
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4094305553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.4094305553
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.4287976096
Short name T669
Test name
Test status
Simulation time 8412820510 ps
CPU time 8.27 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:47 PM PDT 24
Peak memory 204100 kb
Host smart-f3335899-a532-429b-ac0d-0c7c406dcc63
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4287976096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.4287976096
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2614694028
Short name T1352
Test name
Test status
Simulation time 8466614221 ps
CPU time 10.19 seconds
Started May 02 03:48:41 PM PDT 24
Finished May 02 03:48:55 PM PDT 24
Peak memory 204144 kb
Host smart-fa850cad-d996-41c5-862c-d5f9b1685e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
94028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2614694028
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2591775221
Short name T775
Test name
Test status
Simulation time 8382671286 ps
CPU time 8.02 seconds
Started May 02 03:48:37 PM PDT 24
Finished May 02 03:48:48 PM PDT 24
Peak memory 204148 kb
Host smart-2db29587-56ec-49b3-b227-5a059e8b3544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25917
75221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2591775221
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.4068775375
Short name T1114
Test name
Test status
Simulation time 8384204119 ps
CPU time 8.28 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 203888 kb
Host smart-7c8dca27-0d32-4ae9-a81e-59d4c9f762e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
75375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.4068775375
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1294871727
Short name T1080
Test name
Test status
Simulation time 56869029 ps
CPU time 1.33 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:37 PM PDT 24
Peak memory 204184 kb
Host smart-2b54f98c-c068-4c87-9cbb-6104bd56f049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12948
71727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1294871727
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1006602463
Short name T845
Test name
Test status
Simulation time 8382376845 ps
CPU time 7.87 seconds
Started May 02 03:48:33 PM PDT 24
Finished May 02 03:48:42 PM PDT 24
Peak memory 204100 kb
Host smart-86bd35ff-3d07-4327-8d37-2a9a88f8bbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066
02463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1006602463
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.876732092
Short name T189
Test name
Test status
Simulation time 8376693002 ps
CPU time 8.22 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:49 PM PDT 24
Peak memory 204072 kb
Host smart-cd3d147c-c675-4840-bb19-61b5c0dfcfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87673
2092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.876732092
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.932027230
Short name T800
Test name
Test status
Simulation time 8377372026 ps
CPU time 9.08 seconds
Started May 02 03:48:31 PM PDT 24
Finished May 02 03:48:41 PM PDT 24
Peak memory 204140 kb
Host smart-d5db3930-a551-4f4f-90ab-8cde574cc654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93202
7230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.932027230
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.462335644
Short name T676
Test name
Test status
Simulation time 8423007718 ps
CPU time 9.12 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:50 PM PDT 24
Peak memory 204068 kb
Host smart-ba9f52a6-9f56-4ed8-9f79-c5839fc8c526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46233
5644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.462335644
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.212876410
Short name T660
Test name
Test status
Simulation time 8369966204 ps
CPU time 7.36 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:43 PM PDT 24
Peak memory 204060 kb
Host smart-702760cb-fa73-425f-9232-7579ede5894d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21287
6410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.212876410
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.475100218
Short name T1370
Test name
Test status
Simulation time 8411250947 ps
CPU time 7.77 seconds
Started May 02 03:48:39 PM PDT 24
Finished May 02 03:48:51 PM PDT 24
Peak memory 204144 kb
Host smart-7fa59ee2-c7c9-46fa-955f-6b6e7ed3b1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47510
0218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.475100218
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1982088335
Short name T1063
Test name
Test status
Simulation time 8444421143 ps
CPU time 8.35 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 204088 kb
Host smart-40a1c5b3-0697-400e-a4d2-91a90aa6bb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19820
88335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1982088335
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2563083745
Short name T990
Test name
Test status
Simulation time 8427607837 ps
CPU time 9.87 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:48 PM PDT 24
Peak memory 204100 kb
Host smart-ad5f4bdb-e884-4ae3-a0e2-0d6d431169c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25630
83745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2563083745
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2706928884
Short name T1357
Test name
Test status
Simulation time 8386110144 ps
CPU time 8.96 seconds
Started May 02 03:48:35 PM PDT 24
Finished May 02 03:48:45 PM PDT 24
Peak memory 204084 kb
Host smart-4aecea01-a802-4a1e-8658-87c46e274886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
28884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2706928884
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1770243892
Short name T26
Test name
Test status
Simulation time 8369291153 ps
CPU time 9.12 seconds
Started May 02 03:48:40 PM PDT 24
Finished May 02 03:48:53 PM PDT 24
Peak memory 204132 kb
Host smart-a0e48946-31f2-4df6-a37d-dfcd2fe3f1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17702
43892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1770243892
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4125135762
Short name T462
Test name
Test status
Simulation time 108816894 ps
CPU time 0.75 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:39 PM PDT 24
Peak memory 203968 kb
Host smart-5eba73e5-b955-4c7b-acb8-b371613e569a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41251
35762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4125135762
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3549400067
Short name T1136
Test name
Test status
Simulation time 18559013023 ps
CPU time 37.45 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:49:23 PM PDT 24
Peak memory 204420 kb
Host smart-fd2e7a3b-d692-406c-9c03-c169b7727f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35494
00067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3549400067
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2607580077
Short name T991
Test name
Test status
Simulation time 8378055356 ps
CPU time 7.89 seconds
Started May 02 03:48:30 PM PDT 24
Finished May 02 03:48:39 PM PDT 24
Peak memory 204088 kb
Host smart-1e9be269-b015-4a38-937c-83016caaf1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26075
80077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2607580077
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2907532317
Short name T793
Test name
Test status
Simulation time 8387538200 ps
CPU time 7.59 seconds
Started May 02 03:48:36 PM PDT 24
Finished May 02 03:48:46 PM PDT 24
Peak memory 204156 kb
Host smart-283c6926-4281-4f18-bea2-dab1824c42f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29075
32317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2907532317
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2631999900
Short name T1051
Test name
Test status
Simulation time 8422129205 ps
CPU time 7.81 seconds
Started May 02 03:48:38 PM PDT 24
Finished May 02 03:48:49 PM PDT 24
Peak memory 204060 kb
Host smart-2937f0a1-4fed-4fd1-9a45-6546b4e69e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26319
99900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2631999900
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.688747236
Short name T432
Test name
Test status
Simulation time 8368942749 ps
CPU time 7.66 seconds
Started May 02 03:48:52 PM PDT 24
Finished May 02 03:49:01 PM PDT 24
Peak memory 204080 kb
Host smart-265294f5-9e57-4d5e-9984-829b69002259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68874
7236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.688747236
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4088086089
Short name T373
Test name
Test status
Simulation time 8362207016 ps
CPU time 8.57 seconds
Started May 02 03:48:34 PM PDT 24
Finished May 02 03:48:44 PM PDT 24
Peak memory 204096 kb
Host smart-5407b5b4-be0a-4033-b656-5c5c53f6c956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40880
86089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4088086089
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.178674806
Short name T489
Test name
Test status
Simulation time 8440884123 ps
CPU time 8.15 seconds
Started May 02 03:48:33 PM PDT 24
Finished May 02 03:48:42 PM PDT 24
Peak memory 204128 kb
Host smart-e9c98141-1e3c-4d0c-888f-bcd645ee8ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17867
4806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.178674806
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3026299668
Short name T884
Test name
Test status
Simulation time 8383547701 ps
CPU time 8.73 seconds
Started May 02 03:48:33 PM PDT 24
Finished May 02 03:48:43 PM PDT 24
Peak memory 204096 kb
Host smart-cb3c0236-63c7-4be4-b43a-f2489b27ba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262
99668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3026299668
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1237387431
Short name T736
Test name
Test status
Simulation time 8370105590 ps
CPU time 7.64 seconds
Started May 02 03:48:40 PM PDT 24
Finished May 02 03:48:52 PM PDT 24
Peak memory 204128 kb
Host smart-78c3831c-a7ca-4b87-9a78-136cdbb0d9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12373
87431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1237387431
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.826330546
Short name T911
Test name
Test status
Simulation time 8464237312 ps
CPU time 8.91 seconds
Started May 02 03:44:57 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204092 kb
Host smart-b2cc62a9-32d0-43ec-89e5-fc873356d69f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=826330546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.826330546
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.838164611
Short name T996
Test name
Test status
Simulation time 8385607234 ps
CPU time 9.21 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204172 kb
Host smart-2baa4ba4-63cb-45c2-a6df-d6fc6cff3dfb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=838164611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.838164611
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.1045223640
Short name T1365
Test name
Test status
Simulation time 8459447989 ps
CPU time 7.48 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204116 kb
Host smart-48d1a250-2db5-42a6-a1dd-b7786251cd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10452
23640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.1045223640
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2464354873
Short name T1287
Test name
Test status
Simulation time 8377645971 ps
CPU time 8.97 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204104 kb
Host smart-bcab09ac-792e-40cc-ba7f-a23c40bfb043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24643
54873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2464354873
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.3689661683
Short name T520
Test name
Test status
Simulation time 8434798364 ps
CPU time 8.4 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:01 PM PDT 24
Peak memory 204092 kb
Host smart-15647241-4fdb-4318-be99-1a832a054025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36896
61683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3689661683
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3844325670
Short name T2
Test name
Test status
Simulation time 202318191 ps
CPU time 2.14 seconds
Started May 02 03:44:53 PM PDT 24
Finished May 02 03:44:57 PM PDT 24
Peak memory 204168 kb
Host smart-eb160760-7fa0-4b98-8c8e-c99e54c0259c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38443
25670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3844325670
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3209358032
Short name T1040
Test name
Test status
Simulation time 8462782854 ps
CPU time 7.77 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204144 kb
Host smart-56b46c7a-5da2-40d0-b802-c72dc86c9ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32093
58032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3209358032
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3444758166
Short name T1335
Test name
Test status
Simulation time 8366383153 ps
CPU time 8.28 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204104 kb
Host smart-d5b06167-d702-449c-86e5-4eb10735dab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34447
58166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3444758166
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.423391176
Short name T526
Test name
Test status
Simulation time 8460019864 ps
CPU time 7.74 seconds
Started May 02 03:44:51 PM PDT 24
Finished May 02 03:44:59 PM PDT 24
Peak memory 204116 kb
Host smart-c9fdb817-4413-443d-bf2b-7cea88778817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42339
1176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.423391176
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1054229935
Short name T522
Test name
Test status
Simulation time 8417948466 ps
CPU time 10.21 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204064 kb
Host smart-7f1b22ba-1c0c-403b-b12f-c124c13716f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10542
29935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1054229935
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2137886155
Short name T372
Test name
Test status
Simulation time 8375949546 ps
CPU time 9.2 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:08 PM PDT 24
Peak memory 204044 kb
Host smart-df668b66-98b0-4562-8d5d-f15f860fa879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21378
86155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2137886155
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3461517883
Short name T112
Test name
Test status
Simulation time 8432366269 ps
CPU time 7.59 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204072 kb
Host smart-663088a3-c745-402c-8f5e-24967623109d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34615
17883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3461517883
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1145903529
Short name T438
Test name
Test status
Simulation time 8401955913 ps
CPU time 8.71 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204116 kb
Host smart-f76e3d18-37ad-4e9d-862d-3351e2693daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
03529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1145903529
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1909167184
Short name T17
Test name
Test status
Simulation time 8402728973 ps
CPU time 9.97 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204064 kb
Host smart-132d0af7-3962-44df-b584-78b4a5c298b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19091
67184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1909167184
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1917397544
Short name T805
Test name
Test status
Simulation time 8427766401 ps
CPU time 7.82 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204052 kb
Host smart-a4e87162-b419-4155-be25-ac5702caf37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173
97544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1917397544
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.4078992503
Short name T747
Test name
Test status
Simulation time 8371233688 ps
CPU time 7.98 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204088 kb
Host smart-c02a6503-e2d7-4b1e-8084-f7442bf05cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40789
92503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.4078992503
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2634632291
Short name T621
Test name
Test status
Simulation time 55609159 ps
CPU time 0.68 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:44:57 PM PDT 24
Peak memory 204008 kb
Host smart-e1bf08cd-14e1-424f-a8af-1ede118a92b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346
32291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2634632291
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1908465112
Short name T1117
Test name
Test status
Simulation time 27157830972 ps
CPU time 53.97 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:45:51 PM PDT 24
Peak memory 204392 kb
Host smart-ad2db4bb-d50e-4c51-af04-08605668c333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19084
65112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1908465112
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.4884784
Short name T1219
Test name
Test status
Simulation time 8403365606 ps
CPU time 9.54 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204076 kb
Host smart-8508c1a5-3790-4a81-b2ec-36a5e6ba060f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48847
84 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.4884784
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4004300983
Short name T981
Test name
Test status
Simulation time 8415114976 ps
CPU time 8.45 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204100 kb
Host smart-583b5e50-00c6-4b6e-8fd0-98e49e95433b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
00983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4004300983
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1252069100
Short name T1135
Test name
Test status
Simulation time 8406541235 ps
CPU time 8.51 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204048 kb
Host smart-6a122a0a-f7bb-4525-9292-e50d5fc7960b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12520
69100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1252069100
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.403519219
Short name T55
Test name
Test status
Simulation time 8371017018 ps
CPU time 10.5 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:08 PM PDT 24
Peak memory 204152 kb
Host smart-37220c99-e1cc-4706-89b0-6e6313af1eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40351
9219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.403519219
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.533604934
Short name T854
Test name
Test status
Simulation time 8364883186 ps
CPU time 8.3 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204088 kb
Host smart-4b5f5f55-4e53-41e1-88d1-32b84f6796cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53360
4934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.533604934
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.223424262
Short name T136
Test name
Test status
Simulation time 8422449434 ps
CPU time 7.52 seconds
Started May 02 03:44:52 PM PDT 24
Finished May 02 03:45:01 PM PDT 24
Peak memory 204068 kb
Host smart-317e3e55-a986-4d74-8e0e-12d8c5f8ecd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22342
4262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.223424262
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.965989737
Short name T910
Test name
Test status
Simulation time 8395169894 ps
CPU time 8.11 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204076 kb
Host smart-211dc2de-1f0f-44fb-98b0-43b3983a8084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96598
9737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.965989737
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3947963510
Short name T1211
Test name
Test status
Simulation time 8446972786 ps
CPU time 9.73 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204128 kb
Host smart-15fef065-22ed-40ba-bbbd-230451549e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39479
63510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3947963510
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2317217224
Short name T899
Test name
Test status
Simulation time 8470840571 ps
CPU time 7.66 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204132 kb
Host smart-da1b5317-2a17-4136-953e-8f4ea8bd4127
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2317217224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2317217224
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3386515455
Short name T1045
Test name
Test status
Simulation time 8422728134 ps
CPU time 7.41 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:05 PM PDT 24
Peak memory 204136 kb
Host smart-266f571b-4584-475f-ac38-1020910439ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3386515455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3386515455
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.4011584137
Short name T1319
Test name
Test status
Simulation time 8433512926 ps
CPU time 9.41 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204124 kb
Host smart-5f445c3d-f89a-4fd4-8061-876615eb12de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40115
84137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.4011584137
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3844636827
Short name T906
Test name
Test status
Simulation time 8377868392 ps
CPU time 8.17 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:45:05 PM PDT 24
Peak memory 204080 kb
Host smart-42951bc8-71f3-4205-be95-a3c5a8e2e798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38446
36827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3844636827
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.1507822181
Short name T557
Test name
Test status
Simulation time 8376938155 ps
CPU time 8.3 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204156 kb
Host smart-700d2921-88b6-46c7-aeff-17e8a66e71a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15078
22181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1507822181
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3778112524
Short name T978
Test name
Test status
Simulation time 8390451643 ps
CPU time 8.36 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204124 kb
Host smart-369d43a8-e56f-45d4-924e-d9e3a96bc3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
12524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3778112524
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1157914563
Short name T1368
Test name
Test status
Simulation time 8370608310 ps
CPU time 8.74 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204060 kb
Host smart-734aae02-a737-4d63-b9b4-a8638a992d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
14563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1157914563
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2262536034
Short name T606
Test name
Test status
Simulation time 8381651527 ps
CPU time 8.96 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204128 kb
Host smart-15e771eb-000a-4659-bd18-b358a582cd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22625
36034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2262536034
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.31603033
Short name T569
Test name
Test status
Simulation time 8421099285 ps
CPU time 8.18 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204132 kb
Host smart-35391868-f46d-4436-9d04-cfdf46611814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.31603033
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3860463264
Short name T818
Test name
Test status
Simulation time 8372959368 ps
CPU time 8.04 seconds
Started May 02 03:44:57 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204100 kb
Host smart-187a586d-ffcb-473b-a375-7c0822fb86ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38604
63264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3860463264
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.868901891
Short name T33
Test name
Test status
Simulation time 8392233761 ps
CPU time 8.98 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204152 kb
Host smart-596a37a5-0e39-44eb-8d44-b273758a3c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86890
1891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.868901891
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3432922612
Short name T567
Test name
Test status
Simulation time 8385125379 ps
CPU time 7.65 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:05 PM PDT 24
Peak memory 204048 kb
Host smart-1ede8471-246e-4116-ad69-e42f6838e0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34329
22612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3432922612
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3552181432
Short name T974
Test name
Test status
Simulation time 8421106435 ps
CPU time 8.58 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:08 PM PDT 24
Peak memory 204064 kb
Host smart-95a47ae0-f02d-43ee-851c-acd05bf49d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35521
81432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3552181432
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2244815812
Short name T1044
Test name
Test status
Simulation time 8392037087 ps
CPU time 7.55 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:45:05 PM PDT 24
Peak memory 204108 kb
Host smart-ed4b72a9-be65-42df-98e0-ea1b169835a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
15812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2244815812
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2962751408
Short name T25
Test name
Test status
Simulation time 8375555917 ps
CPU time 9.16 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204072 kb
Host smart-d06cd5da-0b77-49ec-aef9-d3b1b1a636eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29627
51408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2962751408
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3833739381
Short name T1151
Test name
Test status
Simulation time 90127276 ps
CPU time 0.71 seconds
Started May 02 03:44:56 PM PDT 24
Finished May 02 03:44:58 PM PDT 24
Peak memory 204004 kb
Host smart-ac2f594f-1c4f-4f26-9beb-2b34ceb5df89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
39381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3833739381
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3335421287
Short name T1021
Test name
Test status
Simulation time 21061367778 ps
CPU time 36.86 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:39 PM PDT 24
Peak memory 204368 kb
Host smart-5275d663-1276-4ea9-9d19-4e1e2d0b9112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33354
21287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3335421287
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3761940469
Short name T497
Test name
Test status
Simulation time 8410908092 ps
CPU time 7.84 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204120 kb
Host smart-50e8c0e0-b66a-4dae-b9d3-fe4c516787d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37619
40469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3761940469
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1533686539
Short name T1188
Test name
Test status
Simulation time 8409441660 ps
CPU time 7.7 seconds
Started May 02 03:44:55 PM PDT 24
Finished May 02 03:45:04 PM PDT 24
Peak memory 204096 kb
Host smart-95afb52a-674e-4b11-bc86-da9aeaf35cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336
86539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1533686539
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3723236475
Short name T622
Test name
Test status
Simulation time 8378959907 ps
CPU time 8.02 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204144 kb
Host smart-9d4651bf-4ee1-44ff-9f28-3a61d8a0449f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37232
36475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3723236475
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1072175636
Short name T802
Test name
Test status
Simulation time 8427479971 ps
CPU time 7.84 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204116 kb
Host smart-8d46f0b9-a685-4445-8d5d-515472288c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10721
75636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1072175636
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.456604049
Short name T455
Test name
Test status
Simulation time 8398066211 ps
CPU time 7.78 seconds
Started May 02 03:44:54 PM PDT 24
Finished May 02 03:45:03 PM PDT 24
Peak memory 204124 kb
Host smart-da09bd2e-93c4-4691-b80f-c9be98b9bc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45660
4049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.456604049
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.847591526
Short name T879
Test name
Test status
Simulation time 8430417029 ps
CPU time 7.54 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204124 kb
Host smart-6954da60-dbd4-4b11-bba6-fc92f0165840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84759
1526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.847591526
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3785657679
Short name T314
Test name
Test status
Simulation time 8427707226 ps
CPU time 7.78 seconds
Started May 02 03:44:58 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204128 kb
Host smart-b3068aba-be83-43de-8cc9-c38c29383341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856
57679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3785657679
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.4262009550
Short name T377
Test name
Test status
Simulation time 8419600224 ps
CPU time 8.6 seconds
Started May 02 03:44:59 PM PDT 24
Finished May 02 03:45:09 PM PDT 24
Peak memory 204148 kb
Host smart-deed955d-e41c-448b-8209-53fe07747b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42620
09550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.4262009550
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.2424032868
Short name T1273
Test name
Test status
Simulation time 8473119175 ps
CPU time 7.51 seconds
Started May 02 03:45:00 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204096 kb
Host smart-7d2216f3-a1f8-4a1c-bacd-dbd1bac50b25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2424032868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.2424032868
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.542581953
Short name T486
Test name
Test status
Simulation time 8418067644 ps
CPU time 7.84 seconds
Started May 02 03:45:04 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204104 kb
Host smart-447b0ee1-be3c-40f3-a651-ada6f96a8ecd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=542581953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.542581953
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.1903835679
Short name T1165
Test name
Test status
Simulation time 8457337927 ps
CPU time 9.04 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:12 PM PDT 24
Peak memory 204132 kb
Host smart-1daf9e21-aef7-44d2-9ecb-36921f5b7be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
35679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.1903835679
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.40771447
Short name T365
Test name
Test status
Simulation time 8377376030 ps
CPU time 8.83 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204104 kb
Host smart-5a0ad3e1-1770-4cd7-b514-ce8031bf38b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40771
447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.40771447
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.1268540854
Short name T364
Test name
Test status
Simulation time 8377553411 ps
CPU time 9.45 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204140 kb
Host smart-c267bf62-16b0-489e-a36b-a96a40855922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12685
40854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1268540854
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2581907776
Short name T853
Test name
Test status
Simulation time 156116707 ps
CPU time 1.77 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:07 PM PDT 24
Peak memory 204196 kb
Host smart-4439238b-c387-470f-9be6-e2f43cebf60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25819
07776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2581907776
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3738116392
Short name T153
Test name
Test status
Simulation time 8393718590 ps
CPU time 7.58 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204064 kb
Host smart-c856d857-81ec-457c-b38a-1d62cd8c33f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37381
16392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3738116392
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3491687327
Short name T1076
Test name
Test status
Simulation time 8366734365 ps
CPU time 9.51 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:12 PM PDT 24
Peak memory 204060 kb
Host smart-e7a7f9af-a268-4a1f-809e-fb9a43df2f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
87327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3491687327
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.918437006
Short name T422
Test name
Test status
Simulation time 8400188235 ps
CPU time 8.86 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:12 PM PDT 24
Peak memory 204136 kb
Host smart-81ca71fc-773b-41ae-8121-3c6e895a9c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91843
7006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.918437006
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2525615314
Short name T1237
Test name
Test status
Simulation time 8420447343 ps
CPU time 8.13 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204068 kb
Host smart-bbccda41-a24a-4ab2-bafa-adf7208c7fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
15314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2525615314
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4060461577
Short name T836
Test name
Test status
Simulation time 8376635150 ps
CPU time 8.1 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204104 kb
Host smart-d09fdcbd-13ca-4275-9c6c-da2e95c14aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40604
61577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4060461577
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.326562553
Short name T121
Test name
Test status
Simulation time 8418221533 ps
CPU time 8.05 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204168 kb
Host smart-82550631-d9c3-4a08-b597-5e2c1dc14ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32656
2553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.326562553
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3896181413
Short name T785
Test name
Test status
Simulation time 8420675715 ps
CPU time 8.4 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:12 PM PDT 24
Peak memory 204136 kb
Host smart-c2c30745-21eb-41cf-a89f-22732c4959f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38961
81413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3896181413
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.388434640
Short name T689
Test name
Test status
Simulation time 8412735631 ps
CPU time 7.48 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204076 kb
Host smart-49470a17-dd1a-444a-bedb-cb59b668cd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
4640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.388434640
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3121067016
Short name T193
Test name
Test status
Simulation time 8405721837 ps
CPU time 8.12 seconds
Started May 02 03:45:05 PM PDT 24
Finished May 02 03:45:15 PM PDT 24
Peak memory 203652 kb
Host smart-2ff72c66-b6b0-45ad-896a-dbd8cdbe270b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
67016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3121067016
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3554637176
Short name T442
Test name
Test status
Simulation time 8376787631 ps
CPU time 10.07 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:14 PM PDT 24
Peak memory 204120 kb
Host smart-91e3d29a-0131-420c-a8d1-0aaf084002a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35546
37176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3554637176
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2913778021
Short name T1303
Test name
Test status
Simulation time 18362693500 ps
CPU time 37.53 seconds
Started May 02 03:45:04 PM PDT 24
Finished May 02 03:45:44 PM PDT 24
Peak memory 204368 kb
Host smart-f27af89d-337d-4d44-ad15-ab8e6fa6c413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137
78021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2913778021
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1864371530
Short name T774
Test name
Test status
Simulation time 8383662452 ps
CPU time 9.2 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204048 kb
Host smart-ca0fc858-9d72-4b07-9d10-4b78a8ef2e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18643
71530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1864371530
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.260299156
Short name T43
Test name
Test status
Simulation time 8385408033 ps
CPU time 8.78 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204140 kb
Host smart-58fb1305-1a86-4de6-afbd-c2fe756a28c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26029
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.260299156
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.382544924
Short name T741
Test name
Test status
Simulation time 8386118512 ps
CPU time 8.42 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204076 kb
Host smart-8094fc17-2809-4046-a77e-4f3b19f82f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38254
4924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.382544924
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2781505133
Short name T844
Test name
Test status
Simulation time 8389915396 ps
CPU time 10.59 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:15 PM PDT 24
Peak memory 204140 kb
Host smart-f2e846f1-d71b-48a6-81f1-70aa55eaaa4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27815
05133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2781505133
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1548040844
Short name T783
Test name
Test status
Simulation time 8397072846 ps
CPU time 8.07 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204092 kb
Host smart-4ef72f6c-e101-4f4b-8e9b-7bff2ef20c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
40844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1548040844
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.549008489
Short name T959
Test name
Test status
Simulation time 8407233198 ps
CPU time 9.35 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:13 PM PDT 24
Peak memory 204132 kb
Host smart-90bd0294-96d4-4e6a-aa91-9faba366542a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54900
8489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.549008489
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3159178337
Short name T695
Test name
Test status
Simulation time 8370075287 ps
CPU time 7.61 seconds
Started May 02 03:45:01 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 204112 kb
Host smart-f528b5b5-4f81-4fda-8253-2515b5cb6c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31591
78337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3159178337
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2535967190
Short name T718
Test name
Test status
Simulation time 8383915993 ps
CPU time 7.69 seconds
Started May 02 03:45:02 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204136 kb
Host smart-d55b1300-4234-4e93-bc86-efebc945c7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25359
67190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2535967190
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.2816560068
Short name T1245
Test name
Test status
Simulation time 8494116084 ps
CPU time 7.58 seconds
Started May 02 03:45:14 PM PDT 24
Finished May 02 03:45:22 PM PDT 24
Peak memory 204104 kb
Host smart-286b2eda-4b6c-4e59-9055-e06d31de8bbf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2816560068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2816560068
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1253921191
Short name T556
Test name
Test status
Simulation time 8376045828 ps
CPU time 7.46 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204068 kb
Host smart-d76d5bd0-2035-4426-8426-863686ea8ad0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1253921191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1253921191
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1782738043
Short name T893
Test name
Test status
Simulation time 8423775508 ps
CPU time 7.54 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:15 PM PDT 24
Peak memory 204064 kb
Host smart-0bdb6c19-98e8-4fbf-9dd1-da020cdb8eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
38043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1782738043
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1720181887
Short name T600
Test name
Test status
Simulation time 8395269398 ps
CPU time 8.93 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:14 PM PDT 24
Peak memory 204100 kb
Host smart-50247c7e-b9ac-44fd-ace5-94bac2dcc0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17201
81887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1720181887
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.3084474952
Short name T1125
Test name
Test status
Simulation time 8373597581 ps
CPU time 10.07 seconds
Started May 02 03:45:05 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204072 kb
Host smart-3bfba8f8-8f2c-4115-8f3d-cbbce7fd1264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844
74952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3084474952
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3598631011
Short name T1373
Test name
Test status
Simulation time 60341921 ps
CPU time 1.56 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:06 PM PDT 24
Peak memory 204212 kb
Host smart-38b03f7e-62bf-49f9-bbba-f1290d0b8405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35986
31011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3598631011
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3420065510
Short name T1262
Test name
Test status
Simulation time 8414175323 ps
CPU time 8.09 seconds
Started May 02 03:45:13 PM PDT 24
Finished May 02 03:45:22 PM PDT 24
Peak memory 204100 kb
Host smart-0cb6a0f8-3015-4ff8-95f2-05366526d0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
65510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3420065510
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3583898732
Short name T185
Test name
Test status
Simulation time 8375115175 ps
CPU time 8.6 seconds
Started May 02 03:45:17 PM PDT 24
Finished May 02 03:45:27 PM PDT 24
Peak memory 204100 kb
Host smart-274a7223-a360-4564-9f61-55f6078db5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35838
98732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3583898732
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.384481433
Short name T627
Test name
Test status
Simulation time 8455733291 ps
CPU time 8.69 seconds
Started May 02 03:45:03 PM PDT 24
Finished May 02 03:45:14 PM PDT 24
Peak memory 204104 kb
Host smart-41a5298d-3eef-4fc0-8fc7-8bf78ed07d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
1433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.384481433
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3675428786
Short name T1249
Test name
Test status
Simulation time 8427446797 ps
CPU time 9.47 seconds
Started May 02 03:45:05 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204136 kb
Host smart-86724e14-e35c-498c-952b-df75ad343e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36754
28786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3675428786
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3505416005
Short name T3
Test name
Test status
Simulation time 8372527147 ps
CPU time 8.82 seconds
Started May 02 03:45:04 PM PDT 24
Finished May 02 03:45:14 PM PDT 24
Peak memory 204072 kb
Host smart-5062c9a2-e933-4299-8f51-fae2d192ffb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
16005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3505416005
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3412506668
Short name T109
Test name
Test status
Simulation time 8424445355 ps
CPU time 8.24 seconds
Started May 02 03:45:04 PM PDT 24
Finished May 02 03:45:14 PM PDT 24
Peak memory 204052 kb
Host smart-29cc50b8-5fd6-4848-b459-cc9f15d8a6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
06668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3412506668
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.630085653
Short name T421
Test name
Test status
Simulation time 8396918480 ps
CPU time 7.83 seconds
Started May 02 03:45:04 PM PDT 24
Finished May 02 03:45:14 PM PDT 24
Peak memory 204072 kb
Host smart-2cbf2464-6bd0-400f-b142-01c30cd31f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63008
5653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.630085653
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.428411791
Short name T722
Test name
Test status
Simulation time 8393172452 ps
CPU time 10.84 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:21 PM PDT 24
Peak memory 204068 kb
Host smart-b4cfd4f4-17d5-48ed-8b94-dfbb7cc493c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
1791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.428411791
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1337419921
Short name T1077
Test name
Test status
Simulation time 8393790382 ps
CPU time 9.12 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204072 kb
Host smart-db46bfff-657b-4066-a287-4f505b2b7511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13374
19921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1337419921
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1279131867
Short name T1361
Test name
Test status
Simulation time 8362351862 ps
CPU time 8.03 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204132 kb
Host smart-e3933848-3ff5-451d-9090-f7c69614e9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12791
31867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1279131867
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2334680015
Short name T1058
Test name
Test status
Simulation time 45040773 ps
CPU time 0.67 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:10 PM PDT 24
Peak memory 203984 kb
Host smart-988a3312-07fb-4de9-bd47-5ccae54d5325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23346
80015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2334680015
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4076540839
Short name T242
Test name
Test status
Simulation time 24758773802 ps
CPU time 50.33 seconds
Started May 02 03:45:09 PM PDT 24
Finished May 02 03:46:01 PM PDT 24
Peak memory 204368 kb
Host smart-6a9feb72-e2c5-4442-803d-65a33186c05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765
40839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4076540839
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2213072792
Short name T508
Test name
Test status
Simulation time 8393169707 ps
CPU time 8.08 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204124 kb
Host smart-3c8eb5af-443a-4c68-bf46-8362b28dab53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22130
72792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2213072792
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1384601554
Short name T157
Test name
Test status
Simulation time 8410826409 ps
CPU time 7.65 seconds
Started May 02 03:45:13 PM PDT 24
Finished May 02 03:45:22 PM PDT 24
Peak memory 204100 kb
Host smart-c492aae7-7ab5-4621-adfc-34545f10ca9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
01554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1384601554
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.370719587
Short name T712
Test name
Test status
Simulation time 8404832597 ps
CPU time 7.7 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204104 kb
Host smart-913a5495-c325-480a-a124-8a95b028195d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37071
9587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.370719587
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.960978369
Short name T1190
Test name
Test status
Simulation time 8380210666 ps
CPU time 7.46 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:15 PM PDT 24
Peak memory 204080 kb
Host smart-dcc9e696-6670-4a0b-9208-9b8af56c8937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96097
8369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.960978369
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2284355212
Short name T414
Test name
Test status
Simulation time 8425960907 ps
CPU time 10.45 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:18 PM PDT 24
Peak memory 204132 kb
Host smart-00425864-12b1-477a-824a-ef6048d36ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22843
55212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2284355212
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3557682417
Short name T1359
Test name
Test status
Simulation time 8411093739 ps
CPU time 9.76 seconds
Started May 02 03:45:05 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204144 kb
Host smart-9975326e-3ad2-4159-9861-9fe3094a7084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35576
82417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3557682417
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2038752088
Short name T409
Test name
Test status
Simulation time 8410334461 ps
CPU time 7.55 seconds
Started May 02 03:45:09 PM PDT 24
Finished May 02 03:45:18 PM PDT 24
Peak memory 204136 kb
Host smart-d8de59c3-9a69-4af4-ae5f-e3568195a9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
52088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2038752088
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3112460770
Short name T1083
Test name
Test status
Simulation time 8382223006 ps
CPU time 8.21 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204096 kb
Host smart-3ac8fe0b-3b80-4435-bd35-036ac5c161c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
60770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3112460770
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.816792450
Short name T744
Test name
Test status
Simulation time 8460292570 ps
CPU time 9.41 seconds
Started May 02 03:45:18 PM PDT 24
Finished May 02 03:45:29 PM PDT 24
Peak memory 204124 kb
Host smart-09de51f5-954a-47a4-9afc-656d6fa4470b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=816792450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.816792450
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.1561956233
Short name T472
Test name
Test status
Simulation time 8381591031 ps
CPU time 10.65 seconds
Started May 02 03:45:17 PM PDT 24
Finished May 02 03:45:29 PM PDT 24
Peak memory 204156 kb
Host smart-57a2c032-48ff-4bda-8f2a-4c4c21711cd2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1561956233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.1561956233
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2588914591
Short name T1336
Test name
Test status
Simulation time 8431334974 ps
CPU time 7.99 seconds
Started May 02 03:45:16 PM PDT 24
Finished May 02 03:45:26 PM PDT 24
Peak memory 204100 kb
Host smart-e2e46fa8-62ac-4194-89c1-b66b3bc3896b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
14591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2588914591
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3023520544
Short name T251
Test name
Test status
Simulation time 8378749391 ps
CPU time 8.38 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204092 kb
Host smart-2dfc310e-8741-4bcb-99db-0b0fa81629c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30235
20544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3023520544
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.245933356
Short name T397
Test name
Test status
Simulation time 8374093215 ps
CPU time 8.57 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204092 kb
Host smart-75cee2fe-db08-4b10-949c-fbc8090cf416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24593
3356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.245933356
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4044211769
Short name T58
Test name
Test status
Simulation time 49440039 ps
CPU time 1.28 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:11 PM PDT 24
Peak memory 204272 kb
Host smart-e2ecf06e-4a72-4be9-b90a-5bdd61e2f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40442
11769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4044211769
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3533602018
Short name T84
Test name
Test status
Simulation time 8391587663 ps
CPU time 10.34 seconds
Started May 02 03:45:17 PM PDT 24
Finished May 02 03:45:29 PM PDT 24
Peak memory 204088 kb
Host smart-b185d475-fff7-4f17-80b1-9a5cd9b0a1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35336
02018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3533602018
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1108193561
Short name T858
Test name
Test status
Simulation time 8379933420 ps
CPU time 8.37 seconds
Started May 02 03:45:19 PM PDT 24
Finished May 02 03:45:28 PM PDT 24
Peak memory 204112 kb
Host smart-70327f50-d96e-45d6-ae54-8400956ec8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
93561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1108193561
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2723026163
Short name T1052
Test name
Test status
Simulation time 8482149537 ps
CPU time 7.63 seconds
Started May 02 03:45:09 PM PDT 24
Finished May 02 03:45:18 PM PDT 24
Peak memory 204072 kb
Host smart-c45d80ec-5ee0-40a6-b2e2-d5cb489d3e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27230
26163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2723026163
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2541973432
Short name T592
Test name
Test status
Simulation time 8422489234 ps
CPU time 9.88 seconds
Started May 02 03:45:09 PM PDT 24
Finished May 02 03:45:20 PM PDT 24
Peak memory 204128 kb
Host smart-44ac80b0-3f74-46b0-8227-9cf9d5485c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419
73432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2541973432
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.680153882
Short name T1200
Test name
Test status
Simulation time 8368875916 ps
CPU time 7.54 seconds
Started May 02 03:45:13 PM PDT 24
Finished May 02 03:45:21 PM PDT 24
Peak memory 204100 kb
Host smart-9dbca0ac-fbb0-469d-94a9-306b2735ee6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68015
3882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.680153882
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3316296067
Short name T126
Test name
Test status
Simulation time 8434474008 ps
CPU time 7.76 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204096 kb
Host smart-0d2fba81-e9ae-494a-b682-68256c68ed9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
96067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3316296067
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2374958966
Short name T337
Test name
Test status
Simulation time 8409783361 ps
CPU time 7.76 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204128 kb
Host smart-8e644cf1-f4f2-4fd5-9bcc-b12cc3986278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23749
58966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2374958966
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3189193828
Short name T1378
Test name
Test status
Simulation time 8394826147 ps
CPU time 7.74 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204152 kb
Host smart-6eacd78b-5756-4ae3-aca0-d7a0d89afa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31891
93828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3189193828
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3606694953
Short name T195
Test name
Test status
Simulation time 8494544468 ps
CPU time 8.29 seconds
Started May 02 03:45:16 PM PDT 24
Finished May 02 03:45:26 PM PDT 24
Peak memory 204136 kb
Host smart-aa5bfd6c-05bb-46c7-b85a-72a1aca87cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
94953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3606694953
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2093335335
Short name T1321
Test name
Test status
Simulation time 8368517194 ps
CPU time 7.5 seconds
Started May 02 03:45:12 PM PDT 24
Finished May 02 03:45:20 PM PDT 24
Peak memory 204132 kb
Host smart-44848565-7803-4a35-a4be-35790ca82624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20933
35335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2093335335
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.780065542
Short name T615
Test name
Test status
Simulation time 60424395 ps
CPU time 0.68 seconds
Started May 02 03:45:17 PM PDT 24
Finished May 02 03:45:19 PM PDT 24
Peak memory 203996 kb
Host smart-f4df9c82-e88e-4801-bfc4-fc62ff2cdfec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78006
5542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.780065542
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2992347773
Short name T256
Test name
Test status
Simulation time 24104025073 ps
CPU time 51.45 seconds
Started May 02 03:45:05 PM PDT 24
Finished May 02 03:45:58 PM PDT 24
Peak memory 204440 kb
Host smart-651750c1-fb18-4271-8354-a5de227265d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29923
47773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2992347773
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1261415702
Short name T496
Test name
Test status
Simulation time 8408274796 ps
CPU time 8.38 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:18 PM PDT 24
Peak memory 204132 kb
Host smart-62fd1b0f-6fdc-4fd8-9ae4-a7a4ba6df3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614
15702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1261415702
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.16157359
Short name T140
Test name
Test status
Simulation time 8425903059 ps
CPU time 8.03 seconds
Started May 02 03:45:13 PM PDT 24
Finished May 02 03:45:22 PM PDT 24
Peak memory 204100 kb
Host smart-4d0fd0e1-0f42-4c02-9a40-c8db7b344888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16157
359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.16157359
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1844128988
Short name T888
Test name
Test status
Simulation time 8380889833 ps
CPU time 9.5 seconds
Started May 02 03:45:08 PM PDT 24
Finished May 02 03:45:19 PM PDT 24
Peak memory 204104 kb
Host smart-9896d05e-358e-412e-8d3f-1ecd338211f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
28988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1844128988
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1691557661
Short name T406
Test name
Test status
Simulation time 8384909798 ps
CPU time 8.3 seconds
Started May 02 03:45:17 PM PDT 24
Finished May 02 03:45:27 PM PDT 24
Peak memory 204088 kb
Host smart-19a6524a-cb96-4c5d-b9c8-de7b26f200ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
57661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1691557661
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1608725495
Short name T904
Test name
Test status
Simulation time 8369007673 ps
CPU time 8.19 seconds
Started May 02 03:45:06 PM PDT 24
Finished May 02 03:45:16 PM PDT 24
Peak memory 204124 kb
Host smart-c0256168-ddf9-483b-b515-ac0542966312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
25495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1608725495
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3292255133
Short name T511
Test name
Test status
Simulation time 8432272796 ps
CPU time 8.27 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204084 kb
Host smart-ca820aad-4d04-4384-b0df-462836c7a57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922
55133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3292255133
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1230036073
Short name T311
Test name
Test status
Simulation time 8431350228 ps
CPU time 7.95 seconds
Started May 02 03:45:07 PM PDT 24
Finished May 02 03:45:17 PM PDT 24
Peak memory 204072 kb
Host smart-0574f7c3-0860-49f4-afd0-15c9411a20fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
36073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1230036073
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1395142149
Short name T1204
Test name
Test status
Simulation time 8395772415 ps
CPU time 9.04 seconds
Started May 02 03:45:09 PM PDT 24
Finished May 02 03:45:19 PM PDT 24
Peak memory 204136 kb
Host smart-a65374cf-5272-4edf-8a41-b0e5ec6190d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13951
42149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1395142149
Directory /workspace/9.usbdev_stall_trans/latest
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