Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	25423	1		T2	4		T3	2		T4	3
all_values[1]	25423	1		T2	4		T3	2		T4	3
all_values[2]	25423	1		T2	4		T3	2		T4	3
all_values[3]	25423	1		T2	4		T3	2		T4	3
all_values[4]	25423	1		T2	4		T3	2		T4	3
all_values[5]	25423	1		T2	4		T3	2		T4	3
all_values[6]	25423	1		T2	4		T3	2		T4	3
all_values[7]	25423	1		T2	4		T3	2		T4	3
all_values[8]	25423	1		T2	4		T3	2		T4	3
all_values[9]	25423	1		T2	4		T3	2		T4	3
all_values[10]	25423	1		T2	4		T3	2		T4	3
all_values[11]	25423	1		T2	4		T3	2		T4	3
all_values[12]	25423	1		T2	4		T3	2		T4	3
all_values[13]	25423	1		T2	4		T3	2		T4	3
all_values[14]	25423	1		T2	4		T3	2		T4	3
all_values[15]	25423	1		T2	4		T3	2		T4	3
all_values[16]	25423	1		T2	4		T3	2		T4	3
all_values[17]	25423	1		T2	4		T3	2		T4	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	453776	1		T2	72		T3	36		T4	54
auto[1]	3838	1		T16	3		T19	4		T20	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	452934	1		T2	72		T3	36		T4	54
auto[1]	4680	1		T71	67		T72	116		T73	129

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24433	1		T2	4		T3	2		T4	3
all_values[0]	auto[0]	auto[1]	130	1		T71	3		T72	3		T73	6
all_values[0]	auto[1]	auto[0]	723	1		T16	3		T19	4		T56	4
all_values[0]	auto[1]	auto[1]	137	1		T72	5		T73	1		T74	5
all_values[1]	auto[0]	auto[0]	24837	1		T2	4		T3	2		T4	3
all_values[1]	auto[0]	auto[1]	133	1		T71	4		T72	2		T73	2
all_values[1]	auto[1]	auto[0]	327	1		T20	3		T38	3		T57	3
all_values[1]	auto[1]	auto[1]	126	1		T71	1		T72	6		T73	6
all_values[2]	auto[0]	auto[0]	25140	1		T2	4		T3	2		T4	3
all_values[2]	auto[0]	auto[1]	103	1		T71	2		T73	1		T74	7
all_values[2]	auto[1]	auto[0]	29	1		T72	3		T73	1		T274	1
all_values[2]	auto[1]	auto[1]	151	1		T71	3		T73	6		T74	1
all_values[3]	auto[0]	auto[0]	25142	1		T2	4		T3	2		T4	3
all_values[3]	auto[0]	auto[1]	132	1		T71	2		T72	3		T73	6
all_values[3]	auto[1]	auto[0]	26	1		T73	1		T74	1		T273	1
all_values[3]	auto[1]	auto[1]	123	1		T71	3		T72	5		T74	4
all_values[4]	auto[0]	auto[0]	25131	1		T2	4		T3	2		T4	3
all_values[4]	auto[0]	auto[1]	122	1		T71	3		T73	6		T74	3
all_values[4]	auto[1]	auto[0]	26	1		T71	2		T72	1		T73	1
all_values[4]	auto[1]	auto[1]	144	1		T72	6		T73	1		T74	5
all_values[5]	auto[0]	auto[0]	25134	1		T2	4		T3	2		T4	3
all_values[5]	auto[0]	auto[1]	134	1		T71	2		T72	3		T74	4
all_values[5]	auto[1]	auto[0]	32	1		T72	1		T73	1		T273	2
all_values[5]	auto[1]	auto[1]	123	1		T71	3		T72	2		T73	4
all_values[6]	auto[0]	auto[0]	25133	1		T2	4		T3	2		T4	3
all_values[6]	auto[0]	auto[1]	140	1		T72	4		T73	2		T74	4
all_values[6]	auto[1]	auto[0]	29	1		T71	4		T72	1		T74	4
all_values[6]	auto[1]	auto[1]	121	1		T72	3		T73	6		T75	1
all_values[7]	auto[0]	auto[0]	25137	1		T2	4		T3	2		T4	3
all_values[7]	auto[0]	auto[1]	112	1		T71	3		T72	5		T73	1
all_values[7]	auto[1]	auto[0]	40	1		T72	1		T74	1		T76	1
all_values[7]	auto[1]	auto[1]	134	1		T71	1		T72	1		T73	7
all_values[8]	auto[0]	auto[0]	25142	1		T2	4		T3	2		T4	3
all_values[8]	auto[0]	auto[1]	141	1		T71	4		T72	5		T73	4
all_values[8]	auto[1]	auto[0]	28	1		T72	2		T75	2		T275	1
all_values[8]	auto[1]	auto[1]	112	1		T71	1		T73	4		T74	6
all_values[9]	auto[0]	auto[0]	25141	1		T2	4		T3	2		T4	3
all_values[9]	auto[0]	auto[1]	115	1		T72	4		T73	3		T74	2
all_values[9]	auto[1]	auto[0]	31	1		T71	1		T75	1		T76	1
all_values[9]	auto[1]	auto[1]	136	1		T71	3		T72	3		T73	5
all_values[10]	auto[0]	auto[0]	25122	1		T2	4		T3	2		T4	3
all_values[10]	auto[0]	auto[1]	143	1		T71	4		T72	6		T73	2
all_values[10]	auto[1]	auto[0]	38	1		T73	2		T75	1		T274	1
all_values[10]	auto[1]	auto[1]	120	1		T71	1		T72	2		T73	4
all_values[11]	auto[0]	auto[0]	25149	1		T2	4		T3	2		T4	3
all_values[11]	auto[0]	auto[1]	134	1		T71	4		T72	5		T73	5
all_values[11]	auto[1]	auto[0]	25	1		T72	1		T73	1		T74	1
all_values[11]	auto[1]	auto[1]	115	1		T71	1		T72	2		T73	1
all_values[12]	auto[0]	auto[0]	25133	1		T2	4		T3	2		T4	3
all_values[12]	auto[0]	auto[1]	124	1		T72	5		T73	6		T74	5
all_values[12]	auto[1]	auto[0]	24	1		T71	1		T72	1		T74	1
all_values[12]	auto[1]	auto[1]	142	1		T71	4		T72	2		T73	2
all_values[13]	auto[0]	auto[0]	25129	1		T2	4		T3	2		T4	3
all_values[13]	auto[0]	auto[1]	132	1		T72	4		T73	4		T74	1
all_values[13]	auto[1]	auto[0]	22	1		T71	2		T74	3		T273	1
all_values[13]	auto[1]	auto[1]	140	1		T71	3		T72	4		T73	4
all_values[14]	auto[0]	auto[0]	25132	1		T2	4		T3	2		T4	3
all_values[14]	auto[0]	auto[1]	143	1		T71	4		T72	5		T73	6
all_values[14]	auto[1]	auto[0]	33	1		T74	6		T276	1		T277	1
all_values[14]	auto[1]	auto[1]	115	1		T71	1		T72	2		T73	2
all_values[15]	auto[0]	auto[0]	25123	1		T2	4		T3	2		T4	3
all_values[15]	auto[0]	auto[1]	144	1		T72	4		T73	5		T74	4
all_values[15]	auto[1]	auto[0]	24	1		T71	1		T72	2		T73	1
all_values[15]	auto[1]	auto[1]	132	1		T71	3		T72	1		T73	2
all_values[16]	auto[0]	auto[0]	25126	1		T2	4		T3	2		T4	3
all_values[16]	auto[0]	auto[1]	151	1		T72	2		T73	4		T74	6
all_values[16]	auto[1]	auto[0]	24	1		T71	4		T72	1		T75	1
all_values[16]	auto[1]	auto[1]	122	1		T72	4		T73	4		T74	2
all_values[17]	auto[0]	auto[0]	25135	1		T2	4		T3	2		T4	3
all_values[17]	auto[0]	auto[1]	124	1		T72	2		T73	1		T74	4
all_values[17]	auto[1]	auto[0]	34	1		T76	2		T276	1		T277	1
all_values[17]	auto[1]	auto[1]	130	1		T71	4		T72	6		T73	6