Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	25423	1		T2	4		T3	2		T4	3
all_pins[1]	25423	1		T2	4		T3	2		T4	3
all_pins[2]	25423	1		T2	4		T3	2		T4	3
all_pins[3]	25423	1		T2	4		T3	2		T4	3
all_pins[4]	25423	1		T2	4		T3	2		T4	3
all_pins[5]	25423	1		T2	4		T3	2		T4	3
all_pins[6]	25423	1		T2	4		T3	2		T4	3
all_pins[7]	25423	1		T2	4		T3	2		T4	3
all_pins[8]	25423	1		T2	4		T3	2		T4	3
all_pins[9]	25423	1		T2	4		T3	2		T4	3
all_pins[10]	25423	1		T2	4		T3	2		T4	3
all_pins[11]	25423	1		T2	4		T3	2		T4	3
all_pins[12]	25423	1		T2	4		T3	2		T4	3
all_pins[13]	25423	1		T2	4		T3	2		T4	3
all_pins[14]	25423	1		T2	4		T3	2		T4	3
all_pins[15]	25423	1		T2	4		T3	2		T4	3
all_pins[16]	25423	1		T2	4		T3	2		T4	3
all_pins[17]	25423	1		T2	4		T3	2		T4	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	456340	1		T2	72		T3	36		T4	54
values[0x1]	1274	1		T19	1		T20	1		T38	1
transitions[0x0=>0x1]	994	1		T19	1		T20	1		T38	1
transitions[0x1=>0x0]	1005	1		T19	1		T20	1		T38	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	25268	1		T2	4		T3	2		T4	3
all_pins[0]	values[0x1]	155	1		T19	1		T56	1		T89	1
all_pins[0]	transitions[0x0=>0x1]	136	1		T19	1		T56	1		T89	1
all_pins[0]	transitions[0x1=>0x0]	138	1		T20	1		T38	1		T57	1
all_pins[1]	values[0x0]	25266	1		T2	4		T3	2		T4	3
all_pins[1]	values[0x1]	157	1		T20	1		T38	1		T57	1
all_pins[1]	transitions[0x0=>0x1]	144	1		T20	1		T38	1		T57	1
all_pins[1]	transitions[0x1=>0x0]	61	1		T73	2		T74	1		T76	1
all_pins[2]	values[0x0]	25349	1		T2	4		T3	2		T4	3
all_pins[2]	values[0x1]	74	1		T73	3		T74	1		T76	1
all_pins[2]	transitions[0x0=>0x1]	60	1		T73	3		T74	1		T76	1
all_pins[2]	transitions[0x1=>0x0]	52	1		T71	2		T72	1		T74	1
all_pins[3]	values[0x0]	25357	1		T2	4		T3	2		T4	3
all_pins[3]	values[0x1]	66	1		T71	2		T72	1		T74	1
all_pins[3]	transitions[0x0=>0x1]	44	1		T71	2		T72	1		T74	1
all_pins[3]	transitions[0x1=>0x0]	39	1		T72	2		T73	1		T74	2
all_pins[4]	values[0x0]	25362	1		T2	4		T3	2		T4	3
all_pins[4]	values[0x1]	61	1		T72	2		T73	1		T74	2
all_pins[4]	transitions[0x0=>0x1]	47	1		T72	1		T73	1		T74	2
all_pins[4]	transitions[0x1=>0x0]	40	1		T71	2		T74	1		T76	3
all_pins[5]	values[0x0]	25369	1		T2	4		T3	2		T4	3
all_pins[5]	values[0x1]	54	1		T71	2		T72	1		T74	1
all_pins[5]	transitions[0x0=>0x1]	41	1		T71	2		T74	1		T75	1
all_pins[5]	transitions[0x1=>0x0]	46	1		T72	2		T73	1		T273	3
all_pins[6]	values[0x0]	25364	1		T2	4		T3	2		T4	3
all_pins[6]	values[0x1]	59	1		T72	3		T73	1		T273	4
all_pins[6]	transitions[0x0=>0x1]	41	1		T72	2		T273	3		T276	3
all_pins[6]	transitions[0x1=>0x0]	44	1		T71	1		T73	2		T75	1
all_pins[7]	values[0x0]	25361	1		T2	4		T3	2		T4	3
all_pins[7]	values[0x1]	62	1		T71	1		T72	1		T73	3
all_pins[7]	transitions[0x0=>0x1]	50	1		T71	1		T72	1		T73	2
all_pins[7]	transitions[0x1=>0x0]	40	1		T71	1		T73	2		T74	4
all_pins[8]	values[0x0]	25371	1		T2	4		T3	2		T4	3
all_pins[8]	values[0x1]	52	1		T71	1		T73	3		T74	4
all_pins[8]	transitions[0x0=>0x1]	34	1		T71	1		T73	2		T74	2
all_pins[8]	transitions[0x1=>0x0]	50	1		T71	2		T72	2		T73	3
all_pins[9]	values[0x0]	25355	1		T2	4		T3	2		T4	3
all_pins[9]	values[0x1]	68	1		T71	2		T72	2		T73	4
all_pins[9]	transitions[0x0=>0x1]	54	1		T71	2		T72	2		T73	4
all_pins[9]	transitions[0x1=>0x0]	38	1		T71	1		T72	1		T74	1
all_pins[10]	values[0x0]	25371	1		T2	4		T3	2		T4	3
all_pins[10]	values[0x1]	52	1		T71	1		T72	1		T74	1
all_pins[10]	transitions[0x0=>0x1]	41	1		T71	1		T72	1		T74	1
all_pins[10]	transitions[0x1=>0x0]	39	1		T72	1		T74	4		T76	2
all_pins[11]	values[0x0]	25373	1		T2	4		T3	2		T4	3
all_pins[11]	values[0x1]	50	1		T72	1		T74	4		T76	3
all_pins[11]	transitions[0x0=>0x1]	35	1		T74	4		T76	2		T274	1
all_pins[11]	transitions[0x1=>0x0]	61	1		T71	3		T73	1		T76	2
all_pins[12]	values[0x0]	25347	1		T2	4		T3	2		T4	3
all_pins[12]	values[0x1]	76	1		T71	3		T72	1		T73	1
all_pins[12]	transitions[0x0=>0x1]	57	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x1=>0x0]	48	1		T72	2		T73	1		T74	2
all_pins[13]	values[0x0]	25356	1		T2	4		T3	2		T4	3
all_pins[13]	values[0x1]	67	1		T71	2		T72	2		T73	1
all_pins[13]	transitions[0x0=>0x1]	53	1		T71	2		T72	2		T74	2
all_pins[13]	transitions[0x1=>0x0]	27	1		T71	1		T72	1		T73	1
all_pins[14]	values[0x0]	25382	1		T2	4		T3	2		T4	3
all_pins[14]	values[0x1]	41	1		T71	1		T72	1		T73	2
all_pins[14]	transitions[0x0=>0x1]	28	1		T71	1		T72	1		T73	2
all_pins[14]	transitions[0x1=>0x0]	53	1		T71	2		T72	1		T75	1
all_pins[15]	values[0x0]	25357	1		T2	4		T3	2		T4	3
all_pins[15]	values[0x1]	66	1		T71	2		T72	1		T75	1
all_pins[15]	transitions[0x0=>0x1]	50	1		T71	2		T72	1		T75	1
all_pins[15]	transitions[0x1=>0x0]	43	1		T72	3		T73	2		T74	2
all_pins[16]	values[0x0]	25364	1		T2	4		T3	2		T4	3
all_pins[16]	values[0x1]	59	1		T72	3		T73	2		T74	2
all_pins[16]	transitions[0x0=>0x1]	46	1		T72	3		T73	2		T74	1
all_pins[16]	transitions[0x1=>0x0]	42	1		T71	1		T72	3		T73	3
all_pins[17]	values[0x0]	25368	1		T2	4		T3	2		T4	3
all_pins[17]	values[0x1]	55	1		T71	1		T72	3		T73	3
all_pins[17]	transitions[0x0=>0x1]	33	1		T71	1		T72	1		T73	3
all_pins[17]	transitions[0x1=>0x0]	144	1		T19	1		T56	1		T89	1