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 LINE       9294
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T34,T35
110CoveredT209,T213,T235
111CoveredT34,T35,T36

 LINE       9313
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T3,T8
110CoveredT208,T234,T240
111CoveredT8,T10,T60

 LINE       9326
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T217,T221
110CoveredT234,T240,T236
111CoveredT61,T69,T62

 LINE       9329
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T4,T21
110CoveredT234,T240,T236
111CoveredT21,T58,T59

 LINE       9336
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T21,T220
110Not Covered
111CoveredT61,T69,T62

 LINE       9337
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T21,T220
110CoveredT208,T213,T235
111CoveredT61,T69,T62

 LINE       9350
 EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T222,T217
110Not Covered
111CoveredT61,T69,T62

 LINE       9351
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T222,T217
110CoveredT208,T209,T213
111CoveredT61,T69,T62

 LINE       9362
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T21,T220
110Not Covered
111CoveredT61,T69,T62

 LINE       9363
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T21,T220
110CoveredT209,T234,T240
111CoveredT61,T69,T62

 LINE       9368
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T220,T217
110Not Covered
111CoveredT61,T69,T62

 LINE       9369
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT3,T220,T217
110CoveredT208,T234,T240
111CoveredT61,T69,T62

 LINE       9881
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT2,T3,T4
01Unreachable
10CoveredT61,T69,T62
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