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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.61 96.24 88.98 96.90 50.00 94.22 97.35 96.58


Total test records in report: 1481
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T1319 /workspace/coverage/default/31.usbdev_nak_trans.4134296182 May 05 03:16:01 PM PDT 24 May 05 03:16:10 PM PDT 24 8420937677 ps
T1320 /workspace/coverage/default/41.usbdev_in_trans.1314879547 May 05 03:17:00 PM PDT 24 May 05 03:17:09 PM PDT 24 8441604784 ps
T1321 /workspace/coverage/default/30.usbdev_out_trans_nak.282852067 May 05 03:15:52 PM PDT 24 May 05 03:16:00 PM PDT 24 8396705387 ps
T1322 /workspace/coverage/default/48.usbdev_random_length_out_trans.2398776424 May 05 03:17:42 PM PDT 24 May 05 03:17:50 PM PDT 24 8370523226 ps
T1323 /workspace/coverage/default/34.usbdev_av_buffer.2717127044 May 05 03:16:17 PM PDT 24 May 05 03:16:26 PM PDT 24 8392237542 ps
T1324 /workspace/coverage/default/41.max_length_in_transaction.957904358 May 05 03:17:13 PM PDT 24 May 05 03:17:24 PM PDT 24 8468017405 ps
T1325 /workspace/coverage/default/40.usbdev_pkt_received.443952439 May 05 03:16:54 PM PDT 24 May 05 03:17:03 PM PDT 24 8404582482 ps
T1326 /workspace/coverage/default/31.usbdev_stall_trans.1290679940 May 05 03:15:59 PM PDT 24 May 05 03:16:07 PM PDT 24 8387995618 ps
T1327 /workspace/coverage/default/47.usbdev_pkt_sent.3842176755 May 05 03:17:34 PM PDT 24 May 05 03:17:43 PM PDT 24 8398991793 ps
T1328 /workspace/coverage/default/37.usbdev_in_iso.4231875025 May 05 03:16:39 PM PDT 24 May 05 03:16:48 PM PDT 24 8461162865 ps
T1329 /workspace/coverage/default/11.usbdev_max_length_out_transaction.2293674182 May 05 03:13:28 PM PDT 24 May 05 03:13:37 PM PDT 24 8416695233 ps
T1330 /workspace/coverage/default/35.usbdev_min_length_out_transaction.4276714 May 05 03:16:26 PM PDT 24 May 05 03:16:35 PM PDT 24 8395360560 ps
T1331 /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2713682044 May 05 03:15:10 PM PDT 24 May 05 03:15:19 PM PDT 24 8492049790 ps
T1332 /workspace/coverage/default/14.usbdev_min_length_out_transaction.1609406784 May 05 03:13:55 PM PDT 24 May 05 03:14:04 PM PDT 24 8372781549 ps
T1333 /workspace/coverage/default/11.usbdev_enable.3387520039 May 05 03:13:27 PM PDT 24 May 05 03:13:36 PM PDT 24 8381380322 ps
T1334 /workspace/coverage/default/21.usbdev_out_stall.1864125554 May 05 03:14:58 PM PDT 24 May 05 03:15:09 PM PDT 24 8389996937 ps
T1335 /workspace/coverage/default/47.min_length_in_transaction.3266728854 May 05 03:17:41 PM PDT 24 May 05 03:17:51 PM PDT 24 8384205786 ps
T1336 /workspace/coverage/default/27.usbdev_min_length_out_transaction.2020685160 May 05 03:15:42 PM PDT 24 May 05 03:15:51 PM PDT 24 8369453476 ps
T1337 /workspace/coverage/default/24.usbdev_phy_pins_sense.4142169571 May 05 03:15:15 PM PDT 24 May 05 03:15:17 PM PDT 24 43664571 ps
T1338 /workspace/coverage/default/31.usbdev_stall_priority_over_nak.4284824410 May 05 03:16:01 PM PDT 24 May 05 03:16:09 PM PDT 24 8402048992 ps
T1339 /workspace/coverage/default/27.max_length_in_transaction.507319398 May 05 03:15:42 PM PDT 24 May 05 03:15:51 PM PDT 24 8467163087 ps
T1340 /workspace/coverage/default/7.usbdev_setup_trans_ignored.3129170389 May 05 03:12:52 PM PDT 24 May 05 03:13:00 PM PDT 24 8378083710 ps
T1341 /workspace/coverage/default/4.usbdev_pkt_sent.3882166196 May 05 03:12:13 PM PDT 24 May 05 03:12:21 PM PDT 24 8464244272 ps
T1342 /workspace/coverage/default/38.usbdev_setup_trans_ignored.950373393 May 05 03:16:41 PM PDT 24 May 05 03:16:49 PM PDT 24 8373052230 ps
T1343 /workspace/coverage/default/12.usbdev_setup_stage.2101949505 May 05 03:13:42 PM PDT 24 May 05 03:13:50 PM PDT 24 8373076340 ps
T1344 /workspace/coverage/default/48.usbdev_stall_trans.2191811833 May 05 03:17:43 PM PDT 24 May 05 03:17:53 PM PDT 24 8390997156 ps
T1345 /workspace/coverage/default/32.usbdev_random_length_out_trans.4201232257 May 05 03:16:04 PM PDT 24 May 05 03:16:13 PM PDT 24 8386184196 ps
T1346 /workspace/coverage/default/21.usbdev_pkt_sent.2704034739 May 05 03:14:53 PM PDT 24 May 05 03:15:02 PM PDT 24 8470098993 ps
T1347 /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2307772323 May 05 03:12:27 PM PDT 24 May 05 03:12:36 PM PDT 24 8368234114 ps
T1348 /workspace/coverage/default/27.usbdev_enable.2200333754 May 05 03:15:35 PM PDT 24 May 05 03:15:44 PM PDT 24 8376033392 ps
T1349 /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3324486481 May 05 03:17:45 PM PDT 24 May 05 03:17:55 PM PDT 24 8367467766 ps
T1350 /workspace/coverage/default/42.usbdev_fifo_rst.1760775006 May 05 03:17:12 PM PDT 24 May 05 03:17:14 PM PDT 24 109298398 ps
T1351 /workspace/coverage/default/34.usbdev_nak_trans.3790303926 May 05 03:16:20 PM PDT 24 May 05 03:16:28 PM PDT 24 8460825524 ps
T1352 /workspace/coverage/default/35.usbdev_fifo_rst.2662232921 May 05 03:16:25 PM PDT 24 May 05 03:16:28 PM PDT 24 205418652 ps
T1353 /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3952052897 May 05 03:14:45 PM PDT 24 May 05 03:14:55 PM PDT 24 8384648959 ps
T1354 /workspace/coverage/default/23.usbdev_av_buffer.3526151744 May 05 03:15:02 PM PDT 24 May 05 03:15:11 PM PDT 24 8393492838 ps
T1355 /workspace/coverage/default/43.usbdev_min_length_out_transaction.1856318756 May 05 03:17:13 PM PDT 24 May 05 03:17:21 PM PDT 24 8388074372 ps
T1356 /workspace/coverage/default/44.usbdev_stall_trans.1493641699 May 05 03:17:20 PM PDT 24 May 05 03:17:29 PM PDT 24 8403161832 ps
T1357 /workspace/coverage/default/39.usbdev_out_trans_nak.677025582 May 05 03:16:45 PM PDT 24 May 05 03:16:55 PM PDT 24 8372034931 ps
T1358 /workspace/coverage/default/45.max_length_in_transaction.3781008197 May 05 03:17:28 PM PDT 24 May 05 03:17:37 PM PDT 24 8457750268 ps
T1359 /workspace/coverage/default/18.usbdev_out_stall.467423396 May 05 03:14:32 PM PDT 24 May 05 03:14:41 PM PDT 24 8417105232 ps
T1360 /workspace/coverage/default/29.usbdev_setup_stage.1518510751 May 05 03:15:51 PM PDT 24 May 05 03:15:59 PM PDT 24 8382322241 ps
T1361 /workspace/coverage/default/14.usbdev_pkt_buffer.3294879334 May 05 03:13:53 PM PDT 24 May 05 03:14:49 PM PDT 24 28506671711 ps
T1362 /workspace/coverage/default/6.usbdev_setup_trans_ignored.433187725 May 05 03:12:45 PM PDT 24 May 05 03:12:54 PM PDT 24 8369721745 ps
T1363 /workspace/coverage/default/8.usbdev_stall_trans.2184037375 May 05 03:12:59 PM PDT 24 May 05 03:13:09 PM PDT 24 8397455383 ps
T1364 /workspace/coverage/default/6.usbdev_in_trans.759915534 May 05 03:12:39 PM PDT 24 May 05 03:12:48 PM PDT 24 8438118973 ps
T1365 /workspace/coverage/default/28.usbdev_smoke.1843220609 May 05 03:15:45 PM PDT 24 May 05 03:15:54 PM PDT 24 8423273180 ps
T1366 /workspace/coverage/default/15.usbdev_pkt_buffer.3052090820 May 05 03:14:08 PM PDT 24 May 05 03:14:40 PM PDT 24 18795562978 ps
T1367 /workspace/coverage/default/1.min_length_in_transaction.1334429983 May 05 03:11:33 PM PDT 24 May 05 03:11:41 PM PDT 24 8375554456 ps
T1368 /workspace/coverage/default/48.usbdev_pkt_received.4234806233 May 05 03:17:43 PM PDT 24 May 05 03:17:52 PM PDT 24 8403411013 ps
T1369 /workspace/coverage/default/41.usbdev_pkt_received.847249609 May 05 03:17:03 PM PDT 24 May 05 03:17:12 PM PDT 24 8438725385 ps
T1370 /workspace/coverage/default/31.max_length_in_transaction.2462537293 May 05 03:15:59 PM PDT 24 May 05 03:16:08 PM PDT 24 8464090858 ps
T1371 /workspace/coverage/default/20.usbdev_in_iso.3143796156 May 05 03:14:53 PM PDT 24 May 05 03:15:01 PM PDT 24 8459245491 ps
T1372 /workspace/coverage/default/35.usbdev_setup_stage.2498571674 May 05 03:16:30 PM PDT 24 May 05 03:16:39 PM PDT 24 8387233943 ps
T1373 /workspace/coverage/default/19.usbdev_smoke.3109246651 May 05 03:14:34 PM PDT 24 May 05 03:14:43 PM PDT 24 8451499204 ps
T1374 /workspace/coverage/default/39.usbdev_in_iso.498148736 May 05 03:16:53 PM PDT 24 May 05 03:17:01 PM PDT 24 8385175251 ps
T61 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1360199121 May 05 02:48:23 PM PDT 24 May 05 02:48:26 PM PDT 24 286349419 ps
T71 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2329190213 May 05 02:48:26 PM PDT 24 May 05 02:48:27 PM PDT 24 30198121 ps
T69 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.355307626 May 05 02:48:30 PM PDT 24 May 05 02:48:32 PM PDT 24 85090967 ps
T62 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2558479233 May 05 02:48:24 PM PDT 24 May 05 02:48:27 PM PDT 24 166353193 ps
T70 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3269296383 May 05 02:48:34 PM PDT 24 May 05 02:48:37 PM PDT 24 123441561 ps
T72 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4291860059 May 05 02:48:44 PM PDT 24 May 05 02:48:45 PM PDT 24 40262797 ps
T97 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1941001609 May 05 02:48:21 PM PDT 24 May 05 02:48:23 PM PDT 24 63662983 ps
T98 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1779460187 May 05 02:48:21 PM PDT 24 May 05 02:48:22 PM PDT 24 65625192 ps
T99 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.495997652 May 05 02:48:27 PM PDT 24 May 05 02:48:29 PM PDT 24 106616423 ps
T73 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2175708044 May 05 02:48:47 PM PDT 24 May 05 02:48:48 PM PDT 24 32279714 ps
T63 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4012713804 May 05 02:48:25 PM PDT 24 May 05 02:48:28 PM PDT 24 134256270 ps
T100 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2928171810 May 05 02:48:29 PM PDT 24 May 05 02:48:32 PM PDT 24 87231791 ps
T101 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.403540426 May 05 02:48:14 PM PDT 24 May 05 02:48:15 PM PDT 24 53004668 ps
T74 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3545314727 May 05 02:48:43 PM PDT 24 May 05 02:48:44 PM PDT 24 31586065 ps
T263 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.88792905 May 05 02:48:16 PM PDT 24 May 05 02:48:18 PM PDT 24 116927555 ps
T208 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1157829278 May 05 02:48:24 PM PDT 24 May 05 02:48:28 PM PDT 24 291361396 ps
T239 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4018709467 May 05 02:48:17 PM PDT 24 May 05 02:48:20 PM PDT 24 97084262 ps
T75 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.562899155 May 05 02:48:45 PM PDT 24 May 05 02:48:47 PM PDT 24 88753688 ps
T209 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.201835861 May 05 02:48:40 PM PDT 24 May 05 02:48:43 PM PDT 24 125081410 ps
T253 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.408910075 May 05 02:48:18 PM PDT 24 May 05 02:48:21 PM PDT 24 157241107 ps
T76 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1607234061 May 05 02:48:42 PM PDT 24 May 05 02:48:44 PM PDT 24 34697143 ps
T264 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1907378369 May 05 02:48:16 PM PDT 24 May 05 02:48:18 PM PDT 24 146539176 ps
T273 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.462030497 May 05 02:48:44 PM PDT 24 May 05 02:48:46 PM PDT 24 50522229 ps
T265 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2400957002 May 05 02:48:25 PM PDT 24 May 05 02:48:26 PM PDT 24 41556966 ps
T266 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1928490128 May 05 02:48:29 PM PDT 24 May 05 02:48:31 PM PDT 24 177086758 ps
T213 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1976247661 May 05 02:48:14 PM PDT 24 May 05 02:48:17 PM PDT 24 117289711 ps
T274 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3186888567 May 05 02:48:45 PM PDT 24 May 05 02:48:47 PM PDT 24 28384302 ps
T235 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1768556069 May 05 02:48:14 PM PDT 24 May 05 02:48:17 PM PDT 24 68782453 ps
T234 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1305870501 May 05 02:48:38 PM PDT 24 May 05 02:48:42 PM PDT 24 223928305 ps
T240 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1343813222 May 05 02:48:31 PM PDT 24 May 05 02:48:34 PM PDT 24 179513377 ps
T258 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4189980227 May 05 02:48:47 PM PDT 24 May 05 02:48:49 PM PDT 24 45828568 ps
T214 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.126356979 May 05 02:48:20 PM PDT 24 May 05 02:48:25 PM PDT 24 448298939 ps
T269 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3891049845 May 05 02:48:22 PM PDT 24 May 05 02:48:24 PM PDT 24 166301987 ps
T276 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2949784298 May 05 02:48:30 PM PDT 24 May 05 02:48:32 PM PDT 24 52856426 ps
T270 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2290806701 May 05 02:48:41 PM PDT 24 May 05 02:48:43 PM PDT 24 72783884 ps
T1375 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3549007588 May 05 02:48:44 PM PDT 24 May 05 02:48:46 PM PDT 24 137051861 ps
T254 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2018810687 May 05 02:48:14 PM PDT 24 May 05 02:48:16 PM PDT 24 105221375 ps
T280 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3350698308 May 05 02:48:19 PM PDT 24 May 05 02:48:20 PM PDT 24 37923485 ps
T1376 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.886171952 May 05 02:48:29 PM PDT 24 May 05 02:48:31 PM PDT 24 56891420 ps
T275 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2963831605 May 05 02:48:48 PM PDT 24 May 05 02:48:49 PM PDT 24 39451203 ps
T1377 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.540821089 May 05 02:48:44 PM PDT 24 May 05 02:48:47 PM PDT 24 166345245 ps
T277 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.412872379 May 05 02:48:18 PM PDT 24 May 05 02:48:24 PM PDT 24 54888846 ps
T1378 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2778348307 May 05 02:48:29 PM PDT 24 May 05 02:48:30 PM PDT 24 50995206 ps
T67 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2717992376 May 05 02:48:16 PM PDT 24 May 05 02:48:18 PM PDT 24 38813354 ps
T68 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3966967574 May 05 02:48:27 PM PDT 24 May 05 02:48:29 PM PDT 24 71010856 ps
T215 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.429459820 May 05 02:48:38 PM PDT 24 May 05 02:48:43 PM PDT 24 634269747 ps
T281 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1281578046 May 05 02:48:43 PM PDT 24 May 05 02:48:45 PM PDT 24 22844962 ps
T210 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.297971752 May 05 02:48:28 PM PDT 24 May 05 02:48:34 PM PDT 24 1679081476 ps
T1379 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.634687816 May 05 02:48:42 PM PDT 24 May 05 02:48:45 PM PDT 24 146807996 ps
T282 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1189565493 May 05 02:48:24 PM PDT 24 May 05 02:48:25 PM PDT 24 107030951 ps
T1380 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4019251437 May 05 02:48:20 PM PDT 24 May 05 02:48:21 PM PDT 24 33906067 ps
T271 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2961266476 May 05 02:48:25 PM PDT 24 May 05 02:48:28 PM PDT 24 511829357 ps
T272 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3975329032 May 05 02:48:38 PM PDT 24 May 05 02:48:41 PM PDT 24 343090067 ps
T255 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3057143905 May 05 02:48:18 PM PDT 24 May 05 02:48:22 PM PDT 24 118253677 ps
T238 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.401307625 May 05 02:48:15 PM PDT 24 May 05 02:48:17 PM PDT 24 63715282 ps
T278 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.463768491 May 05 02:48:32 PM PDT 24 May 05 02:48:33 PM PDT 24 36971031 ps
T1381 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4034437318 May 05 02:48:41 PM PDT 24 May 05 02:48:43 PM PDT 24 72989468 ps
T1382 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3809890163 May 05 02:48:37 PM PDT 24 May 05 02:48:38 PM PDT 24 35231768 ps
T1383 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.918695342 May 05 02:48:15 PM PDT 24 May 05 02:48:19 PM PDT 24 179894164 ps
T256 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.163610921 May 05 02:48:28 PM PDT 24 May 05 02:48:30 PM PDT 24 75689548 ps
T285 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1936069793 May 05 02:48:31 PM PDT 24 May 05 02:48:36 PM PDT 24 465021197 ps
T1384 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1573918155 May 05 02:48:27 PM PDT 24 May 05 02:48:28 PM PDT 24 52677475 ps
T1385 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1259132650 May 05 02:48:20 PM PDT 24 May 05 02:48:22 PM PDT 24 103707898 ps
T1386 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1436694824 May 05 02:48:35 PM PDT 24 May 05 02:48:36 PM PDT 24 43999863 ps
T1387 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.287224733 May 05 02:48:39 PM PDT 24 May 05 02:48:42 PM PDT 24 42700655 ps
T257 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.771513051 May 05 02:48:32 PM PDT 24 May 05 02:48:34 PM PDT 24 32438582 ps
T1 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1919318900 May 05 02:48:15 PM PDT 24 May 05 02:48:17 PM PDT 24 64168278 ps
T1388 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1793707913 May 05 02:48:31 PM PDT 24 May 05 02:48:34 PM PDT 24 144355695 ps
T1389 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2018605043 May 05 02:48:42 PM PDT 24 May 05 02:48:44 PM PDT 24 171741682 ps
T259 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.585481506 May 05 02:48:17 PM PDT 24 May 05 02:48:20 PM PDT 24 66693787 ps
T1390 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.712825163 May 05 02:48:29 PM PDT 24 May 05 02:48:32 PM PDT 24 196288585 ps
T279 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1953621492 May 05 02:48:39 PM PDT 24 May 05 02:48:40 PM PDT 24 68346834 ps
T1391 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3653125571 May 05 02:48:44 PM PDT 24 May 05 02:48:46 PM PDT 24 27941605 ps
T1392 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2442801547 May 05 02:48:37 PM PDT 24 May 05 02:48:38 PM PDT 24 28317015 ps
T1393 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4272734904 May 05 02:48:40 PM PDT 24 May 05 02:48:41 PM PDT 24 32581620 ps
T1394 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2824084380 May 05 02:48:17 PM PDT 24 May 05 02:48:23 PM PDT 24 885767076 ps
T1395 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.225338551 May 05 02:48:42 PM PDT 24 May 05 02:48:43 PM PDT 24 23517852 ps
T211 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2538835749 May 05 02:48:17 PM PDT 24 May 05 02:48:22 PM PDT 24 1067627914 ps
T1396 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3778313720 May 05 02:48:43 PM PDT 24 May 05 02:48:44 PM PDT 24 41213772 ps
T284 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.165586244 May 05 02:48:40 PM PDT 24 May 05 02:48:45 PM PDT 24 724016822 ps
T1397 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2759010573 May 05 02:48:45 PM PDT 24 May 05 02:48:47 PM PDT 24 34227455 ps
T1398 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2295122328 May 05 02:48:23 PM PDT 24 May 05 02:48:25 PM PDT 24 84218505 ps
T1399 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.731859112 May 05 02:48:36 PM PDT 24 May 05 02:48:38 PM PDT 24 178720699 ps
T1400 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1784453890 May 05 02:48:43 PM PDT 24 May 05 02:48:45 PM PDT 24 32035261 ps
T260 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3515611501 May 05 02:48:16 PM PDT 24 May 05 02:48:18 PM PDT 24 36210179 ps
T1401 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3962753372 May 05 02:48:15 PM PDT 24 May 05 02:48:17 PM PDT 24 134681017 ps
T1402 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.847059139 May 05 02:48:20 PM PDT 24 May 05 02:48:22 PM PDT 24 32656131 ps
T212 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1445756571 May 05 02:48:19 PM PDT 24 May 05 02:48:29 PM PDT 24 1382673442 ps
T1403 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3981081215 May 05 02:48:40 PM PDT 24 May 05 02:48:42 PM PDT 24 144276433 ps
T1404 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.684098347 May 05 02:48:33 PM PDT 24 May 05 02:48:35 PM PDT 24 71408407 ps
T1405 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.835783137 May 05 02:48:38 PM PDT 24 May 05 02:48:40 PM PDT 24 188967068 ps
T236 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.480290556 May 05 02:48:23 PM PDT 24 May 05 02:48:27 PM PDT 24 258199314 ps
T283 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3232192846 May 05 02:48:24 PM PDT 24 May 05 02:48:29 PM PDT 24 561537561 ps
T1406 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2947104324 May 05 02:48:15 PM PDT 24 May 05 02:48:17 PM PDT 24 48890608 ps
T1407 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.808753334 May 05 02:48:26 PM PDT 24 May 05 02:48:29 PM PDT 24 151839901 ps
T237 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2710595274 May 05 02:48:18 PM PDT 24 May 05 02:48:22 PM PDT 24 152681377 ps
T1408 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1199823361 May 05 02:48:18 PM PDT 24 May 05 02:48:23 PM PDT 24 179519631 ps
T1409 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2363425129 May 05 02:48:15 PM PDT 24 May 05 02:48:16 PM PDT 24 24260453 ps
T1410 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3096775707 May 05 02:48:40 PM PDT 24 May 05 02:48:41 PM PDT 24 27530572 ps
T1411 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2367741937 May 05 02:48:30 PM PDT 24 May 05 02:48:32 PM PDT 24 32749158 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4236680268 May 05 02:48:16 PM PDT 24 May 05 02:48:17 PM PDT 24 62609874 ps
T1412 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1426117201 May 05 02:48:44 PM PDT 24 May 05 02:48:46 PM PDT 24 28965753 ps
T1413 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.916565593 May 05 02:48:25 PM PDT 24 May 05 02:48:26 PM PDT 24 29819959 ps
T262 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.728609822 May 05 02:48:17 PM PDT 24 May 05 02:48:20 PM PDT 24 52711552 ps
T1414 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1859383589 May 05 02:48:43 PM PDT 24 May 05 02:48:45 PM PDT 24 28710106 ps
T1415 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3764459648 May 05 02:48:14 PM PDT 24 May 05 02:48:15 PM PDT 24 28680621 ps
T1416 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2991329249 May 05 02:48:44 PM PDT 24 May 05 02:48:46 PM PDT 24 65371054 ps
T1417 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1701758841 May 05 02:48:16 PM PDT 24 May 05 02:48:19 PM PDT 24 169131710 ps
T1418 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2145891389 May 05 02:48:40 PM PDT 24 May 05 02:48:44 PM PDT 24 337389879 ps
T286 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3098849279 May 05 02:48:43 PM PDT 24 May 05 02:48:50 PM PDT 24 1200039230 ps
T1419 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3823318697 May 05 02:48:20 PM PDT 24 May 05 02:48:22 PM PDT 24 42191831 ps
T1420 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1358345746 May 05 02:48:26 PM PDT 24 May 05 02:48:31 PM PDT 24 634136751 ps
T1421 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3073740400 May 05 02:48:28 PM PDT 24 May 05 02:48:33 PM PDT 24 115205820 ps
T1422 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3398446101 May 05 02:48:14 PM PDT 24 May 05 02:48:16 PM PDT 24 65207959 ps
T1423 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2493264264 May 05 02:48:44 PM PDT 24 May 05 02:48:47 PM PDT 24 360008332 ps
T1424 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3557101459 May 05 02:48:35 PM PDT 24 May 05 02:48:38 PM PDT 24 150788070 ps
T1425 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1084340106 May 05 02:48:43 PM PDT 24 May 05 02:48:48 PM PDT 24 253060290 ps
T1426 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3950669618 May 05 02:48:26 PM PDT 24 May 05 02:48:30 PM PDT 24 833754841 ps
T1427 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.385906742 May 05 02:48:25 PM PDT 24 May 05 02:48:27 PM PDT 24 211388729 ps
T1428 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1902790207 May 05 02:48:28 PM PDT 24 May 05 02:48:30 PM PDT 24 150601256 ps
T1429 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.884590259 May 05 02:48:15 PM PDT 24 May 05 02:48:18 PM PDT 24 196582103 ps
T1430 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3896709665 May 05 02:48:18 PM PDT 24 May 05 02:48:21 PM PDT 24 362576799 ps
T1431 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.487990212 May 05 02:48:26 PM PDT 24 May 05 02:48:28 PM PDT 24 73112185 ps
T1432 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2021043990 May 05 02:48:27 PM PDT 24 May 05 02:48:28 PM PDT 24 38412558 ps
T1433 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3868809297 May 05 02:48:42 PM PDT 24 May 05 02:48:44 PM PDT 24 29673772 ps
T1434 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3024661268 May 05 02:48:37 PM PDT 24 May 05 02:48:39 PM PDT 24 97077515 ps
T1435 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1142986186 May 05 02:48:45 PM PDT 24 May 05 02:48:47 PM PDT 24 35893428 ps
T1436 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4271962562 May 05 02:48:41 PM PDT 24 May 05 02:48:43 PM PDT 24 71494974 ps
T1437 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1216868204 May 05 02:48:48 PM PDT 24 May 05 02:48:49 PM PDT 24 44475946 ps
T1438 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1172108234 May 05 02:48:17 PM PDT 24 May 05 02:48:22 PM PDT 24 388258560 ps
T1439 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4169866115 May 05 02:48:45 PM PDT 24 May 05 02:48:47 PM PDT 24 29962922 ps
T1440 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2533577416 May 05 02:48:36 PM PDT 24 May 05 02:48:40 PM PDT 24 292759060 ps
T1441 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1935123933 May 05 02:48:46 PM PDT 24 May 05 02:48:49 PM PDT 24 148177636 ps
T1442 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2784049336 May 05 02:48:33 PM PDT 24 May 05 02:48:34 PM PDT 24 34695345 ps
T1443 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1394856460 May 05 02:48:26 PM PDT 24 May 05 02:48:28 PM PDT 24 168161795 ps
T1444 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.207362301 May 05 02:48:32 PM PDT 24 May 05 02:48:33 PM PDT 24 86532545 ps
T1445 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2985364508 May 05 02:48:19 PM PDT 24 May 05 02:48:24 PM PDT 24 244384019 ps
T1446 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3409621493 May 05 02:48:25 PM PDT 24 May 05 02:48:26 PM PDT 24 43544594 ps
T1447 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1508968181 May 05 02:48:29 PM PDT 24 May 05 02:48:32 PM PDT 24 151223764 ps
T1448 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3977247317 May 05 02:48:40 PM PDT 24 May 05 02:48:44 PM PDT 24 209190216 ps
T1449 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.695024918 May 05 02:48:15 PM PDT 24 May 05 02:48:24 PM PDT 24 1145818102 ps
T287 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1072435791 May 05 02:48:19 PM PDT 24 May 05 02:48:26 PM PDT 24 1804983263 ps
T1450 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2121775615 May 05 02:48:21 PM PDT 24 May 05 02:48:24 PM PDT 24 206781740 ps
T1451 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2189841995 May 05 02:48:38 PM PDT 24 May 05 02:48:39 PM PDT 24 30036801 ps
T1452 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3460032098 May 05 02:48:25 PM PDT 24 May 05 02:48:26 PM PDT 24 32660234 ps
T1453 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3461306606 May 05 02:48:27 PM PDT 24 May 05 02:48:28 PM PDT 24 66407449 ps
T1454 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1535927676 May 05 02:48:24 PM PDT 24 May 05 02:48:25 PM PDT 24 36527355 ps
T1455 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3479938346 May 05 02:48:42 PM PDT 24 May 05 02:48:46 PM PDT 24 503966015 ps
T1456 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.417643938 May 05 02:48:23 PM PDT 24 May 05 02:48:26 PM PDT 24 252552168 ps
T1457 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.23034235 May 05 02:48:16 PM PDT 24 May 05 02:48:21 PM PDT 24 600053439 ps
T1458 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1212534889 May 05 02:48:41 PM PDT 24 May 05 02:48:43 PM PDT 24 86106994 ps
T1459 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.943302945 May 05 02:48:40 PM PDT 24 May 05 02:48:42 PM PDT 24 26232348 ps
T1460 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.46257075 May 05 02:48:22 PM PDT 24 May 05 02:48:24 PM PDT 24 66493998 ps
T288 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.550379408 May 05 02:48:23 PM PDT 24 May 05 02:48:28 PM PDT 24 575834221 ps
T1461 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1409520253 May 05 02:48:34 PM PDT 24 May 05 02:48:36 PM PDT 24 61673636 ps
T1462 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1742783660 May 05 02:48:22 PM PDT 24 May 05 02:48:24 PM PDT 24 233912809 ps
T1463 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.300088594 May 05 02:48:18 PM PDT 24 May 05 02:48:20 PM PDT 24 74731078 ps
T1464 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.58919036 May 05 02:48:18 PM PDT 24 May 05 02:48:21 PM PDT 24 81194914 ps
T1465 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4186348496 May 05 02:48:21 PM PDT 24 May 05 02:48:27 PM PDT 24 36550157 ps
T1466 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1606389711 May 05 02:48:39 PM PDT 24 May 05 02:48:41 PM PDT 24 52629350 ps
T1467 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3070099078 May 05 02:48:19 PM PDT 24 May 05 02:48:22 PM PDT 24 94038181 ps
T1468 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3641027502 May 05 02:48:46 PM PDT 24 May 05 02:48:48 PM PDT 24 23625102 ps
T1469 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3847543296 May 05 02:48:27 PM PDT 24 May 05 02:48:30 PM PDT 24 57573696 ps
T1470 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.982216581 May 05 02:48:30 PM PDT 24 May 05 02:48:33 PM PDT 24 246336195 ps
T1471 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1455480190 May 05 02:48:27 PM PDT 24 May 05 02:48:30 PM PDT 24 154980541 ps
T1472 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.126659728 May 05 02:48:26 PM PDT 24 May 05 02:48:28 PM PDT 24 30894051 ps
T1473 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1060275330 May 05 02:48:19 PM PDT 24 May 05 02:48:22 PM PDT 24 176743942 ps
T1474 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1839046500 May 05 02:48:17 PM PDT 24 May 05 02:48:19 PM PDT 24 204480614 ps
T1475 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2881823615 May 05 02:48:33 PM PDT 24 May 05 02:48:34 PM PDT 24 34219738 ps
T1476 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2823459735 May 05 02:48:31 PM PDT 24 May 05 02:48:36 PM PDT 24 1301396502 ps
T1477 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1327121278 May 05 02:48:14 PM PDT 24 May 05 02:48:17 PM PDT 24 190278618 ps
T1478 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1586684744 May 05 02:48:17 PM PDT 24 May 05 02:48:22 PM PDT 24 650807809 ps
T1479 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3311521435 May 05 02:48:21 PM PDT 24 May 05 02:48:23 PM PDT 24 191081249 ps
T1480 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.974430293 May 05 02:48:16 PM PDT 24 May 05 02:48:20 PM PDT 24 120332328 ps
T1481 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.702453157 May 05 02:48:17 PM PDT 24 May 05 02:48:22 PM PDT 24 123269956 ps

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.92828958
Short name T3
Test name
Test status
Simulation time 20977578455 ps
CPU time 38.75 seconds
Started May 05 03:15:58 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204348 kb
Host smart-7e16a670-b9f2-4f38-ace1-bead8cf029e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92828
958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.92828958
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4291860059
Short name T72
Test name
Test status
Simulation time 40262797 ps
CPU time 0.7 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:45 PM PDT 24
Peak memory 203300 kb
Host smart-b8200c1e-0ba4-40a5-96e7-bc79253befa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4291860059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4291860059
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1360199121
Short name T61
Test name
Test status
Simulation time 286349419 ps
CPU time 2.05 seconds
Started May 05 02:48:23 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 215664 kb
Host smart-faa0f898-4e96-414b-b97c-ba51c738d798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360199121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1360199121
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2395233998
Short name T16
Test name
Test status
Simulation time 8430312210 ps
CPU time 8.08 seconds
Started May 05 03:14:16 PM PDT 24
Finished May 05 03:14:24 PM PDT 24
Peak memory 204112 kb
Host smart-46876f0e-b7bd-4e02-9d54-5cc605c08f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
33998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2395233998
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3695953730
Short name T9
Test name
Test status
Simulation time 5167376920 ps
CPU time 31.11 seconds
Started May 05 03:10:39 PM PDT 24
Finished May 05 03:11:10 PM PDT 24
Peak memory 204312 kb
Host smart-5893b027-96f9-4d6d-a99f-710946e8a1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
53730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3695953730
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3545314727
Short name T74
Test name
Test status
Simulation time 31586065 ps
CPU time 0.67 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 203224 kb
Host smart-0ed0431e-bdde-4f47-a49d-8bafde4a3bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3545314727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3545314727
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.4201594555
Short name T35
Test name
Test status
Simulation time 87457613 ps
CPU time 0.74 seconds
Started May 05 03:10:57 PM PDT 24
Finished May 05 03:10:58 PM PDT 24
Peak memory 203964 kb
Host smart-b9b578bb-2caf-44ae-a492-1985912f4626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
94555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.4201594555
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1440337830
Short name T55
Test name
Test status
Simulation time 8462782007 ps
CPU time 8.97 seconds
Started May 05 03:15:31 PM PDT 24
Finished May 05 03:15:41 PM PDT 24
Peak memory 204084 kb
Host smart-6244f904-3d2f-49e4-9752-9cca6fa7ac5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14403
37830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1440337830
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2558479233
Short name T62
Test name
Test status
Simulation time 166353193 ps
CPU time 2.21 seconds
Started May 05 02:48:24 PM PDT 24
Finished May 05 02:48:27 PM PDT 24
Peak memory 204120 kb
Host smart-b58086e8-2f12-4523-ba5f-10662a016f50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2558479233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2558479233
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.714425872
Short name T5
Test name
Test status
Simulation time 8399846219 ps
CPU time 8 seconds
Started May 05 03:15:53 PM PDT 24
Finished May 05 03:16:02 PM PDT 24
Peak memory 204140 kb
Host smart-9616d3ab-146f-4440-8915-d52b89cfd817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71442
5872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.714425872
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.323435362
Short name T102
Test name
Test status
Simulation time 8420464375 ps
CPU time 7.79 seconds
Started May 05 03:13:35 PM PDT 24
Finished May 05 03:13:43 PM PDT 24
Peak memory 204112 kb
Host smart-38966bfb-77d8-4748-8f6f-ae05b6acc4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32343
5362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.323435362
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.469946355
Short name T64
Test name
Test status
Simulation time 137156424 ps
CPU time 0.97 seconds
Started May 05 03:12:09 PM PDT 24
Finished May 05 03:12:10 PM PDT 24
Peak memory 220404 kb
Host smart-82008074-b7f3-442c-9fe5-bb4fc6e129e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=469946355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.469946355
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1919318900
Short name T1
Test name
Test status
Simulation time 64168278 ps
CPU time 0.93 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 203740 kb
Host smart-4739d83c-2124-48ce-a73a-3145e2ab8f2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1919318900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1919318900
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2949784298
Short name T276
Test name
Test status
Simulation time 52856426 ps
CPU time 0.68 seconds
Started May 05 02:48:30 PM PDT 24
Finished May 05 02:48:32 PM PDT 24
Peak memory 203296 kb
Host smart-ccc95502-ff5a-4650-83d4-dffe94f90b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2949784298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2949784298
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2031448750
Short name T455
Test name
Test status
Simulation time 8374195110 ps
CPU time 8.65 seconds
Started May 05 03:13:56 PM PDT 24
Finished May 05 03:14:05 PM PDT 24
Peak memory 204116 kb
Host smart-0358ff9b-7da8-4a99-945b-129bd6488509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20314
48750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2031448750
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1615392007
Short name T21
Test name
Test status
Simulation time 124846312 ps
CPU time 1.32 seconds
Started May 05 03:16:12 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204172 kb
Host smart-8adf7aba-d70b-4f5a-ac8f-5944c233bce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
92007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1615392007
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3273974997
Short name T20
Test name
Test status
Simulation time 8415924387 ps
CPU time 7.91 seconds
Started May 05 03:14:41 PM PDT 24
Finished May 05 03:14:49 PM PDT 24
Peak memory 204136 kb
Host smart-9f9b52d2-1247-47d3-be27-53213d79b36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
74997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3273974997
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1305870501
Short name T234
Test name
Test status
Simulation time 223928305 ps
CPU time 2.82 seconds
Started May 05 02:48:38 PM PDT 24
Finished May 05 02:48:42 PM PDT 24
Peak memory 204020 kb
Host smart-dc611d17-9bc8-40d1-843d-b585c590e970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1305870501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1305870501
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3098849279
Short name T286
Test name
Test status
Simulation time 1200039230 ps
CPU time 5.85 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:50 PM PDT 24
Peak memory 203956 kb
Host smart-2bd5f515-c912-457c-847a-d14667723a21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3098849279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3098849279
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.562899155
Short name T75
Test name
Test status
Simulation time 88753688 ps
CPU time 0.75 seconds
Started May 05 02:48:45 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 203244 kb
Host smart-a3eb99cb-2693-4250-a6fb-742c53cdec59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=562899155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.562899155
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1848278243
Short name T336
Test name
Test status
Simulation time 8399829369 ps
CPU time 7.45 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:13:56 PM PDT 24
Peak memory 204000 kb
Host smart-d9a5ae51-d948-49e8-8da5-6364beb7c6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
78243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1848278243
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1779460187
Short name T98
Test name
Test status
Simulation time 65625192 ps
CPU time 0.95 seconds
Started May 05 02:48:21 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203896 kb
Host smart-f1c0b43c-f692-4622-8792-45a25bf594e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1779460187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1779460187
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1607234061
Short name T76
Test name
Test status
Simulation time 34697143 ps
CPU time 0.73 seconds
Started May 05 02:48:42 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 203224 kb
Host smart-55f76e79-385b-48fb-a0c1-67f8c0a40e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1607234061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1607234061
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1402575231
Short name T230
Test name
Test status
Simulation time 25932962336 ps
CPU time 47.81 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204412 kb
Host smart-2ff6d946-7b30-4575-88cc-f1f13ff809f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
75231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1402575231
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2717992376
Short name T67
Test name
Test status
Simulation time 38813354 ps
CPU time 0.8 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:18 PM PDT 24
Peak memory 203632 kb
Host smart-ae3a5573-eaba-4c2b-b2ed-a80c068bb538
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2717992376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2717992376
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2533577416
Short name T1440
Test name
Test status
Simulation time 292759060 ps
CPU time 2.47 seconds
Started May 05 02:48:36 PM PDT 24
Finished May 05 02:48:40 PM PDT 24
Peak memory 203972 kb
Host smart-7067eecd-2444-49e5-a05d-685877f6bf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2533577416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2533577416
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1690180724
Short name T43
Test name
Test status
Simulation time 31510616 ps
CPU time 0.66 seconds
Started May 05 03:14:22 PM PDT 24
Finished May 05 03:14:24 PM PDT 24
Peak memory 203964 kb
Host smart-40878d5f-c725-42f0-be3e-1bd9e5785c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16901
80724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1690180724
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2047645979
Short name T166
Test name
Test status
Simulation time 8434491238 ps
CPU time 8.09 seconds
Started May 05 03:10:58 PM PDT 24
Finished May 05 03:11:06 PM PDT 24
Peak memory 204072 kb
Host smart-a81fb3db-a596-42f3-a079-4b5c38a3fbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20476
45979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2047645979
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4167637167
Short name T195
Test name
Test status
Simulation time 8387486389 ps
CPU time 8.91 seconds
Started May 05 03:11:25 PM PDT 24
Finished May 05 03:11:34 PM PDT 24
Peak memory 204096 kb
Host smart-75e0cd33-8063-40b6-9d9b-3b2d9db3b744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41676
37167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4167637167
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1355542369
Short name T851
Test name
Test status
Simulation time 8414185730 ps
CPU time 9.29 seconds
Started May 05 03:13:23 PM PDT 24
Finished May 05 03:13:33 PM PDT 24
Peak memory 204108 kb
Host smart-0a4ec580-4e9f-400a-b0b6-25c8ce71b7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13555
42369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1355542369
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.4291787632
Short name T28
Test name
Test status
Simulation time 8407248594 ps
CPU time 9.8 seconds
Started May 05 03:13:32 PM PDT 24
Finished May 05 03:13:42 PM PDT 24
Peak memory 204084 kb
Host smart-3318edd4-55bb-4e34-901b-1963559af5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
87632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.4291787632
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.517204954
Short name T684
Test name
Test status
Simulation time 8413046188 ps
CPU time 7.95 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:52 PM PDT 24
Peak memory 204116 kb
Host smart-6e7a0583-d0d6-4c44-916a-2173d9c0859b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51720
4954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.517204954
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.493330573
Short name T761
Test name
Test status
Simulation time 8421476467 ps
CPU time 8.28 seconds
Started May 05 03:13:55 PM PDT 24
Finished May 05 03:14:04 PM PDT 24
Peak memory 204048 kb
Host smart-94a6322a-b4c8-4c22-99eb-e38574cb418f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49333
0573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.493330573
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1691823133
Short name T993
Test name
Test status
Simulation time 8410585323 ps
CPU time 8.3 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204080 kb
Host smart-b0442ca4-e90c-4c3c-b849-cbde0984113c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
23133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1691823133
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3704573875
Short name T702
Test name
Test status
Simulation time 8400556019 ps
CPU time 7.75 seconds
Started May 05 03:14:36 PM PDT 24
Finished May 05 03:14:45 PM PDT 24
Peak memory 204060 kb
Host smart-d8f4c70a-32fb-4323-a807-38a552693fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045
73875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3704573875
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3135144800
Short name T1085
Test name
Test status
Simulation time 8377262234 ps
CPU time 7.77 seconds
Started May 05 03:15:58 PM PDT 24
Finished May 05 03:16:07 PM PDT 24
Peak memory 204108 kb
Host smart-60ba0668-a299-4096-899f-4f8bbd4029be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31351
44800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3135144800
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.461998501
Short name T298
Test name
Test status
Simulation time 8404078223 ps
CPU time 8.21 seconds
Started May 05 03:11:26 PM PDT 24
Finished May 05 03:11:35 PM PDT 24
Peak memory 204088 kb
Host smart-5ebcefe6-7ec5-493b-9e75-ad86507643c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46199
8501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.461998501
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1768556069
Short name T235
Test name
Test status
Simulation time 68782453 ps
CPU time 2.07 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 204064 kb
Host smart-6404f3ad-1a87-4daa-8c60-656606bbbea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768556069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1768556069
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1638890706
Short name T23
Test name
Test status
Simulation time 8374371004 ps
CPU time 7.84 seconds
Started May 05 03:10:54 PM PDT 24
Finished May 05 03:11:02 PM PDT 24
Peak memory 204080 kb
Host smart-b3ff9531-d1f9-4af3-a15c-681172ace8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
90706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1638890706
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1713513035
Short name T179
Test name
Test status
Simulation time 8427395199 ps
CPU time 7.51 seconds
Started May 05 03:10:37 PM PDT 24
Finished May 05 03:10:45 PM PDT 24
Peak memory 204084 kb
Host smart-bd92306d-d3bd-4492-bb7f-dda5cc1cc269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17135
13035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1713513035
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2713649855
Short name T960
Test name
Test status
Simulation time 8376159524 ps
CPU time 8.91 seconds
Started May 05 03:10:58 PM PDT 24
Finished May 05 03:11:08 PM PDT 24
Peak memory 204076 kb
Host smart-4c577e8c-5414-42d1-8319-b97d75711831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27136
49855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2713649855
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3809173992
Short name T114
Test name
Test status
Simulation time 8432540897 ps
CPU time 8.28 seconds
Started May 05 03:10:46 PM PDT 24
Finished May 05 03:10:54 PM PDT 24
Peak memory 204132 kb
Host smart-bce7fe9a-af26-4658-8947-00e0ea310295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
73992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3809173992
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.782479300
Short name T79
Test name
Test status
Simulation time 8446886327 ps
CPU time 7.67 seconds
Started May 05 03:11:24 PM PDT 24
Finished May 05 03:11:32 PM PDT 24
Peak memory 204108 kb
Host smart-9edddcff-40d1-4961-ad65-1a6970a522eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78247
9300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.782479300
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.382487784
Short name T835
Test name
Test status
Simulation time 8406669946 ps
CPU time 7.5 seconds
Started May 05 03:11:23 PM PDT 24
Finished May 05 03:11:31 PM PDT 24
Peak memory 204052 kb
Host smart-2d05740a-9601-4492-b772-59ff1b753c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38248
7784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.382487784
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_smoke.872195647
Short name T148
Test name
Test status
Simulation time 8448652129 ps
CPU time 10.63 seconds
Started May 05 03:11:12 PM PDT 24
Finished May 05 03:11:23 PM PDT 24
Peak memory 204124 kb
Host smart-724b9eaa-41f5-4649-9797-f0b9305cc436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87219
5647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.872195647
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.90917437
Short name T1213
Test name
Test status
Simulation time 8438589228 ps
CPU time 10.19 seconds
Started May 05 03:13:17 PM PDT 24
Finished May 05 03:13:27 PM PDT 24
Peak memory 204276 kb
Host smart-5ffad302-20f2-4cde-9fdf-ef4e01ca5744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90917
437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.90917437
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.250964604
Short name T850
Test name
Test status
Simulation time 8451465557 ps
CPU time 8.08 seconds
Started May 05 03:13:19 PM PDT 24
Finished May 05 03:13:27 PM PDT 24
Peak memory 204032 kb
Host smart-24e1bcf1-9759-4192-83c4-99e5d3b57269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25096
4604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.250964604
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.4038701448
Short name T155
Test name
Test status
Simulation time 8437217012 ps
CPU time 8.51 seconds
Started May 05 03:13:30 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204136 kb
Host smart-a8630d98-a6e4-41fa-9f7b-b53d7d67bdc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
01448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.4038701448
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1283691229
Short name T1280
Test name
Test status
Simulation time 8469190089 ps
CPU time 7.93 seconds
Started May 05 03:13:27 PM PDT 24
Finished May 05 03:13:36 PM PDT 24
Peak memory 204000 kb
Host smart-14808291-caa8-4d3e-b461-519a666f50f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12836
91229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1283691229
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1612497998
Short name T1153
Test name
Test status
Simulation time 8468539812 ps
CPU time 8.15 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:36 PM PDT 24
Peak memory 204108 kb
Host smart-2e3736ee-a653-472c-b403-b227755ea1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124
97998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1612497998
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.63907865
Short name T107
Test name
Test status
Simulation time 8403281445 ps
CPU time 8.94 seconds
Started May 05 03:13:53 PM PDT 24
Finished May 05 03:14:03 PM PDT 24
Peak memory 204084 kb
Host smart-f0cf6dcd-db36-4f6c-9a7e-3584331c2e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63907
865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.63907865
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.561741253
Short name T556
Test name
Test status
Simulation time 8368740344 ps
CPU time 7.37 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:26 PM PDT 24
Peak memory 204100 kb
Host smart-9ef9e1fc-fa95-4aff-aa6a-a8992a297fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56174
1253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.561741253
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.373933066
Short name T117
Test name
Test status
Simulation time 8404022234 ps
CPU time 7.58 seconds
Started May 05 03:14:10 PM PDT 24
Finished May 05 03:14:19 PM PDT 24
Peak memory 204100 kb
Host smart-b2d1ba87-143b-42fa-a2fb-5b42e3cdc470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
3066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.373933066
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1553833477
Short name T1314
Test name
Test status
Simulation time 30337561856 ps
CPU time 57.71 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:15:09 PM PDT 24
Peak memory 204304 kb
Host smart-f6f75273-7aa8-4eac-b780-2e868ebdb1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
33477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1553833477
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3269762697
Short name T113
Test name
Test status
Simulation time 8403248802 ps
CPU time 7.63 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204072 kb
Host smart-fd2ef93b-8f0e-4824-af29-2069a1f72dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32697
62697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3269762697
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3946489976
Short name T447
Test name
Test status
Simulation time 8410097848 ps
CPU time 7.73 seconds
Started May 05 03:14:27 PM PDT 24
Finished May 05 03:14:35 PM PDT 24
Peak memory 204124 kb
Host smart-2f047822-fdb9-4c09-8097-c5ab51c3d396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39464
89976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3946489976
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3160074332
Short name T120
Test name
Test status
Simulation time 8435316241 ps
CPU time 7.93 seconds
Started May 05 03:14:33 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 204132 kb
Host smart-d738fe8d-018b-4fa2-8904-2d952b4cf0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31600
74332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3160074332
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.27353154
Short name T129
Test name
Test status
Simulation time 8420419898 ps
CPU time 8.27 seconds
Started May 05 03:11:36 PM PDT 24
Finished May 05 03:11:44 PM PDT 24
Peak memory 204100 kb
Host smart-e5c3730d-a609-468c-8123-cce33deb2d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27353
154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.27353154
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.4173157532
Short name T105
Test name
Test status
Simulation time 8413593144 ps
CPU time 7.94 seconds
Started May 05 03:14:46 PM PDT 24
Finished May 05 03:14:54 PM PDT 24
Peak memory 204000 kb
Host smart-7a639232-92f5-4f47-b4e4-e904248020af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41731
57532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.4173157532
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3698183583
Short name T404
Test name
Test status
Simulation time 8418162275 ps
CPU time 8.1 seconds
Started May 05 03:14:45 PM PDT 24
Finished May 05 03:14:53 PM PDT 24
Peak memory 204092 kb
Host smart-aba24f1f-0112-4fb2-a7ce-4c9682aa2bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36981
83583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3698183583
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_smoke.33461467
Short name T631
Test name
Test status
Simulation time 8458134244 ps
CPU time 8.7 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:03 PM PDT 24
Peak memory 204084 kb
Host smart-ce38ab08-4a63-440f-9ac1-3550772931d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.33461467
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.630323045
Short name T109
Test name
Test status
Simulation time 8426183321 ps
CPU time 8.05 seconds
Started May 05 03:15:12 PM PDT 24
Finished May 05 03:15:20 PM PDT 24
Peak memory 204072 kb
Host smart-b387aadc-38f5-49c9-b43a-74ec2d424950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63032
3045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.630323045
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.709244625
Short name T27
Test name
Test status
Simulation time 8371104826 ps
CPU time 7.53 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:35 PM PDT 24
Peak memory 204100 kb
Host smart-7ce36758-9853-418b-802f-d66122f5c2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70924
4625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.709244625
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.702453157
Short name T1481
Test name
Test status
Simulation time 123269956 ps
CPU time 3.3 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203956 kb
Host smart-3ee94c94-3523-4d26-bbfa-5f5e5e7a05b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=702453157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.702453157
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1358345746
Short name T1420
Test name
Test status
Simulation time 634136751 ps
CPU time 4.7 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:31 PM PDT 24
Peak memory 203912 kb
Host smart-1ea8d56c-30b4-42e1-b072-200aace3d6af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1358345746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1358345746
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1839046500
Short name T1474
Test name
Test status
Simulation time 204480614 ps
CPU time 1.09 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:19 PM PDT 24
Peak memory 203724 kb
Host smart-0285cc3c-7cda-4a7d-a866-ac76236f86d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1839046500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1839046500
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1455480190
Short name T1471
Test name
Test status
Simulation time 154980541 ps
CPU time 1.72 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:30 PM PDT 24
Peak memory 212256 kb
Host smart-b00c2bf8-c512-4cea-9209-9f5480a4eedd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455480190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1455480190
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.403540426
Short name T101
Test name
Test status
Simulation time 53004668 ps
CPU time 0.78 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:15 PM PDT 24
Peak memory 203760 kb
Host smart-c5bc5153-5f66-4e89-9307-af32e5da3d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=403540426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.403540426
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1535927676
Short name T1454
Test name
Test status
Simulation time 36527355 ps
CPU time 0.68 seconds
Started May 05 02:48:24 PM PDT 24
Finished May 05 02:48:25 PM PDT 24
Peak memory 203288 kb
Host smart-4124a306-65ab-4160-92ad-df5b361e9463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1535927676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1535927676
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.728609822
Short name T262
Test name
Test status
Simulation time 52711552 ps
CPU time 1.43 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:20 PM PDT 24
Peak memory 204012 kb
Host smart-385d7a22-d133-4535-8127-806c2a65c0e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=728609822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.728609822
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.417643938
Short name T1456
Test name
Test status
Simulation time 252552168 ps
CPU time 2.57 seconds
Started May 05 02:48:23 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 203880 kb
Host smart-5cb76188-9ba1-4f7f-917d-746234b33b65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=417643938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.417643938
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3398446101
Short name T1422
Test name
Test status
Simulation time 65207959 ps
CPU time 1.36 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:16 PM PDT 24
Peak memory 203944 kb
Host smart-790bef2a-a97d-4415-affc-c0588374082f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3398446101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3398446101
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.550379408
Short name T288
Test name
Test status
Simulation time 575834221 ps
CPU time 4.54 seconds
Started May 05 02:48:23 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 203988 kb
Host smart-2a08be00-3541-43bd-8bd1-b863c0078875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=550379408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.550379408
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3057143905
Short name T255
Test name
Test status
Simulation time 118253677 ps
CPU time 3.19 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203920 kb
Host smart-eb11de2a-07d8-4b31-bca9-36003d63f761
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3057143905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3057143905
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2824084380
Short name T1394
Test name
Test status
Simulation time 885767076 ps
CPU time 4.74 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:23 PM PDT 24
Peak memory 203880 kb
Host smart-55d2edf0-9cf6-498f-9b3c-68605618330c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2824084380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2824084380
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4018709467
Short name T239
Test name
Test status
Simulation time 97084262 ps
CPU time 2.58 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:20 PM PDT 24
Peak memory 212240 kb
Host smart-834fc62a-f004-4e5b-9e4c-c730474f1382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018709467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.4018709467
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2947104324
Short name T1406
Test name
Test status
Simulation time 48890608 ps
CPU time 0.83 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 203744 kb
Host smart-6b858d6b-18eb-402e-9f58-2c2276ec8382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2947104324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2947104324
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3764459648
Short name T1415
Test name
Test status
Simulation time 28680621 ps
CPU time 0.63 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:15 PM PDT 24
Peak memory 203188 kb
Host smart-f9bffc69-dd93-472f-975e-81a174da68da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3764459648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3764459648
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2018810687
Short name T254
Test name
Test status
Simulation time 105221375 ps
CPU time 1.45 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:16 PM PDT 24
Peak memory 212192 kb
Host smart-5f01e868-d0a5-4523-85a0-7c40edfd4cc3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2018810687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2018810687
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3896709665
Short name T1430
Test name
Test status
Simulation time 362576799 ps
CPU time 2.58 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:21 PM PDT 24
Peak memory 203872 kb
Host smart-991c0fe7-1910-40a6-9f60-31872e81e4c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3896709665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3896709665
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1907378369
Short name T264
Test name
Test status
Simulation time 146539176 ps
CPU time 1.53 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:18 PM PDT 24
Peak memory 203936 kb
Host smart-aa02a77b-116f-40dd-bb69-ea2ce50d3629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1907378369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1907378369
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1976247661
Short name T213
Test name
Test status
Simulation time 117289711 ps
CPU time 1.59 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 203988 kb
Host smart-9c69f41e-6515-4837-a369-4f9bec1a8a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1976247661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1976247661
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2538835749
Short name T211
Test name
Test status
Simulation time 1067627914 ps
CPU time 4.89 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203992 kb
Host smart-47d52508-3485-4d08-8d5c-689963c6aa20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2538835749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2538835749
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3409621493
Short name T1446
Test name
Test status
Simulation time 43544594 ps
CPU time 0.98 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 203968 kb
Host smart-a9e8f375-37e6-4a7c-8129-e5ebc92cd7f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3409621493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3409621493
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.916565593
Short name T1413
Test name
Test status
Simulation time 29819959 ps
CPU time 0.63 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 203216 kb
Host smart-6a003a3b-4938-43b4-b592-3a4fef4f532b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916565593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.916565593
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.886171952
Short name T1376
Test name
Test status
Simulation time 56891420 ps
CPU time 1.1 seconds
Started May 05 02:48:29 PM PDT 24
Finished May 05 02:48:31 PM PDT 24
Peak memory 204036 kb
Host smart-e6946e73-a8b6-496f-850f-4c0ebf77f7f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=886171952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.886171952
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1902790207
Short name T1428
Test name
Test status
Simulation time 150601256 ps
CPU time 1.81 seconds
Started May 05 02:48:28 PM PDT 24
Finished May 05 02:48:30 PM PDT 24
Peak memory 204004 kb
Host smart-99aca7bd-b701-434f-aa96-76368290ffe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1902790207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1902790207
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1793707913
Short name T1388
Test name
Test status
Simulation time 144355695 ps
CPU time 1.85 seconds
Started May 05 02:48:31 PM PDT 24
Finished May 05 02:48:34 PM PDT 24
Peak memory 212196 kb
Host smart-f94c02ee-e60f-44a4-8fa2-853ec7394dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793707913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1793707913
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1573918155
Short name T1384
Test name
Test status
Simulation time 52677475 ps
CPU time 0.81 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 203724 kb
Host smart-e6699c91-5806-464d-aae2-f6cf0ffdbacf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573918155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1573918155
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2329190213
Short name T71
Test name
Test status
Simulation time 30198121 ps
CPU time 0.63 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:27 PM PDT 24
Peak memory 203204 kb
Host smart-542ed5e4-00e4-4208-bc11-6b36699adf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2329190213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2329190213
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3269296383
Short name T70
Test name
Test status
Simulation time 123441561 ps
CPU time 1.48 seconds
Started May 05 02:48:34 PM PDT 24
Finished May 05 02:48:37 PM PDT 24
Peak memory 204008 kb
Host smart-21a52114-fe4b-4796-81b6-269a6748e9df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3269296383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3269296383
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1508968181
Short name T1447
Test name
Test status
Simulation time 151223764 ps
CPU time 1.89 seconds
Started May 05 02:48:29 PM PDT 24
Finished May 05 02:48:32 PM PDT 24
Peak memory 204088 kb
Host smart-8b523cf3-d0d1-4e01-950f-0b82dce63e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1508968181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1508968181
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2823459735
Short name T1476
Test name
Test status
Simulation time 1301396502 ps
CPU time 4.92 seconds
Started May 05 02:48:31 PM PDT 24
Finished May 05 02:48:36 PM PDT 24
Peak memory 203984 kb
Host smart-2585d8d5-9f01-4cdd-8340-f5d3351087ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2823459735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2823459735
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4012713804
Short name T63
Test name
Test status
Simulation time 134256270 ps
CPU time 1.85 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 212200 kb
Host smart-d5c54b43-ba2f-4802-bdaa-eaa668ce5dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012713804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4012713804
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3461306606
Short name T1453
Test name
Test status
Simulation time 66407449 ps
CPU time 0.98 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 203900 kb
Host smart-d251cb21-7044-4867-9ab4-0cea361a01ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3461306606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3461306606
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1189565493
Short name T282
Test name
Test status
Simulation time 107030951 ps
CPU time 0.7 seconds
Started May 05 02:48:24 PM PDT 24
Finished May 05 02:48:25 PM PDT 24
Peak memory 203132 kb
Host smart-5c3d03ea-440c-4a33-86b2-7865b3944238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1189565493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1189565493
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.287224733
Short name T1387
Test name
Test status
Simulation time 42700655 ps
CPU time 1.06 seconds
Started May 05 02:48:39 PM PDT 24
Finished May 05 02:48:42 PM PDT 24
Peak memory 203912 kb
Host smart-8d8653fc-7a14-4853-8179-a1d9d7b04227
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=287224733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.287224733
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1343813222
Short name T240
Test name
Test status
Simulation time 179513377 ps
CPU time 1.9 seconds
Started May 05 02:48:31 PM PDT 24
Finished May 05 02:48:34 PM PDT 24
Peak memory 204044 kb
Host smart-5a43fe27-4250-4467-bd69-4ef49aa2ffa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1343813222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1343813222
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2961266476
Short name T271
Test name
Test status
Simulation time 511829357 ps
CPU time 2.88 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 204004 kb
Host smart-80c316ed-072e-4dd5-b4fe-81ac03518712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2961266476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2961266476
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2928171810
Short name T100
Test name
Test status
Simulation time 87231791 ps
CPU time 2.48 seconds
Started May 05 02:48:29 PM PDT 24
Finished May 05 02:48:32 PM PDT 24
Peak memory 212216 kb
Host smart-f025f109-a014-4050-9b39-c6c5ff815d34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928171810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2928171810
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.163610921
Short name T256
Test name
Test status
Simulation time 75689548 ps
CPU time 0.97 seconds
Started May 05 02:48:28 PM PDT 24
Finished May 05 02:48:30 PM PDT 24
Peak memory 203964 kb
Host smart-7d840c55-d1ea-4c3f-a26e-46de67beafef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=163610921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.163610921
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2493264264
Short name T1423
Test name
Test status
Simulation time 360008332 ps
CPU time 2.04 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 204004 kb
Host smart-f45903cc-771a-493b-82cc-b61cb020d9ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2493264264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2493264264
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.982216581
Short name T1470
Test name
Test status
Simulation time 246336195 ps
CPU time 2.46 seconds
Started May 05 02:48:30 PM PDT 24
Finished May 05 02:48:33 PM PDT 24
Peak memory 204100 kb
Host smart-6ce73945-e678-40f0-990a-3ee9ee4fbc10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=982216581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.982216581
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.297971752
Short name T210
Test name
Test status
Simulation time 1679081476 ps
CPU time 5.42 seconds
Started May 05 02:48:28 PM PDT 24
Finished May 05 02:48:34 PM PDT 24
Peak memory 204000 kb
Host smart-aca1d73c-35e2-4a54-a191-483ef8934523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=297971752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.297971752
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.540821089
Short name T1377
Test name
Test status
Simulation time 166345245 ps
CPU time 1.78 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 212172 kb
Host smart-a98f2843-90e2-4da6-80db-b495d07c29fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540821089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.540821089
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2290806701
Short name T270
Test name
Test status
Simulation time 72783884 ps
CPU time 0.85 seconds
Started May 05 02:48:41 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203776 kb
Host smart-779808f0-f129-4276-be6b-25873860f300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2290806701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2290806701
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.355307626
Short name T69
Test name
Test status
Simulation time 85090967 ps
CPU time 1.58 seconds
Started May 05 02:48:30 PM PDT 24
Finished May 05 02:48:32 PM PDT 24
Peak memory 204020 kb
Host smart-283ca3a8-5678-4837-b7fc-d812f2a38b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=355307626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.355307626
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3479938346
Short name T1455
Test name
Test status
Simulation time 503966015 ps
CPU time 3.05 seconds
Started May 05 02:48:42 PM PDT 24
Finished May 05 02:48:46 PM PDT 24
Peak memory 203864 kb
Host smart-9ee71e72-a1c5-4866-95be-b24e7c646d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3479938346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3479938346
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.684098347
Short name T1404
Test name
Test status
Simulation time 71408407 ps
CPU time 1.86 seconds
Started May 05 02:48:33 PM PDT 24
Finished May 05 02:48:35 PM PDT 24
Peak memory 212264 kb
Host smart-e07f2db0-e731-4e15-9f84-8656c585c2db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684098347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.684098347
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.771513051
Short name T257
Test name
Test status
Simulation time 32438582 ps
CPU time 0.81 seconds
Started May 05 02:48:32 PM PDT 24
Finished May 05 02:48:34 PM PDT 24
Peak memory 203684 kb
Host smart-f583ce39-94ac-44da-b995-e6ce1f116b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=771513051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.771513051
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.126659728
Short name T1472
Test name
Test status
Simulation time 30894051 ps
CPU time 0.66 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 203260 kb
Host smart-beb0bf39-864e-41db-b07d-bad46dfd1ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126659728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.126659728
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1928490128
Short name T266
Test name
Test status
Simulation time 177086758 ps
CPU time 1.67 seconds
Started May 05 02:48:29 PM PDT 24
Finished May 05 02:48:31 PM PDT 24
Peak memory 204040 kb
Host smart-19d46ec6-869a-40f7-bce0-46136c1a21a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1928490128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1928490128
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3557101459
Short name T1424
Test name
Test status
Simulation time 150788070 ps
CPU time 2.82 seconds
Started May 05 02:48:35 PM PDT 24
Finished May 05 02:48:38 PM PDT 24
Peak memory 204024 kb
Host smart-893e2bd6-cb96-45c6-a815-793fb860196c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3557101459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3557101459
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.634687816
Short name T1379
Test name
Test status
Simulation time 146807996 ps
CPU time 1.98 seconds
Started May 05 02:48:42 PM PDT 24
Finished May 05 02:48:45 PM PDT 24
Peak memory 215084 kb
Host smart-d270b51e-9a46-449b-9dd3-bff63bcf3e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634687816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.634687816
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4189980227
Short name T258
Test name
Test status
Simulation time 45828568 ps
CPU time 0.96 seconds
Started May 05 02:48:47 PM PDT 24
Finished May 05 02:48:49 PM PDT 24
Peak memory 203984 kb
Host smart-95539320-274e-47e5-9550-88ed5bb8e8bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4189980227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.4189980227
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2881823615
Short name T1475
Test name
Test status
Simulation time 34219738 ps
CPU time 0.65 seconds
Started May 05 02:48:33 PM PDT 24
Finished May 05 02:48:34 PM PDT 24
Peak memory 203200 kb
Host smart-063f7d2d-40ed-4882-b9c4-a396c47794f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2881823615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2881823615
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.835783137
Short name T1405
Test name
Test status
Simulation time 188967068 ps
CPU time 1.63 seconds
Started May 05 02:48:38 PM PDT 24
Finished May 05 02:48:40 PM PDT 24
Peak memory 203944 kb
Host smart-0c78a989-588a-4121-bdc1-cc0f5512df7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=835783137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.835783137
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1409520253
Short name T1461
Test name
Test status
Simulation time 61673636 ps
CPU time 1.85 seconds
Started May 05 02:48:34 PM PDT 24
Finished May 05 02:48:36 PM PDT 24
Peak memory 204032 kb
Host smart-ac8d4081-3fd2-4bd6-8f54-3be8bf94c4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1409520253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1409520253
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2145891389
Short name T1418
Test name
Test status
Simulation time 337389879 ps
CPU time 2.77 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 204012 kb
Host smart-33bd9be0-cf15-4ca6-9cce-a1780c8882db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2145891389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2145891389
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.731859112
Short name T1399
Test name
Test status
Simulation time 178720699 ps
CPU time 2.05 seconds
Started May 05 02:48:36 PM PDT 24
Finished May 05 02:48:38 PM PDT 24
Peak memory 215568 kb
Host smart-3885fe8e-f5e0-4bfd-805b-a22fef29cf45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731859112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.731859112
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2778348307
Short name T1378
Test name
Test status
Simulation time 50995206 ps
CPU time 0.8 seconds
Started May 05 02:48:29 PM PDT 24
Finished May 05 02:48:30 PM PDT 24
Peak memory 203760 kb
Host smart-718ca347-bac0-457d-822b-e87f6c091061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2778348307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2778348307
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.225338551
Short name T1395
Test name
Test status
Simulation time 23517852 ps
CPU time 0.65 seconds
Started May 05 02:48:42 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203220 kb
Host smart-a65f3749-92b9-4406-9da2-bc915eb68fd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=225338551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.225338551
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2018605043
Short name T1389
Test name
Test status
Simulation time 171741682 ps
CPU time 1.39 seconds
Started May 05 02:48:42 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 203960 kb
Host smart-5518ae3d-61c7-4829-9bbd-a7abf6fc1ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2018605043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2018605043
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.201835861
Short name T209
Test name
Test status
Simulation time 125081410 ps
CPU time 1.48 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203992 kb
Host smart-9acf1800-3d61-4da2-a68b-fec97deaf1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=201835861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.201835861
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.429459820
Short name T215
Test name
Test status
Simulation time 634269747 ps
CPU time 4.43 seconds
Started May 05 02:48:38 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203812 kb
Host smart-eb3e6573-312c-4c23-9f19-c209cc6f2fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=429459820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.429459820
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3024661268
Short name T1434
Test name
Test status
Simulation time 97077515 ps
CPU time 1.45 seconds
Started May 05 02:48:37 PM PDT 24
Finished May 05 02:48:39 PM PDT 24
Peak memory 212236 kb
Host smart-33ffd454-b67b-415c-ba10-315eeec0f63c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024661268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3024661268
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3549007588
Short name T1375
Test name
Test status
Simulation time 137051861 ps
CPU time 1.11 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:46 PM PDT 24
Peak memory 203944 kb
Host smart-46edb173-c9d2-450b-9df1-069440731fc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3549007588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3549007588
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1436694824
Short name T1386
Test name
Test status
Simulation time 43999863 ps
CPU time 0.67 seconds
Started May 05 02:48:35 PM PDT 24
Finished May 05 02:48:36 PM PDT 24
Peak memory 203200 kb
Host smart-9305bb13-44af-46a2-bb80-32be0d47e061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1436694824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1436694824
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3981081215
Short name T1403
Test name
Test status
Simulation time 144276433 ps
CPU time 1.64 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:42 PM PDT 24
Peak memory 203912 kb
Host smart-95ada896-769a-4306-ac83-7cc567468caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3981081215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3981081215
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1084340106
Short name T1425
Test name
Test status
Simulation time 253060290 ps
CPU time 3.34 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:48 PM PDT 24
Peak memory 204112 kb
Host smart-fa2468c2-de65-4a77-945b-f50f5e5cf63f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1084340106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1084340106
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3975329032
Short name T272
Test name
Test status
Simulation time 343090067 ps
CPU time 2.95 seconds
Started May 05 02:48:38 PM PDT 24
Finished May 05 02:48:41 PM PDT 24
Peak memory 203996 kb
Host smart-ba0df5f3-7294-4d91-8534-6eb47badf6ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3975329032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3975329032
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1935123933
Short name T1441
Test name
Test status
Simulation time 148177636 ps
CPU time 1.85 seconds
Started May 05 02:48:46 PM PDT 24
Finished May 05 02:48:49 PM PDT 24
Peak memory 212196 kb
Host smart-d4dbf4b3-bb2f-419a-bdf7-a9e61bc053e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935123933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1935123933
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1606389711
Short name T1466
Test name
Test status
Simulation time 52629350 ps
CPU time 0.83 seconds
Started May 05 02:48:39 PM PDT 24
Finished May 05 02:48:41 PM PDT 24
Peak memory 203764 kb
Host smart-ca324730-bb63-4a42-86f0-f1d519be4632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1606389711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1606389711
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2189841995
Short name T1451
Test name
Test status
Simulation time 30036801 ps
CPU time 0.64 seconds
Started May 05 02:48:38 PM PDT 24
Finished May 05 02:48:39 PM PDT 24
Peak memory 203188 kb
Host smart-b9860595-5902-4c86-b98c-968d0c131f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2189841995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2189841995
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1212534889
Short name T1458
Test name
Test status
Simulation time 86106994 ps
CPU time 1.27 seconds
Started May 05 02:48:41 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203900 kb
Host smart-8ec1045d-4573-4df4-bb4c-01c5d17fae22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1212534889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1212534889
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3977247317
Short name T1448
Test name
Test status
Simulation time 209190216 ps
CPU time 2.85 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 204000 kb
Host smart-402abbc4-e199-4695-9b60-547f18a77d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3977247317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3977247317
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.165586244
Short name T284
Test name
Test status
Simulation time 724016822 ps
CPU time 4.9 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:45 PM PDT 24
Peak memory 204004 kb
Host smart-0d24c529-16df-40ef-b132-ee64efb9380f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=165586244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.165586244
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1327121278
Short name T1477
Test name
Test status
Simulation time 190278618 ps
CPU time 2.07 seconds
Started May 05 02:48:14 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 203864 kb
Host smart-0e31d9ab-d084-4478-8412-89b89380c15e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1327121278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1327121278
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1445756571
Short name T212
Test name
Test status
Simulation time 1382673442 ps
CPU time 9.08 seconds
Started May 05 02:48:19 PM PDT 24
Finished May 05 02:48:29 PM PDT 24
Peak memory 203920 kb
Host smart-a0d4297d-b55a-49a7-a5c0-7e54aa8b9d73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1445756571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1445756571
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1701758841
Short name T1417
Test name
Test status
Simulation time 169131710 ps
CPU time 1.27 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:19 PM PDT 24
Peak memory 212256 kb
Host smart-e63782cc-c443-42f2-9d86-0a1650018c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701758841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1701758841
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3515611501
Short name T260
Test name
Test status
Simulation time 36210179 ps
CPU time 1.01 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:18 PM PDT 24
Peak memory 203980 kb
Host smart-3c22af45-229a-4bcf-909d-20d1d65338e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3515611501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3515611501
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2363425129
Short name T1409
Test name
Test status
Simulation time 24260453 ps
CPU time 0.63 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:16 PM PDT 24
Peak memory 203220 kb
Host smart-55d46007-1c07-4fe9-b877-195fd4844ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363425129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2363425129
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.585481506
Short name T259
Test name
Test status
Simulation time 66693787 ps
CPU time 2.09 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:20 PM PDT 24
Peak memory 212112 kb
Host smart-ee288771-89a4-43d5-8b32-08f873bb42d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=585481506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.585481506
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.918695342
Short name T1383
Test name
Test status
Simulation time 179894164 ps
CPU time 3.82 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:19 PM PDT 24
Peak memory 203876 kb
Host smart-6c92df2b-b724-4d62-bb3d-1d90e0609917
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=918695342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.918695342
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.88792905
Short name T263
Test name
Test status
Simulation time 116927555 ps
CPU time 1.07 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:18 PM PDT 24
Peak memory 204016 kb
Host smart-49657eed-38d8-4c2a-92e4-cf7b37f879e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=88792905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.88792905
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.401307625
Short name T238
Test name
Test status
Simulation time 63715282 ps
CPU time 1.78 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 204004 kb
Host smart-4b4596fd-ddfb-4608-ab79-9b1cfc18d9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=401307625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.401307625
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1586684744
Short name T1478
Test name
Test status
Simulation time 650807809 ps
CPU time 4.46 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203956 kb
Host smart-0ac233b7-3c2a-480b-825b-9dc3f85118d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1586684744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1586684744
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1281578046
Short name T281
Test name
Test status
Simulation time 22844962 ps
CPU time 0.65 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:45 PM PDT 24
Peak memory 203212 kb
Host smart-27648ca6-826d-4a4e-a94b-99da4535d9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1281578046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1281578046
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2759010573
Short name T1397
Test name
Test status
Simulation time 34227455 ps
CPU time 0.67 seconds
Started May 05 02:48:45 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 203160 kb
Host smart-eb2c21f2-6fdb-40cc-b788-1f9e401d4941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2759010573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2759010573
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3096775707
Short name T1410
Test name
Test status
Simulation time 27530572 ps
CPU time 0.61 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:41 PM PDT 24
Peak memory 203188 kb
Host smart-4cd238e8-efef-454a-bfaa-5aadd514d532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3096775707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3096775707
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4272734904
Short name T1393
Test name
Test status
Simulation time 32581620 ps
CPU time 0.66 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:41 PM PDT 24
Peak memory 203252 kb
Host smart-f5b2069b-e527-4102-bbb3-5cee13ba316f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272734904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4272734904
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3809890163
Short name T1382
Test name
Test status
Simulation time 35231768 ps
CPU time 0.63 seconds
Started May 05 02:48:37 PM PDT 24
Finished May 05 02:48:38 PM PDT 24
Peak memory 203368 kb
Host smart-79661208-ee76-4baa-9dd8-c6b8f9721677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3809890163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3809890163
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4271962562
Short name T1436
Test name
Test status
Simulation time 71494974 ps
CPU time 0.67 seconds
Started May 05 02:48:41 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203072 kb
Host smart-fb526bd9-6c8d-4de9-85f4-8360d15cbe09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4271962562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4271962562
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2442801547
Short name T1392
Test name
Test status
Simulation time 28317015 ps
CPU time 0.66 seconds
Started May 05 02:48:37 PM PDT 24
Finished May 05 02:48:38 PM PDT 24
Peak memory 203280 kb
Host smart-9c4f8aca-740c-4911-87c0-0b9ff0d4aa63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2442801547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2442801547
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.943302945
Short name T1459
Test name
Test status
Simulation time 26232348 ps
CPU time 0.63 seconds
Started May 05 02:48:40 PM PDT 24
Finished May 05 02:48:42 PM PDT 24
Peak memory 203204 kb
Host smart-d7846902-b554-4459-833b-35bd1b4493f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=943302945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.943302945
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.974430293
Short name T1480
Test name
Test status
Simulation time 120332328 ps
CPU time 3.14 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:20 PM PDT 24
Peak memory 203856 kb
Host smart-ab385682-096c-4318-bae6-30c37031a4c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=974430293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.974430293
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.695024918
Short name T1449
Test name
Test status
Simulation time 1145818102 ps
CPU time 7.62 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 203876 kb
Host smart-6809aaf0-7f85-41f6-948c-ce2732aaae34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=695024918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.695024918
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3962753372
Short name T1401
Test name
Test status
Simulation time 134681017 ps
CPU time 0.88 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 203704 kb
Host smart-3fdffad8-96f0-4495-b483-9cd67b6754e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3962753372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3962753372
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.808753334
Short name T1407
Test name
Test status
Simulation time 151839901 ps
CPU time 1.77 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:29 PM PDT 24
Peak memory 212132 kb
Host smart-ec696735-2b80-400d-b6bd-866965464392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808753334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.808753334
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4236680268
Short name T261
Test name
Test status
Simulation time 62609874 ps
CPU time 0.77 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:17 PM PDT 24
Peak memory 203696 kb
Host smart-a94bce2d-a0fc-4229-93dd-b3dabfccee9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4236680268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4236680268
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.412872379
Short name T277
Test name
Test status
Simulation time 54888846 ps
CPU time 0.64 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 203216 kb
Host smart-8d7bbb07-b692-4d22-9e6d-64ceaefce20d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=412872379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.412872379
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.408910075
Short name T253
Test name
Test status
Simulation time 157241107 ps
CPU time 2.39 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:21 PM PDT 24
Peak memory 212168 kb
Host smart-c498acaf-eccb-465c-8a78-e632b05b87a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=408910075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.408910075
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.23034235
Short name T1457
Test name
Test status
Simulation time 600053439 ps
CPU time 4.27 seconds
Started May 05 02:48:16 PM PDT 24
Finished May 05 02:48:21 PM PDT 24
Peak memory 203876 kb
Host smart-c0772c72-3679-4fe3-929f-12a6dc50e15f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=23034235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.23034235
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.712825163
Short name T1390
Test name
Test status
Simulation time 196288585 ps
CPU time 1.68 seconds
Started May 05 02:48:29 PM PDT 24
Finished May 05 02:48:32 PM PDT 24
Peak memory 204000 kb
Host smart-dc9c2a8d-21b3-4c06-9b7e-c41868503fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=712825163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.712825163
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.58919036
Short name T1464
Test name
Test status
Simulation time 81194914 ps
CPU time 1.97 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:21 PM PDT 24
Peak memory 204000 kb
Host smart-2d5eebbc-e09d-49a7-bf27-de77830c46dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58919036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.58919036
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.884590259
Short name T1429
Test name
Test status
Simulation time 196582103 ps
CPU time 2.41 seconds
Started May 05 02:48:15 PM PDT 24
Finished May 05 02:48:18 PM PDT 24
Peak memory 203996 kb
Host smart-86dcd9d0-8c5b-45dc-8cf4-86cbabe41704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=884590259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.884590259
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1953621492
Short name T279
Test name
Test status
Simulation time 68346834 ps
CPU time 0.65 seconds
Started May 05 02:48:39 PM PDT 24
Finished May 05 02:48:40 PM PDT 24
Peak memory 203220 kb
Host smart-30ed0a6b-8d3a-4154-8de1-584fc2cd3ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1953621492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1953621492
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4169866115
Short name T1439
Test name
Test status
Simulation time 29962922 ps
CPU time 0.66 seconds
Started May 05 02:48:45 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 203292 kb
Host smart-c87f7ab7-67f2-4d11-a898-30fcff1d394b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4169866115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4169866115
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3868809297
Short name T1433
Test name
Test status
Simulation time 29673772 ps
CPU time 0.67 seconds
Started May 05 02:48:42 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 203236 kb
Host smart-6b964581-23a6-4554-96ab-07fed9ec0c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3868809297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3868809297
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1426117201
Short name T1412
Test name
Test status
Simulation time 28965753 ps
CPU time 0.62 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:46 PM PDT 24
Peak memory 203284 kb
Host smart-cff01f0c-5f76-41ce-8bfb-2635b2a90393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1426117201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1426117201
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1142986186
Short name T1435
Test name
Test status
Simulation time 35893428 ps
CPU time 0.63 seconds
Started May 05 02:48:45 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 203072 kb
Host smart-b5930e9b-8a90-4fa7-9358-e8e670e7f0f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1142986186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1142986186
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3186888567
Short name T274
Test name
Test status
Simulation time 28384302 ps
CPU time 0.62 seconds
Started May 05 02:48:45 PM PDT 24
Finished May 05 02:48:47 PM PDT 24
Peak memory 203176 kb
Host smart-d54146dd-a836-4d11-8fef-9be2923db3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3186888567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3186888567
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1784453890
Short name T1400
Test name
Test status
Simulation time 32035261 ps
CPU time 0.65 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:45 PM PDT 24
Peak memory 203176 kb
Host smart-117d2913-dc0f-4cdf-99d3-608fd10dc796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1784453890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1784453890
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2784049336
Short name T1442
Test name
Test status
Simulation time 34695345 ps
CPU time 0.69 seconds
Started May 05 02:48:33 PM PDT 24
Finished May 05 02:48:34 PM PDT 24
Peak memory 203268 kb
Host smart-b4d222c3-6687-4612-a08c-c5bc89aca69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2784049336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2784049336
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.463768491
Short name T278
Test name
Test status
Simulation time 36971031 ps
CPU time 0.67 seconds
Started May 05 02:48:32 PM PDT 24
Finished May 05 02:48:33 PM PDT 24
Peak memory 203220 kb
Host smart-0bd409fa-c187-49b8-a924-3f4b29509cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=463768491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.463768491
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1172108234
Short name T1438
Test name
Test status
Simulation time 388258560 ps
CPU time 3.68 seconds
Started May 05 02:48:17 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203960 kb
Host smart-f2f1925a-9f57-42f2-92fd-83ff9a3378c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1172108234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1172108234
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2985364508
Short name T1445
Test name
Test status
Simulation time 244384019 ps
CPU time 4.21 seconds
Started May 05 02:48:19 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 203900 kb
Host smart-9b1947d1-b3b9-4677-bf87-c83d8499c210
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2985364508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2985364508
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3966967574
Short name T68
Test name
Test status
Simulation time 71010856 ps
CPU time 0.91 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:29 PM PDT 24
Peak memory 203560 kb
Host smart-df2c9c41-ec86-4f28-a041-21220c8554bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3966967574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3966967574
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3847543296
Short name T1469
Test name
Test status
Simulation time 57573696 ps
CPU time 1.46 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:30 PM PDT 24
Peak memory 212132 kb
Host smart-0240be6e-faa8-4f24-b7a0-0e668c6b2bf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847543296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3847543296
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.847059139
Short name T1402
Test name
Test status
Simulation time 32656131 ps
CPU time 0.78 seconds
Started May 05 02:48:20 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203756 kb
Host smart-8c1acd7d-ad1a-4607-9805-b30d80f1db4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=847059139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.847059139
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2021043990
Short name T1432
Test name
Test status
Simulation time 38412558 ps
CPU time 0.67 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 203064 kb
Host smart-84622ca8-6c90-4850-bcf3-c86c06d59624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2021043990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2021043990
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1060275330
Short name T1473
Test name
Test status
Simulation time 176743942 ps
CPU time 2.28 seconds
Started May 05 02:48:19 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 212188 kb
Host smart-2b098070-b4ff-4ced-9f7c-9511b5988c76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1060275330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1060275330
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1199823361
Short name T1408
Test name
Test status
Simulation time 179519631 ps
CPU time 3.71 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:23 PM PDT 24
Peak memory 203928 kb
Host smart-b0571aa6-9ff3-4141-b0d7-4d7968e0fec1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1199823361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1199823361
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3891049845
Short name T269
Test name
Test status
Simulation time 166301987 ps
CPU time 1.58 seconds
Started May 05 02:48:22 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 203912 kb
Host smart-6b616a49-b5f6-41bf-ade1-bbee3eb776b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3891049845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3891049845
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2121775615
Short name T1450
Test name
Test status
Simulation time 206781740 ps
CPU time 2.29 seconds
Started May 05 02:48:21 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 203996 kb
Host smart-d40a1bbb-933f-449a-8a72-b6fad1d9a191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2121775615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2121775615
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2991329249
Short name T1416
Test name
Test status
Simulation time 65371054 ps
CPU time 0.72 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:46 PM PDT 24
Peak memory 203216 kb
Host smart-cbbc5fab-c50c-40e9-b2e4-608f651b53ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2991329249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2991329249
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.462030497
Short name T273
Test name
Test status
Simulation time 50522229 ps
CPU time 0.69 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:46 PM PDT 24
Peak memory 203248 kb
Host smart-6c03d3da-fee3-48b2-9de9-5acbcb82b401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=462030497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.462030497
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1216868204
Short name T1437
Test name
Test status
Simulation time 44475946 ps
CPU time 0.69 seconds
Started May 05 02:48:48 PM PDT 24
Finished May 05 02:48:49 PM PDT 24
Peak memory 203300 kb
Host smart-4e229e22-0212-4212-8a80-b5c0c9546b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1216868204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1216868204
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3641027502
Short name T1468
Test name
Test status
Simulation time 23625102 ps
CPU time 0.62 seconds
Started May 05 02:48:46 PM PDT 24
Finished May 05 02:48:48 PM PDT 24
Peak memory 203320 kb
Host smart-21b7f898-bbc7-4e6f-a253-a0ec331840f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3641027502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3641027502
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2175708044
Short name T73
Test name
Test status
Simulation time 32279714 ps
CPU time 0.67 seconds
Started May 05 02:48:47 PM PDT 24
Finished May 05 02:48:48 PM PDT 24
Peak memory 203260 kb
Host smart-b9a1bcbc-ba8c-4a9b-9310-292afcf2d4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2175708044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2175708044
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1859383589
Short name T1414
Test name
Test status
Simulation time 28710106 ps
CPU time 0.64 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:45 PM PDT 24
Peak memory 203228 kb
Host smart-445eeb04-e32c-4598-8856-42ce2b327104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1859383589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1859383589
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3778313720
Short name T1396
Test name
Test status
Simulation time 41213772 ps
CPU time 0.7 seconds
Started May 05 02:48:43 PM PDT 24
Finished May 05 02:48:44 PM PDT 24
Peak memory 203292 kb
Host smart-e06c1c47-4d8d-4f25-adbf-ed51a1aae2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3778313720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3778313720
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2963831605
Short name T275
Test name
Test status
Simulation time 39451203 ps
CPU time 0.66 seconds
Started May 05 02:48:48 PM PDT 24
Finished May 05 02:48:49 PM PDT 24
Peak memory 203212 kb
Host smart-12e0e283-fa71-4b17-8500-f9571c449ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2963831605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2963831605
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3653125571
Short name T1391
Test name
Test status
Simulation time 27941605 ps
CPU time 0.64 seconds
Started May 05 02:48:44 PM PDT 24
Finished May 05 02:48:46 PM PDT 24
Peak memory 203288 kb
Host smart-d2b27573-b50f-4eda-85ab-2ed003b553ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3653125571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3653125571
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4034437318
Short name T1381
Test name
Test status
Simulation time 72989468 ps
CPU time 0.71 seconds
Started May 05 02:48:41 PM PDT 24
Finished May 05 02:48:43 PM PDT 24
Peak memory 203236 kb
Host smart-7bae6d30-fdc0-475e-aaa6-818d7bbefc18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4034437318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4034437318
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2295122328
Short name T1398
Test name
Test status
Simulation time 84218505 ps
CPU time 2.18 seconds
Started May 05 02:48:23 PM PDT 24
Finished May 05 02:48:25 PM PDT 24
Peak memory 212236 kb
Host smart-048aa69d-79f3-4335-8777-65781ec2e7c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295122328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2295122328
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3823318697
Short name T1419
Test name
Test status
Simulation time 42191831 ps
CPU time 0.84 seconds
Started May 05 02:48:20 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203760 kb
Host smart-244554a6-f76a-4ac2-993b-0f9071099db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3823318697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3823318697
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4186348496
Short name T1465
Test name
Test status
Simulation time 36550157 ps
CPU time 0.64 seconds
Started May 05 02:48:21 PM PDT 24
Finished May 05 02:48:27 PM PDT 24
Peak memory 203252 kb
Host smart-9229c1a6-322d-4bfd-9dac-9b48a5e96a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4186348496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.4186348496
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3311521435
Short name T1479
Test name
Test status
Simulation time 191081249 ps
CPU time 1.78 seconds
Started May 05 02:48:21 PM PDT 24
Finished May 05 02:48:23 PM PDT 24
Peak memory 204016 kb
Host smart-98d17b8e-f779-4890-9456-ca1ccc02d9f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3311521435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3311521435
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.480290556
Short name T236
Test name
Test status
Simulation time 258199314 ps
CPU time 2.9 seconds
Started May 05 02:48:23 PM PDT 24
Finished May 05 02:48:27 PM PDT 24
Peak memory 204028 kb
Host smart-6ca9dea1-0b69-4ca5-8de5-518649bd5ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=480290556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.480290556
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1072435791
Short name T287
Test name
Test status
Simulation time 1804983263 ps
CPU time 6.09 seconds
Started May 05 02:48:19 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 204032 kb
Host smart-5065dde9-3a3e-448e-8d17-3107d3e9e5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1072435791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1072435791
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.46257075
Short name T1460
Test name
Test status
Simulation time 66493998 ps
CPU time 1.84 seconds
Started May 05 02:48:22 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 212196 kb
Host smart-8e4ad37f-72b1-4717-9098-74268104adda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46257075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_
csr_mem_rw_with_rand_reset.46257075
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1941001609
Short name T97
Test name
Test status
Simulation time 63662983 ps
CPU time 1.05 seconds
Started May 05 02:48:21 PM PDT 24
Finished May 05 02:48:23 PM PDT 24
Peak memory 203932 kb
Host smart-e865660d-2472-4076-b327-47359f46f413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1941001609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1941001609
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3460032098
Short name T1452
Test name
Test status
Simulation time 32660234 ps
CPU time 0.71 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 203244 kb
Host smart-7d282f8d-9ead-403c-8c60-8efd7eea3f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3460032098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3460032098
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.300088594
Short name T1463
Test name
Test status
Simulation time 74731078 ps
CPU time 1.11 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:20 PM PDT 24
Peak memory 203972 kb
Host smart-ab4fefc4-577a-4765-8441-b91f59612c6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300088594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.300088594
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3070099078
Short name T1467
Test name
Test status
Simulation time 94038181 ps
CPU time 2.65 seconds
Started May 05 02:48:19 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 212204 kb
Host smart-825176aa-a128-4bc4-9fd1-59e7c89da5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3070099078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3070099078
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.126356979
Short name T214
Test name
Test status
Simulation time 448298939 ps
CPU time 4.16 seconds
Started May 05 02:48:20 PM PDT 24
Finished May 05 02:48:25 PM PDT 24
Peak memory 203984 kb
Host smart-81e2635a-2a1b-477c-8f41-09a0bb4777f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=126356979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.126356979
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1742783660
Short name T1462
Test name
Test status
Simulation time 233912809 ps
CPU time 1.28 seconds
Started May 05 02:48:22 PM PDT 24
Finished May 05 02:48:24 PM PDT 24
Peak memory 212200 kb
Host smart-ed826169-ebeb-45bf-b8c9-659471b7600c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742783660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1742783660
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4019251437
Short name T1380
Test name
Test status
Simulation time 33906067 ps
CPU time 0.64 seconds
Started May 05 02:48:20 PM PDT 24
Finished May 05 02:48:21 PM PDT 24
Peak memory 203172 kb
Host smart-21a76922-5b91-455a-8462-f4042914bf81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4019251437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4019251437
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1259132650
Short name T1385
Test name
Test status
Simulation time 103707898 ps
CPU time 1.57 seconds
Started May 05 02:48:20 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 203980 kb
Host smart-7b018426-0bf9-4a86-8575-885cf1081eae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1259132650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1259132650
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3073740400
Short name T1421
Test name
Test status
Simulation time 115205820 ps
CPU time 3.68 seconds
Started May 05 02:48:28 PM PDT 24
Finished May 05 02:48:33 PM PDT 24
Peak memory 204024 kb
Host smart-a4f14c58-50c6-4f0e-b4ae-09b498a4d82f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3073740400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3073740400
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1936069793
Short name T285
Test name
Test status
Simulation time 465021197 ps
CPU time 4.23 seconds
Started May 05 02:48:31 PM PDT 24
Finished May 05 02:48:36 PM PDT 24
Peak memory 203804 kb
Host smart-d195562f-cedb-4d10-b389-e7aefa333670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1936069793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1936069793
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.487990212
Short name T1431
Test name
Test status
Simulation time 73112185 ps
CPU time 1.11 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 212236 kb
Host smart-bfaf1938-8340-4548-8297-c902760d7152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487990212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.487990212
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2367741937
Short name T1411
Test name
Test status
Simulation time 32749158 ps
CPU time 0.81 seconds
Started May 05 02:48:30 PM PDT 24
Finished May 05 02:48:32 PM PDT 24
Peak memory 203760 kb
Host smart-d0490482-91b6-408d-a73c-f9b9f5eaaeab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2367741937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2367741937
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3350698308
Short name T280
Test name
Test status
Simulation time 37923485 ps
CPU time 0.65 seconds
Started May 05 02:48:19 PM PDT 24
Finished May 05 02:48:20 PM PDT 24
Peak memory 203276 kb
Host smart-eb460e6c-1c50-4a37-9f65-fe195d641194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3350698308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3350698308
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.495997652
Short name T99
Test name
Test status
Simulation time 106616423 ps
CPU time 1.12 seconds
Started May 05 02:48:27 PM PDT 24
Finished May 05 02:48:29 PM PDT 24
Peak memory 204152 kb
Host smart-81f338b1-0668-4136-bead-20c8f29f35e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=495997652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.495997652
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2710595274
Short name T237
Test name
Test status
Simulation time 152681377 ps
CPU time 3.18 seconds
Started May 05 02:48:18 PM PDT 24
Finished May 05 02:48:22 PM PDT 24
Peak memory 204052 kb
Host smart-7d908781-1358-4e6b-a028-99865360e9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2710595274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2710595274
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3950669618
Short name T1426
Test name
Test status
Simulation time 833754841 ps
CPU time 2.98 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:30 PM PDT 24
Peak memory 203860 kb
Host smart-a81edb79-e91c-48ea-8614-face16a2432d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3950669618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3950669618
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1394856460
Short name T1443
Test name
Test status
Simulation time 168161795 ps
CPU time 1.76 seconds
Started May 05 02:48:26 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 215980 kb
Host smart-f4ce0be1-7d0f-4867-bc25-3d95db88ac8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394856460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1394856460
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2400957002
Short name T265
Test name
Test status
Simulation time 41556966 ps
CPU time 0.78 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:26 PM PDT 24
Peak memory 203680 kb
Host smart-0b2a690d-75f4-4114-af60-240a5cae69f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2400957002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2400957002
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.207362301
Short name T1444
Test name
Test status
Simulation time 86532545 ps
CPU time 0.7 seconds
Started May 05 02:48:32 PM PDT 24
Finished May 05 02:48:33 PM PDT 24
Peak memory 203188 kb
Host smart-b420b9a1-fef4-4b67-bc56-f3c4786839d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=207362301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.207362301
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.385906742
Short name T1427
Test name
Test status
Simulation time 211388729 ps
CPU time 1.44 seconds
Started May 05 02:48:25 PM PDT 24
Finished May 05 02:48:27 PM PDT 24
Peak memory 203968 kb
Host smart-3b63d343-0cd1-4d65-bff6-5e476a628ac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=385906742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.385906742
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1157829278
Short name T208
Test name
Test status
Simulation time 291361396 ps
CPU time 3.28 seconds
Started May 05 02:48:24 PM PDT 24
Finished May 05 02:48:28 PM PDT 24
Peak memory 204112 kb
Host smart-6eb73a64-52ce-49dd-8ac1-fde8f9d0ba72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1157829278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1157829278
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3232192846
Short name T283
Test name
Test status
Simulation time 561537561 ps
CPU time 4.72 seconds
Started May 05 02:48:24 PM PDT 24
Finished May 05 02:48:29 PM PDT 24
Peak memory 204020 kb
Host smart-e559c310-c904-4c18-99f9-5a54c09f8659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3232192846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3232192846
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.1888935843
Short name T311
Test name
Test status
Simulation time 8480977791 ps
CPU time 8.06 seconds
Started May 05 03:11:05 PM PDT 24
Finished May 05 03:11:13 PM PDT 24
Peak memory 204116 kb
Host smart-72934629-520b-44c6-b04c-58cae3a29494
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1888935843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.1888935843
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2355356484
Short name T37
Test name
Test status
Simulation time 8402980200 ps
CPU time 9.9 seconds
Started May 05 03:11:03 PM PDT 24
Finished May 05 03:11:13 PM PDT 24
Peak memory 204284 kb
Host smart-a5c48a26-de11-40b6-b59e-8dc6b925f935
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2355356484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2355356484
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.568418191
Short name T495
Test name
Test status
Simulation time 8449226023 ps
CPU time 7.93 seconds
Started May 05 03:10:58 PM PDT 24
Finished May 05 03:11:07 PM PDT 24
Peak memory 204140 kb
Host smart-46687d96-65b9-49a3-ad1a-ac415cd8481e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56841
8191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.568418191
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2947482213
Short name T937
Test name
Test status
Simulation time 8381916492 ps
CPU time 10.24 seconds
Started May 05 03:10:38 PM PDT 24
Finished May 05 03:10:49 PM PDT 24
Peak memory 204132 kb
Host smart-8fb2c391-12b6-43ba-85d8-93c6571753e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
82213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2947482213
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.2480429869
Short name T985
Test name
Test status
Simulation time 8387477314 ps
CPU time 8.93 seconds
Started May 05 03:10:39 PM PDT 24
Finished May 05 03:10:48 PM PDT 24
Peak memory 204080 kb
Host smart-c8b864e5-21ac-4a95-917f-7840d85174bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24804
29869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2480429869
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1301787349
Short name T852
Test name
Test status
Simulation time 71498867 ps
CPU time 1.88 seconds
Started May 05 03:10:41 PM PDT 24
Finished May 05 03:10:43 PM PDT 24
Peak memory 204180 kb
Host smart-bfa547d2-1752-4418-b33b-1723d4e708dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017
87349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1301787349
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2217580793
Short name T958
Test name
Test status
Simulation time 8435309493 ps
CPU time 7.8 seconds
Started May 05 03:10:58 PM PDT 24
Finished May 05 03:11:06 PM PDT 24
Peak memory 204116 kb
Host smart-33686642-4dd8-40be-8d94-a50dfacc3ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
80793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2217580793
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3844525789
Short name T1040
Test name
Test status
Simulation time 8465373067 ps
CPU time 8.65 seconds
Started May 05 03:10:40 PM PDT 24
Finished May 05 03:10:49 PM PDT 24
Peak memory 204060 kb
Host smart-9b443956-91be-4f08-8166-5b078eb5ef5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445
25789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3844525789
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2046789533
Short name T654
Test name
Test status
Simulation time 8459833134 ps
CPU time 8.65 seconds
Started May 05 03:10:46 PM PDT 24
Finished May 05 03:10:55 PM PDT 24
Peak memory 204100 kb
Host smart-9fa214fd-2661-4bf3-88d3-507f353cf141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
89533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2046789533
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2104584427
Short name T1078
Test name
Test status
Simulation time 8368532556 ps
CPU time 7.41 seconds
Started May 05 03:10:44 PM PDT 24
Finished May 05 03:10:52 PM PDT 24
Peak memory 204088 kb
Host smart-b290648b-4633-4172-9ee6-541d8998abfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
84427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2104584427
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1476122078
Short name T421
Test name
Test status
Simulation time 8394898094 ps
CPU time 10.58 seconds
Started May 05 03:10:47 PM PDT 24
Finished May 05 03:10:58 PM PDT 24
Peak memory 204128 kb
Host smart-25033416-54ee-4c27-9da4-5402293d5a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761
22078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1476122078
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3634265917
Short name T752
Test name
Test status
Simulation time 8405906826 ps
CPU time 7.54 seconds
Started May 05 03:10:51 PM PDT 24
Finished May 05 03:10:59 PM PDT 24
Peak memory 204140 kb
Host smart-8c6d8f9e-1f22-41cb-b9c9-03f736810525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36342
65917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3634265917
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.891849748
Short name T1252
Test name
Test status
Simulation time 8379006513 ps
CPU time 9.15 seconds
Started May 05 03:10:59 PM PDT 24
Finished May 05 03:11:09 PM PDT 24
Peak memory 204100 kb
Host smart-1aee63c9-642e-4cb7-9980-96b99fce12ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89184
9748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.891849748
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.378112696
Short name T231
Test name
Test status
Simulation time 19174264322 ps
CPU time 38.31 seconds
Started May 05 03:10:51 PM PDT 24
Finished May 05 03:11:30 PM PDT 24
Peak memory 204348 kb
Host smart-20b67c98-408c-4238-8c34-18d59190be86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
2696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.378112696
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.4140280965
Short name T708
Test name
Test status
Simulation time 8387030094 ps
CPU time 7.48 seconds
Started May 05 03:10:51 PM PDT 24
Finished May 05 03:10:59 PM PDT 24
Peak memory 204124 kb
Host smart-7244c07c-ddbb-443d-9a90-0602c32ecd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
80965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.4140280965
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1717685868
Short name T1099
Test name
Test status
Simulation time 8434697748 ps
CPU time 8.03 seconds
Started May 05 03:10:50 PM PDT 24
Finished May 05 03:10:58 PM PDT 24
Peak memory 204056 kb
Host smart-7c677058-0276-41aa-b904-1f7229b93d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17176
85868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1717685868
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3519304032
Short name T396
Test name
Test status
Simulation time 8399482865 ps
CPU time 9.87 seconds
Started May 05 03:10:55 PM PDT 24
Finished May 05 03:11:05 PM PDT 24
Peak memory 204132 kb
Host smart-b7a766c5-3f61-4db2-a091-5016a0d77df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35193
04032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3519304032
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2159671320
Short name T78
Test name
Test status
Simulation time 379097099 ps
CPU time 1.32 seconds
Started May 05 03:11:09 PM PDT 24
Finished May 05 03:11:11 PM PDT 24
Peak memory 220316 kb
Host smart-8e9a4c19-da00-4bac-918e-e1b8a1aede08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2159671320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2159671320
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1753372323
Short name T175
Test name
Test status
Simulation time 8389067053 ps
CPU time 7.86 seconds
Started May 05 03:10:59 PM PDT 24
Finished May 05 03:11:07 PM PDT 24
Peak memory 204068 kb
Host smart-9bdb5b78-346d-4a00-bb82-44f8e28260c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
72323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1753372323
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.4286409342
Short name T699
Test name
Test status
Simulation time 8400467390 ps
CPU time 9.4 seconds
Started May 05 03:10:55 PM PDT 24
Finished May 05 03:11:05 PM PDT 24
Peak memory 204096 kb
Host smart-aca8aae2-0137-4080-a7be-74941f0b7ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
09342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.4286409342
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2630256355
Short name T304
Test name
Test status
Simulation time 8389313385 ps
CPU time 8.01 seconds
Started May 05 03:10:54 PM PDT 24
Finished May 05 03:11:02 PM PDT 24
Peak memory 204068 kb
Host smart-7562e158-c7c1-4fbf-b100-fb72176c8fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26302
56355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2630256355
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.2622745869
Short name T383
Test name
Test status
Simulation time 8489667182 ps
CPU time 8.31 seconds
Started May 05 03:11:32 PM PDT 24
Finished May 05 03:11:41 PM PDT 24
Peak memory 204132 kb
Host smart-b149ead1-9a1b-4064-8f3d-69aa58afbaaf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2622745869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.2622745869
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.1334429983
Short name T1367
Test name
Test status
Simulation time 8375554456 ps
CPU time 7.49 seconds
Started May 05 03:11:33 PM PDT 24
Finished May 05 03:11:41 PM PDT 24
Peak memory 204116 kb
Host smart-b225b34a-9e75-4e6d-9ba4-c6665507572a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1334429983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.1334429983
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.4102592719
Short name T685
Test name
Test status
Simulation time 8467672788 ps
CPU time 7.84 seconds
Started May 05 03:11:33 PM PDT 24
Finished May 05 03:11:41 PM PDT 24
Peak memory 204132 kb
Host smart-12a27aaf-4980-4e80-b056-956a1cd96d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025
92719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.4102592719
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1892671736
Short name T1079
Test name
Test status
Simulation time 8377372732 ps
CPU time 7.83 seconds
Started May 05 03:11:12 PM PDT 24
Finished May 05 03:11:20 PM PDT 24
Peak memory 204080 kb
Host smart-3c89b355-a8fd-4b8f-8420-d6fa73a17d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
71736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1892671736
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.3313547320
Short name T719
Test name
Test status
Simulation time 8376718577 ps
CPU time 8.94 seconds
Started May 05 03:11:17 PM PDT 24
Finished May 05 03:11:26 PM PDT 24
Peak memory 204116 kb
Host smart-5ecb0236-fa49-419e-b15e-5216b28b3ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135
47320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3313547320
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1827306462
Short name T358
Test name
Test status
Simulation time 224438097 ps
CPU time 2.22 seconds
Started May 05 03:11:18 PM PDT 24
Finished May 05 03:11:21 PM PDT 24
Peak memory 204264 kb
Host smart-3c155a5e-fdcd-4d48-bccd-3424a5af5c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18273
06462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1827306462
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.74757222
Short name T1239
Test name
Test status
Simulation time 8490905830 ps
CPU time 8.42 seconds
Started May 05 03:11:31 PM PDT 24
Finished May 05 03:11:40 PM PDT 24
Peak memory 204088 kb
Host smart-d70c216a-33c2-45ad-bad4-41ef48266357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74757
222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.74757222
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4041820724
Short name T189
Test name
Test status
Simulation time 8369960142 ps
CPU time 7.71 seconds
Started May 05 03:11:31 PM PDT 24
Finished May 05 03:11:39 PM PDT 24
Peak memory 204076 kb
Host smart-14bdfda6-c226-4c98-ad72-ccc1634c3645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
20724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4041820724
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1462767043
Short name T691
Test name
Test status
Simulation time 8459676367 ps
CPU time 9.39 seconds
Started May 05 03:11:19 PM PDT 24
Finished May 05 03:11:29 PM PDT 24
Peak memory 204112 kb
Host smart-e283734a-8868-4144-8828-51ec42a61c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14627
67043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1462767043
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1492711353
Short name T1103
Test name
Test status
Simulation time 8421854676 ps
CPU time 9.97 seconds
Started May 05 03:11:19 PM PDT 24
Finished May 05 03:11:29 PM PDT 24
Peak memory 204084 kb
Host smart-6b9907e4-3140-4e49-a8d6-cf4d8d253519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
11353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1492711353
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2349983321
Short name T1017
Test name
Test status
Simulation time 8401172136 ps
CPU time 8.07 seconds
Started May 05 03:11:19 PM PDT 24
Finished May 05 03:11:27 PM PDT 24
Peak memory 204284 kb
Host smart-775a0313-e455-4317-8235-fe4f0341ad57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499
83321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2349983321
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1452896919
Short name T755
Test name
Test status
Simulation time 8425394777 ps
CPU time 8.51 seconds
Started May 05 03:11:24 PM PDT 24
Finished May 05 03:11:33 PM PDT 24
Peak memory 204108 kb
Host smart-bec3688e-9cf6-4492-a716-69af9adef7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
96919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1452896919
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2497654256
Short name T1020
Test name
Test status
Simulation time 8466707311 ps
CPU time 7.92 seconds
Started May 05 03:11:23 PM PDT 24
Finished May 05 03:11:31 PM PDT 24
Peak memory 204064 kb
Host smart-f189ce01-b72f-4869-bbce-2061ca6738fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
54256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2497654256
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.553012029
Short name T1137
Test name
Test status
Simulation time 8370996820 ps
CPU time 7.15 seconds
Started May 05 03:11:29 PM PDT 24
Finished May 05 03:11:37 PM PDT 24
Peak memory 204132 kb
Host smart-c0b24c3d-fdc4-4c2e-b7c6-1b1bb8a3c502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55301
2029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.553012029
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2143932604
Short name T637
Test name
Test status
Simulation time 48933167 ps
CPU time 0.66 seconds
Started May 05 03:11:27 PM PDT 24
Finished May 05 03:11:28 PM PDT 24
Peak memory 203960 kb
Host smart-a27e0421-87d9-47b5-8244-e7fa3d6a8559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21439
32604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2143932604
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3618453751
Short name T947
Test name
Test status
Simulation time 24284874408 ps
CPU time 46.08 seconds
Started May 05 03:11:21 PM PDT 24
Finished May 05 03:12:08 PM PDT 24
Peak memory 204364 kb
Host smart-3de879f2-a325-4767-8e41-5d806789c00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36184
53751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3618453751
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3115177843
Short name T1032
Test name
Test status
Simulation time 8398488372 ps
CPU time 10.01 seconds
Started May 05 03:11:23 PM PDT 24
Finished May 05 03:11:33 PM PDT 24
Peak memory 204080 kb
Host smart-731d12a2-6823-4ff8-b053-affc9df769a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151
77843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3115177843
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1283263107
Short name T753
Test name
Test status
Simulation time 8486451928 ps
CPU time 10.22 seconds
Started May 05 03:11:24 PM PDT 24
Finished May 05 03:11:34 PM PDT 24
Peak memory 204056 kb
Host smart-fa7653dc-62d7-427d-b708-bc6dbc3b512b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
63107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1283263107
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.619079213
Short name T77
Test name
Test status
Simulation time 570564276 ps
CPU time 1.42 seconds
Started May 05 03:11:35 PM PDT 24
Finished May 05 03:11:37 PM PDT 24
Peak memory 221408 kb
Host smart-a59b53f9-428e-46ea-9d47-56c90cd4f461
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=619079213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.619079213
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4021399606
Short name T171
Test name
Test status
Simulation time 8412982343 ps
CPU time 8.61 seconds
Started May 05 03:11:29 PM PDT 24
Finished May 05 03:11:39 PM PDT 24
Peak memory 204100 kb
Host smart-6eaa9b22-80f4-4c2d-84bf-7d32263dd2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40213
99606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4021399606
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3210069273
Short name T1146
Test name
Test status
Simulation time 8370342556 ps
CPU time 8.99 seconds
Started May 05 03:11:26 PM PDT 24
Finished May 05 03:11:35 PM PDT 24
Peak memory 204128 kb
Host smart-939b835d-1af2-4a9a-a863-6c6074046211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
69273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3210069273
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1519690658
Short name T409
Test name
Test status
Simulation time 8394453970 ps
CPU time 8.14 seconds
Started May 05 03:11:28 PM PDT 24
Finished May 05 03:11:36 PM PDT 24
Peak memory 204064 kb
Host smart-cdc641e1-063d-4f66-815b-10d4baf14da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196
90658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1519690658
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.2254985070
Short name T865
Test name
Test status
Simulation time 8460226738 ps
CPU time 8.98 seconds
Started May 05 03:13:29 PM PDT 24
Finished May 05 03:13:38 PM PDT 24
Peak memory 204096 kb
Host smart-bae51f91-ca07-494f-bbdb-0dcd7da72502
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2254985070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.2254985070
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.3188724687
Short name T784
Test name
Test status
Simulation time 8393545454 ps
CPU time 8 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:37 PM PDT 24
Peak memory 204080 kb
Host smart-aaa195fd-c751-4b0e-aed8-23507d00a299
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3188724687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3188724687
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2902769701
Short name T982
Test name
Test status
Simulation time 8420508004 ps
CPU time 7.66 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:36 PM PDT 24
Peak memory 204092 kb
Host smart-54890468-7671-4c4a-baf3-5ad677793e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29027
69701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2902769701
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.686639738
Short name T995
Test name
Test status
Simulation time 8378207403 ps
CPU time 9.66 seconds
Started May 05 03:13:18 PM PDT 24
Finished May 05 03:13:28 PM PDT 24
Peak memory 204164 kb
Host smart-a5475e87-dafd-4c2a-b09c-73c697fc7580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68663
9738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.686639738
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.1561248057
Short name T921
Test name
Test status
Simulation time 8374083316 ps
CPU time 7.42 seconds
Started May 05 03:13:18 PM PDT 24
Finished May 05 03:13:26 PM PDT 24
Peak memory 204056 kb
Host smart-bd3c031f-369d-45b1-8141-bafdff7c84e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15612
48057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1561248057
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3986504374
Short name T1160
Test name
Test status
Simulation time 210079472 ps
CPU time 2.09 seconds
Started May 05 03:13:17 PM PDT 24
Finished May 05 03:13:19 PM PDT 24
Peak memory 204140 kb
Host smart-0e60794e-3f7c-43cd-8d03-c0a8ad0af029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39865
04374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3986504374
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.991013857
Short name T432
Test name
Test status
Simulation time 8447039649 ps
CPU time 10.51 seconds
Started May 05 03:13:29 PM PDT 24
Finished May 05 03:13:40 PM PDT 24
Peak memory 204112 kb
Host smart-986c4d74-dfd2-43c5-bcb1-2f929b5cbc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99101
3857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.991013857
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.868901644
Short name T750
Test name
Test status
Simulation time 8367952336 ps
CPU time 8.47 seconds
Started May 05 03:13:23 PM PDT 24
Finished May 05 03:13:31 PM PDT 24
Peak memory 204056 kb
Host smart-8dd30767-de91-4f5b-a3ea-360f5c118fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86890
1644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.868901644
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3453882751
Short name T1057
Test name
Test status
Simulation time 8482699461 ps
CPU time 10.38 seconds
Started May 05 03:13:17 PM PDT 24
Finished May 05 03:13:28 PM PDT 24
Peak memory 204132 kb
Host smart-d1bb2331-635d-493d-8472-97b032a8f2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
82751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3453882751
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2088926599
Short name T496
Test name
Test status
Simulation time 8417045821 ps
CPU time 10.19 seconds
Started May 05 03:13:20 PM PDT 24
Finished May 05 03:13:31 PM PDT 24
Peak memory 204096 kb
Host smart-44062eec-142c-4f12-8743-d5a4a7653c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20889
26599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2088926599
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3039137386
Short name T1022
Test name
Test status
Simulation time 8386749738 ps
CPU time 7.77 seconds
Started May 05 03:13:16 PM PDT 24
Finished May 05 03:13:24 PM PDT 24
Peak memory 204124 kb
Host smart-480764f7-3b9c-40a6-9e4b-a49f69715d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30391
37386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3039137386
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1649146209
Short name T946
Test name
Test status
Simulation time 8417883712 ps
CPU time 8.8 seconds
Started May 05 03:13:17 PM PDT 24
Finished May 05 03:13:26 PM PDT 24
Peak memory 204132 kb
Host smart-fb5ae362-cff5-492a-ae08-549f1f8f5c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16491
46209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1649146209
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3881832700
Short name T420
Test name
Test status
Simulation time 8379453539 ps
CPU time 10.41 seconds
Started May 05 03:13:20 PM PDT 24
Finished May 05 03:13:31 PM PDT 24
Peak memory 204064 kb
Host smart-7071f0a5-40f4-423b-856e-8102ed95adbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818
32700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3881832700
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1124224100
Short name T841
Test name
Test status
Simulation time 8398951629 ps
CPU time 7.8 seconds
Started May 05 03:13:24 PM PDT 24
Finished May 05 03:13:32 PM PDT 24
Peak memory 204100 kb
Host smart-b0d58b1d-1161-415c-a40f-38e14a936feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11242
24100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1124224100
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1347530099
Short name T1029
Test name
Test status
Simulation time 67340216 ps
CPU time 0.63 seconds
Started May 05 03:13:22 PM PDT 24
Finished May 05 03:13:23 PM PDT 24
Peak memory 203976 kb
Host smart-9b335e85-cd3c-4980-8f9e-410f0032d171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13475
30099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1347530099
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1349666446
Short name T934
Test name
Test status
Simulation time 17566268176 ps
CPU time 32.47 seconds
Started May 05 03:13:17 PM PDT 24
Finished May 05 03:13:50 PM PDT 24
Peak memory 204384 kb
Host smart-d6e2c132-a00f-4925-b0aa-533fbdc284b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13496
66446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1349666446
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.467348112
Short name T1039
Test name
Test status
Simulation time 8421730168 ps
CPU time 7.99 seconds
Started May 05 03:13:17 PM PDT 24
Finished May 05 03:13:26 PM PDT 24
Peak memory 204080 kb
Host smart-8c6c2171-2d5f-495a-b308-c2681d28d46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46734
8112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.467348112
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2116916340
Short name T592
Test name
Test status
Simulation time 8406347884 ps
CPU time 10.14 seconds
Started May 05 03:13:23 PM PDT 24
Finished May 05 03:13:33 PM PDT 24
Peak memory 204120 kb
Host smart-2bc45e9d-ebd9-44ad-bea1-c63d0f28d8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21169
16340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2116916340
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1871083358
Short name T779
Test name
Test status
Simulation time 8373834292 ps
CPU time 8.51 seconds
Started May 05 03:13:23 PM PDT 24
Finished May 05 03:13:32 PM PDT 24
Peak memory 204088 kb
Host smart-2a7c673f-c16a-4ffd-a15b-ab6702b61859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18710
83358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1871083358
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3560780731
Short name T453
Test name
Test status
Simulation time 8375006365 ps
CPU time 10.28 seconds
Started May 05 03:13:25 PM PDT 24
Finished May 05 03:13:35 PM PDT 24
Peak memory 204096 kb
Host smart-46e8b73b-b15e-4e4d-8f72-817c3b607880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35607
80731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3560780731
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.572459706
Short name T1027
Test name
Test status
Simulation time 8439994423 ps
CPU time 8.9 seconds
Started May 05 03:13:15 PM PDT 24
Finished May 05 03:13:24 PM PDT 24
Peak memory 204100 kb
Host smart-05ae357e-73f5-4d9b-af2a-9edc5503d56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57245
9706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.572459706
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3966161333
Short name T355
Test name
Test status
Simulation time 8380713902 ps
CPU time 8.67 seconds
Started May 05 03:13:24 PM PDT 24
Finished May 05 03:13:33 PM PDT 24
Peak memory 204068 kb
Host smart-0f96c6ed-18a4-4720-a1fa-9965b7c1aa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
61333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3966161333
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1694912466
Short name T33
Test name
Test status
Simulation time 8408152470 ps
CPU time 8.1 seconds
Started May 05 03:13:23 PM PDT 24
Finished May 05 03:13:31 PM PDT 24
Peak memory 204016 kb
Host smart-fdf364c1-0ffe-46c1-9d33-212c5708ff70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949
12466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1694912466
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.2467491390
Short name T879
Test name
Test status
Simulation time 8469197078 ps
CPU time 7.59 seconds
Started May 05 03:13:31 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204064 kb
Host smart-5b51d8f6-4929-4572-9b94-d6ded0907d6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2467491390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.2467491390
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.2096008331
Short name T735
Test name
Test status
Simulation time 8376943716 ps
CPU time 8.42 seconds
Started May 05 03:13:31 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204132 kb
Host smart-d4f4a38e-3b05-4881-befd-23997e78a2cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2096008331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.2096008331
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1070398553
Short name T379
Test name
Test status
Simulation time 8456291836 ps
CPU time 9.43 seconds
Started May 05 03:13:31 PM PDT 24
Finished May 05 03:13:41 PM PDT 24
Peak memory 204068 kb
Host smart-4bbd1618-2bff-461d-82de-b531d2e58d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10703
98553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1070398553
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.62457124
Short name T861
Test name
Test status
Simulation time 8412289664 ps
CPU time 8.39 seconds
Started May 05 03:13:27 PM PDT 24
Finished May 05 03:13:35 PM PDT 24
Peak memory 204276 kb
Host smart-0fd31244-cf4d-4147-9a71-70c22b74f0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62457
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.62457124
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3387520039
Short name T1333
Test name
Test status
Simulation time 8381380322 ps
CPU time 8.89 seconds
Started May 05 03:13:27 PM PDT 24
Finished May 05 03:13:36 PM PDT 24
Peak memory 204052 kb
Host smart-8b257e48-8efb-4d57-bc94-124fdafd2de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33875
20039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3387520039
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3638448402
Short name T385
Test name
Test status
Simulation time 218196012 ps
CPU time 2.16 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:31 PM PDT 24
Peak memory 204184 kb
Host smart-3e386ef7-bd44-4dec-a9df-3612b233cc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36384
48402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3638448402
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.146309189
Short name T187
Test name
Test status
Simulation time 8373864853 ps
CPU time 7.9 seconds
Started May 05 03:13:31 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204136 kb
Host smart-99cde9bb-2b5e-4e7f-8618-a2e0f90088d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14630
9189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.146309189
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3455389823
Short name T979
Test name
Test status
Simulation time 8415770575 ps
CPU time 7.53 seconds
Started May 05 03:13:25 PM PDT 24
Finished May 05 03:13:33 PM PDT 24
Peak memory 204124 kb
Host smart-84b809f4-7913-4826-a038-78c37b9c4584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34553
89823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3455389823
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2293674182
Short name T1329
Test name
Test status
Simulation time 8416695233 ps
CPU time 8.48 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:37 PM PDT 24
Peak memory 204144 kb
Host smart-4eecff69-11bf-4655-b92e-9c3195031954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
74182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2293674182
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2061109209
Short name T955
Test name
Test status
Simulation time 8367891865 ps
CPU time 9.69 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:38 PM PDT 24
Peak memory 204140 kb
Host smart-efcc30bd-a7e6-40fe-9a67-baeb4fafd2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20611
09209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2061109209
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3941993539
Short name T246
Test name
Test status
Simulation time 8398867601 ps
CPU time 8.85 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:37 PM PDT 24
Peak memory 204128 kb
Host smart-559362cb-389c-490e-b4a0-f9df8ce4c454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39419
93539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3941993539
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3750930469
Short name T648
Test name
Test status
Simulation time 8405860993 ps
CPU time 9.98 seconds
Started May 05 03:13:28 PM PDT 24
Finished May 05 03:13:38 PM PDT 24
Peak memory 204100 kb
Host smart-d4f7d752-6ff0-4f06-9081-295dbeee01fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37509
30469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3750930469
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1058600622
Short name T1251
Test name
Test status
Simulation time 8370364307 ps
CPU time 7.46 seconds
Started May 05 03:13:33 PM PDT 24
Finished May 05 03:13:41 PM PDT 24
Peak memory 204104 kb
Host smart-d85b1afc-324f-4ef7-bc9a-0e0d2c3325fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
00622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1058600622
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3147224489
Short name T1215
Test name
Test status
Simulation time 31520299 ps
CPU time 0.65 seconds
Started May 05 03:13:32 PM PDT 24
Finished May 05 03:13:33 PM PDT 24
Peak memory 203992 kb
Host smart-b7c45cec-e820-40c5-bb10-d422588ac96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
24489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3147224489
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2137414008
Short name T957
Test name
Test status
Simulation time 15186286696 ps
CPU time 26.87 seconds
Started May 05 03:13:29 PM PDT 24
Finished May 05 03:13:56 PM PDT 24
Peak memory 204428 kb
Host smart-48408d81-6d35-4b86-85b5-5fa00cf028b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21374
14008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2137414008
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1453182459
Short name T922
Test name
Test status
Simulation time 8442256361 ps
CPU time 7.71 seconds
Started May 05 03:13:27 PM PDT 24
Finished May 05 03:13:35 PM PDT 24
Peak memory 204076 kb
Host smart-3585d6d7-67ea-46e6-b1c3-459e9c6e6d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14531
82459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1453182459
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3898243779
Short name T219
Test name
Test status
Simulation time 8421790330 ps
CPU time 8.1 seconds
Started May 05 03:13:26 PM PDT 24
Finished May 05 03:13:34 PM PDT 24
Peak memory 204100 kb
Host smart-bd76a8ac-9805-4d50-b3a4-ef78244bf2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38982
43779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3898243779
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1246220085
Short name T1278
Test name
Test status
Simulation time 8387479000 ps
CPU time 7.33 seconds
Started May 05 03:13:32 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204092 kb
Host smart-038a6c39-caed-40a7-a64c-5ba16ad09f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12462
20085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1246220085
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1904012917
Short name T1053
Test name
Test status
Simulation time 8367660011 ps
CPU time 7.9 seconds
Started May 05 03:13:33 PM PDT 24
Finished May 05 03:13:41 PM PDT 24
Peak memory 204064 kb
Host smart-e971c96b-b7cc-456a-bd1f-60b36b114d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
12917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1904012917
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2858031647
Short name T790
Test name
Test status
Simulation time 8482933694 ps
CPU time 8.98 seconds
Started May 05 03:13:25 PM PDT 24
Finished May 05 03:13:35 PM PDT 24
Peak memory 204068 kb
Host smart-427d7412-c5c1-4722-9371-a1e5efe81f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580
31647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2858031647
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2173149646
Short name T1024
Test name
Test status
Simulation time 8425439533 ps
CPU time 7.82 seconds
Started May 05 03:13:31 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204128 kb
Host smart-c784c5f6-fd45-414a-85db-a10651850609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731
49646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2173149646
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.627467978
Short name T604
Test name
Test status
Simulation time 8413809068 ps
CPU time 8.15 seconds
Started May 05 03:13:32 PM PDT 24
Finished May 05 03:13:41 PM PDT 24
Peak memory 204108 kb
Host smart-f1232a58-4299-47dd-841f-bd4d6f469eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62746
7978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.627467978
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.3495882429
Short name T720
Test name
Test status
Simulation time 8466845302 ps
CPU time 8.19 seconds
Started May 05 03:13:45 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 204092 kb
Host smart-37c1d25a-65f2-4c16-b380-b6044eb8ee25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3495882429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.3495882429
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.4104274271
Short name T994
Test name
Test status
Simulation time 8383731940 ps
CPU time 9.87 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:52 PM PDT 24
Peak memory 204104 kb
Host smart-d59ebbbe-e623-47a7-b34f-5809ef8b5946
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4104274271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.4104274271
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.26054850
Short name T798
Test name
Test status
Simulation time 8463553943 ps
CPU time 7.67 seconds
Started May 05 03:13:40 PM PDT 24
Finished May 05 03:13:48 PM PDT 24
Peak memory 204076 kb
Host smart-935104cf-2d1a-4073-91d9-d27aeda91309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.26054850
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.4098946327
Short name T526
Test name
Test status
Simulation time 8373478012 ps
CPU time 8.3 seconds
Started May 05 03:13:35 PM PDT 24
Finished May 05 03:13:44 PM PDT 24
Peak memory 204044 kb
Host smart-39ba5e5c-016a-4037-a67c-8d10bb31ad9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40989
46327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.4098946327
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.3628936118
Short name T1273
Test name
Test status
Simulation time 8374658942 ps
CPU time 7.53 seconds
Started May 05 03:13:40 PM PDT 24
Finished May 05 03:13:48 PM PDT 24
Peak memory 204120 kb
Host smart-d4fced86-3102-49f5-81be-5d29ce71e9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
36118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3628936118
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.173993628
Short name T871
Test name
Test status
Simulation time 80126689 ps
CPU time 1.97 seconds
Started May 05 03:13:37 PM PDT 24
Finished May 05 03:13:39 PM PDT 24
Peak memory 204172 kb
Host smart-fd81e94a-efe5-4547-800f-fbf98333d4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
3628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.173993628
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2404003319
Short name T908
Test name
Test status
Simulation time 8414333827 ps
CPU time 7.58 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:50 PM PDT 24
Peak memory 204100 kb
Host smart-de69b79d-0aba-45b5-94d0-4b0fe3e72a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24040
03319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2404003319
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3936382865
Short name T182
Test name
Test status
Simulation time 8367665905 ps
CPU time 7.56 seconds
Started May 05 03:13:41 PM PDT 24
Finished May 05 03:13:49 PM PDT 24
Peak memory 204088 kb
Host smart-51cd31ff-13ba-4b4b-827a-dd2f9928c59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363
82865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3936382865
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3184491593
Short name T1067
Test name
Test status
Simulation time 8461191840 ps
CPU time 8.38 seconds
Started May 05 03:13:36 PM PDT 24
Finished May 05 03:13:45 PM PDT 24
Peak memory 204076 kb
Host smart-92d0f74f-be53-4a5b-9d39-09280b0460dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31844
91593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3184491593
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.457896580
Short name T393
Test name
Test status
Simulation time 8440649112 ps
CPU time 10.15 seconds
Started May 05 03:13:35 PM PDT 24
Finished May 05 03:13:46 PM PDT 24
Peak memory 204080 kb
Host smart-67029eb4-ed62-4a50-867b-96eeb1c1a60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45789
6580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.457896580
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.679213644
Short name T333
Test name
Test status
Simulation time 8374949746 ps
CPU time 7.69 seconds
Started May 05 03:13:37 PM PDT 24
Finished May 05 03:13:45 PM PDT 24
Peak memory 204080 kb
Host smart-46384669-b656-470f-a09e-e6b37272cb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67921
3644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.679213644
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2628772683
Short name T1258
Test name
Test status
Simulation time 8392907401 ps
CPU time 8.23 seconds
Started May 05 03:13:35 PM PDT 24
Finished May 05 03:13:43 PM PDT 24
Peak memory 204024 kb
Host smart-47830c1d-969a-40b2-a5a3-5191615af484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26287
72683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2628772683
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1699009854
Short name T1236
Test name
Test status
Simulation time 8425177576 ps
CPU time 7.94 seconds
Started May 05 03:13:34 PM PDT 24
Finished May 05 03:13:42 PM PDT 24
Peak memory 204092 kb
Host smart-8e00e146-8f97-4026-9465-40d5a83b84e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16990
09854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1699009854
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2084936041
Short name T660
Test name
Test status
Simulation time 8380048276 ps
CPU time 8.34 seconds
Started May 05 03:13:46 PM PDT 24
Finished May 05 03:13:54 PM PDT 24
Peak memory 204088 kb
Host smart-699c17d7-83a6-4fed-a8f4-a0d5c36c42f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20849
36041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2084936041
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4106773497
Short name T559
Test name
Test status
Simulation time 51066095 ps
CPU time 0.68 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:43 PM PDT 24
Peak memory 204008 kb
Host smart-2c588cf8-65b4-474f-a28a-c125ec41ec69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41067
73497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4106773497
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1944287254
Short name T11
Test name
Test status
Simulation time 29330604242 ps
CPU time 61.22 seconds
Started May 05 03:13:38 PM PDT 24
Finished May 05 03:14:40 PM PDT 24
Peak memory 204392 kb
Host smart-3c68f511-fc62-46df-a532-8b3aeed6c7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19442
87254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1944287254
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3761579301
Short name T1187
Test name
Test status
Simulation time 8394231390 ps
CPU time 10.26 seconds
Started May 05 03:13:34 PM PDT 24
Finished May 05 03:13:45 PM PDT 24
Peak memory 204092 kb
Host smart-eb80337a-8328-4117-8f77-a04f1c841027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
79301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3761579301
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3394998574
Short name T1156
Test name
Test status
Simulation time 8426766599 ps
CPU time 7.6 seconds
Started May 05 03:13:35 PM PDT 24
Finished May 05 03:13:43 PM PDT 24
Peak memory 204080 kb
Host smart-3eb5c34b-1cf3-4903-8e56-27848549cac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
98574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3394998574
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.3660259456
Short name T877
Test name
Test status
Simulation time 8406736785 ps
CPU time 9.61 seconds
Started May 05 03:13:35 PM PDT 24
Finished May 05 03:13:46 PM PDT 24
Peak memory 204092 kb
Host smart-9b2a982f-f0d5-4a30-aa4e-6a21f6fe656f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36602
59456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.3660259456
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2101949505
Short name T1343
Test name
Test status
Simulation time 8373076340 ps
CPU time 8.19 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:50 PM PDT 24
Peak memory 204132 kb
Host smart-a4e51e57-2fd7-42b8-80c1-0482b4fd89a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21019
49505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2101949505
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1507850636
Short name T775
Test name
Test status
Simulation time 8368717371 ps
CPU time 7.6 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:50 PM PDT 24
Peak memory 204120 kb
Host smart-b2aa17fd-0a03-4482-9e84-46440601b9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15078
50636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1507850636
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3264135536
Short name T1069
Test name
Test status
Simulation time 8447570272 ps
CPU time 7.65 seconds
Started May 05 03:13:41 PM PDT 24
Finished May 05 03:13:49 PM PDT 24
Peak memory 204120 kb
Host smart-c62271ba-41e4-4db2-99d7-63c4028cfc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32641
35536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3264135536
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2815140270
Short name T540
Test name
Test status
Simulation time 8417399499 ps
CPU time 7.51 seconds
Started May 05 03:13:45 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 204084 kb
Host smart-85a38a5e-a51d-4011-9c78-162aab881cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
40270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2815140270
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2464520317
Short name T876
Test name
Test status
Simulation time 8415706379 ps
CPU time 7.54 seconds
Started May 05 03:13:36 PM PDT 24
Finished May 05 03:13:44 PM PDT 24
Peak memory 204120 kb
Host smart-8750c55f-8b92-459b-bba3-616caaa60a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24645
20317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2464520317
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.12554118
Short name T343
Test name
Test status
Simulation time 8468608197 ps
CPU time 7.75 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:13:57 PM PDT 24
Peak memory 204088 kb
Host smart-d7548dbe-7419-4de6-93d8-f6d1b11e6108
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=12554118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.12554118
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.2685231152
Short name T976
Test name
Test status
Simulation time 8387080674 ps
CPU time 7.56 seconds
Started May 05 03:13:47 PM PDT 24
Finished May 05 03:13:55 PM PDT 24
Peak memory 204132 kb
Host smart-f73e1539-cd75-4d55-906b-74e25fe14195
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2685231152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.2685231152
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.653411573
Short name T536
Test name
Test status
Simulation time 8385257188 ps
CPU time 8.42 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:52 PM PDT 24
Peak memory 204096 kb
Host smart-0fcc0ff0-9f74-4fd0-b9ac-e614a72f0476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65341
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.653411573
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3298320401
Short name T618
Test name
Test status
Simulation time 8378832671 ps
CPU time 7.4 seconds
Started May 05 03:13:40 PM PDT 24
Finished May 05 03:13:48 PM PDT 24
Peak memory 204084 kb
Host smart-c4bdc609-a88e-4d67-bd15-ae31940e3bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32983
20401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3298320401
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.3009450940
Short name T1310
Test name
Test status
Simulation time 8375722440 ps
CPU time 9.07 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:54 PM PDT 24
Peak memory 204120 kb
Host smart-7e4c396f-e8b6-44ed-b933-32660165bcc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30094
50940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3009450940
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1886042671
Short name T1163
Test name
Test status
Simulation time 57668307 ps
CPU time 1.45 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:44 PM PDT 24
Peak memory 204156 kb
Host smart-0494d966-5fc5-4d2f-bc55-e2db177126fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860
42671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1886042671
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1753204935
Short name T1250
Test name
Test status
Simulation time 8388667615 ps
CPU time 7.62 seconds
Started May 05 03:13:43 PM PDT 24
Finished May 05 03:13:51 PM PDT 24
Peak memory 204056 kb
Host smart-6f063b73-3dc7-4471-be3d-0a5771631f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532
04935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1753204935
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.967869956
Short name T785
Test name
Test status
Simulation time 8365584242 ps
CPU time 8.2 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 204128 kb
Host smart-812d194a-c597-43a5-ac5f-fc4b0e009cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96786
9956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.967869956
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2701777533
Short name T1147
Test name
Test status
Simulation time 8407561119 ps
CPU time 7.96 seconds
Started May 05 03:13:39 PM PDT 24
Finished May 05 03:13:48 PM PDT 24
Peak memory 204140 kb
Host smart-c67aa9b6-cf0c-4998-9ff1-877c8f207573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27017
77533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2701777533
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1031888253
Short name T325
Test name
Test status
Simulation time 8418022094 ps
CPU time 8.46 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 204088 kb
Host smart-c98b889d-926f-4fcf-9bb0-2c0104209328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10318
88253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1031888253
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.179873892
Short name T739
Test name
Test status
Simulation time 8404206789 ps
CPU time 8.33 seconds
Started May 05 03:13:41 PM PDT 24
Finished May 05 03:13:50 PM PDT 24
Peak memory 204128 kb
Host smart-b5d9208c-818b-48a5-a0f9-8a53b293cc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17987
3892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.179873892
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2031945329
Short name T122
Test name
Test status
Simulation time 8434588577 ps
CPU time 7.9 seconds
Started May 05 03:13:42 PM PDT 24
Finished May 05 03:13:50 PM PDT 24
Peak memory 204112 kb
Host smart-ee684b60-3437-4bce-8c29-89222584ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20319
45329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2031945329
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.988132335
Short name T405
Test name
Test status
Simulation time 8409660319 ps
CPU time 7.75 seconds
Started May 05 03:13:43 PM PDT 24
Finished May 05 03:13:52 PM PDT 24
Peak memory 204120 kb
Host smart-7686a075-08c1-4e11-8814-8a7b55f3d835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98813
2335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.988132335
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2393828908
Short name T309
Test name
Test status
Simulation time 8420032692 ps
CPU time 9.95 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:55 PM PDT 24
Peak memory 204140 kb
Host smart-9960eaa2-1539-46b1-b995-30f35af990ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
28908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2393828908
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.142540597
Short name T1106
Test name
Test status
Simulation time 8439365601 ps
CPU time 8.8 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:13:57 PM PDT 24
Peak memory 204080 kb
Host smart-adff8b55-6ff6-4470-b04e-4bf0804fb811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
0597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.142540597
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1117390898
Short name T1042
Test name
Test status
Simulation time 8381414645 ps
CPU time 8.76 seconds
Started May 05 03:13:47 PM PDT 24
Finished May 05 03:13:56 PM PDT 24
Peak memory 204088 kb
Host smart-b4152985-bfe8-4832-9c2d-c058845ab213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
90898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1117390898
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.989293621
Short name T900
Test name
Test status
Simulation time 55398863 ps
CPU time 0.68 seconds
Started May 05 03:13:45 PM PDT 24
Finished May 05 03:13:46 PM PDT 24
Peak memory 203960 kb
Host smart-ed0f71d2-0bd9-4241-9f4d-9092b96b4e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98929
3621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.989293621
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3944481600
Short name T248
Test name
Test status
Simulation time 18454625914 ps
CPU time 33.53 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:14:22 PM PDT 24
Peak memory 204280 kb
Host smart-77c9b959-a246-43d2-bb6b-69aaf6c9ed4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
81600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3944481600
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3836681195
Short name T695
Test name
Test status
Simulation time 8447088185 ps
CPU time 7.68 seconds
Started May 05 03:13:45 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 204080 kb
Host smart-88fe923b-280d-4367-a4c2-e22632b4afe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
81195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3836681195
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.3738128037
Short name T791
Test name
Test status
Simulation time 8395935335 ps
CPU time 9.94 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:55 PM PDT 24
Peak memory 204112 kb
Host smart-47c4e436-91ae-43c5-be81-573d7cf366a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37381
28037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.3738128037
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2697080467
Short name T716
Test name
Test status
Simulation time 8375315136 ps
CPU time 8.46 seconds
Started May 05 03:13:47 PM PDT 24
Finished May 05 03:13:55 PM PDT 24
Peak memory 204056 kb
Host smart-74c68e90-52f0-43d5-b5f0-62ea21182df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
80467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2697080467
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.230772095
Short name T706
Test name
Test status
Simulation time 8369536649 ps
CPU time 9.07 seconds
Started May 05 03:13:49 PM PDT 24
Finished May 05 03:13:59 PM PDT 24
Peak memory 204008 kb
Host smart-1839654a-ffc0-40c3-b1c1-bff3e3cdb120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.230772095
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1789818208
Short name T1098
Test name
Test status
Simulation time 8458303199 ps
CPU time 7.88 seconds
Started May 05 03:13:44 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 204120 kb
Host smart-faac879b-0c53-450f-97a9-b78dab4b1e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
18208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1789818208
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.213803863
Short name T1139
Test name
Test status
Simulation time 8419627018 ps
CPU time 8.11 seconds
Started May 05 03:13:47 PM PDT 24
Finished May 05 03:13:55 PM PDT 24
Peak memory 204120 kb
Host smart-22ee9418-4ec0-483a-aa33-3335a2e1d94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.213803863
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2402935672
Short name T952
Test name
Test status
Simulation time 8394845702 ps
CPU time 8.36 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:13:57 PM PDT 24
Peak memory 203996 kb
Host smart-2e371571-dfc3-4b8a-8abb-fe392e34c778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
35672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2402935672
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.570483812
Short name T896
Test name
Test status
Simulation time 8475815557 ps
CPU time 8.38 seconds
Started May 05 03:14:02 PM PDT 24
Finished May 05 03:14:11 PM PDT 24
Peak memory 204136 kb
Host smart-a420566e-9ce1-46cf-99be-938c1f03f4b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=570483812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.570483812
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.2370382376
Short name T222
Test name
Test status
Simulation time 8393118817 ps
CPU time 7.36 seconds
Started May 05 03:14:03 PM PDT 24
Finished May 05 03:14:11 PM PDT 24
Peak memory 204172 kb
Host smart-a435323f-2551-4383-9c29-d8264cb25a7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2370382376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.2370382376
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.727053054
Short name T1217
Test name
Test status
Simulation time 8407405187 ps
CPU time 8.12 seconds
Started May 05 03:14:03 PM PDT 24
Finished May 05 03:14:11 PM PDT 24
Peak memory 204048 kb
Host smart-38e35f6a-5983-4037-a4ff-3664cddb312a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72705
3054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.727053054
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.472884578
Short name T490
Test name
Test status
Simulation time 8394439428 ps
CPU time 9.45 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:13:58 PM PDT 24
Peak memory 204120 kb
Host smart-0bf31ecf-07e8-436f-a423-93f40ed97ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47288
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.472884578
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.1708901137
Short name T310
Test name
Test status
Simulation time 8380551687 ps
CPU time 10.33 seconds
Started May 05 03:13:50 PM PDT 24
Finished May 05 03:14:01 PM PDT 24
Peak memory 204068 kb
Host smart-c9369bcd-0bfc-4505-9364-3b437d34be00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
01137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1708901137
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1062277648
Short name T338
Test name
Test status
Simulation time 196857114 ps
CPU time 2.13 seconds
Started May 05 03:13:48 PM PDT 24
Finished May 05 03:13:51 PM PDT 24
Peak memory 204236 kb
Host smart-fea3fb19-e371-434a-b870-5cc8efee5362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10622
77648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1062277648
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2309736695
Short name T1206
Test name
Test status
Simulation time 8423168456 ps
CPU time 8.01 seconds
Started May 05 03:13:59 PM PDT 24
Finished May 05 03:14:07 PM PDT 24
Peak memory 204136 kb
Host smart-5634a556-923f-4e14-9bd4-beab986cdcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23097
36695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2309736695
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1838743895
Short name T926
Test name
Test status
Simulation time 8406651390 ps
CPU time 8.67 seconds
Started May 05 03:13:59 PM PDT 24
Finished May 05 03:14:08 PM PDT 24
Peak memory 204108 kb
Host smart-3cfc41ab-f3f2-424f-b918-0f9dff063e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18387
43895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1838743895
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1370054113
Short name T151
Test name
Test status
Simulation time 8389945940 ps
CPU time 9.72 seconds
Started May 05 03:13:52 PM PDT 24
Finished May 05 03:14:02 PM PDT 24
Peak memory 204068 kb
Host smart-e7b5c39b-1b99-42ec-8f97-b370623063be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13700
54113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1370054113
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2640880291
Short name T645
Test name
Test status
Simulation time 8435125730 ps
CPU time 7.49 seconds
Started May 05 03:13:52 PM PDT 24
Finished May 05 03:14:00 PM PDT 24
Peak memory 204148 kb
Host smart-c3b0e967-f554-4ac3-8e22-f517034c8539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26408
80291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2640880291
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1609406784
Short name T1332
Test name
Test status
Simulation time 8372781549 ps
CPU time 8.18 seconds
Started May 05 03:13:55 PM PDT 24
Finished May 05 03:14:04 PM PDT 24
Peak memory 204136 kb
Host smart-763bd825-7a33-4c6b-a5df-692dfce73019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094
06784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1609406784
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1227085155
Short name T1246
Test name
Test status
Simulation time 8413252229 ps
CPU time 7.98 seconds
Started May 05 03:13:56 PM PDT 24
Finished May 05 03:14:04 PM PDT 24
Peak memory 204068 kb
Host smart-ade87396-6bdb-4b17-9a8d-5a6c81c5f6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270
85155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1227085155
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2163299283
Short name T506
Test name
Test status
Simulation time 8418950980 ps
CPU time 7.7 seconds
Started May 05 03:13:53 PM PDT 24
Finished May 05 03:14:02 PM PDT 24
Peak memory 204160 kb
Host smart-f223136b-851f-4a2c-82fd-3ed536b62c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
99283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2163299283
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.945719241
Short name T1084
Test name
Test status
Simulation time 49181753 ps
CPU time 0.67 seconds
Started May 05 03:13:58 PM PDT 24
Finished May 05 03:14:00 PM PDT 24
Peak memory 203940 kb
Host smart-b834635d-47d1-440d-acca-a7f7f55b3252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94571
9241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.945719241
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3294879334
Short name T1361
Test name
Test status
Simulation time 28506671711 ps
CPU time 54.8 seconds
Started May 05 03:13:53 PM PDT 24
Finished May 05 03:14:49 PM PDT 24
Peak memory 204412 kb
Host smart-0f950df9-105b-4380-bd56-8f4fb6990240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32948
79334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3294879334
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4257847435
Short name T1223
Test name
Test status
Simulation time 8434693257 ps
CPU time 7.88 seconds
Started May 05 03:13:56 PM PDT 24
Finished May 05 03:14:04 PM PDT 24
Peak memory 204084 kb
Host smart-b3012269-ff3d-4874-9a67-1b014a7b6e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
47435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4257847435
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1945472726
Short name T1279
Test name
Test status
Simulation time 8442391565 ps
CPU time 7.95 seconds
Started May 05 03:13:53 PM PDT 24
Finished May 05 03:14:01 PM PDT 24
Peak memory 204108 kb
Host smart-0f70133f-be54-4636-a405-d2bbcb27fd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
72726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1945472726
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1919864920
Short name T456
Test name
Test status
Simulation time 8403117117 ps
CPU time 8.43 seconds
Started May 05 03:13:52 PM PDT 24
Finished May 05 03:14:01 PM PDT 24
Peak memory 204108 kb
Host smart-98474242-8174-4da2-bb30-b1d81552742e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
64920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1919864920
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1089950548
Short name T802
Test name
Test status
Simulation time 8378280818 ps
CPU time 9.95 seconds
Started May 05 03:13:56 PM PDT 24
Finished May 05 03:14:07 PM PDT 24
Peak memory 204000 kb
Host smart-00499d08-3729-4c17-8070-b06b0d15cb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
50548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1089950548
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1209209509
Short name T30
Test name
Test status
Simulation time 8372924829 ps
CPU time 8.44 seconds
Started May 05 03:13:56 PM PDT 24
Finished May 05 03:14:05 PM PDT 24
Peak memory 204132 kb
Host smart-bac115ed-83fe-48d3-9417-866496d2256b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
09509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1209209509
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2429782894
Short name T169
Test name
Test status
Simulation time 8465145585 ps
CPU time 7.96 seconds
Started May 05 03:13:50 PM PDT 24
Finished May 05 03:13:59 PM PDT 24
Peak memory 204084 kb
Host smart-4248387f-8fc6-4a0f-a500-1797cea4cb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24297
82894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2429782894
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2745819138
Short name T351
Test name
Test status
Simulation time 8400525562 ps
CPU time 9.23 seconds
Started May 05 03:13:58 PM PDT 24
Finished May 05 03:14:08 PM PDT 24
Peak memory 204148 kb
Host smart-617ed01d-6b2f-49ef-9a7c-c3005823f812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458
19138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2745819138
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.307080135
Short name T847
Test name
Test status
Simulation time 8385962587 ps
CPU time 8.19 seconds
Started May 05 03:13:56 PM PDT 24
Finished May 05 03:14:05 PM PDT 24
Peak memory 204068 kb
Host smart-59b1e1f7-17cd-4a56-bd72-f7ac0dba27ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30708
0135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.307080135
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.2834313079
Short name T546
Test name
Test status
Simulation time 8463691498 ps
CPU time 8.45 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204008 kb
Host smart-89a6c1b1-8088-41e7-b992-59b5aedab5b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2834313079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.2834313079
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.2261779492
Short name T1231
Test name
Test status
Simulation time 8402888871 ps
CPU time 7.84 seconds
Started May 05 03:14:10 PM PDT 24
Finished May 05 03:14:18 PM PDT 24
Peak memory 204076 kb
Host smart-e4ab6904-2fa6-41d5-ac24-ff77c006e1bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2261779492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.2261779492
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.3467531920
Short name T889
Test name
Test status
Simulation time 8416402229 ps
CPU time 8.71 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204092 kb
Host smart-5e5136ff-f813-473c-9518-1618202be55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675
31920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.3467531920
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3334467701
Short name T427
Test name
Test status
Simulation time 8377450786 ps
CPU time 10.17 seconds
Started May 05 03:14:05 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204100 kb
Host smart-6edf4715-5f53-488a-a9fd-ecbd448e717e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
67701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3334467701
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.1829114177
Short name T1260
Test name
Test status
Simulation time 8408624961 ps
CPU time 8.74 seconds
Started May 05 03:14:04 PM PDT 24
Finished May 05 03:14:13 PM PDT 24
Peak memory 204100 kb
Host smart-86fd6f41-55fe-445e-9d0e-deca2f1dc4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18291
14177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1829114177
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2784443525
Short name T799
Test name
Test status
Simulation time 180650252 ps
CPU time 2.01 seconds
Started May 05 03:14:02 PM PDT 24
Finished May 05 03:14:05 PM PDT 24
Peak memory 204164 kb
Host smart-05ac377b-483e-40ad-a8b8-c2650a681249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27844
43525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2784443525
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3413642228
Short name T1161
Test name
Test status
Simulation time 8427650082 ps
CPU time 8.42 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:28 PM PDT 24
Peak memory 204080 kb
Host smart-46ca4644-62a1-454d-9d6b-b3a6742a7296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34136
42228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3413642228
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2794400657
Short name T200
Test name
Test status
Simulation time 8369445741 ps
CPU time 8.92 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204064 kb
Host smart-4e94c3f0-0cc1-4f28-bbe2-5d006fb3adad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
00657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2794400657
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.691966943
Short name T321
Test name
Test status
Simulation time 8422975162 ps
CPU time 9.07 seconds
Started May 05 03:14:02 PM PDT 24
Finished May 05 03:14:12 PM PDT 24
Peak memory 204100 kb
Host smart-f911ab0c-6389-4f07-baf2-52cc2a37d519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69196
6943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.691966943
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3345003066
Short name T626
Test name
Test status
Simulation time 8424861836 ps
CPU time 7.64 seconds
Started May 05 03:14:05 PM PDT 24
Finished May 05 03:14:13 PM PDT 24
Peak memory 204088 kb
Host smart-7a393af9-78fe-4a6f-895d-36caa37cfda5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33450
03066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3345003066
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2308775201
Short name T696
Test name
Test status
Simulation time 8369159243 ps
CPU time 9.98 seconds
Started May 05 03:14:05 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204052 kb
Host smart-d50029f0-a727-467d-835a-6aa5859d8f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23087
75201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2308775201
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1348866631
Short name T106
Test name
Test status
Simulation time 8446045041 ps
CPU time 7.68 seconds
Started May 05 03:14:05 PM PDT 24
Finished May 05 03:14:13 PM PDT 24
Peak memory 204092 kb
Host smart-970a214f-770f-4feb-b500-c9d8143eaab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13488
66631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1348866631
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.455768075
Short name T676
Test name
Test status
Simulation time 8413110675 ps
CPU time 9.94 seconds
Started May 05 03:14:06 PM PDT 24
Finished May 05 03:14:17 PM PDT 24
Peak memory 204076 kb
Host smart-aa3ad36d-096e-4d42-9af2-ddca35c631b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45576
8075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.455768075
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2543699254
Short name T786
Test name
Test status
Simulation time 8398184935 ps
CPU time 7.96 seconds
Started May 05 03:14:07 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204084 kb
Host smart-8595304f-6e0d-439c-b34f-48f8f94263f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25436
99254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2543699254
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1215032544
Short name T951
Test name
Test status
Simulation time 8375683782 ps
CPU time 9.67 seconds
Started May 05 03:14:08 PM PDT 24
Finished May 05 03:14:18 PM PDT 24
Peak memory 204100 kb
Host smart-373c7da7-d57f-46e6-b9bf-24e48af3b66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12150
32544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1215032544
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2360190229
Short name T46
Test name
Test status
Simulation time 166998911 ps
CPU time 0.84 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 203952 kb
Host smart-5cf726f9-3aaf-45fd-8d75-31628afbbd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23601
90229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2360190229
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3052090820
Short name T1366
Test name
Test status
Simulation time 18795562978 ps
CPU time 31.96 seconds
Started May 05 03:14:08 PM PDT 24
Finished May 05 03:14:40 PM PDT 24
Peak memory 204384 kb
Host smart-8b58c169-9919-436f-8d5d-89b7d3b12865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30520
90820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3052090820
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.522805870
Short name T882
Test name
Test status
Simulation time 8379786646 ps
CPU time 9.04 seconds
Started May 05 03:14:05 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204128 kb
Host smart-70233bf3-fec2-4c00-8cba-15c35af1a8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52280
5870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.522805870
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1011195057
Short name T1172
Test name
Test status
Simulation time 8475927574 ps
CPU time 8.24 seconds
Started May 05 03:14:06 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204096 kb
Host smart-a052c1a7-11f5-409c-ae05-0e62bc43206d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111
95057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1011195057
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1087645803
Short name T517
Test name
Test status
Simulation time 8373857265 ps
CPU time 7.41 seconds
Started May 05 03:14:07 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204132 kb
Host smart-9091c378-69d3-4205-8484-d39d3ffdb2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10876
45803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1087645803
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3457799285
Short name T649
Test name
Test status
Simulation time 8374437977 ps
CPU time 9.19 seconds
Started May 05 03:14:07 PM PDT 24
Finished May 05 03:14:17 PM PDT 24
Peak memory 204060 kb
Host smart-97f4a795-2ed4-4c6e-8162-acdca552dec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34577
99285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3457799285
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2649473903
Short name T1230
Test name
Test status
Simulation time 8366758102 ps
CPU time 7.56 seconds
Started May 05 03:14:06 PM PDT 24
Finished May 05 03:14:14 PM PDT 24
Peak memory 204100 kb
Host smart-656d3835-1923-4e0b-80db-d275ddfa3609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
73903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2649473903
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1045710203
Short name T1315
Test name
Test status
Simulation time 8471614212 ps
CPU time 8.17 seconds
Started May 05 03:14:02 PM PDT 24
Finished May 05 03:14:11 PM PDT 24
Peak memory 204124 kb
Host smart-147362b7-b306-4a57-8c57-8a92e60900c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
10203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1045710203
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1383196438
Short name T989
Test name
Test status
Simulation time 8385560312 ps
CPU time 7.43 seconds
Started May 05 03:14:07 PM PDT 24
Finished May 05 03:14:15 PM PDT 24
Peak memory 204076 kb
Host smart-0a01643c-50f4-4393-ba81-f486bda7abb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13831
96438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1383196438
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.351190861
Short name T480
Test name
Test status
Simulation time 8415936483 ps
CPU time 9.7 seconds
Started May 05 03:14:08 PM PDT 24
Finished May 05 03:14:18 PM PDT 24
Peak memory 204112 kb
Host smart-c281f6bd-135e-4b25-9b00-1a40c2bd6988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
0861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.351190861
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.2109852244
Short name T689
Test name
Test status
Simulation time 8489108689 ps
CPU time 10.4 seconds
Started May 05 03:14:16 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204104 kb
Host smart-72a9f20b-a7eb-4670-96a2-f603541b0100
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2109852244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.2109852244
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.4215702591
Short name T1058
Test name
Test status
Simulation time 8395782019 ps
CPU time 7.89 seconds
Started May 05 03:14:17 PM PDT 24
Finished May 05 03:14:26 PM PDT 24
Peak memory 204008 kb
Host smart-418c0b04-6265-487c-ba7c-8ea6e3f53336
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4215702591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.4215702591
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2196625081
Short name T977
Test name
Test status
Simulation time 8396883442 ps
CPU time 7.93 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204076 kb
Host smart-e161de7b-0513-45b5-a8d1-8b6b7be034f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21966
25081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2196625081
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2671656633
Short name T748
Test name
Test status
Simulation time 8372951638 ps
CPU time 8.66 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204280 kb
Host smart-a73207ee-3773-4e46-8a71-a8908ba54d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26716
56633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2671656633
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2928532710
Short name T776
Test name
Test status
Simulation time 8414834665 ps
CPU time 8.71 seconds
Started May 05 03:14:12 PM PDT 24
Finished May 05 03:14:21 PM PDT 24
Peak memory 204056 kb
Host smart-0cba72c3-d524-4d61-8b77-11a7482f65ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
32710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2928532710
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2457067797
Short name T974
Test name
Test status
Simulation time 156096917 ps
CPU time 1.52 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:13 PM PDT 24
Peak memory 204160 kb
Host smart-e751f77e-31fb-4c11-a3ed-3f7164af90bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
67797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2457067797
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1425211127
Short name T870
Test name
Test status
Simulation time 8457286956 ps
CPU time 9.47 seconds
Started May 05 03:14:16 PM PDT 24
Finished May 05 03:14:26 PM PDT 24
Peak memory 204128 kb
Host smart-e1f47928-894e-4b6c-80ef-3fff8e355520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14252
11127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1425211127
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1868197566
Short name T1111
Test name
Test status
Simulation time 8459797855 ps
CPU time 8.36 seconds
Started May 05 03:14:10 PM PDT 24
Finished May 05 03:14:19 PM PDT 24
Peak memory 204108 kb
Host smart-d5181b7b-760a-424f-b975-d887c2c0a2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681
97566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1868197566
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.4237795806
Short name T539
Test name
Test status
Simulation time 8416229577 ps
CPU time 9.39 seconds
Started May 05 03:14:10 PM PDT 24
Finished May 05 03:14:19 PM PDT 24
Peak memory 204116 kb
Host smart-aa5fdee5-b25e-4d28-8d5f-738bc6e7c063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377
95806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.4237795806
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1917847338
Short name T426
Test name
Test status
Simulation time 8368706423 ps
CPU time 7.42 seconds
Started May 05 03:14:10 PM PDT 24
Finished May 05 03:14:17 PM PDT 24
Peak memory 204092 kb
Host smart-a567e76b-fead-41cb-87be-0de4439ec516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19178
47338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1917847338
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2873944334
Short name T1125
Test name
Test status
Simulation time 8415352174 ps
CPU time 8.67 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204052 kb
Host smart-29e317cc-494f-4586-8272-119e2283f3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28739
44334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2873944334
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4144743393
Short name T619
Test name
Test status
Simulation time 8399612331 ps
CPU time 7.93 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204080 kb
Host smart-041b4f44-be2d-474c-8f5f-506e4820447a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41447
43393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4144743393
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3709776832
Short name T1076
Test name
Test status
Simulation time 8393348457 ps
CPU time 8.42 seconds
Started May 05 03:14:14 PM PDT 24
Finished May 05 03:14:24 PM PDT 24
Peak memory 204040 kb
Host smart-97d4374c-9f73-4050-9298-d26eecaccce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37097
76832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3709776832
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.633078921
Short name T603
Test name
Test status
Simulation time 8382506079 ps
CPU time 8.67 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204036 kb
Host smart-3f302293-734f-487f-9ca7-1356f6fb5f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63307
8921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.633078921
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.474437351
Short name T1313
Test name
Test status
Simulation time 47046685 ps
CPU time 0.73 seconds
Started May 05 03:14:16 PM PDT 24
Finished May 05 03:14:17 PM PDT 24
Peak memory 204016 kb
Host smart-9e59c024-2746-4ab8-82ec-4ac9924bcf06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47443
7351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.474437351
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3647805751
Short name T552
Test name
Test status
Simulation time 8387473695 ps
CPU time 7.67 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204080 kb
Host smart-eded37b5-91ac-4c16-a75f-33e76289d15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
05751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3647805751
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3954196401
Short name T1041
Test name
Test status
Simulation time 8528602080 ps
CPU time 8.46 seconds
Started May 05 03:14:10 PM PDT 24
Finished May 05 03:14:19 PM PDT 24
Peak memory 204084 kb
Host smart-d642356c-0089-4df7-973a-4733ce5f4b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39541
96401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3954196401
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.339345802
Short name T693
Test name
Test status
Simulation time 8452750226 ps
CPU time 10.25 seconds
Started May 05 03:14:16 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204144 kb
Host smart-9721af8b-1c34-41b4-8b1a-4e7dcb2c8d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33934
5802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.339345802
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3270262095
Short name T873
Test name
Test status
Simulation time 8388364324 ps
CPU time 7.57 seconds
Started May 05 03:14:15 PM PDT 24
Finished May 05 03:14:23 PM PDT 24
Peak memory 204136 kb
Host smart-65c4d1e3-b20e-413a-9219-6fcebaa9c760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
62095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3270262095
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2344565945
Short name T1281
Test name
Test status
Simulation time 8368243141 ps
CPU time 8.01 seconds
Started May 05 03:14:14 PM PDT 24
Finished May 05 03:14:23 PM PDT 24
Peak memory 204132 kb
Host smart-ff9d6dbe-432f-495f-9df1-6941609e23c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23445
65945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2344565945
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.4069063863
Short name T147
Test name
Test status
Simulation time 8427939116 ps
CPU time 8.17 seconds
Started May 05 03:14:11 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204120 kb
Host smart-5e26d791-2ef6-4bba-a116-353c7e0544eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40690
63863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.4069063863
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2540077969
Short name T519
Test name
Test status
Simulation time 8380382616 ps
CPU time 7.58 seconds
Started May 05 03:14:14 PM PDT 24
Finished May 05 03:14:23 PM PDT 24
Peak memory 204100 kb
Host smart-669e09bd-c863-40c0-a7a5-0a2e3afb06eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25400
77969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2540077969
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1345461361
Short name T440
Test name
Test status
Simulation time 8387952646 ps
CPU time 8.08 seconds
Started May 05 03:14:15 PM PDT 24
Finished May 05 03:14:24 PM PDT 24
Peak memory 204124 kb
Host smart-0d7ee20c-1f15-4c11-b125-9707c8c35a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13454
61361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1345461361
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.897052261
Short name T49
Test name
Test status
Simulation time 8465974073 ps
CPU time 8.37 seconds
Started May 05 03:14:30 PM PDT 24
Finished May 05 03:14:38 PM PDT 24
Peak memory 204136 kb
Host smart-fc9d8014-7152-4025-ab93-8a8d846fe929
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=897052261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.897052261
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.4049560927
Short name T514
Test name
Test status
Simulation time 8379444941 ps
CPU time 8.11 seconds
Started May 05 03:14:24 PM PDT 24
Finished May 05 03:14:33 PM PDT 24
Peak memory 204116 kb
Host smart-cdfbf2e7-2eff-4806-84c0-49332bd1c777
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4049560927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.4049560927
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.843441441
Short name T1023
Test name
Test status
Simulation time 8470565583 ps
CPU time 7.75 seconds
Started May 05 03:14:21 PM PDT 24
Finished May 05 03:14:30 PM PDT 24
Peak memory 204132 kb
Host smart-585021ab-22e8-4ad8-9078-27a02c80dfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84344
1441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.843441441
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.661476275
Short name T1018
Test name
Test status
Simulation time 8372775282 ps
CPU time 9.83 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:29 PM PDT 24
Peak memory 204012 kb
Host smart-f9ee0b46-1ca3-4ba8-9330-a8528cac3005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66147
6275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.661476275
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.551896520
Short name T738
Test name
Test status
Simulation time 8392336652 ps
CPU time 7.76 seconds
Started May 05 03:14:16 PM PDT 24
Finished May 05 03:14:24 PM PDT 24
Peak memory 204112 kb
Host smart-4f568245-f70c-4ab6-b40f-3af63320d45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55189
6520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.551896520
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3424750507
Short name T1214
Test name
Test status
Simulation time 210862310 ps
CPU time 1.93 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:20 PM PDT 24
Peak memory 204264 kb
Host smart-c285dcc2-d971-49d0-90e8-29b8f3ae9798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34247
50507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3424750507
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1600534464
Short name T134
Test name
Test status
Simulation time 8487817245 ps
CPU time 7.94 seconds
Started May 05 03:14:23 PM PDT 24
Finished May 05 03:14:31 PM PDT 24
Peak memory 204108 kb
Host smart-89a15d3f-f244-4634-8b7a-ed524f432717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16005
34464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1600534464
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.4147267222
Short name T813
Test name
Test status
Simulation time 8362289809 ps
CPU time 7.37 seconds
Started May 05 03:14:22 PM PDT 24
Finished May 05 03:14:30 PM PDT 24
Peak memory 204076 kb
Host smart-bcd29585-73bc-468d-829f-3200e0d4b131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41472
67222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.4147267222
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.563036817
Short name T154
Test name
Test status
Simulation time 8434872945 ps
CPU time 7.62 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204100 kb
Host smart-331cbf5a-1539-4c9f-b469-70fa032ca9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56303
6817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.563036817
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2863257380
Short name T661
Test name
Test status
Simulation time 8412348879 ps
CPU time 8.28 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:28 PM PDT 24
Peak memory 204136 kb
Host smart-174f45ca-389b-494b-8a91-819e7f674066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
57380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2863257380
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.547707837
Short name T1229
Test name
Test status
Simulation time 8365324516 ps
CPU time 8.4 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 204132 kb
Host smart-f8670f97-c5a6-4ff1-8bcb-b199e74542a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54770
7837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.547707837
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3119750131
Short name T1277
Test name
Test status
Simulation time 8399196211 ps
CPU time 7.47 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:14:26 PM PDT 24
Peak memory 204132 kb
Host smart-5eb13855-314e-497f-a7a9-38bec9243853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31197
50131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3119750131
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.4146674063
Short name T774
Test name
Test status
Simulation time 8397813626 ps
CPU time 8.33 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:28 PM PDT 24
Peak memory 204064 kb
Host smart-09db9469-e743-416f-a8b4-65f86aff4ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
74063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.4146674063
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.493526357
Short name T22
Test name
Test status
Simulation time 8415395061 ps
CPU time 7.55 seconds
Started May 05 03:14:30 PM PDT 24
Finished May 05 03:14:38 PM PDT 24
Peak memory 204128 kb
Host smart-38c5322c-c899-440c-961d-b7b7df6bc74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49352
6357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.493526357
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1810554902
Short name T690
Test name
Test status
Simulation time 8367244640 ps
CPU time 8.64 seconds
Started May 05 03:14:30 PM PDT 24
Finished May 05 03:14:39 PM PDT 24
Peak memory 204132 kb
Host smart-59dde855-c402-40af-afd2-cdc9cec143cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105
54902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1810554902
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1559321905
Short name T583
Test name
Test status
Simulation time 29364519653 ps
CPU time 59 seconds
Started May 05 03:14:18 PM PDT 24
Finished May 05 03:15:18 PM PDT 24
Peak memory 204348 kb
Host smart-dc232ec3-301b-47d3-9400-b86e15223149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15593
21905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1559321905
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2626740933
Short name T1082
Test name
Test status
Simulation time 8440584873 ps
CPU time 7.92 seconds
Started May 05 03:14:19 PM PDT 24
Finished May 05 03:14:28 PM PDT 24
Peak memory 204068 kb
Host smart-8d307725-6a9d-406f-9863-0790ae16ed0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
40933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2626740933
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2132882277
Short name T1013
Test name
Test status
Simulation time 8493359494 ps
CPU time 8.18 seconds
Started May 05 03:14:22 PM PDT 24
Finished May 05 03:14:31 PM PDT 24
Peak memory 204108 kb
Host smart-7b1a40da-e1ce-4d5c-896b-f7f2dda397e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21328
82277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2132882277
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2889858389
Short name T1063
Test name
Test status
Simulation time 8382163929 ps
CPU time 8.43 seconds
Started May 05 03:14:22 PM PDT 24
Finished May 05 03:14:31 PM PDT 24
Peak memory 204056 kb
Host smart-6e159c7c-d488-4d6f-a7fc-86c172ff238b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
58389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2889858389
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2895097464
Short name T990
Test name
Test status
Simulation time 8376931521 ps
CPU time 7.58 seconds
Started May 05 03:14:23 PM PDT 24
Finished May 05 03:14:32 PM PDT 24
Peak memory 204060 kb
Host smart-38b5d3b6-970a-4129-86f1-32d840043780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
97464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2895097464
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.891842200
Short name T357
Test name
Test status
Simulation time 8374521011 ps
CPU time 9.28 seconds
Started May 05 03:14:22 PM PDT 24
Finished May 05 03:14:32 PM PDT 24
Peak memory 204104 kb
Host smart-3f61b490-92e7-4e48-8508-44edd5a164c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89184
2200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.891842200
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2875272477
Short name T800
Test name
Test status
Simulation time 8390256888 ps
CPU time 8.07 seconds
Started May 05 03:14:24 PM PDT 24
Finished May 05 03:14:33 PM PDT 24
Peak memory 204056 kb
Host smart-8623302d-dfdc-4672-a33e-fe40481ad009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28752
72477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2875272477
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2172267450
Short name T485
Test name
Test status
Simulation time 8399949069 ps
CPU time 9.96 seconds
Started May 05 03:14:24 PM PDT 24
Finished May 05 03:14:34 PM PDT 24
Peak memory 204108 kb
Host smart-b605a59b-5b62-4e39-b688-9b0e51a8bfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
67450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2172267450
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.132364001
Short name T320
Test name
Test status
Simulation time 8465942681 ps
CPU time 8.57 seconds
Started May 05 03:14:31 PM PDT 24
Finished May 05 03:14:40 PM PDT 24
Peak memory 204112 kb
Host smart-f45834cf-dbfa-4bc8-ad4d-16df90e78818
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=132364001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.132364001
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.719033026
Short name T909
Test name
Test status
Simulation time 8388210839 ps
CPU time 8.17 seconds
Started May 05 03:14:33 PM PDT 24
Finished May 05 03:14:42 PM PDT 24
Peak memory 204148 kb
Host smart-e7d78e7b-b284-413c-a07f-6907d152b8bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=719033026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.719033026
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.4191776068
Short name T445
Test name
Test status
Simulation time 8436936486 ps
CPU time 8.5 seconds
Started May 05 03:14:32 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 204140 kb
Host smart-ee219472-94c9-4575-a56c-f7f1661413ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
76068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.4191776068
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1836015098
Short name T608
Test name
Test status
Simulation time 8383620308 ps
CPU time 8.75 seconds
Started May 05 03:14:24 PM PDT 24
Finished May 05 03:14:34 PM PDT 24
Peak memory 204108 kb
Host smart-6f955fd0-e80a-42e3-9b95-2f0ced95c861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18360
15098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1836015098
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.1968240262
Short name T1225
Test name
Test status
Simulation time 8398721497 ps
CPU time 7.67 seconds
Started May 05 03:14:24 PM PDT 24
Finished May 05 03:14:32 PM PDT 24
Peak memory 204108 kb
Host smart-fd226f5d-4d22-4a72-93dd-015f56326b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
40262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1968240262
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.4213859277
Short name T597
Test name
Test status
Simulation time 90845314 ps
CPU time 2.34 seconds
Started May 05 03:14:21 PM PDT 24
Finished May 05 03:14:24 PM PDT 24
Peak memory 204176 kb
Host smart-c17e4e82-419b-4d7e-ac34-175ba88193fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
59277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.4213859277
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.299353749
Short name T198
Test name
Test status
Simulation time 8413272949 ps
CPU time 7.88 seconds
Started May 05 03:14:30 PM PDT 24
Finished May 05 03:14:38 PM PDT 24
Peak memory 204136 kb
Host smart-85d4cd31-d606-4158-8db7-704e18fe6c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
3749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.299353749
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2161930759
Short name T950
Test name
Test status
Simulation time 8468631716 ps
CPU time 8.1 seconds
Started May 05 03:14:24 PM PDT 24
Finished May 05 03:14:33 PM PDT 24
Peak memory 204080 kb
Host smart-3633fd0c-1b00-4255-b026-ab860982d05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21619
30759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2161930759
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.217272243
Short name T760
Test name
Test status
Simulation time 8417338305 ps
CPU time 7.81 seconds
Started May 05 03:14:28 PM PDT 24
Finished May 05 03:14:36 PM PDT 24
Peak memory 204080 kb
Host smart-94a0e693-af49-4e14-935a-9eeb17d4b579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21727
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.217272243
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3127124612
Short name T970
Test name
Test status
Simulation time 8392062206 ps
CPU time 10.13 seconds
Started May 05 03:14:28 PM PDT 24
Finished May 05 03:14:39 PM PDT 24
Peak memory 204112 kb
Host smart-a87ae5fc-7c3b-4a4e-87d6-987f44054700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31271
24612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3127124612
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2218735470
Short name T127
Test name
Test status
Simulation time 8433883556 ps
CPU time 8.74 seconds
Started May 05 03:14:26 PM PDT 24
Finished May 05 03:14:36 PM PDT 24
Peak memory 204092 kb
Host smart-9a4938d7-645a-418e-a2df-a15ff4cfad18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22187
35470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2218735470
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.467423396
Short name T1359
Test name
Test status
Simulation time 8417105232 ps
CPU time 8.88 seconds
Started May 05 03:14:32 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 204084 kb
Host smart-6e8fa203-0142-427e-bf43-8270d0fea054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46742
3396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.467423396
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.336865309
Short name T1129
Test name
Test status
Simulation time 8443319573 ps
CPU time 7.72 seconds
Started May 05 03:14:26 PM PDT 24
Finished May 05 03:14:35 PM PDT 24
Peak memory 204100 kb
Host smart-4c58bc27-f7e6-40ad-bef0-d7c6f4776001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33686
5309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.336865309
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2383106205
Short name T888
Test name
Test status
Simulation time 8408827732 ps
CPU time 9.8 seconds
Started May 05 03:14:30 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 204124 kb
Host smart-abfce57f-0e6d-45e2-9d28-0545c69bb02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23831
06205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2383106205
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3657291512
Short name T611
Test name
Test status
Simulation time 8368755118 ps
CPU time 9.93 seconds
Started May 05 03:14:28 PM PDT 24
Finished May 05 03:14:38 PM PDT 24
Peak memory 204112 kb
Host smart-8922749b-009d-4c38-a4cc-1c7b27b1e451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
91512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3657291512
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.95951659
Short name T860
Test name
Test status
Simulation time 66913881 ps
CPU time 0.7 seconds
Started May 05 03:14:26 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 203892 kb
Host smart-d0817362-b04c-413c-8b18-410012aea97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95951
659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.95951659
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.187514442
Short name T1126
Test name
Test status
Simulation time 21149624030 ps
CPU time 42.82 seconds
Started May 05 03:14:28 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204340 kb
Host smart-16740f62-884e-4de1-9e63-50a0704bff55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18751
4442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.187514442
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4223938035
Short name T659
Test name
Test status
Simulation time 8373097092 ps
CPU time 7.94 seconds
Started May 05 03:14:29 PM PDT 24
Finished May 05 03:14:37 PM PDT 24
Peak memory 204124 kb
Host smart-cc0d4877-539d-450a-8599-8b336785b5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42239
38035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4223938035
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.357496580
Short name T156
Test name
Test status
Simulation time 8454548924 ps
CPU time 7.64 seconds
Started May 05 03:14:27 PM PDT 24
Finished May 05 03:14:35 PM PDT 24
Peak memory 204104 kb
Host smart-9d8d4724-6ec6-4f0b-be77-6cfeba24dfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35749
6580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.357496580
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1751426097
Short name T216
Test name
Test status
Simulation time 8422674160 ps
CPU time 8.22 seconds
Started May 05 03:14:27 PM PDT 24
Finished May 05 03:14:36 PM PDT 24
Peak memory 204144 kb
Host smart-4b37379a-0a59-4d65-9a38-3cfd082174be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17514
26097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1751426097
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2046786773
Short name T81
Test name
Test status
Simulation time 8387348916 ps
CPU time 7.93 seconds
Started May 05 03:14:27 PM PDT 24
Finished May 05 03:14:36 PM PDT 24
Peak memory 204100 kb
Host smart-8ecd7b34-3fb0-453f-bdbe-9789aa28d058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
86773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2046786773
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3492996099
Short name T945
Test name
Test status
Simulation time 8373544575 ps
CPU time 8.32 seconds
Started May 05 03:14:31 PM PDT 24
Finished May 05 03:14:40 PM PDT 24
Peak memory 204000 kb
Host smart-4ac8f1af-8a16-45e1-8276-65d2fa981831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
96099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3492996099
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1048517481
Short name T448
Test name
Test status
Simulation time 8508072879 ps
CPU time 8.99 seconds
Started May 05 03:14:22 PM PDT 24
Finished May 05 03:14:32 PM PDT 24
Peak memory 204120 kb
Host smart-7004c2f8-8278-4e3c-a266-f990c3ef5655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485
17481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1048517481
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3391935943
Short name T1148
Test name
Test status
Simulation time 8389326753 ps
CPU time 7.78 seconds
Started May 05 03:14:27 PM PDT 24
Finished May 05 03:14:36 PM PDT 24
Peak memory 204096 kb
Host smart-55f30adf-d800-44ee-a8bc-bbce2a84a829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
35943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3391935943
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2754011657
Short name T782
Test name
Test status
Simulation time 8390122873 ps
CPU time 8.23 seconds
Started May 05 03:14:32 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 204080 kb
Host smart-c0b538ad-1ce4-4d8d-819d-5c0c650db43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27540
11657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2754011657
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.300956599
Short name T1222
Test name
Test status
Simulation time 8475114563 ps
CPU time 7.84 seconds
Started May 05 03:14:35 PM PDT 24
Finished May 05 03:14:43 PM PDT 24
Peak memory 204108 kb
Host smart-970b5b98-8722-4a4a-8828-5dd483eb6453
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=300956599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.300956599
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2988433355
Short name T512
Test name
Test status
Simulation time 8383971105 ps
CPU time 9.6 seconds
Started May 05 03:14:34 PM PDT 24
Finished May 05 03:14:44 PM PDT 24
Peak memory 204156 kb
Host smart-a1f88f79-d0ad-4ac8-bf2c-cbac8b667372
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2988433355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2988433355
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.3306003773
Short name T687
Test name
Test status
Simulation time 8436610052 ps
CPU time 9.06 seconds
Started May 05 03:14:35 PM PDT 24
Finished May 05 03:14:45 PM PDT 24
Peak memory 204052 kb
Host smart-7ce707eb-0da3-4151-b354-38c8b3505850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33060
03773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3306003773
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3695526123
Short name T328
Test name
Test status
Simulation time 8385787348 ps
CPU time 8.41 seconds
Started May 05 03:14:37 PM PDT 24
Finished May 05 03:14:46 PM PDT 24
Peak memory 204000 kb
Host smart-7cfa8089-c664-452b-ac40-31c4f7b5cb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
26123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3695526123
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.200417362
Short name T829
Test name
Test status
Simulation time 8408076277 ps
CPU time 8.02 seconds
Started May 05 03:14:30 PM PDT 24
Finished May 05 03:14:38 PM PDT 24
Peak memory 204096 kb
Host smart-ac3c3e13-7109-4078-a720-8c6583fb3db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20041
7362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.200417362
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1792568489
Short name T428
Test name
Test status
Simulation time 179253288 ps
CPU time 2.11 seconds
Started May 05 03:14:31 PM PDT 24
Finished May 05 03:14:33 PM PDT 24
Peak memory 204172 kb
Host smart-3bf2fe13-e2b7-4d77-98e2-5a31e5fd124a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17925
68489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1792568489
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2049016308
Short name T751
Test name
Test status
Simulation time 8402846531 ps
CPU time 7.44 seconds
Started May 05 03:14:35 PM PDT 24
Finished May 05 03:14:43 PM PDT 24
Peak memory 204164 kb
Host smart-938d0967-4030-4187-8677-7570478bb97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
16308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2049016308
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3506455762
Short name T1102
Test name
Test status
Simulation time 8368588956 ps
CPU time 7.66 seconds
Started May 05 03:14:36 PM PDT 24
Finished May 05 03:14:45 PM PDT 24
Peak memory 204112 kb
Host smart-c367d1e9-f6e5-4e2f-928f-566451caadd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35064
55762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3506455762
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3394547336
Short name T1051
Test name
Test status
Simulation time 8465061667 ps
CPU time 8.5 seconds
Started May 05 03:14:31 PM PDT 24
Finished May 05 03:14:40 PM PDT 24
Peak memory 204128 kb
Host smart-dd4411c3-7b38-49c6-a248-e36bba554570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
47336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3394547336
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3342572668
Short name T86
Test name
Test status
Simulation time 8418393665 ps
CPU time 8.47 seconds
Started May 05 03:14:37 PM PDT 24
Finished May 05 03:14:46 PM PDT 24
Peak memory 204016 kb
Host smart-cff16bb7-75d2-4497-9f32-84c59a8cfd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
72668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3342572668
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2005980757
Short name T523
Test name
Test status
Simulation time 8368296391 ps
CPU time 8.03 seconds
Started May 05 03:14:33 PM PDT 24
Finished May 05 03:14:42 PM PDT 24
Peak memory 204060 kb
Host smart-ebdff47c-cf14-433a-8bda-3e77de7ddb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20059
80757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2005980757
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3631508039
Short name T682
Test name
Test status
Simulation time 8407012553 ps
CPU time 7.85 seconds
Started May 05 03:14:32 PM PDT 24
Finished May 05 03:14:40 PM PDT 24
Peak memory 204080 kb
Host smart-0394c25d-eee1-41e6-8a30-083e22e7097a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315
08039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3631508039
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1437056150
Short name T377
Test name
Test status
Simulation time 8420031611 ps
CPU time 7.96 seconds
Started May 05 03:14:38 PM PDT 24
Finished May 05 03:14:47 PM PDT 24
Peak memory 204000 kb
Host smart-dae1ef9e-ed27-4f29-b73f-a35f936be724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14370
56150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1437056150
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2731533129
Short name T1077
Test name
Test status
Simulation time 8410087581 ps
CPU time 8.57 seconds
Started May 05 03:14:34 PM PDT 24
Finished May 05 03:14:43 PM PDT 24
Peak memory 204120 kb
Host smart-f89c4683-d444-41b7-9b5e-902183338382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
33129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2731533129
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2425807695
Short name T498
Test name
Test status
Simulation time 35767975 ps
CPU time 0.63 seconds
Started May 05 03:14:37 PM PDT 24
Finished May 05 03:14:38 PM PDT 24
Peak memory 203940 kb
Host smart-5e2616e1-8c2e-49e7-9f31-fa1300bb5d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24258
07695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2425807695
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1572844197
Short name T12
Test name
Test status
Simulation time 27193856402 ps
CPU time 52.35 seconds
Started May 05 03:14:38 PM PDT 24
Finished May 05 03:15:31 PM PDT 24
Peak memory 204372 kb
Host smart-b2214b42-12ef-4c21-857d-4cbeca82de37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15728
44197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1572844197
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2818995948
Short name T610
Test name
Test status
Simulation time 8404014353 ps
CPU time 8.24 seconds
Started May 05 03:14:34 PM PDT 24
Finished May 05 03:14:43 PM PDT 24
Peak memory 204100 kb
Host smart-8adb303b-a9a0-49a1-80f6-699165f47929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
95948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2818995948
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3524131366
Short name T1086
Test name
Test status
Simulation time 8437179888 ps
CPU time 8.17 seconds
Started May 05 03:14:35 PM PDT 24
Finished May 05 03:14:44 PM PDT 24
Peak memory 204076 kb
Host smart-fb37ef39-3406-445a-81bf-58e0401d1b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35241
31366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3524131366
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3503090555
Short name T1180
Test name
Test status
Simulation time 8415789726 ps
CPU time 7.72 seconds
Started May 05 03:14:39 PM PDT 24
Finished May 05 03:14:47 PM PDT 24
Peak memory 204084 kb
Host smart-64d19fca-3e59-4704-9244-ad6d02b2225c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35030
90555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3503090555
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1614155561
Short name T859
Test name
Test status
Simulation time 8386567951 ps
CPU time 8.95 seconds
Started May 05 03:14:35 PM PDT 24
Finished May 05 03:14:44 PM PDT 24
Peak memory 204020 kb
Host smart-49417d16-575d-417a-afac-16afcd0ae202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
55561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1614155561
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3428457875
Short name T441
Test name
Test status
Simulation time 8415513745 ps
CPU time 7.62 seconds
Started May 05 03:14:36 PM PDT 24
Finished May 05 03:14:44 PM PDT 24
Peak memory 204064 kb
Host smart-ef9ed916-9a25-4659-b540-08f2c0ce0205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34284
57875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3428457875
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3109246651
Short name T1373
Test name
Test status
Simulation time 8451499204 ps
CPU time 7.95 seconds
Started May 05 03:14:34 PM PDT 24
Finished May 05 03:14:43 PM PDT 24
Peak memory 204100 kb
Host smart-faaa92ff-407a-4b17-84f6-f10bf2c3292c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31092
46651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3109246651
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.764271161
Short name T226
Test name
Test status
Simulation time 8393964145 ps
CPU time 10.14 seconds
Started May 05 03:14:36 PM PDT 24
Finished May 05 03:14:47 PM PDT 24
Peak memory 204100 kb
Host smart-5e733e49-15e0-4c5f-ba7c-0ee16045c333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76427
1161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.764271161
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1983379836
Short name T85
Test name
Test status
Simulation time 8424178679 ps
CPU time 8.02 seconds
Started May 05 03:14:38 PM PDT 24
Finished May 05 03:14:46 PM PDT 24
Peak memory 204084 kb
Host smart-56c51b39-8081-44d0-858f-d291d9b19412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
79836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1983379836
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2936974405
Short name T941
Test name
Test status
Simulation time 8463776538 ps
CPU time 8.01 seconds
Started May 05 03:11:46 PM PDT 24
Finished May 05 03:11:54 PM PDT 24
Peak memory 204080 kb
Host smart-d7b1b36f-b947-4500-861b-e89c8533755e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2936974405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2936974405
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.2593037487
Short name T1080
Test name
Test status
Simulation time 8373873158 ps
CPU time 8.23 seconds
Started May 05 03:11:48 PM PDT 24
Finished May 05 03:11:57 PM PDT 24
Peak memory 204112 kb
Host smart-548152ee-32fd-42d2-977b-8cb5a6086406
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2593037487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.2593037487
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.2395382758
Short name T516
Test name
Test status
Simulation time 8460506579 ps
CPU time 7.83 seconds
Started May 05 03:11:47 PM PDT 24
Finished May 05 03:11:56 PM PDT 24
Peak memory 204064 kb
Host smart-5f33dfdc-6a6f-4459-b3ed-26d426118bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953
82758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.2395382758
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1937669926
Short name T771
Test name
Test status
Simulation time 8382045723 ps
CPU time 8.93 seconds
Started May 05 03:11:35 PM PDT 24
Finished May 05 03:11:45 PM PDT 24
Peak memory 204088 kb
Host smart-85e77d1c-c7c6-4e22-a73f-9f4b2f2104fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376
69926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1937669926
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.3577212234
Short name T373
Test name
Test status
Simulation time 8373974411 ps
CPU time 7.89 seconds
Started May 05 03:11:38 PM PDT 24
Finished May 05 03:11:47 PM PDT 24
Peak memory 204112 kb
Host smart-3f2ffcc2-f4b0-462d-a632-5a14204c257b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
12234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3577212234
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2042561148
Short name T822
Test name
Test status
Simulation time 43068765 ps
CPU time 1.28 seconds
Started May 05 03:11:35 PM PDT 24
Finished May 05 03:11:37 PM PDT 24
Peak memory 204256 kb
Host smart-b232a152-18b8-45f2-ac67-8ca23a991c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425
61148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2042561148
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2752104582
Short name T1237
Test name
Test status
Simulation time 8400615185 ps
CPU time 8.69 seconds
Started May 05 03:11:45 PM PDT 24
Finished May 05 03:11:54 PM PDT 24
Peak memory 204116 kb
Host smart-adf57435-ec0b-4f34-a9b2-234b9dad280e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27521
04582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2752104582
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1852737822
Short name T201
Test name
Test status
Simulation time 8364047090 ps
CPU time 8.12 seconds
Started May 05 03:11:45 PM PDT 24
Finished May 05 03:11:54 PM PDT 24
Peak memory 204144 kb
Host smart-9d6db98e-ab4a-4b94-ad9d-79bc0228afbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18527
37822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1852737822
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1923215953
Short name T529
Test name
Test status
Simulation time 8446566886 ps
CPU time 10.35 seconds
Started May 05 03:11:38 PM PDT 24
Finished May 05 03:11:48 PM PDT 24
Peak memory 204036 kb
Host smart-1e0712ca-28c1-42bf-adfd-26b0e0430a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19232
15953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1923215953
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4154966117
Short name T1070
Test name
Test status
Simulation time 8456931750 ps
CPU time 9.27 seconds
Started May 05 03:11:35 PM PDT 24
Finished May 05 03:11:44 PM PDT 24
Peak memory 204080 kb
Host smart-8a63f312-48ac-4e7a-8ea2-56ae607b6dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41549
66117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4154966117
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.815360416
Short name T1285
Test name
Test status
Simulation time 8377730904 ps
CPU time 8.15 seconds
Started May 05 03:11:36 PM PDT 24
Finished May 05 03:11:45 PM PDT 24
Peak memory 204096 kb
Host smart-96c72a1a-72fe-4f72-9a40-6eb68903c77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81536
0416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.815360416
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2624608439
Short name T1162
Test name
Test status
Simulation time 8405668332 ps
CPU time 8.85 seconds
Started May 05 03:11:37 PM PDT 24
Finished May 05 03:11:47 PM PDT 24
Peak memory 204036 kb
Host smart-5ef9d3b6-2af4-4491-b593-25074714cb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
08439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2624608439
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2394914016
Short name T1095
Test name
Test status
Simulation time 8403716196 ps
CPU time 10.14 seconds
Started May 05 03:11:37 PM PDT 24
Finished May 05 03:11:48 PM PDT 24
Peak memory 204064 kb
Host smart-63d63ad9-d635-41d2-a8db-c20593ed53fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23949
14016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2394914016
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3643651846
Short name T185
Test name
Test status
Simulation time 8379229157 ps
CPU time 7.76 seconds
Started May 05 03:11:43 PM PDT 24
Finished May 05 03:11:51 PM PDT 24
Peak memory 204072 kb
Host smart-29e54ccd-17a1-42db-b528-0bcecff67a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
51846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3643651846
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2970678762
Short name T723
Test name
Test status
Simulation time 8364652810 ps
CPU time 7.2 seconds
Started May 05 03:11:41 PM PDT 24
Finished May 05 03:11:48 PM PDT 24
Peak memory 204120 kb
Host smart-1ed03787-43d3-4644-bdb4-3f868c5ca945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
78762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2970678762
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3963202097
Short name T47
Test name
Test status
Simulation time 145449996 ps
CPU time 0.78 seconds
Started May 05 03:11:46 PM PDT 24
Finished May 05 03:11:47 PM PDT 24
Peak memory 204040 kb
Host smart-bddbca9c-37b2-48ab-8fe5-b848114954b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39632
02097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3963202097
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1869686226
Short name T625
Test name
Test status
Simulation time 23138753999 ps
CPU time 46.02 seconds
Started May 05 03:11:40 PM PDT 24
Finished May 05 03:12:26 PM PDT 24
Peak memory 204384 kb
Host smart-86f94d4f-5875-41aa-8122-17d814d7258c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18696
86226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1869686226
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1656356755
Short name T1259
Test name
Test status
Simulation time 8394405429 ps
CPU time 7.94 seconds
Started May 05 03:11:42 PM PDT 24
Finished May 05 03:11:50 PM PDT 24
Peak memory 204128 kb
Host smart-d682327d-3ecd-4e58-9b56-bac7629f7045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16563
56755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1656356755
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2247006723
Short name T869
Test name
Test status
Simulation time 8451427808 ps
CPU time 8.1 seconds
Started May 05 03:11:40 PM PDT 24
Finished May 05 03:11:49 PM PDT 24
Peak memory 204036 kb
Host smart-7b66cdb2-7ddb-49bb-8833-69bbc557fe2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22470
06723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2247006723
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.2904263322
Short name T527
Test name
Test status
Simulation time 8405436738 ps
CPU time 7.76 seconds
Started May 05 03:11:41 PM PDT 24
Finished May 05 03:11:49 PM PDT 24
Peak memory 204144 kb
Host smart-928be4fb-9be6-4953-a0a1-7aab6cb87375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29042
63322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.2904263322
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1046770212
Short name T65
Test name
Test status
Simulation time 1025136029 ps
CPU time 1.78 seconds
Started May 05 03:11:50 PM PDT 24
Finished May 05 03:11:52 PM PDT 24
Peak memory 221564 kb
Host smart-b0a7d1e5-f31f-42a8-8190-178b32ce8435
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1046770212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1046770212
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3892233225
Short name T172
Test name
Test status
Simulation time 8376115292 ps
CPU time 7.95 seconds
Started May 05 03:11:42 PM PDT 24
Finished May 05 03:11:50 PM PDT 24
Peak memory 204100 kb
Host smart-b3ada642-7e82-44f4-bd8d-fa719888a3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
33225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3892233225
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.874316927
Short name T1094
Test name
Test status
Simulation time 8365107734 ps
CPU time 8.12 seconds
Started May 05 03:11:41 PM PDT 24
Finished May 05 03:11:50 PM PDT 24
Peak memory 204076 kb
Host smart-c2cb2bf5-c5ba-46bb-8f52-4dd5286e9d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87431
6927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.874316927
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.124595524
Short name T167
Test name
Test status
Simulation time 8454216507 ps
CPU time 8.72 seconds
Started May 05 03:11:36 PM PDT 24
Finished May 05 03:11:45 PM PDT 24
Peak memory 204140 kb
Host smart-0996e24d-33c6-4744-9b46-d905c60d77ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12459
5524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.124595524
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.224873639
Short name T703
Test name
Test status
Simulation time 8394736122 ps
CPU time 7.74 seconds
Started May 05 03:11:40 PM PDT 24
Finished May 05 03:11:48 PM PDT 24
Peak memory 204080 kb
Host smart-4a90faf4-759b-46dc-96ef-f8f56f23ae4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
3639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.224873639
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2636056158
Short name T1186
Test name
Test status
Simulation time 8400278153 ps
CPU time 7.93 seconds
Started May 05 03:11:45 PM PDT 24
Finished May 05 03:11:53 PM PDT 24
Peak memory 204096 kb
Host smart-995e4d7a-3430-4178-af68-280acac8285d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26360
56158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2636056158
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.233419086
Short name T473
Test name
Test status
Simulation time 8514423066 ps
CPU time 7.79 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:02 PM PDT 24
Peak memory 204092 kb
Host smart-65ff595b-4d30-42f5-a18e-48709c2a80be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=233419086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.233419086
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.3790554711
Short name T1135
Test name
Test status
Simulation time 8378686444 ps
CPU time 8.47 seconds
Started May 05 03:14:50 PM PDT 24
Finished May 05 03:14:59 PM PDT 24
Peak memory 204148 kb
Host smart-f015aeeb-548d-4f22-b42b-535253daf89b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3790554711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.3790554711
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.4099034622
Short name T1154
Test name
Test status
Simulation time 8462764679 ps
CPU time 8.26 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:02 PM PDT 24
Peak memory 204092 kb
Host smart-5b91d769-cc4a-439b-b3ae-a93db67db847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40990
34622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.4099034622
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3581776749
Short name T82
Test name
Test status
Simulation time 8378408877 ps
CPU time 8.81 seconds
Started May 05 03:14:39 PM PDT 24
Finished May 05 03:14:48 PM PDT 24
Peak memory 204040 kb
Host smart-8c0f598f-3fbc-419e-ba9d-2e2671b10114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35817
76749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3581776749
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.357952832
Short name T56
Test name
Test status
Simulation time 8380300290 ps
CPU time 10.02 seconds
Started May 05 03:14:41 PM PDT 24
Finished May 05 03:14:51 PM PDT 24
Peak memory 204088 kb
Host smart-1961309f-f063-42f0-9c12-681793945cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
2832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.357952832
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2537485553
Short name T828
Test name
Test status
Simulation time 52332933 ps
CPU time 1.36 seconds
Started May 05 03:14:39 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 204204 kb
Host smart-d930394e-5efc-4610-ab84-804fa8f6d450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25374
85553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2537485553
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3143796156
Short name T1371
Test name
Test status
Simulation time 8459245491 ps
CPU time 7.4 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:01 PM PDT 24
Peak memory 204088 kb
Host smart-6c0a5ae9-043b-4ab6-aff4-8013d503044e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31437
96156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3143796156
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3248862582
Short name T7
Test name
Test status
Simulation time 8373132245 ps
CPU time 7.77 seconds
Started May 05 03:14:48 PM PDT 24
Finished May 05 03:14:57 PM PDT 24
Peak memory 204132 kb
Host smart-ec29d090-2b7e-4c2c-a8d9-b3a531efd05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32488
62582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3248862582
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1197628330
Short name T668
Test name
Test status
Simulation time 8419933981 ps
CPU time 7.93 seconds
Started May 05 03:14:46 PM PDT 24
Finished May 05 03:14:54 PM PDT 24
Peak memory 204108 kb
Host smart-40e71b90-6fc6-47f6-968a-b0096279e159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11976
28330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1197628330
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1763943719
Short name T754
Test name
Test status
Simulation time 8418911642 ps
CPU time 7.48 seconds
Started May 05 03:14:43 PM PDT 24
Finished May 05 03:14:51 PM PDT 24
Peak memory 204020 kb
Host smart-fdc5c7c4-e22d-4d2f-ad8b-db5c977020b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17639
43719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1763943719
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3152211404
Short name T229
Test name
Test status
Simulation time 8482602028 ps
CPU time 7.86 seconds
Started May 05 03:14:47 PM PDT 24
Finished May 05 03:14:55 PM PDT 24
Peak memory 204164 kb
Host smart-38ab007c-fe9b-4ec8-a6f5-a897acd9020f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31522
11404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3152211404
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2735858343
Short name T299
Test name
Test status
Simulation time 8382671661 ps
CPU time 7.79 seconds
Started May 05 03:14:43 PM PDT 24
Finished May 05 03:14:52 PM PDT 24
Peak memory 204104 kb
Host smart-bcaec907-0a70-44d6-8fba-9cb693746512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27358
58343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2735858343
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.86290874
Short name T1109
Test name
Test status
Simulation time 8393377542 ps
CPU time 7.84 seconds
Started May 05 03:14:49 PM PDT 24
Finished May 05 03:14:57 PM PDT 24
Peak memory 204060 kb
Host smart-86d7827c-717f-4d23-b410-25a81de0da27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86290
874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.86290874
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1054174163
Short name T672
Test name
Test status
Simulation time 8367065710 ps
CPU time 8.89 seconds
Started May 05 03:14:45 PM PDT 24
Finished May 05 03:14:54 PM PDT 24
Peak memory 204284 kb
Host smart-9efbb558-2a93-4aa2-bd22-7b00477b7ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10541
74163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1054174163
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3124048601
Short name T44
Test name
Test status
Simulation time 35034906 ps
CPU time 0.66 seconds
Started May 05 03:14:49 PM PDT 24
Finished May 05 03:14:50 PM PDT 24
Peak memory 203940 kb
Host smart-632fa7cd-3a6d-4b3f-a59b-f5d9debdfa3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240
48601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3124048601
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3777880362
Short name T915
Test name
Test status
Simulation time 15148004143 ps
CPU time 29.98 seconds
Started May 05 03:14:46 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204420 kb
Host smart-6db18440-685b-4b9a-a126-60c1caa5e925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37778
80362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3777880362
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3374076640
Short name T1238
Test name
Test status
Simulation time 8443400987 ps
CPU time 9.26 seconds
Started May 05 03:14:49 PM PDT 24
Finished May 05 03:14:59 PM PDT 24
Peak memory 204064 kb
Host smart-02a9279a-b2e0-46cc-a0c6-27913c9bb289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740
76640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3374076640
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3238798138
Short name T88
Test name
Test status
Simulation time 8396421704 ps
CPU time 7.82 seconds
Started May 05 03:14:44 PM PDT 24
Finished May 05 03:14:52 PM PDT 24
Peak memory 204072 kb
Host smart-a3bbdbbc-dff0-4012-96a8-951f59effe25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
98138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3238798138
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2319758995
Short name T831
Test name
Test status
Simulation time 8374805813 ps
CPU time 7.69 seconds
Started May 05 03:14:46 PM PDT 24
Finished May 05 03:14:54 PM PDT 24
Peak memory 204052 kb
Host smart-2a8e0d8e-c3ba-44e3-9258-bc280389a3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23197
58995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2319758995
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.455407544
Short name T510
Test name
Test status
Simulation time 8366678471 ps
CPU time 7.92 seconds
Started May 05 03:14:49 PM PDT 24
Finished May 05 03:14:58 PM PDT 24
Peak memory 204064 kb
Host smart-95778d56-4bd8-4b81-a007-b00f5f815d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45540
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.455407544
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3167672755
Short name T1256
Test name
Test status
Simulation time 8427640848 ps
CPU time 9.02 seconds
Started May 05 03:14:39 PM PDT 24
Finished May 05 03:14:48 PM PDT 24
Peak memory 204116 kb
Host smart-c9dcb1c6-2ca1-4c8a-88f0-c08f117a2039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
72755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3167672755
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3952052897
Short name T1353
Test name
Test status
Simulation time 8384648959 ps
CPU time 9.49 seconds
Started May 05 03:14:45 PM PDT 24
Finished May 05 03:14:55 PM PDT 24
Peak memory 204124 kb
Host smart-d7b4921b-f482-4dcd-b0d8-df87f5a93ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39520
52897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3952052897
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.219098941
Short name T403
Test name
Test status
Simulation time 8394881817 ps
CPU time 8.04 seconds
Started May 05 03:14:45 PM PDT 24
Finished May 05 03:14:54 PM PDT 24
Peak memory 204132 kb
Host smart-2e503891-809d-43ae-abc9-4275833e125c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21909
8941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.219098941
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.343950655
Short name T347
Test name
Test status
Simulation time 8464513721 ps
CPU time 8.4 seconds
Started May 05 03:14:55 PM PDT 24
Finished May 05 03:15:04 PM PDT 24
Peak memory 204112 kb
Host smart-39fd95e3-815a-4da4-9aa5-ef13273337e1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=343950655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.343950655
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.1887196516
Short name T818
Test name
Test status
Simulation time 8381123251 ps
CPU time 9.16 seconds
Started May 05 03:14:54 PM PDT 24
Finished May 05 03:15:04 PM PDT 24
Peak memory 204064 kb
Host smart-624643eb-4463-4f7d-b201-6ab18ff5de8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1887196516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.1887196516
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.2624654127
Short name T736
Test name
Test status
Simulation time 8399693984 ps
CPU time 7.69 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:02 PM PDT 24
Peak memory 204108 kb
Host smart-4d461f7a-6a6d-43a6-aaf7-37a2867779e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
54127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.2624654127
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2790438389
Short name T762
Test name
Test status
Simulation time 8377896233 ps
CPU time 10.06 seconds
Started May 05 03:14:48 PM PDT 24
Finished May 05 03:14:59 PM PDT 24
Peak memory 204044 kb
Host smart-fc909d01-07dd-4250-b2b0-8d2d10bc5a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27904
38389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2790438389
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.3576762840
Short name T468
Test name
Test status
Simulation time 8439314976 ps
CPU time 7.47 seconds
Started May 05 03:14:48 PM PDT 24
Finished May 05 03:14:56 PM PDT 24
Peak memory 204092 kb
Host smart-726fdfbd-e0a3-40bb-8d53-1d2eeb1faca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
62840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3576762840
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1586736720
Short name T1036
Test name
Test status
Simulation time 121844141 ps
CPU time 1.47 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:00 PM PDT 24
Peak memory 204248 kb
Host smart-7cc5f540-bc41-4180-93df-76cf17bb104f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
36720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1586736720
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1979849764
Short name T414
Test name
Test status
Simulation time 8424970946 ps
CPU time 8.46 seconds
Started May 05 03:14:54 PM PDT 24
Finished May 05 03:15:03 PM PDT 24
Peak memory 204136 kb
Host smart-39c99fbc-6f77-4ac9-b830-7e18fc304505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19798
49764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1979849764
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1502939117
Short name T434
Test name
Test status
Simulation time 8417475026 ps
CPU time 9.72 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:04 PM PDT 24
Peak memory 204112 kb
Host smart-6f6f4a9a-8802-4109-b1a6-a2caf798b832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15029
39117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1502939117
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3032574534
Short name T475
Test name
Test status
Simulation time 8421429444 ps
CPU time 9.79 seconds
Started May 05 03:14:48 PM PDT 24
Finished May 05 03:14:59 PM PDT 24
Peak memory 204124 kb
Host smart-d39e6e80-0058-443d-b219-24d6f468f378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30325
74534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3032574534
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.729574916
Short name T1037
Test name
Test status
Simulation time 8416631767 ps
CPU time 9.7 seconds
Started May 05 03:14:47 PM PDT 24
Finished May 05 03:14:57 PM PDT 24
Peak memory 204128 kb
Host smart-b242b381-1a03-4174-b021-edf5ff69916a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72957
4916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.729574916
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.551771695
Short name T709
Test name
Test status
Simulation time 8370041219 ps
CPU time 8.93 seconds
Started May 05 03:14:49 PM PDT 24
Finished May 05 03:14:59 PM PDT 24
Peak memory 204096 kb
Host smart-f47279dd-6b86-4621-b2e1-0f51a603cdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55177
1695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.551771695
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1148887324
Short name T225
Test name
Test status
Simulation time 8408226435 ps
CPU time 7.66 seconds
Started May 05 03:14:48 PM PDT 24
Finished May 05 03:14:56 PM PDT 24
Peak memory 204164 kb
Host smart-4d570a3f-9e18-4fc3-bfc1-afe4e7ba7722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11488
87324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1148887324
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1864125554
Short name T1334
Test name
Test status
Simulation time 8389996937 ps
CPU time 10.36 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:09 PM PDT 24
Peak memory 204120 kb
Host smart-4057a2b6-32ea-4b86-a9a3-927b22877638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18641
25554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1864125554
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.492108962
Short name T675
Test name
Test status
Simulation time 8384510611 ps
CPU time 7.74 seconds
Started May 05 03:14:52 PM PDT 24
Finished May 05 03:15:00 PM PDT 24
Peak memory 204084 kb
Host smart-a7501f03-4a52-4ecb-90d8-649cc3315e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49210
8962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.492108962
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1254465837
Short name T914
Test name
Test status
Simulation time 8393568442 ps
CPU time 7.47 seconds
Started May 05 03:14:55 PM PDT 24
Finished May 05 03:15:03 PM PDT 24
Peak memory 204080 kb
Host smart-1c1620d1-1ab8-47e0-a068-d84805b52022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544
65837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1254465837
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1238738370
Short name T10
Test name
Test status
Simulation time 8376696155 ps
CPU time 9.2 seconds
Started May 05 03:14:52 PM PDT 24
Finished May 05 03:15:02 PM PDT 24
Peak memory 204092 kb
Host smart-9aa7d52f-f1c5-496f-9226-01c59cb6ca40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12387
38370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1238738370
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2375593171
Short name T975
Test name
Test status
Simulation time 50737016 ps
CPU time 0.68 seconds
Started May 05 03:14:55 PM PDT 24
Finished May 05 03:14:56 PM PDT 24
Peak memory 203968 kb
Host smart-35eb9ca2-e8f7-40b3-a181-1e61d16c1a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23755
93171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2375593171
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2862579149
Short name T961
Test name
Test status
Simulation time 27815982871 ps
CPU time 53.2 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:52 PM PDT 24
Peak memory 204404 kb
Host smart-7c62bc77-84b8-4b50-b60b-121937ccb391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28625
79149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2862579149
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2828950253
Short name T312
Test name
Test status
Simulation time 8387001501 ps
CPU time 7.83 seconds
Started May 05 03:14:52 PM PDT 24
Finished May 05 03:15:01 PM PDT 24
Peak memory 204064 kb
Host smart-c39bdfe0-7086-46a8-b31a-cf3ad9d5b891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28289
50253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2828950253
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2704034739
Short name T1346
Test name
Test status
Simulation time 8470098993 ps
CPU time 8.13 seconds
Started May 05 03:14:53 PM PDT 24
Finished May 05 03:15:02 PM PDT 24
Peak memory 204100 kb
Host smart-0511abb7-52cd-4a0c-8d4b-5a8d0f1f1bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27040
34739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2704034739
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.864318050
Short name T521
Test name
Test status
Simulation time 8378463185 ps
CPU time 7.64 seconds
Started May 05 03:14:54 PM PDT 24
Finished May 05 03:15:02 PM PDT 24
Peak memory 204144 kb
Host smart-f90d102c-001e-49a3-834f-af411fd404ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86431
8050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.864318050
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3075360173
Short name T52
Test name
Test status
Simulation time 8371653280 ps
CPU time 8.58 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:07 PM PDT 24
Peak memory 204112 kb
Host smart-37757261-3134-4c6b-a0e3-503682f595e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
60173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3075360173
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.624113303
Short name T581
Test name
Test status
Simulation time 8374687095 ps
CPU time 7.52 seconds
Started May 05 03:14:55 PM PDT 24
Finished May 05 03:15:03 PM PDT 24
Peak memory 204108 kb
Host smart-d31d3f97-fb78-47cd-a2bb-4c6db51aa615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62411
3303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.624113303
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2167413952
Short name T579
Test name
Test status
Simulation time 8375550013 ps
CPU time 8.95 seconds
Started May 05 03:14:52 PM PDT 24
Finished May 05 03:15:01 PM PDT 24
Peak memory 204052 kb
Host smart-0fd5f7dc-825c-4200-851f-5b421f085d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21674
13952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2167413952
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2336630693
Short name T647
Test name
Test status
Simulation time 8369063104 ps
CPU time 10.3 seconds
Started May 05 03:14:54 PM PDT 24
Finished May 05 03:15:05 PM PDT 24
Peak memory 204084 kb
Host smart-789aef60-019f-4c2b-be04-3e5cdbfd3981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23366
30693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2336630693
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.76954683
Short name T247
Test name
Test status
Simulation time 8464966391 ps
CPU time 7.61 seconds
Started May 05 03:15:03 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204076 kb
Host smart-ec7ab671-350e-4ba1-b13f-f5c3b62a98e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=76954683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.76954683
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3787216950
Short name T1316
Test name
Test status
Simulation time 8397633305 ps
CPU time 8.01 seconds
Started May 05 03:15:08 PM PDT 24
Finished May 05 03:15:16 PM PDT 24
Peak memory 204104 kb
Host smart-ac0fb0a3-d068-4433-9819-705f7fe73623
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3787216950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3787216950
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.3006553589
Short name T465
Test name
Test status
Simulation time 8423495146 ps
CPU time 8.24 seconds
Started May 05 03:15:03 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204100 kb
Host smart-5fd8bacd-0b6a-4838-8158-c34330f73725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30065
53589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.3006553589
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4037798010
Short name T301
Test name
Test status
Simulation time 8391200621 ps
CPU time 8.23 seconds
Started May 05 03:14:59 PM PDT 24
Finished May 05 03:15:08 PM PDT 24
Peak memory 204052 kb
Host smart-2e746212-bdf8-4526-bd4d-b6bb519269a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
98010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4037798010
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.3498788966
Short name T511
Test name
Test status
Simulation time 8382253969 ps
CPU time 8.05 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:06 PM PDT 24
Peak memory 204072 kb
Host smart-c996bdd8-55ec-4a23-884e-784c721b5191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34987
88966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3498788966
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2472527913
Short name T1159
Test name
Test status
Simulation time 67422480 ps
CPU time 1.48 seconds
Started May 05 03:14:57 PM PDT 24
Finished May 05 03:14:59 PM PDT 24
Peak memory 204124 kb
Host smart-58ad354c-e39f-472e-88cc-c75a4e8c6d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24725
27913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2472527913
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1215309443
Short name T586
Test name
Test status
Simulation time 8434953031 ps
CPU time 8.72 seconds
Started May 05 03:15:04 PM PDT 24
Finished May 05 03:15:14 PM PDT 24
Peak memory 204084 kb
Host smart-ea80dd9b-c737-4c95-a944-a4f9eed0fcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12153
09443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1215309443
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.653354172
Short name T1283
Test name
Test status
Simulation time 8404641680 ps
CPU time 8.1 seconds
Started May 05 03:15:03 PM PDT 24
Finished May 05 03:15:12 PM PDT 24
Peak memory 204108 kb
Host smart-497ee382-1a05-4e01-b724-ea54b399bb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65335
4172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.653354172
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1056527279
Short name T145
Test name
Test status
Simulation time 8403998505 ps
CPU time 9.51 seconds
Started May 05 03:14:59 PM PDT 24
Finished May 05 03:15:09 PM PDT 24
Peak memory 204076 kb
Host smart-33a63eab-c3f2-40b8-ba5d-a1950239c35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
27279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1056527279
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1788314180
Short name T451
Test name
Test status
Simulation time 8424662145 ps
CPU time 8.32 seconds
Started May 05 03:14:59 PM PDT 24
Finished May 05 03:15:08 PM PDT 24
Peak memory 204068 kb
Host smart-073c99f9-ebc9-44eb-8f94-ef413d2fe88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17883
14180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1788314180
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.120132081
Short name T332
Test name
Test status
Simulation time 8365930655 ps
CPU time 7.31 seconds
Started May 05 03:14:57 PM PDT 24
Finished May 05 03:15:05 PM PDT 24
Peak memory 204284 kb
Host smart-8733266e-72a0-4785-b407-66557a50649d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12013
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.120132081
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2727472136
Short name T1124
Test name
Test status
Simulation time 8453168843 ps
CPU time 10.6 seconds
Started May 05 03:14:59 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204064 kb
Host smart-f0a51906-7ec8-458d-8ef1-a8da06e679bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27274
72136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2727472136
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1990449756
Short name T242
Test name
Test status
Simulation time 8407242557 ps
CPU time 8.07 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:07 PM PDT 24
Peak memory 204088 kb
Host smart-c78b60a7-07ff-469a-b8b7-8b03b5c98788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
49756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1990449756
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.651453174
Short name T574
Test name
Test status
Simulation time 8396053124 ps
CPU time 10.13 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:09 PM PDT 24
Peak memory 204124 kb
Host smart-d263a742-8fda-4db0-841e-cedb03586c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65145
3174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.651453174
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2834275402
Short name T1173
Test name
Test status
Simulation time 8378529294 ps
CPU time 7.99 seconds
Started May 05 03:15:02 PM PDT 24
Finished May 05 03:15:10 PM PDT 24
Peak memory 204128 kb
Host smart-045e3acb-600f-4961-a579-327be37596ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342
75402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2834275402
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4103913801
Short name T26
Test name
Test status
Simulation time 8384386470 ps
CPU time 7.63 seconds
Started May 05 03:15:01 PM PDT 24
Finished May 05 03:15:10 PM PDT 24
Peak memory 204128 kb
Host smart-15f08435-7bbe-4c53-b593-a217ce87021f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41039
13801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4103913801
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3282071056
Short name T686
Test name
Test status
Simulation time 74108153 ps
CPU time 0.71 seconds
Started May 05 03:15:02 PM PDT 24
Finished May 05 03:15:04 PM PDT 24
Peak memory 204016 kb
Host smart-1e74754e-44b6-4900-bf98-f462b161272f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
71056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3282071056
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1962622268
Short name T267
Test name
Test status
Simulation time 27123746370 ps
CPU time 52.53 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204372 kb
Host smart-b5e4c3c3-8699-486a-8431-ea7f2d35d675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
22268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1962622268
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1088596847
Short name T481
Test name
Test status
Simulation time 8383542767 ps
CPU time 7.96 seconds
Started May 05 03:14:57 PM PDT 24
Finished May 05 03:15:05 PM PDT 24
Peak memory 204120 kb
Host smart-2e1e4a97-fe41-4a11-acea-57d163a961db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885
96847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1088596847
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1450814475
Short name T988
Test name
Test status
Simulation time 8408930219 ps
CPU time 8.04 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:06 PM PDT 24
Peak memory 204100 kb
Host smart-cd5e9b0d-d2ae-4b8a-adc6-64db74bca0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14508
14475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1450814475
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.249217583
Short name T856
Test name
Test status
Simulation time 8374731390 ps
CPU time 8 seconds
Started May 05 03:14:58 PM PDT 24
Finished May 05 03:15:06 PM PDT 24
Peak memory 204120 kb
Host smart-c6f213ae-1d6f-4fbc-a4e0-cbc668742660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24921
7583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.249217583
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3109339237
Short name T168
Test name
Test status
Simulation time 8398383928 ps
CPU time 7.63 seconds
Started May 05 03:15:07 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204080 kb
Host smart-d39a262b-419e-41ff-afa5-63acf105f889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31093
39237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3109339237
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.968903318
Short name T1127
Test name
Test status
Simulation time 8373478918 ps
CPU time 8.1 seconds
Started May 05 03:15:03 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204124 kb
Host smart-19801871-0372-498d-961e-d1d24c8ceb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96890
3318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.968903318
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.289222637
Short name T938
Test name
Test status
Simulation time 8410318219 ps
CPU time 8.19 seconds
Started May 05 03:14:59 PM PDT 24
Finished May 05 03:15:08 PM PDT 24
Peak memory 204112 kb
Host smart-5e72bbd8-fdd2-4b35-a4a7-ff040cadbbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28922
2637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.289222637
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1247324263
Short name T897
Test name
Test status
Simulation time 8410655478 ps
CPU time 8.7 seconds
Started May 05 03:15:02 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204028 kb
Host smart-984ce32c-bfe5-417d-bab0-0e05aaff82f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12473
24263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1247324263
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.4056795553
Short name T902
Test name
Test status
Simulation time 8390644669 ps
CPU time 7.59 seconds
Started May 05 03:15:03 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204092 kb
Host smart-7f35a69d-8183-44fa-9218-47216cb25978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40567
95553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.4056795553
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.931888639
Short name T821
Test name
Test status
Simulation time 8468297389 ps
CPU time 7.92 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204112 kb
Host smart-f4c63955-8e9d-47b3-b611-10f2e4d2935c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=931888639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.931888639
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.1791936305
Short name T361
Test name
Test status
Simulation time 8389121663 ps
CPU time 8.27 seconds
Started May 05 03:15:08 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204104 kb
Host smart-c754a457-420f-48f6-b3c0-d076ce29a0d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1791936305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.1791936305
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.100641808
Short name T1003
Test name
Test status
Simulation time 8446634735 ps
CPU time 8 seconds
Started May 05 03:15:07 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204104 kb
Host smart-67ccd184-e91f-422b-a258-fb7cd969f7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10064
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.100641808
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3526151744
Short name T1354
Test name
Test status
Simulation time 8393492838 ps
CPU time 8.1 seconds
Started May 05 03:15:02 PM PDT 24
Finished May 05 03:15:11 PM PDT 24
Peak memory 204136 kb
Host smart-79e83cf5-e9fe-490f-94fd-c49a4c8cf517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35261
51744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3526151744
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2151928516
Short name T732
Test name
Test status
Simulation time 8388087066 ps
CPU time 9.65 seconds
Started May 05 03:15:03 PM PDT 24
Finished May 05 03:15:13 PM PDT 24
Peak memory 204144 kb
Host smart-dd62f984-6897-4ee3-bf85-b08d302d8868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21519
28516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2151928516
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1980367697
Short name T478
Test name
Test status
Simulation time 114284323 ps
CPU time 1.41 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:08 PM PDT 24
Peak memory 204212 kb
Host smart-713d0ce8-0079-408b-b7ba-d401a424b1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
67697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1980367697
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2662359654
Short name T810
Test name
Test status
Simulation time 8387381863 ps
CPU time 8.7 seconds
Started May 05 03:15:07 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204128 kb
Host smart-1ac5665b-b2c4-4bde-9272-6be81bf79c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26623
59654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2662359654
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3655778373
Short name T817
Test name
Test status
Simulation time 8368520025 ps
CPU time 7.75 seconds
Started May 05 03:15:13 PM PDT 24
Finished May 05 03:15:22 PM PDT 24
Peak memory 204084 kb
Host smart-310af4fc-2987-4a82-be4c-24d18c628061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36557
78373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3655778373
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3657467694
Short name T423
Test name
Test status
Simulation time 8413400660 ps
CPU time 7.86 seconds
Started May 05 03:15:02 PM PDT 24
Finished May 05 03:15:10 PM PDT 24
Peak memory 204036 kb
Host smart-2ce53afb-c5e6-4348-b866-145b7a4f25b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
67694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3657467694
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1483193992
Short name T710
Test name
Test status
Simulation time 8417342131 ps
CPU time 9.24 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204024 kb
Host smart-5be63bfb-407d-4fb4-9c36-87118f3fce91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
93992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1483193992
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4210091214
Short name T245
Test name
Test status
Simulation time 8368770537 ps
CPU time 8.84 seconds
Started May 05 03:15:05 PM PDT 24
Finished May 05 03:15:14 PM PDT 24
Peak memory 204032 kb
Host smart-dbd42da6-ee2b-4435-93bc-86a68de9dc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42100
91214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4210091214
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2417463764
Short name T130
Test name
Test status
Simulation time 8426946558 ps
CPU time 7.78 seconds
Started May 05 03:15:13 PM PDT 24
Finished May 05 03:15:21 PM PDT 24
Peak memory 204084 kb
Host smart-ff5c67cb-9574-4688-b9af-fb9cce2ca326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24174
63764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2417463764
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2639139801
Short name T462
Test name
Test status
Simulation time 8391509181 ps
CPU time 7.51 seconds
Started May 05 03:15:09 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204100 kb
Host smart-8aeea456-48d4-4fbd-bc39-83d7ce6f3eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26391
39801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2639139801
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3124329888
Short name T297
Test name
Test status
Simulation time 8435086877 ps
CPU time 9.9 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204096 kb
Host smart-6f06498b-6e4b-4ffd-a33c-789470ef7842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31243
29888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3124329888
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3342179645
Short name T1134
Test name
Test status
Simulation time 8389717441 ps
CPU time 8.63 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204056 kb
Host smart-e216183e-1348-4944-9031-5c9b06c01ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33421
79645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3342179645
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.4162169556
Short name T60
Test name
Test status
Simulation time 8369851642 ps
CPU time 8.11 seconds
Started May 05 03:15:12 PM PDT 24
Finished May 05 03:15:21 PM PDT 24
Peak memory 204084 kb
Host smart-962c8661-9648-49b4-9e9c-5da52f27016f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41621
69556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.4162169556
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.835136381
Short name T638
Test name
Test status
Simulation time 37981442 ps
CPU time 0.66 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:07 PM PDT 24
Peak memory 203984 kb
Host smart-320d69b7-608f-4f63-8818-304a1284b2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83513
6381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.835136381
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2604453403
Short name T1108
Test name
Test status
Simulation time 19953575264 ps
CPU time 37.15 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:44 PM PDT 24
Peak memory 204420 kb
Host smart-4608b3cb-acbb-4388-a111-83bdeb47a1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044
53403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2604453403
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3689617650
Short name T745
Test name
Test status
Simulation time 8500909518 ps
CPU time 9.5 seconds
Started May 05 03:15:12 PM PDT 24
Finished May 05 03:15:22 PM PDT 24
Peak memory 204080 kb
Host smart-8d1b69ab-73f0-4bd5-b6d7-a47cbe539ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36896
17650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3689617650
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4043010203
Short name T807
Test name
Test status
Simulation time 8445367294 ps
CPU time 8.34 seconds
Started May 05 03:15:09 PM PDT 24
Finished May 05 03:15:18 PM PDT 24
Peak memory 204100 kb
Host smart-1b4299c6-c0a1-4f05-aa37-4bfe81d823b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430
10203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4043010203
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3739511915
Short name T504
Test name
Test status
Simulation time 8384515381 ps
CPU time 10.15 seconds
Started May 05 03:15:05 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204056 kb
Host smart-7963081d-b1c4-4ca5-8493-fd74539e311c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37395
11915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3739511915
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3718870040
Short name T824
Test name
Test status
Simulation time 8392302586 ps
CPU time 8.59 seconds
Started May 05 03:15:07 PM PDT 24
Finished May 05 03:15:16 PM PDT 24
Peak memory 204128 kb
Host smart-4af2802e-9e81-482a-86ac-d8dc695b400b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37188
70040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3718870040
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3644113079
Short name T1292
Test name
Test status
Simulation time 8366468472 ps
CPU time 8.4 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:15 PM PDT 24
Peak memory 204064 kb
Host smart-cf638dc0-7fdb-4f7e-a10d-4edb7c076832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
13079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3644113079
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.408074746
Short name T138
Test name
Test status
Simulation time 8406782942 ps
CPU time 8.8 seconds
Started May 05 03:15:00 PM PDT 24
Finished May 05 03:15:10 PM PDT 24
Peak memory 204084 kb
Host smart-bdacf150-ccac-47fa-9d09-353e3cc11f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40807
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.408074746
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.4161567476
Short name T622
Test name
Test status
Simulation time 8438367322 ps
CPU time 10.13 seconds
Started May 05 03:15:06 PM PDT 24
Finished May 05 03:15:16 PM PDT 24
Peak memory 204136 kb
Host smart-83b79e98-e209-4d6c-8663-2aacc842369e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41615
67476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.4161567476
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3684956162
Short name T651
Test name
Test status
Simulation time 8412039353 ps
CPU time 7.33 seconds
Started May 05 03:15:08 PM PDT 24
Finished May 05 03:15:16 PM PDT 24
Peak memory 204092 kb
Host smart-3666504a-6d3b-47d0-9c9c-1e8d51cc71a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36849
56162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3684956162
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.4036597077
Short name T1048
Test name
Test status
Simulation time 8468177078 ps
CPU time 7.92 seconds
Started May 05 03:15:17 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204140 kb
Host smart-ac009583-bfe6-40c4-963a-b8058bb048ef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4036597077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.4036597077
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1018087937
Short name T863
Test name
Test status
Simulation time 8383111630 ps
CPU time 7.62 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204092 kb
Host smart-53461528-9a1a-4d51-99da-bc4c39a32990
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1018087937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1018087937
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.1842208409
Short name T418
Test name
Test status
Simulation time 8433029500 ps
CPU time 9.66 seconds
Started May 05 03:15:14 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204060 kb
Host smart-e9257c2b-6516-4ac2-b66f-5fcb85a68c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
08409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.1842208409
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2704840219
Short name T590
Test name
Test status
Simulation time 8377454145 ps
CPU time 8.96 seconds
Started May 05 03:15:14 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204120 kb
Host smart-8b4f4898-aa8c-47eb-8d56-e2eb1e682884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
40219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2704840219
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.1325542031
Short name T376
Test name
Test status
Simulation time 8378735444 ps
CPU time 8.89 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:26 PM PDT 24
Peak memory 204084 kb
Host smart-27410c86-cd40-4665-9330-12396bac21d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13255
42031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1325542031
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.840343433
Short name T1088
Test name
Test status
Simulation time 344529329 ps
CPU time 2.72 seconds
Started May 05 03:15:15 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204244 kb
Host smart-4f42bed3-04bc-4140-94bf-e33fa0d95fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84034
3433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.840343433
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3895753426
Short name T537
Test name
Test status
Simulation time 8428539191 ps
CPU time 7.43 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204136 kb
Host smart-c47bf95e-aef7-4aad-ac50-ba6b9a58b5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
53426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3895753426
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.392982737
Short name T964
Test name
Test status
Simulation time 8362738320 ps
CPU time 7.64 seconds
Started May 05 03:15:21 PM PDT 24
Finished May 05 03:15:29 PM PDT 24
Peak memory 204080 kb
Host smart-64e0fa7a-f258-4a11-a392-b39417506946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39298
2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.392982737
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.800211212
Short name T615
Test name
Test status
Simulation time 8450323483 ps
CPU time 7.6 seconds
Started May 05 03:15:10 PM PDT 24
Finished May 05 03:15:18 PM PDT 24
Peak memory 204104 kb
Host smart-9adf56e0-dc4e-4c99-8bf2-8e1c8e73f77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80021
1212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.800211212
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.4252621951
Short name T1133
Test name
Test status
Simulation time 8439471517 ps
CPU time 7.62 seconds
Started May 05 03:15:12 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204124 kb
Host smart-8cc55e34-ec0f-4d50-99fa-8a6263a9b513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42526
21951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.4252621951
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2314651200
Short name T415
Test name
Test status
Simulation time 8381815028 ps
CPU time 8.64 seconds
Started May 05 03:15:12 PM PDT 24
Finished May 05 03:15:21 PM PDT 24
Peak memory 204116 kb
Host smart-3aa81275-403a-47ca-afcc-d1afa53bddc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23146
51200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2314651200
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1283238116
Short name T600
Test name
Test status
Simulation time 8400835728 ps
CPU time 8.25 seconds
Started May 05 03:15:10 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204068 kb
Host smart-23f91329-2fb9-443f-bf58-1134516ecaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
38116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1283238116
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3689707378
Short name T13
Test name
Test status
Simulation time 8384353890 ps
CPU time 8.59 seconds
Started May 05 03:15:10 PM PDT 24
Finished May 05 03:15:20 PM PDT 24
Peak memory 204140 kb
Host smart-5f50f821-765f-48bd-a6de-52f188da54f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36897
07378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3689707378
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.723070375
Short name T1190
Test name
Test status
Simulation time 8384308016 ps
CPU time 8.83 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204104 kb
Host smart-7ecfd245-a763-4239-8bcc-114a3afeecbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72307
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.723070375
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3345514484
Short name T743
Test name
Test status
Simulation time 8385328743 ps
CPU time 8.32 seconds
Started May 05 03:15:09 PM PDT 24
Finished May 05 03:15:18 PM PDT 24
Peak memory 204120 kb
Host smart-104d9918-2be5-42a9-9121-94a7ffdba538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33455
14484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3345514484
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.4142169571
Short name T1337
Test name
Test status
Simulation time 43664571 ps
CPU time 0.66 seconds
Started May 05 03:15:15 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204000 kb
Host smart-270135e2-eef8-41d9-8482-2e67e38566c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41421
69571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.4142169571
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1876500452
Short name T241
Test name
Test status
Simulation time 17507868236 ps
CPU time 29.72 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:46 PM PDT 24
Peak memory 204364 kb
Host smart-669c6cca-392c-4ddd-9f29-5992b8ec00a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18765
00452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1876500452
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2576790746
Short name T1242
Test name
Test status
Simulation time 8373041280 ps
CPU time 8.91 seconds
Started May 05 03:15:10 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204124 kb
Host smart-cd6f2af9-bf3e-4f23-8f7c-7de740ff195f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25767
90746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2576790746
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3345576317
Short name T894
Test name
Test status
Simulation time 8432604956 ps
CPU time 7.39 seconds
Started May 05 03:15:11 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204080 kb
Host smart-07329455-6c77-463e-8c41-e31f53d5e181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33455
76317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3345576317
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1914836961
Short name T931
Test name
Test status
Simulation time 8459703288 ps
CPU time 9.5 seconds
Started May 05 03:15:11 PM PDT 24
Finished May 05 03:15:21 PM PDT 24
Peak memory 204108 kb
Host smart-62b6f092-2460-4485-a354-293348561d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19148
36961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1914836961
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1733190713
Short name T162
Test name
Test status
Simulation time 8378918941 ps
CPU time 9.18 seconds
Started May 05 03:15:15 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204076 kb
Host smart-f7a55fec-16bd-4a59-a248-41d6115d1a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17331
90713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1733190713
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.654289008
Short name T864
Test name
Test status
Simulation time 8364849108 ps
CPU time 8.61 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:26 PM PDT 24
Peak memory 204080 kb
Host smart-ee98155b-83ca-4f03-a7d4-0b956d8cee8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65428
9008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.654289008
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2172915368
Short name T883
Test name
Test status
Simulation time 8433650238 ps
CPU time 8.99 seconds
Started May 05 03:15:10 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204128 kb
Host smart-3d92eaf2-de62-4cf8-a44f-be61ef5b2d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21729
15368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2172915368
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2713682044
Short name T1331
Test name
Test status
Simulation time 8492049790 ps
CPU time 7.69 seconds
Started May 05 03:15:10 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204076 kb
Host smart-5380170a-fd66-4c5c-b73b-b9b0186dd323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27136
82044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2713682044
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.4057944980
Short name T587
Test name
Test status
Simulation time 8410319932 ps
CPU time 7.27 seconds
Started May 05 03:15:09 PM PDT 24
Finished May 05 03:15:17 PM PDT 24
Peak memory 204092 kb
Host smart-ad253c04-fd16-4b58-8f7f-2f92c8d0b76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40579
44980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.4057944980
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.1525256667
Short name T152
Test name
Test status
Simulation time 8475282695 ps
CPU time 8.07 seconds
Started May 05 03:15:21 PM PDT 24
Finished May 05 03:15:29 PM PDT 24
Peak memory 204116 kb
Host smart-c07898b1-b207-4399-96a1-ae84b51336e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1525256667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.1525256667
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.4176853480
Short name T724
Test name
Test status
Simulation time 8386557782 ps
CPU time 10.18 seconds
Started May 05 03:15:20 PM PDT 24
Finished May 05 03:15:31 PM PDT 24
Peak memory 204108 kb
Host smart-16fd22c8-6f33-4f2d-88f5-65e1594af6a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4176853480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.4176853480
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.2966859048
Short name T624
Test name
Test status
Simulation time 8424066374 ps
CPU time 7.77 seconds
Started May 05 03:15:18 PM PDT 24
Finished May 05 03:15:26 PM PDT 24
Peak memory 204136 kb
Host smart-2ae385f8-566b-42a1-96b0-bae76a3caa22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29668
59048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.2966859048
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3886150229
Short name T363
Test name
Test status
Simulation time 8374952528 ps
CPU time 7.82 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204100 kb
Host smart-d2c4585e-df01-4548-b8a3-87db4691be35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38861
50229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3886150229
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.4091054376
Short name T711
Test name
Test status
Simulation time 8372609145 ps
CPU time 8.57 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204084 kb
Host smart-7e3289be-ef29-416a-9101-4c8de52b8879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40910
54376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.4091054376
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1986258189
Short name T1054
Test name
Test status
Simulation time 58720835 ps
CPU time 1.43 seconds
Started May 05 03:15:20 PM PDT 24
Finished May 05 03:15:22 PM PDT 24
Peak memory 204156 kb
Host smart-29ee02a3-4cf8-4a9f-affe-c93f7be9dc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19862
58189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1986258189
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1972058935
Short name T940
Test name
Test status
Simulation time 8406902825 ps
CPU time 8.56 seconds
Started May 05 03:15:19 PM PDT 24
Finished May 05 03:15:28 PM PDT 24
Peak memory 204128 kb
Host smart-9962aa3e-0137-4a7a-920c-553ab19aa108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19720
58935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1972058935
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3264414188
Short name T202
Test name
Test status
Simulation time 8379001110 ps
CPU time 8.9 seconds
Started May 05 03:15:18 PM PDT 24
Finished May 05 03:15:28 PM PDT 24
Peak memory 204128 kb
Host smart-c0f49632-45b9-415d-add9-dd3a582e5a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32644
14188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3264414188
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3651950715
Short name T446
Test name
Test status
Simulation time 8445066068 ps
CPU time 7.68 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204108 kb
Host smart-a43fa49d-5452-475d-8f44-87568523412a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
50715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3651950715
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3029014646
Short name T565
Test name
Test status
Simulation time 8485716209 ps
CPU time 7.86 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204060 kb
Host smart-41bc3d74-bdca-413f-bf37-e62ebb433d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
14646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3029014646
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3406949194
Short name T956
Test name
Test status
Simulation time 8377409705 ps
CPU time 8.18 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204124 kb
Host smart-800770e4-833d-49d8-a265-24a1d6e3ae47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
49194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3406949194
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2946300948
Short name T1300
Test name
Test status
Simulation time 8457584910 ps
CPU time 7.54 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204088 kb
Host smart-0bda544f-f77e-4ba9-a533-2abe4e6f6e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463
00948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2946300948
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2206487984
Short name T507
Test name
Test status
Simulation time 8403292484 ps
CPU time 8.47 seconds
Started May 05 03:15:21 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204072 kb
Host smart-c0acbef2-db3b-419e-9b61-81e8c5b08334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
87984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2206487984
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.595513540
Short name T353
Test name
Test status
Simulation time 8411182857 ps
CPU time 8.66 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:31 PM PDT 24
Peak memory 204116 kb
Host smart-d00df675-adb6-44f6-bd67-cf4e483f5488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59551
3540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.595513540
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3049043840
Short name T1198
Test name
Test status
Simulation time 8438450266 ps
CPU time 7.63 seconds
Started May 05 03:15:19 PM PDT 24
Finished May 05 03:15:27 PM PDT 24
Peak memory 204156 kb
Host smart-f9b5935e-40ef-48cc-b544-c1d3f69ee455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30490
43840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3049043840
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1580932134
Short name T1282
Test name
Test status
Simulation time 8366062086 ps
CPU time 8.14 seconds
Started May 05 03:15:19 PM PDT 24
Finished May 05 03:15:27 PM PDT 24
Peak memory 204120 kb
Host smart-5e1acd6c-6cd9-46b9-a686-bc686a70bec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
32134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1580932134
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3503927683
Short name T463
Test name
Test status
Simulation time 94525166 ps
CPU time 0.7 seconds
Started May 05 03:15:18 PM PDT 24
Finished May 05 03:15:19 PM PDT 24
Peak memory 204004 kb
Host smart-a5719968-a3a9-4829-be68-519c0f5dfef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35039
27683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3503927683
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.978834736
Short name T1227
Test name
Test status
Simulation time 23084521478 ps
CPU time 42.74 seconds
Started May 05 03:15:14 PM PDT 24
Finished May 05 03:15:57 PM PDT 24
Peak memory 204376 kb
Host smart-a4751e0c-5f4f-46fe-8c3d-6738554dcab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97883
4736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.978834736
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.199283225
Short name T318
Test name
Test status
Simulation time 8399771792 ps
CPU time 8.35 seconds
Started May 05 03:15:16 PM PDT 24
Finished May 05 03:15:25 PM PDT 24
Peak memory 204048 kb
Host smart-16fb1756-825c-48f5-a743-ed2b5171ddd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19928
3225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.199283225
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1361593804
Short name T617
Test name
Test status
Simulation time 8413337289 ps
CPU time 8.46 seconds
Started May 05 03:15:20 PM PDT 24
Finished May 05 03:15:29 PM PDT 24
Peak memory 204084 kb
Host smart-d4462b5c-65f8-40b8-9c60-b0731c0bedf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
93804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1361593804
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2786555550
Short name T838
Test name
Test status
Simulation time 8387477551 ps
CPU time 8.43 seconds
Started May 05 03:15:15 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204076 kb
Host smart-f3eca32f-ef10-4262-838b-f245d8a75afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27865
55550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2786555550
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2440612634
Short name T630
Test name
Test status
Simulation time 8374752248 ps
CPU time 8.5 seconds
Started May 05 03:15:19 PM PDT 24
Finished May 05 03:15:28 PM PDT 24
Peak memory 204096 kb
Host smart-614033b2-a3ff-494d-a0c4-09da93da47fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24406
12634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2440612634
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2724740442
Short name T1170
Test name
Test status
Simulation time 8378079567 ps
CPU time 7.52 seconds
Started May 05 03:15:21 PM PDT 24
Finished May 05 03:15:29 PM PDT 24
Peak memory 204072 kb
Host smart-85622fd7-3fb9-4445-82f8-ae043ff3ac09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
40442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2724740442
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1458649821
Short name T725
Test name
Test status
Simulation time 8431009363 ps
CPU time 7.81 seconds
Started May 05 03:15:15 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204060 kb
Host smart-84f8c562-1c7d-42ac-ac4a-f072dad1fadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14586
49821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1458649821
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3557381563
Short name T948
Test name
Test status
Simulation time 8394290141 ps
CPU time 8.49 seconds
Started May 05 03:15:17 PM PDT 24
Finished May 05 03:15:26 PM PDT 24
Peak memory 204108 kb
Host smart-bc12ca6d-af1e-401e-9988-5c97ca2661bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35573
81563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3557381563
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3389138747
Short name T96
Test name
Test status
Simulation time 8417816838 ps
CPU time 7.94 seconds
Started May 05 03:15:15 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204056 kb
Host smart-8f8c8609-262e-44d7-acd3-4eb82457f3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33891
38747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3389138747
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.1654238190
Short name T438
Test name
Test status
Simulation time 8464098172 ps
CPU time 7.78 seconds
Started May 05 03:15:35 PM PDT 24
Finished May 05 03:15:43 PM PDT 24
Peak memory 204048 kb
Host smart-0f8d9d2a-6683-4965-bbbf-3851d3d28299
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1654238190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.1654238190
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.1573883135
Short name T1234
Test name
Test status
Simulation time 8390023915 ps
CPU time 7.52 seconds
Started May 05 03:15:32 PM PDT 24
Finished May 05 03:15:40 PM PDT 24
Peak memory 204136 kb
Host smart-7fbe77d8-eee1-4f7c-bb10-ab0aa922720d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1573883135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.1573883135
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.2522389163
Short name T308
Test name
Test status
Simulation time 8472922776 ps
CPU time 8.93 seconds
Started May 05 03:15:31 PM PDT 24
Finished May 05 03:15:41 PM PDT 24
Peak memory 204084 kb
Host smart-cfb91d4b-d1cc-4093-998f-f2bc25a51f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
89163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.2522389163
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.716735457
Short name T1014
Test name
Test status
Simulation time 8378097376 ps
CPU time 7.96 seconds
Started May 05 03:15:23 PM PDT 24
Finished May 05 03:15:31 PM PDT 24
Peak memory 204112 kb
Host smart-947ee2db-9d52-4b8f-bf74-0b0402d69541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71673
5457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.716735457
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.599734209
Short name T356
Test name
Test status
Simulation time 8456959164 ps
CPU time 7.87 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204056 kb
Host smart-f9bf3dc1-097d-472b-827b-dfe36eb72ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59973
4209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.599734209
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3611781322
Short name T497
Test name
Test status
Simulation time 74837948 ps
CPU time 2.01 seconds
Started May 05 03:15:21 PM PDT 24
Finished May 05 03:15:24 PM PDT 24
Peak memory 204216 kb
Host smart-2ee0694e-3cc0-4144-9210-9d40045b9df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36117
81322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3611781322
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2403010025
Short name T644
Test name
Test status
Simulation time 8370311805 ps
CPU time 7.6 seconds
Started May 05 03:15:27 PM PDT 24
Finished May 05 03:15:35 PM PDT 24
Peak memory 204016 kb
Host smart-f2414603-7060-45d3-bbcd-6db91fc10ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
10025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2403010025
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2773533864
Short name T1026
Test name
Test status
Simulation time 8397713502 ps
CPU time 7.81 seconds
Started May 05 03:15:24 PM PDT 24
Finished May 05 03:15:32 PM PDT 24
Peak memory 204036 kb
Host smart-892eb062-5c69-4132-982b-61be58020bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27735
33864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2773533864
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4175199665
Short name T1228
Test name
Test status
Simulation time 8414954791 ps
CPU time 8.38 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:31 PM PDT 24
Peak memory 204060 kb
Host smart-f3370081-b97b-4bc1-9144-30221f6a35fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41751
99665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4175199665
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.4055198963
Short name T670
Test name
Test status
Simulation time 8380797622 ps
CPU time 8.97 seconds
Started May 05 03:15:23 PM PDT 24
Finished May 05 03:15:32 PM PDT 24
Peak memory 204076 kb
Host smart-62d4f6bf-b547-4b78-ac79-16e25535a9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40551
98963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.4055198963
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2210316279
Short name T1101
Test name
Test status
Simulation time 8484464794 ps
CPU time 9.08 seconds
Started May 05 03:15:23 PM PDT 24
Finished May 05 03:15:33 PM PDT 24
Peak memory 204112 kb
Host smart-251efcf7-4c89-4779-9563-1f15b29740f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
16279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2210316279
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2647088808
Short name T757
Test name
Test status
Simulation time 8406201975 ps
CPU time 8.07 seconds
Started May 05 03:15:22 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204144 kb
Host smart-c4853c8b-7801-4e53-88c3-074bb0d24b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470
88808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2647088808
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3569828855
Short name T429
Test name
Test status
Simulation time 8436601367 ps
CPU time 9.94 seconds
Started May 05 03:15:33 PM PDT 24
Finished May 05 03:15:43 PM PDT 24
Peak memory 204064 kb
Host smart-70139a7b-1659-4961-8925-da47a4d83376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35698
28855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3569828855
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.4228796979
Short name T765
Test name
Test status
Simulation time 8404956875 ps
CPU time 7.6 seconds
Started May 05 03:15:35 PM PDT 24
Finished May 05 03:15:43 PM PDT 24
Peak memory 204108 kb
Host smart-06ec3044-a381-4788-a293-cc0904e5582c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42287
96979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.4228796979
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3110972410
Short name T499
Test name
Test status
Simulation time 8372219685 ps
CPU time 8.91 seconds
Started May 05 03:15:29 PM PDT 24
Finished May 05 03:15:38 PM PDT 24
Peak memory 204128 kb
Host smart-5cd78186-ba67-4c9b-9147-37791f311720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
72410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3110972410
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3331574313
Short name T783
Test name
Test status
Simulation time 33572974 ps
CPU time 0.65 seconds
Started May 05 03:15:27 PM PDT 24
Finished May 05 03:15:28 PM PDT 24
Peak memory 203976 kb
Host smart-61ac7c0e-e2d7-4748-b270-e8416388772e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33315
74313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3331574313
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2073196763
Short name T249
Test name
Test status
Simulation time 16040285992 ps
CPU time 32.53 seconds
Started May 05 03:15:28 PM PDT 24
Finished May 05 03:16:01 PM PDT 24
Peak memory 204340 kb
Host smart-1f78f413-16b0-4be9-91bf-066eb655cc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20731
96763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2073196763
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2539187084
Short name T1303
Test name
Test status
Simulation time 8393663067 ps
CPU time 10.05 seconds
Started May 05 03:15:31 PM PDT 24
Finished May 05 03:15:41 PM PDT 24
Peak memory 204080 kb
Host smart-7ab06683-8b17-4fe4-b53d-f39f0948be88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
87084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2539187084
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1621462262
Short name T1110
Test name
Test status
Simulation time 8432918877 ps
CPU time 7.78 seconds
Started May 05 03:15:33 PM PDT 24
Finished May 05 03:15:41 PM PDT 24
Peak memory 204092 kb
Host smart-055d1961-74d2-434e-8206-b8cdc5b3834f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
62262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1621462262
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3510079901
Short name T1185
Test name
Test status
Simulation time 8404722156 ps
CPU time 7.52 seconds
Started May 05 03:15:29 PM PDT 24
Finished May 05 03:15:37 PM PDT 24
Peak memory 204104 kb
Host smart-7b1846a7-5b39-4ebe-903a-5cd629e1a838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35100
79901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3510079901
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.4228420643
Short name T84
Test name
Test status
Simulation time 8373509122 ps
CPU time 7.92 seconds
Started May 05 03:15:30 PM PDT 24
Finished May 05 03:15:38 PM PDT 24
Peak memory 204084 kb
Host smart-e140e802-1868-4c74-a168-a2cbf314b31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284
20643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.4228420643
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2050175740
Short name T898
Test name
Test status
Simulation time 8384656752 ps
CPU time 7.83 seconds
Started May 05 03:15:33 PM PDT 24
Finished May 05 03:15:41 PM PDT 24
Peak memory 204080 kb
Host smart-34f99a88-4f13-4546-b1c3-ee8d76493a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20501
75740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2050175740
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1884815195
Short name T747
Test name
Test status
Simulation time 8438884482 ps
CPU time 9.63 seconds
Started May 05 03:15:20 PM PDT 24
Finished May 05 03:15:30 PM PDT 24
Peak memory 204040 kb
Host smart-280879f2-f971-434c-9cd2-9370acee4a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848
15195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1884815195
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.4239190014
Short name T300
Test name
Test status
Simulation time 8428359733 ps
CPU time 8.08 seconds
Started May 05 03:15:31 PM PDT 24
Finished May 05 03:15:39 PM PDT 24
Peak memory 204036 kb
Host smart-922a6193-addf-49b2-9fa8-3b9c5bebd865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
90014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.4239190014
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2801667649
Short name T1061
Test name
Test status
Simulation time 8390605239 ps
CPU time 7.88 seconds
Started May 05 03:15:28 PM PDT 24
Finished May 05 03:15:36 PM PDT 24
Peak memory 204088 kb
Host smart-81428cff-bd85-4a6f-9e49-26bc8dcd3754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28016
67649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2801667649
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.507319398
Short name T1339
Test name
Test status
Simulation time 8467163087 ps
CPU time 8.52 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204124 kb
Host smart-dda65538-10fc-42e7-9332-18fa37cc9c96
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=507319398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.507319398
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.3668127647
Short name T1290
Test name
Test status
Simulation time 8390257172 ps
CPU time 8.57 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204132 kb
Host smart-7d60eb31-1648-4b2b-8c01-776f270510c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3668127647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.3668127647
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.2777755501
Short name T728
Test name
Test status
Simulation time 8408179955 ps
CPU time 10.37 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204108 kb
Host smart-91afbddf-52ab-4307-b2fe-7976f89799ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27777
55501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.2777755501
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3514433606
Short name T641
Test name
Test status
Simulation time 8379428540 ps
CPU time 7.53 seconds
Started May 05 03:15:34 PM PDT 24
Finished May 05 03:15:42 PM PDT 24
Peak memory 204136 kb
Host smart-953b1f1e-4daf-484d-a3f2-1c7ba7e6aac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35144
33606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3514433606
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.2200333754
Short name T1348
Test name
Test status
Simulation time 8376033392 ps
CPU time 8.82 seconds
Started May 05 03:15:35 PM PDT 24
Finished May 05 03:15:44 PM PDT 24
Peak memory 204104 kb
Host smart-8ffa6bfe-3994-4fe1-b602-3f78d95a7bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
33754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2200333754
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1057027498
Short name T342
Test name
Test status
Simulation time 206763442 ps
CPU time 1.61 seconds
Started May 05 03:15:35 PM PDT 24
Finished May 05 03:15:37 PM PDT 24
Peak memory 204104 kb
Host smart-cc7ae5d3-beda-498b-a7e8-fd366ab3c022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10570
27498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1057027498
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2329329901
Short name T53
Test name
Test status
Simulation time 8380230525 ps
CPU time 8.07 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204064 kb
Host smart-3426c42b-2321-46c1-aafe-2f931ac1e14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23293
29901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2329329901
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1048672457
Short name T1074
Test name
Test status
Simulation time 8370397007 ps
CPU time 10.2 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204280 kb
Host smart-c1208d86-6e2e-43f2-8782-387a73af8583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
72457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1048672457
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3892763379
Short name T901
Test name
Test status
Simulation time 8402097887 ps
CPU time 10.04 seconds
Started May 05 03:15:33 PM PDT 24
Finished May 05 03:15:43 PM PDT 24
Peak memory 204088 kb
Host smart-efc018e4-8e4a-435e-a8c9-5cd0d0a9e02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38927
63379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3892763379
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1629304772
Short name T349
Test name
Test status
Simulation time 8428771593 ps
CPU time 8.81 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204084 kb
Host smart-47fe9c97-021a-4351-94cc-adcb74c3086d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16293
04772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1629304772
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2020685160
Short name T1336
Test name
Test status
Simulation time 8369453476 ps
CPU time 8.33 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204080 kb
Host smart-9052e8d9-66a5-4e3f-9774-ad87e7426079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
85160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2020685160
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2449505064
Short name T591
Test name
Test status
Simulation time 8425213889 ps
CPU time 8.26 seconds
Started May 05 03:15:34 PM PDT 24
Finished May 05 03:15:42 PM PDT 24
Peak memory 204084 kb
Host smart-7a970780-6291-48b3-a091-efa075070604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24495
05064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2449505064
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3538810395
Short name T360
Test name
Test status
Simulation time 8379203290 ps
CPU time 7.57 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204084 kb
Host smart-a86c8dd1-dc9e-4e54-959b-fb04e3298041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
10395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3538810395
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1980305205
Short name T31
Test name
Test status
Simulation time 8394915577 ps
CPU time 7.95 seconds
Started May 05 03:15:32 PM PDT 24
Finished May 05 03:15:40 PM PDT 24
Peak memory 204096 kb
Host smart-33ae793d-56cc-4243-8cf0-254dc5251fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
05205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1980305205
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3866911410
Short name T746
Test name
Test status
Simulation time 8449225296 ps
CPU time 8.57 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204080 kb
Host smart-f3a223c5-b4eb-408e-848f-c4fcd87f7a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
11410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3866911410
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.443574792
Short name T1046
Test name
Test status
Simulation time 8369204662 ps
CPU time 8.15 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:50 PM PDT 24
Peak memory 204080 kb
Host smart-d2dca072-50fe-4a8c-a88d-8ba363a41175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44357
4792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.443574792
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.991015724
Short name T1142
Test name
Test status
Simulation time 49363255 ps
CPU time 0.7 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:46 PM PDT 24
Peak memory 203912 kb
Host smart-f21ea881-7963-43c9-9d98-f086d7581c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99101
5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.991015724
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.724119059
Short name T1197
Test name
Test status
Simulation time 29138179810 ps
CPU time 57.79 seconds
Started May 05 03:15:34 PM PDT 24
Finished May 05 03:16:32 PM PDT 24
Peak memory 204348 kb
Host smart-7faa0361-091c-4aae-ac71-8db778f71607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72411
9059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.724119059
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.859575500
Short name T874
Test name
Test status
Simulation time 8404279426 ps
CPU time 8.07 seconds
Started May 05 03:15:35 PM PDT 24
Finished May 05 03:15:44 PM PDT 24
Peak memory 204064 kb
Host smart-3ae6a263-6a1e-44f0-91be-46a4bf0ad1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85957
5500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.859575500
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.741047052
Short name T868
Test name
Test status
Simulation time 8428638182 ps
CPU time 9 seconds
Started May 05 03:15:34 PM PDT 24
Finished May 05 03:15:43 PM PDT 24
Peak memory 204136 kb
Host smart-89562e6a-0e81-4a54-b87a-f7e582645ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74104
7052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.741047052
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.470235602
Short name T875
Test name
Test status
Simulation time 8427917100 ps
CPU time 8.07 seconds
Started May 05 03:15:34 PM PDT 24
Finished May 05 03:15:42 PM PDT 24
Peak memory 204136 kb
Host smart-03167f3f-9e34-4585-9ae0-d4fcdf67f5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47023
5602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.470235602
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1962590364
Short name T1224
Test name
Test status
Simulation time 8463414618 ps
CPU time 8.35 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204100 kb
Host smart-fe64ce0e-50f1-443b-bf87-1966001b1f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
90364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1962590364
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1045520822
Short name T920
Test name
Test status
Simulation time 8373857376 ps
CPU time 7.87 seconds
Started May 05 03:15:32 PM PDT 24
Finished May 05 03:15:40 PM PDT 24
Peak memory 204128 kb
Host smart-f3614af4-79d6-4cbf-b594-7a4f303931c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
20822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1045520822
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1617746203
Short name T996
Test name
Test status
Simulation time 8437660397 ps
CPU time 7.83 seconds
Started May 05 03:15:31 PM PDT 24
Finished May 05 03:15:39 PM PDT 24
Peak memory 204132 kb
Host smart-e8b304ed-2a3a-418e-a931-65502ffdde16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16177
46203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1617746203
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3273795463
Short name T306
Test name
Test status
Simulation time 8392520855 ps
CPU time 9.38 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:56 PM PDT 24
Peak memory 204092 kb
Host smart-b5febe1d-d257-44e3-864c-9fe9f07556cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
95463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3273795463
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2302589841
Short name T560
Test name
Test status
Simulation time 8403330173 ps
CPU time 7.57 seconds
Started May 05 03:15:33 PM PDT 24
Finished May 05 03:15:41 PM PDT 24
Peak memory 204108 kb
Host smart-e71b6b92-4d95-4e71-887e-467c8009c6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
89841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2302589841
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1585054068
Short name T1151
Test name
Test status
Simulation time 8475217561 ps
CPU time 9.25 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:56 PM PDT 24
Peak memory 204172 kb
Host smart-6c5fdda2-785a-49c2-8eff-c853559d1073
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1585054068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1585054068
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3748046052
Short name T1049
Test name
Test status
Simulation time 8377007264 ps
CPU time 7.42 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204104 kb
Host smart-1317ed32-1e88-4978-96f4-007ffb1627e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3748046052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3748046052
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.3860369694
Short name T1176
Test name
Test status
Simulation time 8437643892 ps
CPU time 8.26 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204052 kb
Host smart-c0c63c24-890e-4fd1-a0be-b23d1f0ae184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
69694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.3860369694
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.743015770
Short name T918
Test name
Test status
Simulation time 8373076638 ps
CPU time 10.74 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204128 kb
Host smart-27c1da7c-9db9-4cd1-9198-27679bb3dff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74301
5770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.743015770
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.1435099463
Short name T413
Test name
Test status
Simulation time 8390808104 ps
CPU time 8.56 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:52 PM PDT 24
Peak memory 204112 kb
Host smart-907b3799-67f8-4cdc-a81a-9524e15ad308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
99463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1435099463
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3543832376
Short name T59
Test name
Test status
Simulation time 86268808 ps
CPU time 1.35 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:15:49 PM PDT 24
Peak memory 204272 kb
Host smart-24f02a03-c6ee-4dc0-955b-39d716f3f0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35438
32376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3543832376
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1346813339
Short name T773
Test name
Test status
Simulation time 8391815642 ps
CPU time 7.87 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204068 kb
Host smart-76101f39-9bde-433b-90a0-bf300f0369d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468
13339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1346813339
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2935289027
Short name T980
Test name
Test status
Simulation time 8384358420 ps
CPU time 7.96 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204080 kb
Host smart-10fb2dc3-62c0-4ac1-b12e-0aa99a4cbf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29352
89027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2935289027
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1086278351
Short name T1104
Test name
Test status
Simulation time 8434198727 ps
CPU time 7.98 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204056 kb
Host smart-24472f13-577b-41a7-af3c-c02e1888bc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10862
78351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1086278351
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2943449149
Short name T293
Test name
Test status
Simulation time 8418480187 ps
CPU time 8.12 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204112 kb
Host smart-44e72c17-fd74-48e3-9f20-190ecca9b0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
49149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2943449149
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1052083991
Short name T1116
Test name
Test status
Simulation time 8382209487 ps
CPU time 7.54 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204088 kb
Host smart-61c8652b-5563-474c-a9f9-3fd80ff2c907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
83991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1052083991
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.182194936
Short name T125
Test name
Test status
Simulation time 8486743835 ps
CPU time 7.8 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:50 PM PDT 24
Peak memory 204108 kb
Host smart-8bdc868d-618f-4dbd-abe3-d478e9f7c1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18219
4936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.182194936
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.804803092
Short name T1105
Test name
Test status
Simulation time 8417353384 ps
CPU time 7.81 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204056 kb
Host smart-0ea2b8fd-80f3-4b18-9607-419e8fb7e219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80480
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.804803092
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2330005361
Short name T705
Test name
Test status
Simulation time 8380671822 ps
CPU time 7.29 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204068 kb
Host smart-c6e34f86-055a-4e89-8f7f-a21169f26adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23300
05361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2330005361
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1659466136
Short name T163
Test name
Test status
Simulation time 8399747062 ps
CPU time 7.88 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:52 PM PDT 24
Peak memory 204080 kb
Host smart-a4e9d272-01ba-4542-8026-eb1fedd84d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16594
66136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1659466136
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1616173283
Short name T1034
Test name
Test status
Simulation time 8368008804 ps
CPU time 8.33 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:51 PM PDT 24
Peak memory 204148 kb
Host smart-f8f881db-addc-4817-997c-1dbfd66d0ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16161
73283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1616173283
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2065301184
Short name T45
Test name
Test status
Simulation time 33822143 ps
CPU time 0.68 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:45 PM PDT 24
Peak memory 204000 kb
Host smart-b3f02625-f36a-4d87-8f6e-fe319abe20b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20653
01184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2065301184
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.557440978
Short name T252
Test name
Test status
Simulation time 16596163790 ps
CPU time 32.89 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:16:20 PM PDT 24
Peak memory 204428 kb
Host smart-53d04da5-b357-48fa-9e77-61645d3f443b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55744
0978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.557440978
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3289366871
Short name T962
Test name
Test status
Simulation time 8399585804 ps
CPU time 8.08 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204056 kb
Host smart-db8eefda-0153-4d16-9b36-9d34ca5e1350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32893
66871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3289366871
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2639186484
Short name T1145
Test name
Test status
Simulation time 8414451616 ps
CPU time 8.4 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204164 kb
Host smart-26b8090b-f1d4-44af-9a6f-709f5f98528f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26391
86484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2639186484
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2376631410
Short name T90
Test name
Test status
Simulation time 8415427903 ps
CPU time 9.19 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204096 kb
Host smart-f0acdd55-32ac-4e0e-be99-d43abb195ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766
31410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2376631410
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2595959378
Short name T173
Test name
Test status
Simulation time 8375672963 ps
CPU time 9.12 seconds
Started May 05 03:15:44 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204084 kb
Host smart-360b3abf-c839-46ba-8395-4120268e1c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25959
59378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2595959378
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1701310135
Short name T666
Test name
Test status
Simulation time 8370720788 ps
CPU time 7.26 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:50 PM PDT 24
Peak memory 204064 kb
Host smart-660da85d-26be-499c-81ad-c252b485efec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17013
10135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1701310135
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1843220609
Short name T1365
Test name
Test status
Simulation time 8423273180 ps
CPU time 8.08 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204068 kb
Host smart-3c832891-a608-4594-8dc1-669c91d5e3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18432
20609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1843220609
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3817680349
Short name T433
Test name
Test status
Simulation time 8381912148 ps
CPU time 9 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204132 kb
Host smart-f7faa641-5874-49f5-80c5-e9020bb50560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
80349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3817680349
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.94624207
Short name T925
Test name
Test status
Simulation time 8376852388 ps
CPU time 7.35 seconds
Started May 05 03:15:42 PM PDT 24
Finished May 05 03:15:50 PM PDT 24
Peak memory 204124 kb
Host smart-3e6bff89-f6cf-4284-ae2d-84d8fc2b04ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94624
207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.94624207
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.2416959098
Short name T844
Test name
Test status
Simulation time 8467233419 ps
CPU time 7.77 seconds
Started May 05 03:15:51 PM PDT 24
Finished May 05 03:15:59 PM PDT 24
Peak memory 204096 kb
Host smart-5d064d55-f403-48d1-ad55-44bb4fcb6fcd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2416959098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.2416959098
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.299043554
Short name T337
Test name
Test status
Simulation time 8405697817 ps
CPU time 7.64 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204088 kb
Host smart-18915bbd-6a1d-44f7-8677-0e50628a44da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=299043554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.299043554
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.46726550
Short name T323
Test name
Test status
Simulation time 8456943210 ps
CPU time 7.59 seconds
Started May 05 03:15:49 PM PDT 24
Finished May 05 03:15:57 PM PDT 24
Peak memory 204016 kb
Host smart-45115f66-8d2c-447d-a73e-27749904c413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46726
550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.46726550
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4271135905
Short name T1035
Test name
Test status
Simulation time 8394979358 ps
CPU time 8.6 seconds
Started May 05 03:15:44 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204060 kb
Host smart-b9fefbc5-d128-4bbe-a113-d73e6adb10f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42711
35905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4271135905
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.3417246514
Short name T89
Test name
Test status
Simulation time 8389713658 ps
CPU time 7.74 seconds
Started May 05 03:15:41 PM PDT 24
Finished May 05 03:15:49 PM PDT 24
Peak memory 204080 kb
Host smart-bacc3e14-b9a5-4d44-b4c1-898e9bdf6edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
46514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3417246514
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3471580420
Short name T1298
Test name
Test status
Simulation time 174482628 ps
CPU time 1.67 seconds
Started May 05 03:15:43 PM PDT 24
Finished May 05 03:15:45 PM PDT 24
Peak memory 204216 kb
Host smart-e6a78d24-5f6d-4658-b788-e53001e2cd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34715
80420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3471580420
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1504097541
Short name T1015
Test name
Test status
Simulation time 8408589446 ps
CPU time 9.11 seconds
Started May 05 03:15:49 PM PDT 24
Finished May 05 03:15:59 PM PDT 24
Peak memory 204084 kb
Host smart-9292a527-3191-4d23-a976-a3f0a1536c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15040
97541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1504097541
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.332621379
Short name T1275
Test name
Test status
Simulation time 8377331094 ps
CPU time 8.89 seconds
Started May 05 03:15:50 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204276 kb
Host smart-33cd0dde-4579-4898-8ea1-f971f50f327d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33262
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.332621379
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3640992901
Short name T513
Test name
Test status
Simulation time 8384876102 ps
CPU time 7.5 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204108 kb
Host smart-e6a6c402-c3b6-4100-9463-2b08ae76a638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36409
92901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3640992901
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1158172203
Short name T442
Test name
Test status
Simulation time 8461623846 ps
CPU time 7.46 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204128 kb
Host smart-a1a08e3e-22f1-4991-8b6e-98f4ad488d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
72203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1158172203
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2532541317
Short name T391
Test name
Test status
Simulation time 8407714192 ps
CPU time 9 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:15:56 PM PDT 24
Peak memory 204036 kb
Host smart-bb8457c8-2e98-42ee-8d47-71885e813fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25325
41317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2532541317
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1286635311
Short name T115
Test name
Test status
Simulation time 8418184988 ps
CPU time 7.77 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204024 kb
Host smart-1c4cd0c0-da7c-4d18-8cd5-75738b21abb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12866
35311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1286635311
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1433444037
Short name T588
Test name
Test status
Simulation time 8415347216 ps
CPU time 8.31 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204056 kb
Host smart-44a41b4a-cdb4-4bc0-b060-1275e7fd65b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14334
44037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1433444037
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.579674005
Short name T368
Test name
Test status
Simulation time 8414637219 ps
CPU time 7.83 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204068 kb
Host smart-4e66047f-4d7a-4112-b07d-b82074823ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57967
4005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.579674005
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3150077854
Short name T911
Test name
Test status
Simulation time 8380085124 ps
CPU time 8.51 seconds
Started May 05 03:15:50 PM PDT 24
Finished May 05 03:15:58 PM PDT 24
Peak memory 204112 kb
Host smart-fb85e924-3ac4-40b0-ab09-658256ee25ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500
77854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3150077854
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2689454842
Short name T1263
Test name
Test status
Simulation time 8369796194 ps
CPU time 8.47 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204084 kb
Host smart-668547a5-b998-4b14-abb1-c53d13c94046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
54842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2689454842
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.394198185
Short name T969
Test name
Test status
Simulation time 66332634 ps
CPU time 0.69 seconds
Started May 05 03:15:54 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 203988 kb
Host smart-5b187fe9-7276-416e-8400-9464789257d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39419
8185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.394198185
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2887233099
Short name T576
Test name
Test status
Simulation time 8386596456 ps
CPU time 7.85 seconds
Started May 05 03:15:47 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204128 kb
Host smart-9d692976-db01-41ec-b609-306e0611f35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
33099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2887233099
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.623957861
Short name T140
Test name
Test status
Simulation time 8451569957 ps
CPU time 8.24 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204024 kb
Host smart-c44d436b-ecfb-44bd-afc9-c2965f1c02ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62395
7861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.623957861
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3145796180
Short name T457
Test name
Test status
Simulation time 8405064641 ps
CPU time 7.77 seconds
Started May 05 03:15:46 PM PDT 24
Finished May 05 03:15:54 PM PDT 24
Peak memory 204132 kb
Host smart-b4f066c2-c253-4e5b-b278-4f886623aa67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
96180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3145796180
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1518510751
Short name T1360
Test name
Test status
Simulation time 8382322241 ps
CPU time 7.65 seconds
Started May 05 03:15:51 PM PDT 24
Finished May 05 03:15:59 PM PDT 24
Peak memory 204084 kb
Host smart-8bc76a63-0e1f-411d-a69b-3f37b41fa352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15185
10751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1518510751
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2462495546
Short name T528
Test name
Test status
Simulation time 8366813796 ps
CPU time 9.84 seconds
Started May 05 03:15:45 PM PDT 24
Finished May 05 03:15:56 PM PDT 24
Peak memory 204064 kb
Host smart-d475587a-f203-46eb-93f2-e8b7e82c2f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24624
95546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2462495546
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3675260672
Short name T551
Test name
Test status
Simulation time 8433677399 ps
CPU time 8.4 seconds
Started May 05 03:15:44 PM PDT 24
Finished May 05 03:15:53 PM PDT 24
Peak memory 204124 kb
Host smart-c2f9222d-c1a8-4706-b7b7-a6888f7445e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
60672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3675260672
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.250855304
Short name T718
Test name
Test status
Simulation time 8408943811 ps
CPU time 8.62 seconds
Started May 05 03:15:48 PM PDT 24
Finished May 05 03:15:57 PM PDT 24
Peak memory 204076 kb
Host smart-6095db45-8487-4c88-996d-786346a0e0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25085
5304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.250855304
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1622556667
Short name T502
Test name
Test status
Simulation time 8432797555 ps
CPU time 9.54 seconds
Started May 05 03:15:48 PM PDT 24
Finished May 05 03:15:58 PM PDT 24
Peak memory 204096 kb
Host smart-d07e86a1-9aaf-4442-9518-4aa6adfaefb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16225
56667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1622556667
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.3934563236
Short name T1165
Test name
Test status
Simulation time 8464613239 ps
CPU time 8.35 seconds
Started May 05 03:12:05 PM PDT 24
Finished May 05 03:12:14 PM PDT 24
Peak memory 204044 kb
Host smart-80de6589-f4eb-4783-a064-28def91c13b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3934563236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.3934563236
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2404103936
Short name T410
Test name
Test status
Simulation time 8381282676 ps
CPU time 9.04 seconds
Started May 05 03:12:05 PM PDT 24
Finished May 05 03:12:14 PM PDT 24
Peak memory 204060 kb
Host smart-dd8b68fe-976f-468b-871e-c3624a4a4177
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2404103936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2404103936
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.403485071
Short name T483
Test name
Test status
Simulation time 8477981155 ps
CPU time 8.33 seconds
Started May 05 03:12:04 PM PDT 24
Finished May 05 03:12:13 PM PDT 24
Peak memory 204068 kb
Host smart-49168736-5dc0-4fec-9d5b-3041542cc1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
5071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.403485071
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3425695823
Short name T677
Test name
Test status
Simulation time 8391739546 ps
CPU time 9.33 seconds
Started May 05 03:11:53 PM PDT 24
Finished May 05 03:12:03 PM PDT 24
Peak memory 204092 kb
Host smart-f90874f4-15e6-464a-85c6-41a2d4a26a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34256
95823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3425695823
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.1901010572
Short name T401
Test name
Test status
Simulation time 8376050940 ps
CPU time 9.15 seconds
Started May 05 03:11:55 PM PDT 24
Finished May 05 03:12:04 PM PDT 24
Peak memory 204136 kb
Host smart-12ab5588-aa29-46c2-a3b2-2161faa7ad6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010
10572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1901010572
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3493658728
Short name T1312
Test name
Test status
Simulation time 76900121 ps
CPU time 1.87 seconds
Started May 05 03:11:54 PM PDT 24
Finished May 05 03:11:56 PM PDT 24
Peak memory 204192 kb
Host smart-205bd683-e4a9-460c-9667-f45f35d3f002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34936
58728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3493658728
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1361867892
Short name T542
Test name
Test status
Simulation time 8422231029 ps
CPU time 7.96 seconds
Started May 05 03:12:05 PM PDT 24
Finished May 05 03:12:13 PM PDT 24
Peak memory 204100 kb
Host smart-71397764-d85f-46b8-a17d-d541e2ccc0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
67892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1361867892
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1796429636
Short name T203
Test name
Test status
Simulation time 8379981565 ps
CPU time 8.32 seconds
Started May 05 03:12:04 PM PDT 24
Finished May 05 03:12:13 PM PDT 24
Peak memory 204112 kb
Host smart-158f70f5-42a9-4b4e-8a5e-7796dda4873a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17964
29636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1796429636
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1040307429
Short name T673
Test name
Test status
Simulation time 8416798543 ps
CPU time 8.07 seconds
Started May 05 03:11:54 PM PDT 24
Finished May 05 03:12:03 PM PDT 24
Peak memory 204056 kb
Host smart-cd8052bd-5ead-4d2c-99e8-3e603320ed18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10403
07429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1040307429
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1959649937
Short name T1052
Test name
Test status
Simulation time 8415123757 ps
CPU time 10.51 seconds
Started May 05 03:11:56 PM PDT 24
Finished May 05 03:12:07 PM PDT 24
Peak memory 204124 kb
Host smart-8b2fc31e-84cc-40f5-950f-385d37ff6093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19596
49937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1959649937
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1037779419
Short name T290
Test name
Test status
Simulation time 8377098920 ps
CPU time 7.73 seconds
Started May 05 03:12:02 PM PDT 24
Finished May 05 03:12:10 PM PDT 24
Peak memory 204128 kb
Host smart-ba15a09e-1a39-4b52-86d2-b7f969da0e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10377
79419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1037779419
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.531456209
Short name T110
Test name
Test status
Simulation time 8440032419 ps
CPU time 10.21 seconds
Started May 05 03:12:01 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204080 kb
Host smart-6371d68c-7e36-400d-89cd-920ce9054323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53145
6209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.531456209
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3545658048
Short name T558
Test name
Test status
Simulation time 8393399736 ps
CPU time 8.18 seconds
Started May 05 03:12:02 PM PDT 24
Finished May 05 03:12:11 PM PDT 24
Peak memory 204080 kb
Host smart-1be21587-cfeb-4d5d-bf76-0d8104a74d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35456
58048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3545658048
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.491873479
Short name T350
Test name
Test status
Simulation time 8467732829 ps
CPU time 7.78 seconds
Started May 05 03:12:04 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204104 kb
Host smart-f9271e62-455f-4c23-97e5-29d2bf064b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49187
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.491873479
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3319032247
Short name T206
Test name
Test status
Simulation time 8404849405 ps
CPU time 8.86 seconds
Started May 05 03:12:03 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204104 kb
Host smart-35d696f2-7dae-4680-a2ce-ea218d40d463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33190
32247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3319032247
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1382365482
Short name T717
Test name
Test status
Simulation time 8404237328 ps
CPU time 7.54 seconds
Started May 05 03:12:06 PM PDT 24
Finished May 05 03:12:14 PM PDT 24
Peak memory 204084 kb
Host smart-02919fbd-0d6b-4ea1-a850-391b464f67de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13823
65482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1382365482
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.685895594
Short name T694
Test name
Test status
Simulation time 32339075 ps
CPU time 0.65 seconds
Started May 05 03:12:03 PM PDT 24
Finished May 05 03:12:04 PM PDT 24
Peak memory 203960 kb
Host smart-834608d6-f54f-48c0-a146-59fc8639d2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68589
5594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.685895594
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2736107702
Short name T1113
Test name
Test status
Simulation time 29783959033 ps
CPU time 69.4 seconds
Started May 05 03:12:02 PM PDT 24
Finished May 05 03:13:12 PM PDT 24
Peak memory 204388 kb
Host smart-64138edf-394d-4f4c-a3cf-aae761aa4571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27361
07702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2736107702
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.88177724
Short name T999
Test name
Test status
Simulation time 8411242473 ps
CPU time 8.5 seconds
Started May 05 03:12:03 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204132 kb
Host smart-eea51519-ae0c-4820-92c8-a49c504083c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88177
724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.88177724
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1656568453
Short name T1191
Test name
Test status
Simulation time 8413003682 ps
CPU time 7.86 seconds
Started May 05 03:12:02 PM PDT 24
Finished May 05 03:12:11 PM PDT 24
Peak memory 204280 kb
Host smart-b0efdefa-4ccb-435b-a5cc-b2cf7274beb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16565
68453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1656568453
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.587317450
Short name T372
Test name
Test status
Simulation time 8373766344 ps
CPU time 7.59 seconds
Started May 05 03:12:01 PM PDT 24
Finished May 05 03:12:09 PM PDT 24
Peak memory 204124 kb
Host smart-736efdc1-9dd3-434f-a684-f318cbd1e1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58731
7450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.587317450
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3797633812
Short name T1012
Test name
Test status
Simulation time 8375071550 ps
CPU time 7.44 seconds
Started May 05 03:12:05 PM PDT 24
Finished May 05 03:12:13 PM PDT 24
Peak memory 204072 kb
Host smart-2635ceea-5dfc-471b-a66c-e1325922d29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37976
33812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3797633812
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3406970668
Short name T29
Test name
Test status
Simulation time 8368552209 ps
CPU time 7.85 seconds
Started May 05 03:12:03 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204092 kb
Host smart-108a0dd5-4ed8-4ccf-a723-9bdf4cde0067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
70668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3406970668
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1625852601
Short name T1093
Test name
Test status
Simulation time 8451226357 ps
CPU time 8.06 seconds
Started May 05 03:11:56 PM PDT 24
Finished May 05 03:12:04 PM PDT 24
Peak memory 204068 kb
Host smart-5dec6786-60c3-4e35-b979-97d5ef00ad61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16258
52601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1625852601
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.720458394
Short name T227
Test name
Test status
Simulation time 8437624823 ps
CPU time 7.3 seconds
Started May 05 03:12:05 PM PDT 24
Finished May 05 03:12:13 PM PDT 24
Peak memory 204100 kb
Host smart-12a6378f-8277-46cd-9420-6351cfd0540e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72045
8394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.720458394
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2603314266
Short name T965
Test name
Test status
Simulation time 8413878560 ps
CPU time 9.62 seconds
Started May 05 03:12:02 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204088 kb
Host smart-ccd180b3-2cca-4fb4-85a9-962c4d82875e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26033
14266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2603314266
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1382365441
Short name T634
Test name
Test status
Simulation time 8466104948 ps
CPU time 9.27 seconds
Started May 05 03:15:53 PM PDT 24
Finished May 05 03:16:03 PM PDT 24
Peak memory 204136 kb
Host smart-f5e2451f-7868-4cab-ba52-fead17327348
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1382365441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1382365441
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.7063823
Short name T1192
Test name
Test status
Simulation time 8378819661 ps
CPU time 8.12 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204132 kb
Host smart-a184fa0d-31f2-4a01-bf98-da87d07170b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=7063823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.7063823
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.637631651
Short name T302
Test name
Test status
Simulation time 8417051433 ps
CPU time 7.98 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204092 kb
Host smart-8adcae69-2a65-441f-abfe-cd8a05ddd78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63763
1651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.637631651
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1863569696
Short name T518
Test name
Test status
Simulation time 8371055811 ps
CPU time 8.45 seconds
Started May 05 03:15:51 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204280 kb
Host smart-8d13c7d5-c6b2-4fe1-87ba-567ef9f3681f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18635
69696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1863569696
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.1390086422
Short name T19
Test name
Test status
Simulation time 8459619111 ps
CPU time 7.53 seconds
Started May 05 03:15:50 PM PDT 24
Finished May 05 03:15:57 PM PDT 24
Peak memory 204100 kb
Host smart-9ff0b1bc-4f0e-41c2-95b9-69fdcf6bce33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
86422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1390086422
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3161826942
Short name T563
Test name
Test status
Simulation time 76502072 ps
CPU time 1.86 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:15:58 PM PDT 24
Peak memory 204180 kb
Host smart-b4aef402-4f07-4ec0-beaa-60ef0ee6d5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
26942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3161826942
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.844356392
Short name T766
Test name
Test status
Simulation time 8453867709 ps
CPU time 8.1 seconds
Started May 05 03:15:55 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204124 kb
Host smart-eaa25813-aa83-4612-b8eb-934e68c17f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84435
6392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.844356392
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2075448642
Short name T139
Test name
Test status
Simulation time 8398131223 ps
CPU time 8.64 seconds
Started May 05 03:15:55 PM PDT 24
Finished May 05 03:16:05 PM PDT 24
Peak memory 204088 kb
Host smart-4c387dd6-9e3f-4de6-90f5-2ef16845c858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20754
48642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2075448642
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1411776035
Short name T1307
Test name
Test status
Simulation time 8427979716 ps
CPU time 8.14 seconds
Started May 05 03:15:51 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204104 kb
Host smart-164894d4-ed22-45c6-b99e-66f30e780967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14117
76035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1411776035
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4026395982
Short name T621
Test name
Test status
Simulation time 8375837177 ps
CPU time 8.39 seconds
Started May 05 03:15:57 PM PDT 24
Finished May 05 03:16:06 PM PDT 24
Peak memory 204140 kb
Host smart-24258448-b795-4049-9c19-ce5d5a4dea3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
95982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4026395982
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2280485302
Short name T1274
Test name
Test status
Simulation time 8458026929 ps
CPU time 7.65 seconds
Started May 05 03:15:50 PM PDT 24
Finished May 05 03:15:58 PM PDT 24
Peak memory 204068 kb
Host smart-00a32df0-acae-4760-a27b-bc2a4f265197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22804
85302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2280485302
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.4201469663
Short name T424
Test name
Test status
Simulation time 8386369721 ps
CPU time 7.84 seconds
Started May 05 03:15:50 PM PDT 24
Finished May 05 03:15:58 PM PDT 24
Peak memory 204040 kb
Host smart-02c7f04d-d002-484a-a264-eef508043711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42014
69663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.4201469663
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.282852067
Short name T1321
Test name
Test status
Simulation time 8396705387 ps
CPU time 8.22 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204140 kb
Host smart-4b4bd52b-ae76-4954-bfa8-2d11ea3938a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
2067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.282852067
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4220172699
Short name T159
Test name
Test status
Simulation time 8371544037 ps
CPU time 9.34 seconds
Started May 05 03:15:54 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204112 kb
Host smart-90f290b0-4bac-40be-b91d-f63495895d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
72699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4220172699
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.440605913
Short name T1245
Test name
Test status
Simulation time 8376220354 ps
CPU time 8.68 seconds
Started May 05 03:15:50 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204080 kb
Host smart-6715e553-0941-41b7-b173-25ee95495bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44060
5913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.440605913
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.501184977
Short name T905
Test name
Test status
Simulation time 49532287 ps
CPU time 0.68 seconds
Started May 05 03:15:54 PM PDT 24
Finished May 05 03:15:56 PM PDT 24
Peak memory 203944 kb
Host smart-9187dcc3-3fd6-4f8f-8bfa-a2dcfe7202d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50118
4977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.501184977
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3334532362
Short name T1241
Test name
Test status
Simulation time 28665839216 ps
CPU time 52.49 seconds
Started May 05 03:15:53 PM PDT 24
Finished May 05 03:16:46 PM PDT 24
Peak memory 204404 kb
Host smart-c76a3f74-4bb3-4366-b217-d733fb51cb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33345
32362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3334532362
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1043571797
Short name T1081
Test name
Test status
Simulation time 8385851897 ps
CPU time 9.96 seconds
Started May 05 03:15:49 PM PDT 24
Finished May 05 03:15:59 PM PDT 24
Peak memory 204024 kb
Host smart-03837cb3-d4f4-4b00-bf32-8895c3594ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10435
71797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1043571797
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2804205589
Short name T998
Test name
Test status
Simulation time 8412580117 ps
CPU time 8.38 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:16:01 PM PDT 24
Peak memory 204060 kb
Host smart-b475e628-359d-4925-a4fe-0ccfd086aec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
05589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2804205589
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.4033495302
Short name T1253
Test name
Test status
Simulation time 8428559622 ps
CPU time 7.81 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:16:01 PM PDT 24
Peak memory 204056 kb
Host smart-547fde98-730c-43a9-879c-25469edca2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
95302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.4033495302
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4232000637
Short name T664
Test name
Test status
Simulation time 8384646908 ps
CPU time 8.85 seconds
Started May 05 03:15:53 PM PDT 24
Finished May 05 03:16:02 PM PDT 24
Peak memory 204120 kb
Host smart-2af9c0be-3498-4329-8497-07a3ba5f6351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
00637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4232000637
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1311249768
Short name T407
Test name
Test status
Simulation time 8403475531 ps
CPU time 7.62 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204108 kb
Host smart-1e3e6dae-4b74-43df-83fd-7fa677b54a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13112
49768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1311249768
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2453463554
Short name T1219
Test name
Test status
Simulation time 8438091867 ps
CPU time 8 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:16:00 PM PDT 24
Peak memory 204060 kb
Host smart-6ae5d790-7122-491a-be0c-05c9e8202af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24534
63554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2453463554
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1646232335
Short name T1016
Test name
Test status
Simulation time 8387078057 ps
CPU time 7.95 seconds
Started May 05 03:15:53 PM PDT 24
Finished May 05 03:16:01 PM PDT 24
Peak memory 204056 kb
Host smart-f23d7a78-95ac-4d28-a5e2-239d25b9ec9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16462
32335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1646232335
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3374326397
Short name T1011
Test name
Test status
Simulation time 8408488669 ps
CPU time 8.27 seconds
Started May 05 03:15:54 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204116 kb
Host smart-dc2941e2-a2d4-49f0-9834-fd66e4d3fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33743
26397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3374326397
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.2462537293
Short name T1370
Test name
Test status
Simulation time 8464090858 ps
CPU time 7.88 seconds
Started May 05 03:15:59 PM PDT 24
Finished May 05 03:16:08 PM PDT 24
Peak memory 204088 kb
Host smart-b8ad1dde-e3f6-44c7-98b4-c759b00d27e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2462537293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.2462537293
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.4174300903
Short name T826
Test name
Test status
Simulation time 8380023029 ps
CPU time 8.77 seconds
Started May 05 03:16:00 PM PDT 24
Finished May 05 03:16:09 PM PDT 24
Peak memory 204132 kb
Host smart-06d8f22c-0b56-411b-8a65-b2e2e09d7507
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4174300903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.4174300903
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2620020943
Short name T1203
Test name
Test status
Simulation time 8394381492 ps
CPU time 8.17 seconds
Started May 05 03:15:59 PM PDT 24
Finished May 05 03:16:07 PM PDT 24
Peak memory 204080 kb
Host smart-f1fb3443-a3fd-4425-a1b6-33203c1318b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26200
20943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2620020943
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.382990317
Short name T1118
Test name
Test status
Simulation time 8387914918 ps
CPU time 9.17 seconds
Started May 05 03:15:53 PM PDT 24
Finished May 05 03:16:02 PM PDT 24
Peak memory 204108 kb
Host smart-1410e48d-1f77-4022-9f34-05865623316e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38299
0317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.382990317
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.1745299852
Short name T530
Test name
Test status
Simulation time 8394368611 ps
CPU time 7.78 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204100 kb
Host smart-a4a89792-8ee1-460a-ace6-8039b66d271b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17452
99852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1745299852
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2411841619
Short name T569
Test name
Test status
Simulation time 264289103 ps
CPU time 2.27 seconds
Started May 05 03:15:52 PM PDT 24
Finished May 05 03:15:55 PM PDT 24
Peak memory 204252 kb
Host smart-304275ad-b9cd-455a-b6ea-cc9653c34717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24118
41619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2411841619
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.89233010
Short name T968
Test name
Test status
Simulation time 8390016588 ps
CPU time 8.29 seconds
Started May 05 03:16:02 PM PDT 24
Finished May 05 03:16:11 PM PDT 24
Peak memory 204112 kb
Host smart-c7ad7cf2-34cd-45a7-a881-3ec3366819d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89233
010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.89233010
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3889984901
Short name T197
Test name
Test status
Simulation time 8367450939 ps
CPU time 7.59 seconds
Started May 05 03:16:03 PM PDT 24
Finished May 05 03:16:11 PM PDT 24
Peak memory 204108 kb
Host smart-851209f3-e57c-457f-ad47-7fdec33b97ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38899
84901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3889984901
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3593145915
Short name T359
Test name
Test status
Simulation time 8460692621 ps
CPU time 7.54 seconds
Started May 05 03:15:54 PM PDT 24
Finished May 05 03:16:02 PM PDT 24
Peak memory 204076 kb
Host smart-a40d4020-1b30-4034-9d3f-aca0159b6e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
45915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3593145915
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2621005931
Short name T1204
Test name
Test status
Simulation time 8446424106 ps
CPU time 7.67 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204068 kb
Host smart-afb4d4bf-847e-4f30-b691-0a49a70706f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26210
05931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2621005931
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2667337052
Short name T872
Test name
Test status
Simulation time 8372921001 ps
CPU time 7.92 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204136 kb
Host smart-aebce88c-d8cd-49cf-ba2d-187baf0355d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26673
37052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2667337052
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4134296182
Short name T1319
Test name
Test status
Simulation time 8420937677 ps
CPU time 8.49 seconds
Started May 05 03:16:01 PM PDT 24
Finished May 05 03:16:10 PM PDT 24
Peak memory 203864 kb
Host smart-ea310165-8903-42d8-b0a0-aeacf09bfca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
96182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4134296182
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3153363200
Short name T1001
Test name
Test status
Simulation time 8374642748 ps
CPU time 9.27 seconds
Started May 05 03:16:01 PM PDT 24
Finished May 05 03:16:11 PM PDT 24
Peak memory 204072 kb
Host smart-695a09fc-e787-4760-85d0-0855d4de5ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31533
63200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3153363200
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.980728573
Short name T636
Test name
Test status
Simulation time 8397581993 ps
CPU time 8.53 seconds
Started May 05 03:15:59 PM PDT 24
Finished May 05 03:16:08 PM PDT 24
Peak memory 204068 kb
Host smart-41eafbde-cc34-4d73-91db-3770967cf7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98072
8573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.980728573
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2159300701
Short name T688
Test name
Test status
Simulation time 8368894145 ps
CPU time 8.99 seconds
Started May 05 03:15:59 PM PDT 24
Finished May 05 03:16:08 PM PDT 24
Peak memory 204148 kb
Host smart-b92a690d-e8f3-4eab-b441-894a50f9cb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21593
00701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2159300701
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2645009202
Short name T439
Test name
Test status
Simulation time 47780298 ps
CPU time 0.65 seconds
Started May 05 03:16:00 PM PDT 24
Finished May 05 03:16:01 PM PDT 24
Peak memory 204004 kb
Host smart-3375d59d-db62-41d0-9c7a-d058bc782385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26450
09202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2645009202
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2411405164
Short name T1143
Test name
Test status
Simulation time 8404474276 ps
CPU time 10.13 seconds
Started May 05 03:16:01 PM PDT 24
Finished May 05 03:16:11 PM PDT 24
Peak memory 204052 kb
Host smart-f8b6de60-e6f5-4c58-9215-3dd9815d786f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
05164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2411405164
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2240151956
Short name T136
Test name
Test status
Simulation time 8468690615 ps
CPU time 8.69 seconds
Started May 05 03:15:58 PM PDT 24
Finished May 05 03:16:08 PM PDT 24
Peak memory 204092 kb
Host smart-740027ef-b563-4f48-8ef2-63da11856a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22401
51956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2240151956
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2425211138
Short name T880
Test name
Test status
Simulation time 8398325288 ps
CPU time 10.34 seconds
Started May 05 03:16:02 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204128 kb
Host smart-644c2732-ca2d-4424-966e-6b0a669068a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24252
11138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2425211138
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2820309002
Short name T1059
Test name
Test status
Simulation time 8371150430 ps
CPU time 7.92 seconds
Started May 05 03:16:03 PM PDT 24
Finished May 05 03:16:11 PM PDT 24
Peak memory 204080 kb
Host smart-7fc9d94a-e013-4126-b642-79f48c18a54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28203
09002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2820309002
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2029440728
Short name T458
Test name
Test status
Simulation time 8373211702 ps
CPU time 7.98 seconds
Started May 05 03:15:59 PM PDT 24
Finished May 05 03:16:07 PM PDT 24
Peak memory 204064 kb
Host smart-b772d705-877d-403c-9dfd-7b3a56267784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
40728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2029440728
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2323926140
Short name T131
Test name
Test status
Simulation time 8423143660 ps
CPU time 8.29 seconds
Started May 05 03:15:56 PM PDT 24
Finished May 05 03:16:04 PM PDT 24
Peak memory 204084 kb
Host smart-1d6139a1-c6ab-4a16-9d97-46187fdddeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
26140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2323926140
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.4284824410
Short name T1338
Test name
Test status
Simulation time 8402048992 ps
CPU time 7.65 seconds
Started May 05 03:16:01 PM PDT 24
Finished May 05 03:16:09 PM PDT 24
Peak memory 203884 kb
Host smart-be093945-b2ad-4001-ab7d-284ec2cd21b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42848
24410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.4284824410
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1290679940
Short name T1326
Test name
Test status
Simulation time 8387995618 ps
CPU time 7.58 seconds
Started May 05 03:15:59 PM PDT 24
Finished May 05 03:16:07 PM PDT 24
Peak memory 204056 kb
Host smart-acf5ff6d-88a2-4006-8e86-263d96a3d527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12906
79940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1290679940
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1414224252
Short name T1117
Test name
Test status
Simulation time 8458652974 ps
CPU time 9.29 seconds
Started May 05 03:16:14 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204112 kb
Host smart-11265e33-0435-4506-91d4-f3dfadd8f740
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1414224252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1414224252
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1338027898
Short name T1131
Test name
Test status
Simulation time 8417871878 ps
CPU time 9.38 seconds
Started May 05 03:16:11 PM PDT 24
Finished May 05 03:16:21 PM PDT 24
Peak memory 204064 kb
Host smart-5a48e815-9c6e-434c-81ed-4ac0651361b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1338027898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1338027898
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.2574036489
Short name T39
Test name
Test status
Simulation time 8459985301 ps
CPU time 8.4 seconds
Started May 05 03:16:07 PM PDT 24
Finished May 05 03:16:15 PM PDT 24
Peak memory 204096 kb
Host smart-7dac1188-8a2d-44ed-b4cc-49a399689eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25740
36489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.2574036489
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.742928507
Short name T1299
Test name
Test status
Simulation time 8394685434 ps
CPU time 8.29 seconds
Started May 05 03:16:05 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 204120 kb
Host smart-9793730b-69a2-4e55-8ddf-1c1013082300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74292
8507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.742928507
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.2164577844
Short name T487
Test name
Test status
Simulation time 8389207457 ps
CPU time 8.42 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204084 kb
Host smart-af63cc5a-ee8a-4754-a4f9-28822772b13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21645
77844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2164577844
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3983034915
Short name T917
Test name
Test status
Simulation time 47942126 ps
CPU time 1.17 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:05 PM PDT 24
Peak memory 204204 kb
Host smart-1ce4b63e-c4fe-4f2e-86e2-0445a7201d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39830
34915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3983034915
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.548558649
Short name T737
Test name
Test status
Simulation time 8476126482 ps
CPU time 8.15 seconds
Started May 05 03:16:07 PM PDT 24
Finished May 05 03:16:16 PM PDT 24
Peak memory 204040 kb
Host smart-2ad2676b-6814-4260-9e28-fe26fcc8f259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54855
8649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.548558649
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2614007782
Short name T191
Test name
Test status
Simulation time 8381604704 ps
CPU time 8.06 seconds
Started May 05 03:16:07 PM PDT 24
Finished May 05 03:16:16 PM PDT 24
Peak memory 204088 kb
Host smart-457f8564-4fd8-4442-901e-29c281a24854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140
07782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2614007782
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.505146515
Short name T150
Test name
Test status
Simulation time 8457463720 ps
CPU time 8.97 seconds
Started May 05 03:16:05 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 204104 kb
Host smart-8f0aa072-8d70-4811-87bc-720f9ba3e495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50514
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.505146515
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.484754127
Short name T1071
Test name
Test status
Simulation time 8416207139 ps
CPU time 7.66 seconds
Started May 05 03:16:03 PM PDT 24
Finished May 05 03:16:12 PM PDT 24
Peak memory 204144 kb
Host smart-a10dc77c-c04c-4687-8ba0-eaf994f200c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48475
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.484754127
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3055137315
Short name T303
Test name
Test status
Simulation time 8382472604 ps
CPU time 7.59 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204112 kb
Host smart-65d5db64-7a8d-48dd-b25a-83644f0c4b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
37315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3055137315
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.638860834
Short name T121
Test name
Test status
Simulation time 8415920465 ps
CPU time 8.73 seconds
Started May 05 03:16:03 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204128 kb
Host smart-4ddc094d-9891-4b2e-8c5d-f07014b833ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63886
0834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.638860834
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.244737764
Short name T380
Test name
Test status
Simulation time 8415062201 ps
CPU time 10.12 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:15 PM PDT 24
Peak memory 204108 kb
Host smart-7365337f-0651-4b6b-bca2-6334a759bb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
7764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.244737764
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3408931936
Short name T834
Test name
Test status
Simulation time 8391790815 ps
CPU time 7.51 seconds
Started May 05 03:16:03 PM PDT 24
Finished May 05 03:16:10 PM PDT 24
Peak memory 204140 kb
Host smart-bc9df848-e46d-4e4f-a0bb-375670c2787c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
31936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3408931936
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1088461309
Short name T194
Test name
Test status
Simulation time 8402908208 ps
CPU time 9.48 seconds
Started May 05 03:16:07 PM PDT 24
Finished May 05 03:16:17 PM PDT 24
Peak memory 204056 kb
Host smart-eed97d2d-38ba-4b90-84ba-76f97097a7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
61309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1088461309
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2577516332
Short name T1138
Test name
Test status
Simulation time 8369475797 ps
CPU time 7.75 seconds
Started May 05 03:16:02 PM PDT 24
Finished May 05 03:16:10 PM PDT 24
Peak memory 204120 kb
Host smart-808557e3-b9b9-4850-8d71-6e289d938455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25775
16332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2577516332
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.798031483
Short name T1248
Test name
Test status
Simulation time 40826261 ps
CPU time 0.64 seconds
Started May 05 03:16:07 PM PDT 24
Finished May 05 03:16:09 PM PDT 24
Peak memory 204016 kb
Host smart-b9b8ea58-b552-4714-a93e-d11e68eaa4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79803
1483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.798031483
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3233167229
Short name T935
Test name
Test status
Simulation time 24850350586 ps
CPU time 48.81 seconds
Started May 05 03:16:02 PM PDT 24
Finished May 05 03:16:51 PM PDT 24
Peak memory 204420 kb
Host smart-8c3654cd-c44c-498b-ae9f-5955f0014f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
67229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3233167229
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1819173993
Short name T907
Test name
Test status
Simulation time 8376088850 ps
CPU time 8.9 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 204160 kb
Host smart-af2f4398-496d-4394-989e-96eea86b9a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18191
73993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1819173993
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.190439535
Short name T1169
Test name
Test status
Simulation time 8424971171 ps
CPU time 7.93 seconds
Started May 05 03:16:06 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 204052 kb
Host smart-5cf271d9-cbba-4ed5-9c33-fbc66dd317f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19043
9535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.190439535
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.4201232257
Short name T1345
Test name
Test status
Simulation time 8386184196 ps
CPU time 8.39 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204124 kb
Host smart-380f9869-f62b-4932-8579-773b8ee2a037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42012
32257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.4201232257
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.912966208
Short name T839
Test name
Test status
Simulation time 8380645840 ps
CPU time 9.61 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 204168 kb
Host smart-57492d0b-dd88-4d25-9629-a662a9bd3e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91296
6208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.912966208
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3301514681
Short name T840
Test name
Test status
Simulation time 8360144991 ps
CPU time 7.73 seconds
Started May 05 03:16:06 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 204044 kb
Host smart-fc232672-26e6-4f3b-b845-f80782cf6b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
14681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3301514681
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2313982061
Short name T92
Test name
Test status
Simulation time 8410721195 ps
CPU time 8.15 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:13 PM PDT 24
Peak memory 204100 kb
Host smart-c6c70ac8-60a8-41f2-9156-1794cc42cd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23139
82061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2313982061
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2990287736
Short name T449
Test name
Test status
Simulation time 8387406556 ps
CPU time 7.81 seconds
Started May 05 03:16:04 PM PDT 24
Finished May 05 03:16:12 PM PDT 24
Peak memory 204084 kb
Host smart-7070b4c9-887e-42a5-bd31-450901bbb352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
87736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2990287736
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1384049687
Short name T1294
Test name
Test status
Simulation time 8403855672 ps
CPU time 8.42 seconds
Started May 05 03:16:02 PM PDT 24
Finished May 05 03:16:11 PM PDT 24
Peak memory 204100 kb
Host smart-12880fdb-7df7-4a71-8001-3e74129c7214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
49687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1384049687
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.2789452085
Short name T767
Test name
Test status
Simulation time 8467216410 ps
CPU time 8.86 seconds
Started May 05 03:16:19 PM PDT 24
Finished May 05 03:16:28 PM PDT 24
Peak memory 204032 kb
Host smart-128d183d-783e-4c94-8cf8-912482a590dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2789452085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.2789452085
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.2496503117
Short name T1167
Test name
Test status
Simulation time 8378169466 ps
CPU time 8.84 seconds
Started May 05 03:16:14 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204136 kb
Host smart-7d0b62a6-1c5e-463b-8538-d3b5bdd9ce37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2496503117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.2496503117
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.1568722179
Short name T734
Test name
Test status
Simulation time 8434378721 ps
CPU time 8.2 seconds
Started May 05 03:16:16 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204112 kb
Host smart-08e5858f-4c1e-487b-8abe-4470654a4a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15687
22179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.1568722179
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2551744663
Short name T1179
Test name
Test status
Simulation time 8382908397 ps
CPU time 10.32 seconds
Started May 05 03:16:14 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204100 kb
Host smart-bd76f31b-8d7e-450c-9a36-643af27e226f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25517
44663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2551744663
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.472428285
Short name T460
Test name
Test status
Simulation time 8377442189 ps
CPU time 7.31 seconds
Started May 05 03:16:11 PM PDT 24
Finished May 05 03:16:19 PM PDT 24
Peak memory 204112 kb
Host smart-1c773856-f4f2-42cc-910c-6d4fdcdbd3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47242
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.472428285
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3127339109
Short name T54
Test name
Test status
Simulation time 8432702319 ps
CPU time 8.5 seconds
Started May 05 03:16:16 PM PDT 24
Finished May 05 03:16:25 PM PDT 24
Peak memory 204100 kb
Host smart-b3670f91-3984-4b86-b3e2-9775239a8747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
39109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3127339109
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3958837018
Short name T787
Test name
Test status
Simulation time 8395814042 ps
CPU time 7.75 seconds
Started May 05 03:16:18 PM PDT 24
Finished May 05 03:16:26 PM PDT 24
Peak memory 204132 kb
Host smart-b8155db1-af91-4948-adba-af423646df31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39588
37018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3958837018
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2969523618
Short name T531
Test name
Test status
Simulation time 8452597766 ps
CPU time 8 seconds
Started May 05 03:16:11 PM PDT 24
Finished May 05 03:16:20 PM PDT 24
Peak memory 204128 kb
Host smart-a80c337d-cfdf-408f-94ab-5b6921fc971f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29695
23618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2969523618
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1092531956
Short name T891
Test name
Test status
Simulation time 8420703984 ps
CPU time 8.1 seconds
Started May 05 03:16:14 PM PDT 24
Finished May 05 03:16:22 PM PDT 24
Peak memory 204100 kb
Host smart-bd96fe6d-7ce1-4ed3-a6c0-5ab6ab60f6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10925
31956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1092531956
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2800679369
Short name T796
Test name
Test status
Simulation time 8371927495 ps
CPU time 8.11 seconds
Started May 05 03:16:15 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204088 kb
Host smart-4a45ee27-8e83-4e3b-9eac-72cd01a871dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28006
79369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2800679369
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.520885460
Short name T118
Test name
Test status
Simulation time 8398431145 ps
CPU time 8.07 seconds
Started May 05 03:16:10 PM PDT 24
Finished May 05 03:16:18 PM PDT 24
Peak memory 204016 kb
Host smart-90f821c0-3cc0-4ab5-aca6-eb93b25c0041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52088
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.520885460
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2508526111
Short name T382
Test name
Test status
Simulation time 8383557755 ps
CPU time 7.65 seconds
Started May 05 03:16:11 PM PDT 24
Finished May 05 03:16:19 PM PDT 24
Peak memory 204092 kb
Host smart-8c8391e9-9535-4096-8356-cd7e919cdbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25085
26111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2508526111
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.494445071
Short name T474
Test name
Test status
Simulation time 8404519999 ps
CPU time 8.91 seconds
Started May 05 03:16:12 PM PDT 24
Finished May 05 03:16:21 PM PDT 24
Peak memory 204084 kb
Host smart-2ce6ce46-9aba-48a7-8708-46dc9b6d99ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49444
5071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.494445071
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2720036531
Short name T1181
Test name
Test status
Simulation time 8408910184 ps
CPU time 7.66 seconds
Started May 05 03:16:16 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204104 kb
Host smart-5e3eab80-618f-4646-bda2-bccb4e73c9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27200
36531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2720036531
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1594831302
Short name T614
Test name
Test status
Simulation time 8369433842 ps
CPU time 8.19 seconds
Started May 05 03:16:19 PM PDT 24
Finished May 05 03:16:27 PM PDT 24
Peak memory 204040 kb
Host smart-80c2a18e-70e6-4cdf-9d83-17ad73ac1053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15948
31302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1594831302
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.290957109
Short name T547
Test name
Test status
Simulation time 39979256 ps
CPU time 0.66 seconds
Started May 05 03:16:18 PM PDT 24
Finished May 05 03:16:19 PM PDT 24
Peak memory 203948 kb
Host smart-4461cb99-8660-4ba4-8d0c-08a0210a28cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
7109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.290957109
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.894780615
Short name T95
Test name
Test status
Simulation time 25166600649 ps
CPU time 52.6 seconds
Started May 05 03:16:15 PM PDT 24
Finished May 05 03:17:08 PM PDT 24
Peak memory 204388 kb
Host smart-bb5c63a2-f125-4c73-a868-f7c1662cbccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89478
0615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.894780615
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1308636088
Short name T845
Test name
Test status
Simulation time 8406694682 ps
CPU time 8.84 seconds
Started May 05 03:16:15 PM PDT 24
Finished May 05 03:16:25 PM PDT 24
Peak memory 204088 kb
Host smart-f5d64352-e683-49d2-b874-51f57efc7650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
36088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1308636088
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2482086107
Short name T653
Test name
Test status
Simulation time 8447892605 ps
CPU time 8.2 seconds
Started May 05 03:16:17 PM PDT 24
Finished May 05 03:16:25 PM PDT 24
Peak memory 204080 kb
Host smart-8de07c5c-114b-473f-923d-4dc1deb7a6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24820
86107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2482086107
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3782241809
Short name T575
Test name
Test status
Simulation time 8394724892 ps
CPU time 9.45 seconds
Started May 05 03:16:17 PM PDT 24
Finished May 05 03:16:27 PM PDT 24
Peak memory 204052 kb
Host smart-cf4bf6f2-06d7-40c5-ac68-47a691646d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37822
41809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3782241809
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.912254164
Short name T1183
Test name
Test status
Simulation time 8381611060 ps
CPU time 8.07 seconds
Started May 05 03:16:15 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204080 kb
Host smart-6565af5c-084b-42b6-9843-8402464715e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91225
4164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.912254164
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1613112107
Short name T943
Test name
Test status
Simulation time 8371290908 ps
CPU time 8.04 seconds
Started May 05 03:16:15 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204128 kb
Host smart-d5426808-9d22-473a-88ac-09b094e174d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
12107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1613112107
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.249123054
Short name T170
Test name
Test status
Simulation time 8412622465 ps
CPU time 8.2 seconds
Started May 05 03:16:14 PM PDT 24
Finished May 05 03:16:23 PM PDT 24
Peak memory 204108 kb
Host smart-7f4372b7-12de-4ace-92a3-de70333d42fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24912
3054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.249123054
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3361154649
Short name T80
Test name
Test status
Simulation time 8394994358 ps
CPU time 7.89 seconds
Started May 05 03:16:19 PM PDT 24
Finished May 05 03:16:27 PM PDT 24
Peak memory 204080 kb
Host smart-deebb30e-d25c-4ed0-851b-39d234a04d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33611
54649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3361154649
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.525111870
Short name T1276
Test name
Test status
Simulation time 8389421083 ps
CPU time 9.33 seconds
Started May 05 03:16:14 PM PDT 24
Finished May 05 03:16:24 PM PDT 24
Peak memory 204080 kb
Host smart-2e2be349-93dc-4e18-9232-fea46b47ac31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52511
1870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.525111870
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.740789899
Short name T364
Test name
Test status
Simulation time 8465239657 ps
CPU time 8.29 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204084 kb
Host smart-80a6acaf-c8b1-47f7-b446-c09bd3505997
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=740789899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.740789899
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.956813042
Short name T568
Test name
Test status
Simulation time 8428434536 ps
CPU time 9.98 seconds
Started May 05 03:16:27 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204060 kb
Host smart-0fd9d188-099c-40e3-aeb7-53af37699d19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=956813042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.956813042
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.799999591
Short name T489
Test name
Test status
Simulation time 8461097389 ps
CPU time 9.34 seconds
Started May 05 03:16:24 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204096 kb
Host smart-efc1a475-6e6d-4853-9a54-b6f8bcece5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79999
9591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.799999591
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2717127044
Short name T1323
Test name
Test status
Simulation time 8392237542 ps
CPU time 8.01 seconds
Started May 05 03:16:17 PM PDT 24
Finished May 05 03:16:26 PM PDT 24
Peak memory 204088 kb
Host smart-dca1b542-2882-42fc-aa72-897ce47f3f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171
27044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2717127044
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.3736436152
Short name T1210
Test name
Test status
Simulation time 8369335788 ps
CPU time 9.79 seconds
Started May 05 03:16:20 PM PDT 24
Finished May 05 03:16:31 PM PDT 24
Peak memory 204104 kb
Host smart-34498d54-cc88-45d2-8ef8-b5446fcde508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364
36152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3736436152
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1099383581
Short name T388
Test name
Test status
Simulation time 74141261 ps
CPU time 2.03 seconds
Started May 05 03:16:21 PM PDT 24
Finished May 05 03:16:23 PM PDT 24
Peak memory 204168 kb
Host smart-48ee6385-1a07-4524-a7ad-71efbfc82b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
83581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1099383581
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1641886464
Short name T1174
Test name
Test status
Simulation time 8393264476 ps
CPU time 7.83 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:41 PM PDT 24
Peak memory 204060 kb
Host smart-c5df6661-c14c-4cdb-bef3-0299240a5565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
86464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1641886464
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3542527181
Short name T184
Test name
Test status
Simulation time 8363975141 ps
CPU time 8.52 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:36 PM PDT 24
Peak memory 204116 kb
Host smart-da59ede3-6442-4829-97f5-70b7ed6629b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
27181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3542527181
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2182925645
Short name T158
Test name
Test status
Simulation time 8436967930 ps
CPU time 8.8 seconds
Started May 05 03:16:20 PM PDT 24
Finished May 05 03:16:29 PM PDT 24
Peak memory 204064 kb
Host smart-c80a5936-06ac-441e-b010-85a07cad5b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21829
25645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2182925645
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4254098643
Short name T2
Test name
Test status
Simulation time 8418795692 ps
CPU time 7.86 seconds
Started May 05 03:16:20 PM PDT 24
Finished May 05 03:16:28 PM PDT 24
Peak memory 204136 kb
Host smart-3adc566d-ef2e-4916-baae-95ec3f4a52c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
98643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4254098643
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3065850768
Short name T655
Test name
Test status
Simulation time 8439754901 ps
CPU time 8.2 seconds
Started May 05 03:16:20 PM PDT 24
Finished May 05 03:16:28 PM PDT 24
Peak memory 204052 kb
Host smart-d6837447-1244-44be-97bd-d14740422a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30658
50768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3065850768
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3790303926
Short name T1351
Test name
Test status
Simulation time 8460825524 ps
CPU time 7.65 seconds
Started May 05 03:16:20 PM PDT 24
Finished May 05 03:16:28 PM PDT 24
Peak memory 204044 kb
Host smart-a123944b-4bb2-4961-9b68-76538ec4b72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37903
03926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3790303926
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.643335169
Short name T1075
Test name
Test status
Simulation time 8387370122 ps
CPU time 8.43 seconds
Started May 05 03:16:20 PM PDT 24
Finished May 05 03:16:29 PM PDT 24
Peak memory 204076 kb
Host smart-3ce39720-e81a-42a3-bacf-fce1b9f4b741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64333
5169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.643335169
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.4230792906
Short name T814
Test name
Test status
Simulation time 8384177155 ps
CPU time 7.74 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:35 PM PDT 24
Peak memory 204104 kb
Host smart-6c28eeb0-4df2-4f5e-82f0-fa1bf9f11769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
92906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.4230792906
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2495415816
Short name T205
Test name
Test status
Simulation time 8404527361 ps
CPU time 7.74 seconds
Started May 05 03:16:24 PM PDT 24
Finished May 05 03:16:32 PM PDT 24
Peak memory 204116 kb
Host smart-5a36adac-6aa0-4d27-81d4-ddcf4e85e629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24954
15816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2495415816
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.11275301
Short name T936
Test name
Test status
Simulation time 55721638 ps
CPU time 0.66 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:26 PM PDT 24
Peak memory 203920 kb
Host smart-23f0464c-ce1a-4b42-b363-72c1250a260c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11275
301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.11275301
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.879833191
Short name T700
Test name
Test status
Simulation time 26822967856 ps
CPU time 54.7 seconds
Started May 05 03:16:24 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204416 kb
Host smart-29db19ad-62d9-4e6a-9f42-69c274d830b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87983
3191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.879833191
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3680069306
Short name T505
Test name
Test status
Simulation time 8403349486 ps
CPU time 8.91 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204084 kb
Host smart-ef785586-8a85-4f2e-8048-56eba1061258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
69306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3680069306
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3712455106
Short name T1262
Test name
Test status
Simulation time 8432366840 ps
CPU time 7.84 seconds
Started May 05 03:16:24 PM PDT 24
Finished May 05 03:16:33 PM PDT 24
Peak memory 204108 kb
Host smart-56fafa86-a348-4767-b4b7-973bdb907af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37124
55106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3712455106
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3167408540
Short name T1193
Test name
Test status
Simulation time 8413155224 ps
CPU time 7.51 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:35 PM PDT 24
Peak memory 204136 kb
Host smart-7af38a85-e7c6-4df8-8c09-3ceab70bd277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31674
08540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3167408540
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1184606408
Short name T1004
Test name
Test status
Simulation time 8389541056 ps
CPU time 8.74 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:42 PM PDT 24
Peak memory 204032 kb
Host smart-5726eb3a-9403-4f97-b29b-6b20491d6b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11846
06408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1184606408
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.407569092
Short name T389
Test name
Test status
Simulation time 8371678164 ps
CPU time 8.32 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:33 PM PDT 24
Peak memory 204088 kb
Host smart-6bf5c662-d8af-41e4-a849-e6a363cc6019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40756
9092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.407569092
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1814798279
Short name T1123
Test name
Test status
Simulation time 8480094845 ps
CPU time 8.39 seconds
Started May 05 03:16:18 PM PDT 24
Finished May 05 03:16:27 PM PDT 24
Peak memory 204088 kb
Host smart-43e606bf-16c9-4006-a233-db6541bf749f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18147
98279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1814798279
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.232733937
Short name T1257
Test name
Test status
Simulation time 8425582851 ps
CPU time 8.38 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:33 PM PDT 24
Peak memory 204124 kb
Host smart-f89aa70c-174d-4778-8c0a-9bcad9a8553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23273
3937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.232733937
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.476791417
Short name T362
Test name
Test status
Simulation time 8416711391 ps
CPU time 8.79 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:36 PM PDT 24
Peak memory 204064 kb
Host smart-7f9dfdd7-ab1c-4fe4-b011-ef82f374436a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47679
1417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.476791417
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.1842110177
Short name T51
Test name
Test status
Simulation time 8485210780 ps
CPU time 7.99 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204072 kb
Host smart-01c9a7a2-c8aa-473c-ab6f-1ca1da47fed1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1842110177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.1842110177
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.175907201
Short name T135
Test name
Test status
Simulation time 8382142741 ps
CPU time 10.19 seconds
Started May 05 03:16:32 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 203820 kb
Host smart-124fce69-87e9-4c99-8d2f-da1440095a38
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=175907201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.175907201
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3940888253
Short name T906
Test name
Test status
Simulation time 8388214407 ps
CPU time 10.05 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:40 PM PDT 24
Peak memory 204104 kb
Host smart-cd995a0a-ec74-4587-b317-ff01b131aefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39408
88253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3940888253
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2338060346
Short name T1141
Test name
Test status
Simulation time 8372787903 ps
CPU time 8.29 seconds
Started May 05 03:16:23 PM PDT 24
Finished May 05 03:16:32 PM PDT 24
Peak memory 204100 kb
Host smart-dadbde41-0508-445e-a4e8-376e9f71e40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23380
60346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2338060346
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.1680068905
Short name T992
Test name
Test status
Simulation time 8386992024 ps
CPU time 8.32 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204088 kb
Host smart-caafb609-4649-4622-9383-8466d630ca83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16800
68905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1680068905
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2662232921
Short name T1352
Test name
Test status
Simulation time 205418652 ps
CPU time 2.06 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:28 PM PDT 24
Peak memory 204180 kb
Host smart-14653567-04a6-487e-8b41-a6d7e528607b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
32921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2662232921
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2317868866
Short name T1136
Test name
Test status
Simulation time 8403460994 ps
CPU time 8.11 seconds
Started May 05 03:16:28 PM PDT 24
Finished May 05 03:16:37 PM PDT 24
Peak memory 204108 kb
Host smart-ddca67fc-bb7f-4856-baa4-d98bdd5e3754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23178
68866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2317868866
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3359284720
Short name T842
Test name
Test status
Simulation time 8375640687 ps
CPU time 7.79 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204120 kb
Host smart-e1b35787-74e9-4222-a63a-f3c70de871c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33592
84720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3359284720
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3792120393
Short name T153
Test name
Test status
Simulation time 8433241714 ps
CPU time 8.26 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:36 PM PDT 24
Peak memory 204128 kb
Host smart-d70d7e68-2ad2-477e-a700-809145d9dade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37921
20393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3792120393
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.898019216
Short name T780
Test name
Test status
Simulation time 8416672350 ps
CPU time 9.15 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:16:35 PM PDT 24
Peak memory 204128 kb
Host smart-cc472a03-205d-449a-9f81-6e6787a06a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89801
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.898019216
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4276714
Short name T1330
Test name
Test status
Simulation time 8395360560 ps
CPU time 7.72 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:35 PM PDT 24
Peak memory 204076 kb
Host smart-40538885-6b73-4d9d-ae6a-dc9b4eca6480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42767
14 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4276714
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3256663498
Short name T18
Test name
Test status
Simulation time 8425316679 ps
CPU time 9.12 seconds
Started May 05 03:16:24 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204116 kb
Host smart-0412c103-5fd5-4882-af63-c016b7ea6fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
63498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3256663498
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1741795043
Short name T1309
Test name
Test status
Simulation time 8404628154 ps
CPU time 10.01 seconds
Started May 05 03:16:26 PM PDT 24
Finished May 05 03:16:36 PM PDT 24
Peak memory 204136 kb
Host smart-2f63de64-6e6c-41bc-87bf-fb08046c5d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
95043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1741795043
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.426417754
Short name T1196
Test name
Test status
Simulation time 8399971403 ps
CPU time 10.05 seconds
Started May 05 03:16:24 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204140 kb
Host smart-98db58f8-e4b6-4608-95ca-844dc9c00ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42641
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.426417754
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.839278286
Short name T899
Test name
Test status
Simulation time 8412026580 ps
CPU time 9.19 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204080 kb
Host smart-c88251cd-ab7d-47ae-a398-9908952c7836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83927
8286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.839278286
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.600196267
Short name T566
Test name
Test status
Simulation time 8368974231 ps
CPU time 8.99 seconds
Started May 05 03:16:28 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204104 kb
Host smart-e3aebaea-4549-4bee-beda-f3169fd44b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60019
6267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.600196267
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.737678851
Short name T561
Test name
Test status
Simulation time 64642833 ps
CPU time 0.71 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:31 PM PDT 24
Peak memory 204152 kb
Host smart-6433597a-61c9-4196-b874-0c52704fc6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73767
8851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.737678851
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3527881035
Short name T924
Test name
Test status
Simulation time 29256705021 ps
CPU time 59.11 seconds
Started May 05 03:16:25 PM PDT 24
Finished May 05 03:17:24 PM PDT 24
Peak memory 204376 kb
Host smart-56d2f9c5-5bf6-4586-aed5-4acca3223ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278
81035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3527881035
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4181243000
Short name T564
Test name
Test status
Simulation time 8392081549 ps
CPU time 8.41 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204132 kb
Host smart-888d3ba2-14ae-45aa-8d5d-e248662edc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41812
43000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4181243000
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2278978628
Short name T584
Test name
Test status
Simulation time 8419849636 ps
CPU time 8.34 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204140 kb
Host smart-bc73b782-2c01-42d9-b418-a242f298a69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
78628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2278978628
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.552858369
Short name T846
Test name
Test status
Simulation time 8411199512 ps
CPU time 8.27 seconds
Started May 05 03:16:28 PM PDT 24
Finished May 05 03:16:37 PM PDT 24
Peak memory 204096 kb
Host smart-23884023-ad92-4239-8967-e8b448a1324e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55285
8369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.552858369
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2498571674
Short name T1372
Test name
Test status
Simulation time 8387233943 ps
CPU time 8.58 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204124 kb
Host smart-0996bf5a-0ef7-453c-9246-a9cc4820a6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24985
71674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2498571674
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3710164746
Short name T1269
Test name
Test status
Simulation time 8367295185 ps
CPU time 7.81 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204132 kb
Host smart-5f367b29-3466-4a3f-9c1b-017d53934c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37101
64746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3710164746
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2010618046
Short name T1247
Test name
Test status
Simulation time 8418916110 ps
CPU time 8.34 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:40 PM PDT 24
Peak memory 204060 kb
Host smart-4f6e11ce-3ea4-4514-98f7-b0c596253a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
18046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2010618046
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1817722091
Short name T470
Test name
Test status
Simulation time 8410610600 ps
CPU time 7.65 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204024 kb
Host smart-726d5f47-5984-486a-ab41-f8391db01b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18177
22091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1817722091
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3402186568
Short name T1089
Test name
Test status
Simulation time 8400055098 ps
CPU time 8.37 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:42 PM PDT 24
Peak memory 204116 kb
Host smart-ad1a815d-04b6-4524-8e82-d28588130986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34021
86568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3402186568
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3425016236
Short name T50
Test name
Test status
Simulation time 8463805652 ps
CPU time 9.84 seconds
Started May 05 03:16:37 PM PDT 24
Finished May 05 03:16:47 PM PDT 24
Peak memory 204072 kb
Host smart-097fb490-86af-42ed-825d-12efbb05b72f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3425016236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3425016236
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.477360446
Short name T789
Test name
Test status
Simulation time 8381175657 ps
CPU time 8.47 seconds
Started May 05 03:16:32 PM PDT 24
Finished May 05 03:16:41 PM PDT 24
Peak memory 204104 kb
Host smart-abbf8f31-0403-4830-ae6f-d6785be27dea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=477360446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.477360446
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.3276461674
Short name T698
Test name
Test status
Simulation time 8469986330 ps
CPU time 7.7 seconds
Started May 05 03:16:35 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 203892 kb
Host smart-e8ca3966-6edb-497e-ae28-f6c2f15394c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32764
61674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.3276461674
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1147881444
Short name T893
Test name
Test status
Simulation time 8375789491 ps
CPU time 9.6 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:40 PM PDT 24
Peak memory 204112 kb
Host smart-cc8b8bfc-2c62-46d7-9b49-72540ece3e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
81444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1147881444
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.3028469339
Short name T430
Test name
Test status
Simulation time 8429997822 ps
CPU time 7.74 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204100 kb
Host smart-da947a67-d2c3-4257-a50a-34768d8a1f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30284
69339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3028469339
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4032135650
Short name T613
Test name
Test status
Simulation time 170759792 ps
CPU time 1.85 seconds
Started May 05 03:16:32 PM PDT 24
Finished May 05 03:16:34 PM PDT 24
Peak memory 204136 kb
Host smart-33526cf3-1673-4496-aabe-9c6081841b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40321
35650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4032135650
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.206984588
Short name T991
Test name
Test status
Simulation time 8443879198 ps
CPU time 7.68 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:41 PM PDT 24
Peak memory 204168 kb
Host smart-5054e6f6-9713-4a30-907f-c2ba3dffedd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
4588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.206984588
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.451530053
Short name T1296
Test name
Test status
Simulation time 8377924962 ps
CPU time 7.55 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:41 PM PDT 24
Peak memory 204104 kb
Host smart-83ccd673-4db4-4189-a174-b080215a524d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45153
0053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.451530053
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3363336879
Short name T1068
Test name
Test status
Simulation time 8490165294 ps
CPU time 7.96 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204128 kb
Host smart-6cbca869-adfe-444a-9b3b-4175867ea1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
36879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3363336879
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1499310423
Short name T534
Test name
Test status
Simulation time 8419108794 ps
CPU time 8.29 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204104 kb
Host smart-9448aaad-816d-4213-b581-017f4b947128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14993
10423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1499310423
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4075746752
Short name T585
Test name
Test status
Simulation time 8371699471 ps
CPU time 8.61 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:42 PM PDT 24
Peak memory 204120 kb
Host smart-293e3658-afba-46fc-b822-88dc900adf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40757
46752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4075746752
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.338422620
Short name T524
Test name
Test status
Simulation time 8421285998 ps
CPU time 8.28 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204108 kb
Host smart-9b002ab4-8ba0-42a7-b0d5-da644e1326cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33842
2620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.338422620
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3577607567
Short name T228
Test name
Test status
Simulation time 8386096289 ps
CPU time 8.16 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204056 kb
Host smart-a8e7790f-bdfa-4288-b743-f93e929e1316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35776
07567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3577607567
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.371534542
Short name T488
Test name
Test status
Simulation time 8376763225 ps
CPU time 8.17 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204088 kb
Host smart-490fc2f8-eb78-406a-a20f-0301e096f672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37153
4542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.371534542
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3006745632
Short name T1033
Test name
Test status
Simulation time 8412463627 ps
CPU time 8.68 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 204156 kb
Host smart-07b868ee-a14e-46c0-b562-9a1d2a9eddf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
45632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3006745632
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.340349450
Short name T605
Test name
Test status
Simulation time 8373587701 ps
CPU time 7.96 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204084 kb
Host smart-fcc3386a-36a8-4733-b7a2-4f96af84735f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34034
9450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.340349450
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.717174680
Short name T34
Test name
Test status
Simulation time 58736347 ps
CPU time 0.67 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:36 PM PDT 24
Peak memory 204004 kb
Host smart-6251840b-ca20-471e-9912-3fef7fda3faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71717
4680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.717174680
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3758783027
Short name T251
Test name
Test status
Simulation time 23550917030 ps
CPU time 45.8 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:17:17 PM PDT 24
Peak memory 204384 kb
Host smart-24e398cc-5934-43eb-b811-b5ffe8d8c9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
83027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3758783027
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3253491120
Short name T503
Test name
Test status
Simulation time 8383848442 ps
CPU time 7.59 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:40 PM PDT 24
Peak memory 204052 kb
Host smart-5d1cb6c1-a4ee-4b65-bc27-81f4dc643366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32534
91120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3253491120
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3478476476
Short name T715
Test name
Test status
Simulation time 8428510281 ps
CPU time 8.74 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204076 kb
Host smart-280a0453-2fa4-4a9b-a458-259d9724a8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34784
76476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3478476476
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.620679988
Short name T319
Test name
Test status
Simulation time 8387441864 ps
CPU time 8.52 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204120 kb
Host smart-ee8234dd-d514-4ee1-b568-d1897d21146f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62067
9988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.620679988
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3474899663
Short name T180
Test name
Test status
Simulation time 8378808063 ps
CPU time 7.59 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 204084 kb
Host smart-ddd39f82-c282-4d7c-85c2-323de124de52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34748
99663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3474899663
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3985289079
Short name T740
Test name
Test status
Simulation time 8384895515 ps
CPU time 9.23 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 204124 kb
Host smart-0b1f0545-9b64-437e-8cdd-76969645450a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39852
89079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3985289079
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1680506265
Short name T797
Test name
Test status
Simulation time 8456143672 ps
CPU time 8.31 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:40 PM PDT 24
Peak memory 204084 kb
Host smart-7fedeeeb-2757-4646-94a2-5ebe1f7e9de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
06265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1680506265
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1769246528
Short name T598
Test name
Test status
Simulation time 8433502127 ps
CPU time 8.65 seconds
Started May 05 03:16:29 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204120 kb
Host smart-93f9cc4f-3fa5-458f-8591-3f3553d5578f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17692
46528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1769246528
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1555153235
Short name T749
Test name
Test status
Simulation time 8411669136 ps
CPU time 7.75 seconds
Started May 05 03:16:30 PM PDT 24
Finished May 05 03:16:38 PM PDT 24
Peak memory 204048 kb
Host smart-9343900e-5dcb-4dd9-b586-68efea4d910d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15551
53235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1555153235
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3811821999
Short name T352
Test name
Test status
Simulation time 8490850542 ps
CPU time 10.42 seconds
Started May 05 03:16:38 PM PDT 24
Finished May 05 03:16:49 PM PDT 24
Peak memory 204092 kb
Host smart-07e7e07a-21f1-4426-8ca5-8e4cd95ee4a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3811821999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3811821999
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.3676371114
Short name T327
Test name
Test status
Simulation time 8389163986 ps
CPU time 10.47 seconds
Started May 05 03:16:38 PM PDT 24
Finished May 05 03:16:50 PM PDT 24
Peak memory 204092 kb
Host smart-48b85814-4124-4b65-b8f8-56e3eb4f776a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3676371114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.3676371114
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.3309941885
Short name T141
Test name
Test status
Simulation time 8392084242 ps
CPU time 7.29 seconds
Started May 05 03:16:39 PM PDT 24
Finished May 05 03:16:47 PM PDT 24
Peak memory 204048 kb
Host smart-b165aced-6b82-4587-8723-035a53d5c52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33099
41885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.3309941885
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.4268711824
Short name T1267
Test name
Test status
Simulation time 8376422818 ps
CPU time 8.12 seconds
Started May 05 03:16:35 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204032 kb
Host smart-0211a63c-d592-47b4-ae9b-bdf952e16faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42687
11824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.4268711824
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.4288438206
Short name T1305
Test name
Test status
Simulation time 8415384824 ps
CPU time 8.1 seconds
Started May 05 03:16:32 PM PDT 24
Finished May 05 03:16:41 PM PDT 24
Peak memory 204100 kb
Host smart-ade7b15d-c248-44f6-bc37-122cc8d8cf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
38206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.4288438206
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1107344677
Short name T484
Test name
Test status
Simulation time 183308748 ps
CPU time 1.65 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:37 PM PDT 24
Peak memory 203852 kb
Host smart-0faadac7-8dc7-4475-80e8-37e1257487aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11073
44677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1107344677
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.4231875025
Short name T1328
Test name
Test status
Simulation time 8461162865 ps
CPU time 7.72 seconds
Started May 05 03:16:39 PM PDT 24
Finished May 05 03:16:48 PM PDT 24
Peak memory 204084 kb
Host smart-f3f6b59f-2366-4885-bb26-27ef29086ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42318
75025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.4231875025
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.728494363
Short name T679
Test name
Test status
Simulation time 8371706301 ps
CPU time 8.45 seconds
Started May 05 03:16:36 PM PDT 24
Finished May 05 03:16:45 PM PDT 24
Peak memory 204104 kb
Host smart-cdc5e6de-e02d-40e7-9f80-b37036600aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72849
4363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.728494363
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1372159909
Short name T144
Test name
Test status
Simulation time 8394816397 ps
CPU time 7.68 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 204088 kb
Host smart-6842df49-6e61-459d-a483-0f2de0431001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13721
59909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1372159909
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.237817667
Short name T953
Test name
Test status
Simulation time 8412245117 ps
CPU time 8.73 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 204132 kb
Host smart-d1ac253e-ca1d-4960-8738-5905c6eb05c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
7667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.237817667
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2522034193
Short name T316
Test name
Test status
Simulation time 8395877287 ps
CPU time 8.05 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204088 kb
Host smart-3dab0c3f-0549-4f5b-a6f6-ce22f0b80df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25220
34193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2522034193
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.367429716
Short name T116
Test name
Test status
Simulation time 8427331012 ps
CPU time 9.52 seconds
Started May 05 03:16:36 PM PDT 24
Finished May 05 03:16:46 PM PDT 24
Peak memory 204120 kb
Host smart-b9f1766b-4ffc-4227-ac54-5de23a2ab665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
9716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.367429716
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3853295265
Short name T15
Test name
Test status
Simulation time 8376202321 ps
CPU time 7.56 seconds
Started May 05 03:16:36 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204068 kb
Host smart-31ba815e-0ce7-4b80-8b53-322dfb4cac25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38532
95265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3853295265
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3415954408
Short name T642
Test name
Test status
Simulation time 8379841955 ps
CPU time 7.59 seconds
Started May 05 03:16:31 PM PDT 24
Finished May 05 03:16:40 PM PDT 24
Peak memory 204016 kb
Host smart-c7fed0d5-4eec-44a4-ae56-3269973d4c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159
54408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3415954408
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2050976406
Short name T932
Test name
Test status
Simulation time 8399497651 ps
CPU time 9.51 seconds
Started May 05 03:16:39 PM PDT 24
Finished May 05 03:16:49 PM PDT 24
Peak memory 204124 kb
Host smart-0f321e1e-f63b-46d0-ade5-500c34387a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20509
76406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2050976406
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1529791768
Short name T1199
Test name
Test status
Simulation time 8388940538 ps
CPU time 8.61 seconds
Started May 05 03:16:40 PM PDT 24
Finished May 05 03:16:49 PM PDT 24
Peak memory 204140 kb
Host smart-5958a49b-7d34-4af8-93f5-decb8d8401ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15297
91768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1529791768
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.257084070
Short name T1240
Test name
Test status
Simulation time 55854602 ps
CPU time 0.67 seconds
Started May 05 03:16:37 PM PDT 24
Finished May 05 03:16:39 PM PDT 24
Peak memory 203996 kb
Host smart-c922c140-af50-464d-9ddc-79aa96fd95b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
4070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.257084070
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2940403878
Short name T217
Test name
Test status
Simulation time 16313421818 ps
CPU time 27.39 seconds
Started May 05 03:16:35 PM PDT 24
Finished May 05 03:17:03 PM PDT 24
Peak memory 203908 kb
Host smart-30e8b520-d76e-4fdb-a6cd-7e71b7a4745d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
03878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2940403878
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2882536518
Short name T207
Test name
Test status
Simulation time 8394919556 ps
CPU time 9.23 seconds
Started May 05 03:16:33 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 204064 kb
Host smart-bf3939b7-9353-4a95-9fa9-be884159997e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
36518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2882536518
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1152270118
Short name T959
Test name
Test status
Simulation time 8396792965 ps
CPU time 7.82 seconds
Started May 05 03:16:36 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204120 kb
Host smart-480a7077-071a-4593-8877-1d013c93ef40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11522
70118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1152270118
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.138214033
Short name T307
Test name
Test status
Simulation time 8388885154 ps
CPU time 8.38 seconds
Started May 05 03:16:36 PM PDT 24
Finished May 05 03:16:45 PM PDT 24
Peak memory 204120 kb
Host smart-4d786cc2-5eec-47df-a306-990c7c47c73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13821
4033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.138214033
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2452779775
Short name T161
Test name
Test status
Simulation time 8397770409 ps
CPU time 7.6 seconds
Started May 05 03:16:39 PM PDT 24
Finished May 05 03:16:47 PM PDT 24
Peak memory 204072 kb
Host smart-3437b08d-1c8a-4140-94cc-65d47de3bf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
79775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2452779775
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3556592499
Short name T895
Test name
Test status
Simulation time 8362160806 ps
CPU time 8.03 seconds
Started May 05 03:16:37 PM PDT 24
Finished May 05 03:16:46 PM PDT 24
Peak memory 204136 kb
Host smart-28e3bd93-0a06-4b8c-8ab3-2bb34e23896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35565
92499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3556592499
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.916175680
Short name T912
Test name
Test status
Simulation time 8422517172 ps
CPU time 7.83 seconds
Started May 05 03:16:35 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 203900 kb
Host smart-3574f0d5-8712-48a8-a7a5-dcaeba15a942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91617
5680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.916175680
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3197119176
Short name T616
Test name
Test status
Simulation time 8429632343 ps
CPU time 7.87 seconds
Started May 05 03:16:38 PM PDT 24
Finished May 05 03:16:46 PM PDT 24
Peak memory 204128 kb
Host smart-0e858d3a-9ac2-4428-b80a-0b92dd2297ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31971
19176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3197119176
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3998079798
Short name T1287
Test name
Test status
Simulation time 8370654713 ps
CPU time 7.99 seconds
Started May 05 03:16:34 PM PDT 24
Finished May 05 03:16:43 PM PDT 24
Peak memory 204064 kb
Host smart-ff76e6c1-b09b-4554-a728-573154f3da14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39980
79798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3998079798
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3157941742
Short name T1007
Test name
Test status
Simulation time 8460448381 ps
CPU time 9.72 seconds
Started May 05 03:16:48 PM PDT 24
Finished May 05 03:16:59 PM PDT 24
Peak memory 204096 kb
Host smart-2b109156-7bfa-4d7c-82ab-c3a1edb693c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3157941742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3157941742
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.3702993756
Short name T335
Test name
Test status
Simulation time 8375095743 ps
CPU time 7.24 seconds
Started May 05 03:16:47 PM PDT 24
Finished May 05 03:16:55 PM PDT 24
Peak memory 204096 kb
Host smart-6e11c1ed-6619-46e3-ba55-865cb2b99b6e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3702993756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.3702993756
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.837790527
Short name T1293
Test name
Test status
Simulation time 8395651664 ps
CPU time 8.42 seconds
Started May 05 03:16:49 PM PDT 24
Finished May 05 03:16:58 PM PDT 24
Peak memory 204052 kb
Host smart-540682dd-fd9c-4622-aca8-7f04eb6d2b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83779
0527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.837790527
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2200941535
Short name T1122
Test name
Test status
Simulation time 8392355458 ps
CPU time 7.46 seconds
Started May 05 03:16:36 PM PDT 24
Finished May 05 03:16:44 PM PDT 24
Peak memory 204024 kb
Host smart-b49b123e-67a6-4786-8e22-240b107611d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22009
41535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2200941535
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.1901322471
Short name T809
Test name
Test status
Simulation time 8404781247 ps
CPU time 7.49 seconds
Started May 05 03:16:38 PM PDT 24
Finished May 05 03:16:46 PM PDT 24
Peak memory 204088 kb
Host smart-6e96ff9a-1d3a-4e9f-a418-abb484ab3a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19013
22471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1901322471
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.4156932703
Short name T949
Test name
Test status
Simulation time 181294705 ps
CPU time 1.55 seconds
Started May 05 03:16:39 PM PDT 24
Finished May 05 03:16:41 PM PDT 24
Peak memory 204240 kb
Host smart-01f5494c-ef84-4e76-bfff-56217afacd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
32703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.4156932703
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.823934486
Short name T1055
Test name
Test status
Simulation time 8391705582 ps
CPU time 10.05 seconds
Started May 05 03:16:42 PM PDT 24
Finished May 05 03:16:53 PM PDT 24
Peak memory 204132 kb
Host smart-aa5f2d51-471f-430a-a01a-52b831fb22ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82393
4486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.823934486
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2556272178
Short name T186
Test name
Test status
Simulation time 8384493705 ps
CPU time 8.49 seconds
Started May 05 03:16:41 PM PDT 24
Finished May 05 03:16:50 PM PDT 24
Peak memory 204080 kb
Host smart-3255010e-8572-483f-b2be-47bb5b9d7781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25562
72178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2556272178
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.79948961
Short name T422
Test name
Test status
Simulation time 8419718030 ps
CPU time 7.96 seconds
Started May 05 03:16:39 PM PDT 24
Finished May 05 03:16:48 PM PDT 24
Peak memory 204068 kb
Host smart-ceb25062-8688-4999-b7e5-401cd0619e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79948
961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.79948961
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.473017081
Short name T1045
Test name
Test status
Simulation time 8417486390 ps
CPU time 9.03 seconds
Started May 05 03:16:40 PM PDT 24
Finished May 05 03:16:50 PM PDT 24
Peak memory 204116 kb
Host smart-10f4d2de-bee1-4a0b-be29-e810ba774229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47301
7081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.473017081
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.393397861
Short name T461
Test name
Test status
Simulation time 8368334796 ps
CPU time 7.53 seconds
Started May 05 03:16:41 PM PDT 24
Finished May 05 03:16:49 PM PDT 24
Peak memory 204100 kb
Host smart-9bf6c968-4333-471b-a23e-9405ecdee72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339
7861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.393397861
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1224903168
Short name T41
Test name
Test status
Simulation time 8438631252 ps
CPU time 8.84 seconds
Started May 05 03:16:41 PM PDT 24
Finished May 05 03:16:51 PM PDT 24
Peak memory 204112 kb
Host smart-b7662963-7406-4942-a2cd-3116a8209f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249
03168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1224903168
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.741156061
Short name T466
Test name
Test status
Simulation time 8420800546 ps
CPU time 9.94 seconds
Started May 05 03:16:42 PM PDT 24
Finished May 05 03:16:52 PM PDT 24
Peak memory 204132 kb
Host smart-3ef4d9be-f86c-4f37-976e-3a4754a612be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74115
6061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.741156061
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1442135320
Short name T669
Test name
Test status
Simulation time 8379800010 ps
CPU time 7.64 seconds
Started May 05 03:16:42 PM PDT 24
Finished May 05 03:16:50 PM PDT 24
Peak memory 204084 kb
Host smart-9b487668-a2ad-43f4-8415-f1464003f1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
35320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1442135320
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2666019446
Short name T1060
Test name
Test status
Simulation time 8397265671 ps
CPU time 8.98 seconds
Started May 05 03:16:50 PM PDT 24
Finished May 05 03:16:59 PM PDT 24
Peak memory 204056 kb
Host smart-acd9008e-bb8d-4ef3-be77-0cf82dac7b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
19446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2666019446
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.446876567
Short name T24
Test name
Test status
Simulation time 8369149679 ps
CPU time 9.91 seconds
Started May 05 03:16:43 PM PDT 24
Finished May 05 03:16:53 PM PDT 24
Peak memory 204284 kb
Host smart-5524e960-7a56-4ca1-ab01-5efb42e3b116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44687
6567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.446876567
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3720282365
Short name T48
Test name
Test status
Simulation time 56027245 ps
CPU time 0.71 seconds
Started May 05 03:16:45 PM PDT 24
Finished May 05 03:16:47 PM PDT 24
Peak memory 203968 kb
Host smart-a438a80f-914d-42c0-a624-e4786b6b8cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37202
82365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3720282365
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1374210596
Short name T232
Test name
Test status
Simulation time 16076535264 ps
CPU time 26.94 seconds
Started May 05 03:16:41 PM PDT 24
Finished May 05 03:17:08 PM PDT 24
Peak memory 204380 kb
Host smart-4f3dafc5-07e7-4b80-8992-ce82f46024ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
10596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1374210596
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1587107788
Short name T444
Test name
Test status
Simulation time 8397707898 ps
CPU time 8.32 seconds
Started May 05 03:16:43 PM PDT 24
Finished May 05 03:16:52 PM PDT 24
Peak memory 204116 kb
Host smart-b82f2167-4710-4d4a-a391-c4542526bc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
07788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1587107788
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3116584619
Short name T1261
Test name
Test status
Simulation time 8402520070 ps
CPU time 8.41 seconds
Started May 05 03:16:43 PM PDT 24
Finished May 05 03:16:52 PM PDT 24
Peak memory 204280 kb
Host smart-dbaef5b2-ab80-4bd8-8cce-6339b78dd2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
84619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3116584619
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3108051602
Short name T628
Test name
Test status
Simulation time 8399324798 ps
CPU time 7.73 seconds
Started May 05 03:16:40 PM PDT 24
Finished May 05 03:16:48 PM PDT 24
Peak memory 204156 kb
Host smart-f95ae7d3-857e-4297-8ccd-db66eaaf0253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
51602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3108051602
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.678776655
Short name T978
Test name
Test status
Simulation time 8375565033 ps
CPU time 8.11 seconds
Started May 05 03:16:44 PM PDT 24
Finished May 05 03:16:52 PM PDT 24
Peak memory 204084 kb
Host smart-dd103508-055d-43f7-82d2-042b281a61b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67877
6655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.678776655
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.950373393
Short name T1342
Test name
Test status
Simulation time 8373052230 ps
CPU time 7.62 seconds
Started May 05 03:16:41 PM PDT 24
Finished May 05 03:16:49 PM PDT 24
Peak memory 204104 kb
Host smart-f1a74413-3130-47f0-acb3-d350dde2eb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95037
3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.950373393
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.4213034083
Short name T885
Test name
Test status
Simulation time 8466965374 ps
CPU time 8.19 seconds
Started May 05 03:16:38 PM PDT 24
Finished May 05 03:16:47 PM PDT 24
Peak memory 204056 kb
Host smart-06be5806-3d65-4fed-ade1-b3cb7a86b3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130
34083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4213034083
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.611866971
Short name T843
Test name
Test status
Simulation time 8402429325 ps
CPU time 10.2 seconds
Started May 05 03:16:43 PM PDT 24
Finished May 05 03:16:54 PM PDT 24
Peak memory 204128 kb
Host smart-a2964ee1-5fc0-4592-bb33-ae56ea85bbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61186
6971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.611866971
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3530036305
Short name T683
Test name
Test status
Simulation time 8403428113 ps
CPU time 8.61 seconds
Started May 05 03:16:46 PM PDT 24
Finished May 05 03:16:56 PM PDT 24
Peak memory 204096 kb
Host smart-8ef692a0-cea4-461a-9236-8b5ada47bc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
36305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3530036305
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.392104648
Short name T340
Test name
Test status
Simulation time 8457388468 ps
CPU time 8.2 seconds
Started May 05 03:16:52 PM PDT 24
Finished May 05 03:17:01 PM PDT 24
Peak memory 204112 kb
Host smart-dc0c9f0c-f637-490b-8a0a-6688e93b41af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=392104648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.392104648
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.561148868
Short name T640
Test name
Test status
Simulation time 8389871626 ps
CPU time 9.33 seconds
Started May 05 03:16:53 PM PDT 24
Finished May 05 03:17:03 PM PDT 24
Peak memory 204112 kb
Host smart-0576cfc3-efb1-4f67-b795-b63cd10abf2b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=561148868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.561148868
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.1843386406
Short name T366
Test name
Test status
Simulation time 8416778338 ps
CPU time 7.82 seconds
Started May 05 03:16:51 PM PDT 24
Finished May 05 03:16:59 PM PDT 24
Peak memory 204064 kb
Host smart-4b0622d5-1618-4280-9e72-6b363512e749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18433
86406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.1843386406
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1163915442
Short name T1284
Test name
Test status
Simulation time 8381376927 ps
CPU time 9.73 seconds
Started May 05 03:16:46 PM PDT 24
Finished May 05 03:16:56 PM PDT 24
Peak memory 204128 kb
Host smart-632c2900-3940-4aa2-9984-d43089bb61c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11639
15442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1163915442
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.1735145651
Short name T554
Test name
Test status
Simulation time 8387939345 ps
CPU time 7.97 seconds
Started May 05 03:16:47 PM PDT 24
Finished May 05 03:16:56 PM PDT 24
Peak memory 204100 kb
Host smart-beee3c51-7103-4d16-b540-3a0d99a3306a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
45651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1735145651
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3470040556
Short name T220
Test name
Test status
Simulation time 206442933 ps
CPU time 1.82 seconds
Started May 05 03:16:51 PM PDT 24
Finished May 05 03:16:53 PM PDT 24
Peak memory 204132 kb
Host smart-fdce8872-9d75-486a-bc75-333e1d7f0c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34700
40556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3470040556
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.498148736
Short name T1374
Test name
Test status
Simulation time 8385175251 ps
CPU time 8.45 seconds
Started May 05 03:16:53 PM PDT 24
Finished May 05 03:17:01 PM PDT 24
Peak memory 204108 kb
Host smart-b21f2da5-87b5-4614-b954-5fe8c86eb4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49814
8736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.498148736
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.724478091
Short name T190
Test name
Test status
Simulation time 8367879509 ps
CPU time 7.53 seconds
Started May 05 03:16:52 PM PDT 24
Finished May 05 03:17:00 PM PDT 24
Peak memory 204100 kb
Host smart-c44c9e9e-357d-4a16-9b31-6b870fac7edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72447
8091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.724478091
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3249455699
Short name T57
Test name
Test status
Simulation time 8433828410 ps
CPU time 8.85 seconds
Started May 05 03:16:47 PM PDT 24
Finished May 05 03:16:57 PM PDT 24
Peak memory 204060 kb
Host smart-d73fbf1a-2673-4cd6-9609-b2f7380a6e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32494
55699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3249455699
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1140806728
Short name T1205
Test name
Test status
Simulation time 8423042030 ps
CPU time 8.26 seconds
Started May 05 03:16:48 PM PDT 24
Finished May 05 03:16:57 PM PDT 24
Peak memory 204116 kb
Host smart-d3c02555-12c4-4ca0-a843-3c60c8d077bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11408
06728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1140806728
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3386489177
Short name T1158
Test name
Test status
Simulation time 8392398780 ps
CPU time 8.31 seconds
Started May 05 03:16:49 PM PDT 24
Finished May 05 03:16:58 PM PDT 24
Peak memory 204088 kb
Host smart-6e88d50b-3e0f-4ce1-af5f-d7c4ad514915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33864
89177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3386489177
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.4048016684
Short name T731
Test name
Test status
Simulation time 8396550752 ps
CPU time 8.2 seconds
Started May 05 03:16:49 PM PDT 24
Finished May 05 03:16:58 PM PDT 24
Peak memory 204084 kb
Host smart-02c140f5-ccdf-4f71-8d1c-5c9a9e0bc52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
16684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.4048016684
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3679409647
Short name T987
Test name
Test status
Simulation time 8402211397 ps
CPU time 8.24 seconds
Started May 05 03:16:51 PM PDT 24
Finished May 05 03:17:00 PM PDT 24
Peak memory 204084 kb
Host smart-10c254a0-1f39-4d88-978c-f20cb434c3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794
09647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3679409647
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.677025582
Short name T1357
Test name
Test status
Simulation time 8372034931 ps
CPU time 9.06 seconds
Started May 05 03:16:45 PM PDT 24
Finished May 05 03:16:55 PM PDT 24
Peak memory 204080 kb
Host smart-e7ff0783-edae-401a-9ea6-d761cb333397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67702
5582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.677025582
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3706994865
Short name T165
Test name
Test status
Simulation time 8405985358 ps
CPU time 7.87 seconds
Started May 05 03:16:47 PM PDT 24
Finished May 05 03:16:56 PM PDT 24
Peak memory 204148 kb
Host smart-3976d066-0352-4fba-bd55-4edd29f9116d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
94865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3706994865
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1362305399
Short name T1090
Test name
Test status
Simulation time 8376391489 ps
CPU time 7.78 seconds
Started May 05 03:16:46 PM PDT 24
Finished May 05 03:16:54 PM PDT 24
Peak memory 204120 kb
Host smart-24c24511-4933-4ad7-b0a3-91bf77fb6132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13623
05399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1362305399
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3527076930
Short name T525
Test name
Test status
Simulation time 42977635 ps
CPU time 0.67 seconds
Started May 05 03:16:51 PM PDT 24
Finished May 05 03:16:52 PM PDT 24
Peak memory 203972 kb
Host smart-c2b16f28-c944-4cab-92c0-6f83b3f974ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
76930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3527076930
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2234393664
Short name T1233
Test name
Test status
Simulation time 20111637497 ps
CPU time 40.42 seconds
Started May 05 03:16:49 PM PDT 24
Finished May 05 03:17:31 PM PDT 24
Peak memory 204416 kb
Host smart-5472a81f-d3e0-43f3-99d0-3d2a0a7e3db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22343
93664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2234393664
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1179770874
Short name T658
Test name
Test status
Simulation time 8380833349 ps
CPU time 7.68 seconds
Started May 05 03:16:48 PM PDT 24
Finished May 05 03:16:57 PM PDT 24
Peak memory 204100 kb
Host smart-d90e74cc-2ff9-462f-8b2d-3f03c6b28128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11797
70874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1179770874
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1748388709
Short name T1128
Test name
Test status
Simulation time 8415553598 ps
CPU time 7.54 seconds
Started May 05 03:16:45 PM PDT 24
Finished May 05 03:16:53 PM PDT 24
Peak memory 204104 kb
Host smart-7cf119ea-7e32-4912-aa7a-8a785013b6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
88709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1748388709
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3965412139
Short name T437
Test name
Test status
Simulation time 8396743842 ps
CPU time 8.11 seconds
Started May 05 03:16:48 PM PDT 24
Finished May 05 03:16:56 PM PDT 24
Peak memory 204084 kb
Host smart-6215e8fd-121d-474d-be62-a59053b9dc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39654
12139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3965412139
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2816830844
Short name T398
Test name
Test status
Simulation time 8373760709 ps
CPU time 7.89 seconds
Started May 05 03:16:49 PM PDT 24
Finished May 05 03:16:58 PM PDT 24
Peak memory 204068 kb
Host smart-a82e811d-83a8-4761-8a5d-92c194e70ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28168
30844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2816830844
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3304242828
Short name T1297
Test name
Test status
Simulation time 8469335363 ps
CPU time 7.76 seconds
Started May 05 03:16:48 PM PDT 24
Finished May 05 03:16:56 PM PDT 24
Peak memory 204096 kb
Host smart-64f96c14-2eb5-4cc6-b897-3e3b97a20cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33042
42828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3304242828
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2546333970
Short name T160
Test name
Test status
Simulation time 8448963344 ps
CPU time 8.12 seconds
Started May 05 03:16:46 PM PDT 24
Finished May 05 03:16:55 PM PDT 24
Peak memory 204144 kb
Host smart-2385e1e9-495d-4fe1-9203-167edbbf8db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25463
33970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2546333970
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1460802923
Short name T1025
Test name
Test status
Simulation time 8387279288 ps
CPU time 8.07 seconds
Started May 05 03:16:49 PM PDT 24
Finished May 05 03:16:58 PM PDT 24
Peak memory 204128 kb
Host smart-3b517235-0424-4ecd-bae3-0c1d245467c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
02923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1460802923
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.872722636
Short name T295
Test name
Test status
Simulation time 8399087846 ps
CPU time 7.74 seconds
Started May 05 03:16:48 PM PDT 24
Finished May 05 03:16:57 PM PDT 24
Peak memory 204096 kb
Host smart-656694fc-dd6a-4ccb-ae98-d8b860825b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87272
2636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.872722636
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3737597248
Short name T836
Test name
Test status
Simulation time 8476443776 ps
CPU time 8.02 seconds
Started May 05 03:12:17 PM PDT 24
Finished May 05 03:12:25 PM PDT 24
Peak memory 204088 kb
Host smart-73b7c89b-5ccf-4e7b-be68-155771a02e47
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3737597248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3737597248
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2214017590
Short name T538
Test name
Test status
Simulation time 8450932053 ps
CPU time 8.35 seconds
Started May 05 03:12:16 PM PDT 24
Finished May 05 03:12:25 PM PDT 24
Peak memory 204060 kb
Host smart-fd1c0935-2014-4ab1-8d36-8aeb99a1c238
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2214017590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2214017590
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.1130112212
Short name T567
Test name
Test status
Simulation time 8413341913 ps
CPU time 10.47 seconds
Started May 05 03:12:17 PM PDT 24
Finished May 05 03:12:28 PM PDT 24
Peak memory 204108 kb
Host smart-ca297871-bb3b-4709-a0c5-ff198d73cdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11301
12212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.1130112212
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1430622612
Short name T788
Test name
Test status
Simulation time 8421640620 ps
CPU time 7.77 seconds
Started May 05 03:12:10 PM PDT 24
Finished May 05 03:12:18 PM PDT 24
Peak memory 204108 kb
Host smart-d6c4204a-e023-4047-bc00-137557d11060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14306
22612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1430622612
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1229280727
Short name T1286
Test name
Test status
Simulation time 8372710531 ps
CPU time 7.7 seconds
Started May 05 03:12:10 PM PDT 24
Finished May 05 03:12:18 PM PDT 24
Peak memory 204088 kb
Host smart-52658caf-48d4-4a86-a9ef-b2415513d673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292
80727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1229280727
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.739699957
Short name T381
Test name
Test status
Simulation time 115841871 ps
CPU time 1.13 seconds
Started May 05 03:12:10 PM PDT 24
Finished May 05 03:12:12 PM PDT 24
Peak memory 204224 kb
Host smart-1b6c4cf2-e149-4cd0-a1b8-a2b7bd677559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73969
9957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.739699957
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.548088686
Short name T759
Test name
Test status
Simulation time 8472526726 ps
CPU time 8.68 seconds
Started May 05 03:12:16 PM PDT 24
Finished May 05 03:12:25 PM PDT 24
Peak memory 204108 kb
Host smart-9995248e-768c-48ae-bf77-c1d06cae0b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54808
8686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.548088686
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3618744635
Short name T772
Test name
Test status
Simulation time 8371759218 ps
CPU time 8.49 seconds
Started May 05 03:12:19 PM PDT 24
Finished May 05 03:12:28 PM PDT 24
Peak memory 204128 kb
Host smart-d12dc854-90eb-4619-a9dc-f5deebfc7ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36187
44635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3618744635
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2512275105
Short name T143
Test name
Test status
Simulation time 8513041513 ps
CPU time 8.92 seconds
Started May 05 03:12:10 PM PDT 24
Finished May 05 03:12:19 PM PDT 24
Peak memory 204060 kb
Host smart-1c71cf46-65a0-465d-af13-94e449803e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25122
75105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2512275105
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4001176362
Short name T729
Test name
Test status
Simulation time 8417027955 ps
CPU time 8.06 seconds
Started May 05 03:12:09 PM PDT 24
Finished May 05 03:12:17 PM PDT 24
Peak memory 204100 kb
Host smart-fad7bbe6-ed52-4835-afdf-4724a8159ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
76362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4001176362
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.948261328
Short name T1112
Test name
Test status
Simulation time 8376488229 ps
CPU time 7.73 seconds
Started May 05 03:12:10 PM PDT 24
Finished May 05 03:12:18 PM PDT 24
Peak memory 204088 kb
Host smart-0a72b712-f790-4e21-825a-4fb165d576e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94826
1328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.948261328
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1221603211
Short name T124
Test name
Test status
Simulation time 8410142522 ps
CPU time 7.75 seconds
Started May 05 03:12:10 PM PDT 24
Finished May 05 03:12:19 PM PDT 24
Peak memory 204084 kb
Host smart-ad72aaf6-8053-457c-a6db-ab6bf3f55b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12216
03211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1221603211
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.320500896
Short name T1212
Test name
Test status
Simulation time 8386663019 ps
CPU time 8.13 seconds
Started May 05 03:12:11 PM PDT 24
Finished May 05 03:12:19 PM PDT 24
Peak memory 204100 kb
Host smart-7e7a822b-af43-4237-93cd-2d1dfadd6284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
0896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.320500896
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3343924186
Short name T848
Test name
Test status
Simulation time 8373889197 ps
CPU time 7.97 seconds
Started May 05 03:12:15 PM PDT 24
Finished May 05 03:12:23 PM PDT 24
Peak memory 204096 kb
Host smart-c9e6d206-f539-42aa-918e-32d4371a4e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33439
24186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3343924186
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3633832473
Short name T177
Test name
Test status
Simulation time 8490166188 ps
CPU time 7.74 seconds
Started May 05 03:12:18 PM PDT 24
Finished May 05 03:12:26 PM PDT 24
Peak memory 204128 kb
Host smart-b4d4995c-adf9-4bf7-bf95-e0728aaef5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338
32473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3633832473
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.101691627
Short name T494
Test name
Test status
Simulation time 8370123854 ps
CPU time 8.12 seconds
Started May 05 03:12:12 PM PDT 24
Finished May 05 03:12:21 PM PDT 24
Peak memory 204124 kb
Host smart-1749ca0b-b9dc-4a4a-b27a-f323b1927ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10169
1627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.101691627
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2107986378
Short name T623
Test name
Test status
Simulation time 67866761 ps
CPU time 0.71 seconds
Started May 05 03:12:25 PM PDT 24
Finished May 05 03:12:26 PM PDT 24
Peak memory 203860 kb
Host smart-830a07bb-2b64-4302-9263-8c8ed24d431a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21079
86378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2107986378
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3664341088
Short name T508
Test name
Test status
Simulation time 29392131575 ps
CPU time 55.83 seconds
Started May 05 03:12:22 PM PDT 24
Finished May 05 03:13:19 PM PDT 24
Peak memory 204284 kb
Host smart-12ea7645-df47-43b6-bbbe-0414e30898d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
41088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3664341088
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2080006680
Short name T1226
Test name
Test status
Simulation time 8389337076 ps
CPU time 7.41 seconds
Started May 05 03:12:14 PM PDT 24
Finished May 05 03:12:22 PM PDT 24
Peak memory 204096 kb
Host smart-820cc8a4-f272-4753-804c-864e3650b3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
06680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2080006680
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3882166196
Short name T1341
Test name
Test status
Simulation time 8464244272 ps
CPU time 8.06 seconds
Started May 05 03:12:13 PM PDT 24
Finished May 05 03:12:21 PM PDT 24
Peak memory 204076 kb
Host smart-24947067-c69a-44b4-90a5-3bc0363cb5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38821
66196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3882166196
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.922008566
Short name T764
Test name
Test status
Simulation time 8395230135 ps
CPU time 7.94 seconds
Started May 05 03:12:14 PM PDT 24
Finished May 05 03:12:23 PM PDT 24
Peak memory 204148 kb
Host smart-769bcf47-9f2a-4b47-be88-60f0c24dc1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92200
8566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.922008566
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.705978747
Short name T66
Test name
Test status
Simulation time 323636144 ps
CPU time 1.28 seconds
Started May 05 03:12:20 PM PDT 24
Finished May 05 03:12:21 PM PDT 24
Peak memory 221464 kb
Host smart-fbcd8471-7bed-4afd-95ef-340cbc9916bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=705978747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.705978747
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2693851166
Short name T1270
Test name
Test status
Simulation time 8373933836 ps
CPU time 8.23 seconds
Started May 05 03:12:18 PM PDT 24
Finished May 05 03:12:27 PM PDT 24
Peak memory 204068 kb
Host smart-b73806fb-d5b6-43f0-b683-9fc2a6c516b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26938
51166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2693851166
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2910167314
Short name T781
Test name
Test status
Simulation time 8369765719 ps
CPU time 9.02 seconds
Started May 05 03:12:13 PM PDT 24
Finished May 05 03:12:22 PM PDT 24
Peak memory 204120 kb
Host smart-b21d9777-ee42-4bbd-a676-700d7e3c3d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
67314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2910167314
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3967511641
Short name T1209
Test name
Test status
Simulation time 8434224065 ps
CPU time 8.8 seconds
Started May 05 03:12:09 PM PDT 24
Finished May 05 03:12:19 PM PDT 24
Peak memory 204136 kb
Host smart-359beb3c-9b46-49b4-81af-866dbc03ba9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
11641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3967511641
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4113016984
Short name T1208
Test name
Test status
Simulation time 8393814291 ps
CPU time 9.54 seconds
Started May 05 03:12:15 PM PDT 24
Finished May 05 03:12:24 PM PDT 24
Peak memory 204128 kb
Host smart-1ea98bcd-548a-4b4e-8d7d-4bb5708ab7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
16984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4113016984
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1959808945
Short name T1008
Test name
Test status
Simulation time 8427242803 ps
CPU time 8.1 seconds
Started May 05 03:12:14 PM PDT 24
Finished May 05 03:12:23 PM PDT 24
Peak memory 204112 kb
Host smart-d317fbea-f6f8-4bc3-8fd5-66bc8250372f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
08945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1959808945
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.1994559085
Short name T408
Test name
Test status
Simulation time 8464588639 ps
CPU time 7.44 seconds
Started May 05 03:16:58 PM PDT 24
Finished May 05 03:17:06 PM PDT 24
Peak memory 204088 kb
Host smart-2be88b58-3d74-4f52-87d5-8b6063bfd1bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1994559085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.1994559085
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.1034133318
Short name T40
Test name
Test status
Simulation time 8407683463 ps
CPU time 7.58 seconds
Started May 05 03:17:00 PM PDT 24
Finished May 05 03:17:09 PM PDT 24
Peak memory 204096 kb
Host smart-904ea9b5-0986-4ff4-92bb-04f45df38859
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1034133318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.1034133318
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.708884566
Short name T572
Test name
Test status
Simulation time 8476767136 ps
CPU time 8.11 seconds
Started May 05 03:17:00 PM PDT 24
Finished May 05 03:17:08 PM PDT 24
Peak memory 204084 kb
Host smart-629f92ba-530b-4e29-89be-c365b176c979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70888
4566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.708884566
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.22935016
Short name T609
Test name
Test status
Simulation time 8376651894 ps
CPU time 9.91 seconds
Started May 05 03:16:52 PM PDT 24
Finished May 05 03:17:02 PM PDT 24
Peak memory 204128 kb
Host smart-ca660aef-8f61-48a2-b9d2-1567d7470520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22935
016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.22935016
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.2486802640
Short name T1175
Test name
Test status
Simulation time 8379602100 ps
CPU time 8.63 seconds
Started May 05 03:16:54 PM PDT 24
Finished May 05 03:17:03 PM PDT 24
Peak memory 204112 kb
Host smart-d61d6336-158c-491a-96d2-6006fd1bfc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24868
02640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2486802640
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.627943549
Short name T58
Test name
Test status
Simulation time 87835806 ps
CPU time 2.21 seconds
Started May 05 03:16:56 PM PDT 24
Finished May 05 03:16:58 PM PDT 24
Peak memory 204168 kb
Host smart-4f3118cc-b289-4112-b528-568dbf367cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62794
3549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.627943549
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.454494950
Short name T1178
Test name
Test status
Simulation time 8386830302 ps
CPU time 8.49 seconds
Started May 05 03:17:01 PM PDT 24
Finished May 05 03:17:10 PM PDT 24
Peak memory 204084 kb
Host smart-992cfa82-72de-448e-a7ac-cd966ac9fc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45449
4950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.454494950
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.549971311
Short name T635
Test name
Test status
Simulation time 8366686128 ps
CPU time 8.74 seconds
Started May 05 03:16:58 PM PDT 24
Finished May 05 03:17:07 PM PDT 24
Peak memory 204144 kb
Host smart-47f06eea-58be-4569-bf68-6fff400affc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54997
1311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.549971311
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2138786513
Short name T742
Test name
Test status
Simulation time 8463827299 ps
CPU time 10.41 seconds
Started May 05 03:16:54 PM PDT 24
Finished May 05 03:17:04 PM PDT 24
Peak memory 204016 kb
Host smart-9e4c9fa9-1ce8-477f-aa75-321060fc3833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21387
86513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2138786513
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.168931024
Short name T808
Test name
Test status
Simulation time 8451319666 ps
CPU time 7.63 seconds
Started May 05 03:16:56 PM PDT 24
Finished May 05 03:17:05 PM PDT 24
Peak memory 204080 kb
Host smart-d31c3f9a-7752-4a1c-b179-844b5f2b77c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
1024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.168931024
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2866425674
Short name T330
Test name
Test status
Simulation time 8373907196 ps
CPU time 8.68 seconds
Started May 05 03:16:56 PM PDT 24
Finished May 05 03:17:05 PM PDT 24
Peak memory 204284 kb
Host smart-fcb9201c-44e5-4978-a4d6-121fe7b9608b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28664
25674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2866425674
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1596858356
Short name T944
Test name
Test status
Simulation time 8424468731 ps
CPU time 7.96 seconds
Started May 05 03:16:56 PM PDT 24
Finished May 05 03:17:05 PM PDT 24
Peak memory 204132 kb
Host smart-fec2212f-cce7-4725-937f-cc972da0e615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15968
58356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1596858356
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2019936608
Short name T344
Test name
Test status
Simulation time 8396470150 ps
CPU time 8.12 seconds
Started May 05 03:16:55 PM PDT 24
Finished May 05 03:17:04 PM PDT 24
Peak memory 204128 kb
Host smart-52509804-1489-42cf-8106-62534fd0e012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20199
36608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2019936608
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2395931247
Short name T374
Test name
Test status
Simulation time 8411246982 ps
CPU time 8.28 seconds
Started May 05 03:16:59 PM PDT 24
Finished May 05 03:17:08 PM PDT 24
Peak memory 204160 kb
Host smart-07b32878-3a6a-44fd-bc66-c519e54dd38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
31247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2395931247
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.206426777
Short name T667
Test name
Test status
Simulation time 8412311633 ps
CPU time 7.71 seconds
Started May 05 03:16:59 PM PDT 24
Finished May 05 03:17:07 PM PDT 24
Peak memory 204128 kb
Host smart-48357522-2bbd-46a1-9ace-b77b84ddc24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20642
6777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.206426777
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2221754590
Short name T662
Test name
Test status
Simulation time 8374879015 ps
CPU time 8.01 seconds
Started May 05 03:16:55 PM PDT 24
Finished May 05 03:17:03 PM PDT 24
Peak memory 204056 kb
Host smart-fae052f4-561f-4a49-89f8-3432eb3773b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22217
54590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2221754590
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3422378918
Short name T712
Test name
Test status
Simulation time 53758140 ps
CPU time 0.69 seconds
Started May 05 03:16:56 PM PDT 24
Finished May 05 03:16:57 PM PDT 24
Peak memory 203896 kb
Host smart-97a85443-22b9-4f69-b3cd-ab226cc49ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34223
78918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3422378918
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3879576513
Short name T1021
Test name
Test status
Simulation time 21189689713 ps
CPU time 39.82 seconds
Started May 05 03:16:54 PM PDT 24
Finished May 05 03:17:34 PM PDT 24
Peak memory 204376 kb
Host smart-5ac25eb2-47a7-4347-8e81-777162d12cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38795
76513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3879576513
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.443952439
Short name T1325
Test name
Test status
Simulation time 8404582482 ps
CPU time 8.29 seconds
Started May 05 03:16:54 PM PDT 24
Finished May 05 03:17:03 PM PDT 24
Peak memory 204124 kb
Host smart-9f091191-fc93-44c0-8f51-e4144996b387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44395
2439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.443952439
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.20042879
Short name T132
Test name
Test status
Simulation time 8403993103 ps
CPU time 7.99 seconds
Started May 05 03:16:56 PM PDT 24
Finished May 05 03:17:05 PM PDT 24
Peak memory 204100 kb
Host smart-0318a891-f054-41ef-a038-eb66c8390de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20042
879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.20042879
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1352600925
Short name T392
Test name
Test status
Simulation time 8441506538 ps
CPU time 7.6 seconds
Started May 05 03:16:58 PM PDT 24
Finished May 05 03:17:06 PM PDT 24
Peak memory 204140 kb
Host smart-bd9024c8-c56b-4357-a37d-c8c42b4ae23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
00925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1352600925
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.7907371
Short name T454
Test name
Test status
Simulation time 8379198609 ps
CPU time 8.25 seconds
Started May 05 03:16:55 PM PDT 24
Finished May 05 03:17:04 PM PDT 24
Peak memory 204072 kb
Host smart-235b9a75-db92-42ec-8e5b-e379e69ca639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79073
71 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.7907371
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3752025620
Short name T1184
Test name
Test status
Simulation time 8409895114 ps
CPU time 8.27 seconds
Started May 05 03:16:58 PM PDT 24
Finished May 05 03:17:07 PM PDT 24
Peak memory 204128 kb
Host smart-9ad18a15-2943-4fcd-ace7-261182bcb99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
25620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3752025620
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2926123779
Short name T643
Test name
Test status
Simulation time 8459641118 ps
CPU time 7.95 seconds
Started May 05 03:16:51 PM PDT 24
Finished May 05 03:16:59 PM PDT 24
Peak memory 204100 kb
Host smart-e3f6c967-8fcb-4832-a690-a91703aae370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29261
23779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2926123779
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.732974317
Short name T314
Test name
Test status
Simulation time 8408902697 ps
CPU time 8.01 seconds
Started May 05 03:16:53 PM PDT 24
Finished May 05 03:17:02 PM PDT 24
Peak memory 204028 kb
Host smart-dabe4876-02bc-428e-95dc-b77b0d6f3cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73297
4317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.732974317
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1335700443
Short name T549
Test name
Test status
Simulation time 8397149822 ps
CPU time 8.18 seconds
Started May 05 03:16:59 PM PDT 24
Finished May 05 03:17:08 PM PDT 24
Peak memory 204160 kb
Host smart-aa706653-d30f-4c33-8323-a26cbd6b37ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13357
00443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1335700443
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.957904358
Short name T1324
Test name
Test status
Simulation time 8468017405 ps
CPU time 10 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:24 PM PDT 24
Peak memory 204088 kb
Host smart-e70bb67d-1ed3-4fd3-adcf-8d40dd3fd49a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=957904358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.957904358
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3126090479
Short name T4
Test name
Test status
Simulation time 8382812196 ps
CPU time 7.58 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:21 PM PDT 24
Peak memory 204088 kb
Host smart-d2ab86bd-58b1-4ffc-ba37-b5013cc61f09
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3126090479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3126090479
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.2892309789
Short name T1271
Test name
Test status
Simulation time 8412284901 ps
CPU time 10.23 seconds
Started May 05 03:17:07 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 204076 kb
Host smart-79578557-d3b6-4778-86a1-ab144a600c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
09789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.2892309789
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1131991587
Short name T1265
Test name
Test status
Simulation time 8385980996 ps
CPU time 8.58 seconds
Started May 05 03:17:02 PM PDT 24
Finished May 05 03:17:11 PM PDT 24
Peak memory 204100 kb
Host smart-441d41cb-5ae1-4dbd-bb04-af66406aa273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319
91587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1131991587
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.2373756621
Short name T629
Test name
Test status
Simulation time 8374468454 ps
CPU time 9.11 seconds
Started May 05 03:17:01 PM PDT 24
Finished May 05 03:17:10 PM PDT 24
Peak memory 204140 kb
Host smart-9e66c6ba-4bac-4918-bfcc-678648d4d3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23737
56621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2373756621
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2876422528
Short name T816
Test name
Test status
Simulation time 297481996 ps
CPU time 2.56 seconds
Started May 05 03:17:00 PM PDT 24
Finished May 05 03:17:03 PM PDT 24
Peak memory 204104 kb
Host smart-4bcf84fd-5de0-4f5d-9728-b673d90cf7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764
22528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2876422528
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.817158408
Short name T892
Test name
Test status
Simulation time 8385818298 ps
CPU time 8.03 seconds
Started May 05 03:17:09 PM PDT 24
Finished May 05 03:17:17 PM PDT 24
Peak memory 204068 kb
Host smart-43f5e161-032c-41a7-aa5f-55c8e1ec0b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81715
8408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.817158408
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2719212909
Short name T192
Test name
Test status
Simulation time 8361114320 ps
CPU time 7.85 seconds
Started May 05 03:17:09 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 204068 kb
Host smart-5531989c-2db3-4584-b1bb-a9858a00ffef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27192
12909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2719212909
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1314879547
Short name T1320
Test name
Test status
Simulation time 8441604784 ps
CPU time 8.34 seconds
Started May 05 03:17:00 PM PDT 24
Finished May 05 03:17:09 PM PDT 24
Peak memory 204084 kb
Host smart-8f3eaffb-46af-40de-ac34-a66cdaf64057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13148
79547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1314879547
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3412509874
Short name T365
Test name
Test status
Simulation time 8436153694 ps
CPU time 8.13 seconds
Started May 05 03:17:01 PM PDT 24
Finished May 05 03:17:10 PM PDT 24
Peak memory 204100 kb
Host smart-6859d2e8-09f8-48d9-96ab-fafa0461acc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
09874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3412509874
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.357487241
Short name T469
Test name
Test status
Simulation time 8376244984 ps
CPU time 7.78 seconds
Started May 05 03:17:01 PM PDT 24
Finished May 05 03:17:09 PM PDT 24
Peak memory 204080 kb
Host smart-788a30c6-f340-413d-9c48-8894a62d1f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35748
7241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.357487241
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.4065423216
Short name T103
Test name
Test status
Simulation time 8493498658 ps
CPU time 8.11 seconds
Started May 05 03:17:00 PM PDT 24
Finished May 05 03:17:08 PM PDT 24
Peak memory 204132 kb
Host smart-8c42257d-e539-4b7b-9289-0a7e36a90db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654
23216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.4065423216
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.86662118
Short name T331
Test name
Test status
Simulation time 8395095215 ps
CPU time 7.4 seconds
Started May 05 03:16:58 PM PDT 24
Finished May 05 03:17:06 PM PDT 24
Peak memory 204132 kb
Host smart-cbee2762-c8b1-47b6-bee6-a48f8e2cf07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86662
118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.86662118
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3725870580
Short name T815
Test name
Test status
Simulation time 8375858531 ps
CPU time 7.98 seconds
Started May 05 03:17:07 PM PDT 24
Finished May 05 03:17:16 PM PDT 24
Peak memory 204056 kb
Host smart-b3a3a181-a0f4-4bcb-87d4-fedce738f1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
70580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3725870580
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1336156046
Short name T178
Test name
Test status
Simulation time 8389635318 ps
CPU time 9.74 seconds
Started May 05 03:17:07 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 204080 kb
Host smart-c9eac96f-0b78-46d5-9f49-919a37b6aa62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
56046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1336156046
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3820291724
Short name T722
Test name
Test status
Simulation time 8369493652 ps
CPU time 9.93 seconds
Started May 05 03:17:03 PM PDT 24
Finished May 05 03:17:14 PM PDT 24
Peak memory 204148 kb
Host smart-e0f46c17-d571-446e-b358-fedf740ffcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
91724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3820291724
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.840812653
Short name T1047
Test name
Test status
Simulation time 40730676 ps
CPU time 0.67 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:14 PM PDT 24
Peak memory 203980 kb
Host smart-a0aeb179-1803-4e43-ab90-7b15c93d6c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84081
2653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.840812653
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1870903826
Short name T233
Test name
Test status
Simulation time 31019945752 ps
CPU time 64.91 seconds
Started May 05 03:17:04 PM PDT 24
Finished May 05 03:18:10 PM PDT 24
Peak memory 204420 kb
Host smart-c8bf6d85-340a-4f09-a892-9925ad458bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
03826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1870903826
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.847249609
Short name T1369
Test name
Test status
Simulation time 8438725385 ps
CPU time 8.39 seconds
Started May 05 03:17:03 PM PDT 24
Finished May 05 03:17:12 PM PDT 24
Peak memory 204084 kb
Host smart-c1ade873-be64-47b0-a4e3-1a2d7b3bb321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84724
9609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.847249609
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3379939194
Short name T142
Test name
Test status
Simulation time 8460515976 ps
CPU time 7.52 seconds
Started May 05 03:17:04 PM PDT 24
Finished May 05 03:17:12 PM PDT 24
Peak memory 204052 kb
Host smart-9a3b0e1e-2420-4d29-a345-f5022395ca77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
39194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3379939194
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1248370902
Short name T399
Test name
Test status
Simulation time 8394293886 ps
CPU time 8.04 seconds
Started May 05 03:17:05 PM PDT 24
Finished May 05 03:17:13 PM PDT 24
Peak memory 204128 kb
Host smart-9ed3a254-cbf1-4874-aa6e-45cf7090025a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
70902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1248370902
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.561770271
Short name T1171
Test name
Test status
Simulation time 8390391371 ps
CPU time 8.26 seconds
Started May 05 03:17:08 PM PDT 24
Finished May 05 03:17:17 PM PDT 24
Peak memory 204100 kb
Host smart-8b1a33e8-014b-47dc-a0f5-52fb638fb453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56177
0271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.561770271
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3103095440
Short name T1087
Test name
Test status
Simulation time 8370278267 ps
CPU time 8.07 seconds
Started May 05 03:17:04 PM PDT 24
Finished May 05 03:17:12 PM PDT 24
Peak memory 204100 kb
Host smart-fd2899fc-e8cf-4fcd-a4d6-d02d4fcdb213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030
95440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3103095440
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.229709896
Short name T866
Test name
Test status
Simulation time 8443156360 ps
CPU time 10.5 seconds
Started May 05 03:16:59 PM PDT 24
Finished May 05 03:17:10 PM PDT 24
Peak memory 204128 kb
Host smart-d93445ea-90a6-4dcc-ad15-c3d55c71ad26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970
9896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.229709896
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3620762641
Short name T594
Test name
Test status
Simulation time 8438373398 ps
CPU time 8.54 seconds
Started May 05 03:17:05 PM PDT 24
Finished May 05 03:17:14 PM PDT 24
Peak memory 204124 kb
Host smart-4fb5373b-e561-4130-b7bf-19fb9fb09f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36207
62641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3620762641
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.895457414
Short name T612
Test name
Test status
Simulation time 8388671508 ps
CPU time 7.62 seconds
Started May 05 03:17:04 PM PDT 24
Finished May 05 03:17:12 PM PDT 24
Peak memory 204072 kb
Host smart-6bdfe335-13ba-4b2f-97bf-0391ab5f954a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89545
7414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.895457414
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2401398701
Short name T933
Test name
Test status
Simulation time 8469815472 ps
CPU time 7.89 seconds
Started May 05 03:17:26 PM PDT 24
Finished May 05 03:17:34 PM PDT 24
Peak memory 204088 kb
Host smart-ebad41f1-e21c-4b81-9595-9a5ce5e0a513
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2401398701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2401398701
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.744971432
Short name T849
Test name
Test status
Simulation time 8379389591 ps
CPU time 7.73 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:21 PM PDT 24
Peak memory 204132 kb
Host smart-ce3be14c-069e-48b8-9c9b-af9d6be48b6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=744971432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.744971432
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.646617187
Short name T1000
Test name
Test status
Simulation time 8448963785 ps
CPU time 7.63 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204096 kb
Host smart-7315729f-219b-475f-b221-3bd47b39aeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64661
7187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.646617187
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2216272517
Short name T436
Test name
Test status
Simulation time 8378151338 ps
CPU time 9.11 seconds
Started May 05 03:17:08 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 204124 kb
Host smart-8071f249-e94a-4813-b75d-3e0c150776fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22162
72517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2216272517
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.3463846673
Short name T657
Test name
Test status
Simulation time 8372123789 ps
CPU time 7.59 seconds
Started May 05 03:17:10 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 204028 kb
Host smart-72e9178d-d7e2-4ed6-b232-4dc3cb6c907f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34638
46673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3463846673
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1760775006
Short name T1350
Test name
Test status
Simulation time 109298398 ps
CPU time 1.16 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:14 PM PDT 24
Peak memory 204236 kb
Host smart-f5dc8869-263f-41d0-b907-d1b3ef3a90ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17607
75006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1760775006
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3565932990
Short name T1268
Test name
Test status
Simulation time 8413470206 ps
CPU time 7.94 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:21 PM PDT 24
Peak memory 204072 kb
Host smart-fafd8b83-0d48-4cb6-9951-cda137542cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
32990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3565932990
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1257566944
Short name T726
Test name
Test status
Simulation time 8370881028 ps
CPU time 7.59 seconds
Started May 05 03:17:11 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204088 kb
Host smart-a6361c89-ea70-4e42-a046-ceceb771db1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575
66944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1257566944
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1537181734
Short name T1043
Test name
Test status
Simulation time 8519464401 ps
CPU time 8.96 seconds
Started May 05 03:17:10 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204036 kb
Host smart-83e69eb5-96c0-4ad0-ba8b-9b5a82c1a872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
81734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1537181734
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3286517306
Short name T803
Test name
Test status
Simulation time 8434594380 ps
CPU time 7.95 seconds
Started May 05 03:17:10 PM PDT 24
Finished May 05 03:17:19 PM PDT 24
Peak memory 203540 kb
Host smart-333f8b50-561a-424b-aab5-491a88f43ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
17306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3286517306
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3154483459
Short name T1044
Test name
Test status
Simulation time 8373641682 ps
CPU time 10.42 seconds
Started May 05 03:17:11 PM PDT 24
Finished May 05 03:17:22 PM PDT 24
Peak memory 204084 kb
Host smart-f10b3475-4dff-4ec9-bf06-275fdf4a678f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
83459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3154483459
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3629311441
Short name T112
Test name
Test status
Simulation time 8467764436 ps
CPU time 8.13 seconds
Started May 05 03:17:10 PM PDT 24
Finished May 05 03:17:19 PM PDT 24
Peak memory 203584 kb
Host smart-5cd548a5-93ee-42ac-8897-7c9b40327125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
11441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3629311441
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.428556543
Short name T14
Test name
Test status
Simulation time 8406334650 ps
CPU time 7.8 seconds
Started May 05 03:17:11 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204080 kb
Host smart-ea55df39-1f79-4151-b0f0-c2806bf54238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42855
6543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.428556543
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1137851246
Short name T443
Test name
Test status
Simulation time 8410074011 ps
CPU time 7.98 seconds
Started May 05 03:17:08 PM PDT 24
Finished May 05 03:17:17 PM PDT 24
Peak memory 204100 kb
Host smart-045bdcae-5359-4c4f-a87e-8f7fc0b68369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
51246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1137851246
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3505783244
Short name T758
Test name
Test status
Simulation time 8396457038 ps
CPU time 10.16 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204128 kb
Host smart-97d23cc9-1817-4fe4-bf7c-6e76e9460a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35057
83244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3505783244
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2161858329
Short name T713
Test name
Test status
Simulation time 8387242072 ps
CPU time 7.65 seconds
Started May 05 03:17:26 PM PDT 24
Finished May 05 03:17:34 PM PDT 24
Peak memory 204084 kb
Host smart-1518f0d5-c686-4325-9965-6358f112fc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21618
58329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2161858329
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2121626039
Short name T339
Test name
Test status
Simulation time 39871559 ps
CPU time 0.66 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:13 PM PDT 24
Peak memory 203944 kb
Host smart-337259ce-9280-4d03-b79e-fc6262a580ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21216
26039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2121626039
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.778800615
Short name T606
Test name
Test status
Simulation time 28766559543 ps
CPU time 66.25 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:18:20 PM PDT 24
Peak memory 204368 kb
Host smart-e63b27cd-866b-4f6e-a3a7-ed6212098801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77880
0615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.778800615
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3225066544
Short name T1002
Test name
Test status
Simulation time 8423226522 ps
CPU time 8.06 seconds
Started May 05 03:17:07 PM PDT 24
Finished May 05 03:17:16 PM PDT 24
Peak memory 204044 kb
Host smart-cdeb1d45-e1b1-4886-8f9d-ba7f360c4b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
66544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3225066544
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1811520702
Short name T1243
Test name
Test status
Simulation time 8412385060 ps
CPU time 7.72 seconds
Started May 05 03:17:09 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 204280 kb
Host smart-1d17e501-69c3-4b74-8bd7-6564c98cf5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18115
20702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1811520702
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.2660410464
Short name T1107
Test name
Test status
Simulation time 8474528488 ps
CPU time 8.62 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:22 PM PDT 24
Peak memory 204104 kb
Host smart-01096eef-1448-43da-8786-38e3733ec958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
10464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.2660410464
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2986167120
Short name T1308
Test name
Test status
Simulation time 8375818411 ps
CPU time 8.09 seconds
Started May 05 03:17:26 PM PDT 24
Finished May 05 03:17:35 PM PDT 24
Peak memory 204080 kb
Host smart-5dd88bcc-cd01-4f72-b6c2-5605da363572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
67120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2986167120
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.989652094
Short name T341
Test name
Test status
Simulation time 8369710597 ps
CPU time 7.63 seconds
Started May 05 03:17:15 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204064 kb
Host smart-f5a651cc-e5d8-4420-a13e-badf3a759c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98965
2094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.989652094
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.152795737
Short name T620
Test name
Test status
Simulation time 8431787960 ps
CPU time 8.89 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204084 kb
Host smart-64ce3270-2c71-4b5d-950e-829347a64056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15279
5737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.152795737
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.345256009
Short name T520
Test name
Test status
Simulation time 8396043712 ps
CPU time 8.93 seconds
Started May 05 03:17:26 PM PDT 24
Finished May 05 03:17:36 PM PDT 24
Peak memory 204076 kb
Host smart-5b897632-1f04-47c3-bc1e-2d22ecf5ce45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
6009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.345256009
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1923890329
Short name T431
Test name
Test status
Simulation time 8403891344 ps
CPU time 9.95 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204136 kb
Host smart-cabb491b-30c6-4748-b6b6-c2ef17fc6a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
90329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1923890329
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.2614578784
Short name T459
Test name
Test status
Simulation time 8464450510 ps
CPU time 7.74 seconds
Started May 05 03:17:18 PM PDT 24
Finished May 05 03:17:26 PM PDT 24
Peak memory 204132 kb
Host smart-5e8aaf1b-2852-40c5-ab72-1d8e51fce2f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2614578784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.2614578784
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.4286453985
Short name T395
Test name
Test status
Simulation time 8382293959 ps
CPU time 7.83 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204032 kb
Host smart-60a9ea1a-75e7-4a42-a883-51bad5fedaaa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4286453985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.4286453985
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.4080371979
Short name T1050
Test name
Test status
Simulation time 8413760561 ps
CPU time 10.19 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:31 PM PDT 24
Peak memory 204016 kb
Host smart-599edd28-c586-463f-b0cc-8f735cd266d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40803
71979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.4080371979
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.4211617276
Short name T639
Test name
Test status
Simulation time 8390511274 ps
CPU time 9.08 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204104 kb
Host smart-7da6d154-11d3-42a0-b1f3-e044bbdb1d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116
17276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.4211617276
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.3962865573
Short name T827
Test name
Test status
Simulation time 8375448471 ps
CPU time 7.65 seconds
Started May 05 03:17:22 PM PDT 24
Finished May 05 03:17:30 PM PDT 24
Peak memory 204084 kb
Host smart-48bc0027-cc69-4782-a15f-8a52ec93b0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39628
65573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3962865573
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3996376109
Short name T218
Test name
Test status
Simulation time 166489072 ps
CPU time 1.2 seconds
Started May 05 03:17:26 PM PDT 24
Finished May 05 03:17:28 PM PDT 24
Peak memory 204212 kb
Host smart-302a01d2-a1d9-46d9-84ef-a801492be1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
76109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3996376109
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3133731273
Short name T387
Test name
Test status
Simulation time 8458162829 ps
CPU time 9.69 seconds
Started May 05 03:17:18 PM PDT 24
Finished May 05 03:17:29 PM PDT 24
Peak memory 204100 kb
Host smart-6e623a4c-7ecd-4566-88a8-6c484b65371e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
31273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3133731273
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2660391309
Short name T1221
Test name
Test status
Simulation time 8366006182 ps
CPU time 7.72 seconds
Started May 05 03:17:11 PM PDT 24
Finished May 05 03:17:19 PM PDT 24
Peak memory 204112 kb
Host smart-c1f10fd5-3521-43ef-aea0-ca3085221b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
91309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2660391309
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1201962290
Short name T133
Test name
Test status
Simulation time 8412127274 ps
CPU time 9.9 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204120 kb
Host smart-902841f9-7def-45fc-9000-1298e4656228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
62290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1201962290
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3637689752
Short name T533
Test name
Test status
Simulation time 8426495523 ps
CPU time 7.86 seconds
Started May 05 03:17:14 PM PDT 24
Finished May 05 03:17:22 PM PDT 24
Peak memory 204120 kb
Host smart-416f9a92-37b5-4986-970f-b4fe2406def2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
89752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3637689752
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1856318756
Short name T1355
Test name
Test status
Simulation time 8388074372 ps
CPU time 7.76 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:21 PM PDT 24
Peak memory 204132 kb
Host smart-a875d7b4-2388-477e-be9c-177ba848331d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18563
18756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1856318756
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3175317601
Short name T123
Test name
Test status
Simulation time 8452827278 ps
CPU time 10.65 seconds
Started May 05 03:17:14 PM PDT 24
Finished May 05 03:17:25 PM PDT 24
Peak memory 204052 kb
Host smart-2fbcc73e-d3db-4d19-97e0-ee4237802a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31753
17601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3175317601
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3033762506
Short name T369
Test name
Test status
Simulation time 8378297015 ps
CPU time 7.66 seconds
Started May 05 03:17:14 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204104 kb
Host smart-a83e4a3f-8903-424f-84b5-ebfa99bdd6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30337
62506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3033762506
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3720400817
Short name T812
Test name
Test status
Simulation time 8440790341 ps
CPU time 7.54 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:22 PM PDT 24
Peak memory 204068 kb
Host smart-eda56cdf-7c42-4967-a4be-a12adc6c4239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37204
00817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3720400817
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3645585910
Short name T910
Test name
Test status
Simulation time 8412443754 ps
CPU time 8.31 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:22 PM PDT 24
Peak memory 204080 kb
Host smart-2c7743e8-7156-4b00-8781-d6bd06976810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455
85910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3645585910
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2363573986
Short name T701
Test name
Test status
Simulation time 8384065041 ps
CPU time 9.34 seconds
Started May 05 03:17:11 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204132 kb
Host smart-0675871c-e273-46b4-8f4a-00da008c7f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635
73986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2363573986
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3380467250
Short name T652
Test name
Test status
Simulation time 54984930 ps
CPU time 0.67 seconds
Started May 05 03:17:13 PM PDT 24
Finished May 05 03:17:15 PM PDT 24
Peak memory 203940 kb
Host smart-e890f106-a1c0-446f-a49c-ca817d07803a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
67250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3380467250
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.4245641655
Short name T862
Test name
Test status
Simulation time 29795928321 ps
CPU time 56.26 seconds
Started May 05 03:17:14 PM PDT 24
Finished May 05 03:18:11 PM PDT 24
Peak memory 204348 kb
Host smart-ed5380be-3c87-4c0a-a005-2a7fd1424cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
41655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.4245641655
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3343700037
Short name T419
Test name
Test status
Simulation time 8417174237 ps
CPU time 10.56 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204092 kb
Host smart-24566d6e-f477-41d0-8391-becb123ea60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33437
00037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3343700037
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2153394331
Short name T801
Test name
Test status
Simulation time 8451412580 ps
CPU time 9.66 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204128 kb
Host smart-aeff1ef7-c31e-4a97-b646-7e23cc1b0ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
94331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2153394331
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1411817704
Short name T916
Test name
Test status
Simulation time 8421837267 ps
CPU time 7.74 seconds
Started May 05 03:17:15 PM PDT 24
Finished May 05 03:17:23 PM PDT 24
Peak memory 204052 kb
Host smart-32ce79b8-b7cd-4e14-9cf4-dfcd7713d78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14118
17704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1411817704
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3544055763
Short name T769
Test name
Test status
Simulation time 8370406165 ps
CPU time 9.24 seconds
Started May 05 03:17:16 PM PDT 24
Finished May 05 03:17:26 PM PDT 24
Peak memory 204132 kb
Host smart-4ae7f3cf-7a53-44bd-87d2-59a6cecc9c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35440
55763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3544055763
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3020502526
Short name T853
Test name
Test status
Simulation time 8387493080 ps
CPU time 7.63 seconds
Started May 05 03:17:14 PM PDT 24
Finished May 05 03:17:22 PM PDT 24
Peak memory 204084 kb
Host smart-8a523191-306b-40d1-8a78-af59ea8bd744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30205
02526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3020502526
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3890317921
Short name T535
Test name
Test status
Simulation time 8412220474 ps
CPU time 7.78 seconds
Started May 05 03:17:12 PM PDT 24
Finished May 05 03:17:20 PM PDT 24
Peak memory 204120 kb
Host smart-a93a1edc-50b5-4ef6-aefe-19440f263a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38903
17921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3890317921
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1998168674
Short name T983
Test name
Test status
Simulation time 8415433869 ps
CPU time 8.65 seconds
Started May 05 03:17:16 PM PDT 24
Finished May 05 03:17:24 PM PDT 24
Peak memory 204060 kb
Host smart-582008ce-941e-4bc6-9092-b7ecab7dea52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
68674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1998168674
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.362117741
Short name T296
Test name
Test status
Simulation time 8380502726 ps
CPU time 7.69 seconds
Started May 05 03:17:16 PM PDT 24
Finished May 05 03:17:24 PM PDT 24
Peak memory 204052 kb
Host smart-c7836004-3660-49e3-830a-e9f36b3dabba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211
7741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.362117741
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1064643288
Short name T1097
Test name
Test status
Simulation time 8485462530 ps
CPU time 9.35 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:33 PM PDT 24
Peak memory 204108 kb
Host smart-09ca80ad-8357-432d-9ec6-8a291638d0c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1064643288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1064643288
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2953146190
Short name T555
Test name
Test status
Simulation time 8384154066 ps
CPU time 8.85 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204064 kb
Host smart-6dbc87bc-438b-419f-be60-77e3ceef521b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953146190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2953146190
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1227610251
Short name T541
Test name
Test status
Simulation time 8420791763 ps
CPU time 8.3 seconds
Started May 05 03:17:24 PM PDT 24
Finished May 05 03:17:33 PM PDT 24
Peak memory 204080 kb
Host smart-caf95eab-56e2-4ce5-a4ec-193ece032480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12276
10251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1227610251
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3256863011
Short name T744
Test name
Test status
Simulation time 8379651473 ps
CPU time 8.07 seconds
Started May 05 03:17:19 PM PDT 24
Finished May 05 03:17:28 PM PDT 24
Peak memory 204144 kb
Host smart-bebd5727-0182-4b3e-9941-4b81edfeeb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32568
63011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3256863011
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.1551795934
Short name T378
Test name
Test status
Simulation time 8378275055 ps
CPU time 10 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:30 PM PDT 24
Peak memory 204112 kb
Host smart-28a6f17c-5031-4453-a425-b0310fe16ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
95934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1551795934
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1176000504
Short name T224
Test name
Test status
Simulation time 94494370 ps
CPU time 1.76 seconds
Started May 05 03:17:18 PM PDT 24
Finished May 05 03:17:21 PM PDT 24
Peak memory 204192 kb
Host smart-b8abdef8-3b8b-4235-a66d-4b06753e3a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
00504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1176000504
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3457830382
Short name T697
Test name
Test status
Simulation time 8379672392 ps
CPU time 8.67 seconds
Started May 05 03:17:21 PM PDT 24
Finished May 05 03:17:30 PM PDT 24
Peak memory 204068 kb
Host smart-090ad395-ce8f-4584-8ce8-e71b078490ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34578
30382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3457830382
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1131709734
Short name T6
Test name
Test status
Simulation time 8365291289 ps
CPU time 8.84 seconds
Started May 05 03:17:28 PM PDT 24
Finished May 05 03:17:37 PM PDT 24
Peak memory 204060 kb
Host smart-49e295d4-f72f-4448-81d2-778e4e415ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11317
09734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1131709734
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.425321026
Short name T966
Test name
Test status
Simulation time 8446890222 ps
CPU time 8.11 seconds
Started May 05 03:17:19 PM PDT 24
Finished May 05 03:17:27 PM PDT 24
Peak memory 204104 kb
Host smart-0308d54d-a8da-4fc4-b1c0-a962f426c61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42532
1026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.425321026
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3861694053
Short name T315
Test name
Test status
Simulation time 8420610433 ps
CPU time 8.18 seconds
Started May 05 03:17:19 PM PDT 24
Finished May 05 03:17:27 PM PDT 24
Peak memory 204100 kb
Host smart-4f490492-809f-4acd-bed4-c44532cc4b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38616
94053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3861694053
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1165045656
Short name T292
Test name
Test status
Simulation time 8368390854 ps
CPU time 7.94 seconds
Started May 05 03:17:24 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204136 kb
Host smart-f591a749-ad83-41a9-abbc-02485f694caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650
45656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1165045656
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3311575445
Short name T108
Test name
Test status
Simulation time 8441402875 ps
CPU time 9.75 seconds
Started May 05 03:17:19 PM PDT 24
Finished May 05 03:17:29 PM PDT 24
Peak memory 204016 kb
Host smart-b866fa1f-2bd7-4db3-a342-76b5def301a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
75445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3311575445
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3103225958
Short name T929
Test name
Test status
Simulation time 8373724459 ps
CPU time 9.61 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:30 PM PDT 24
Peak memory 204100 kb
Host smart-7a568065-d3b2-49d3-ac63-0c1b37a8056b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31032
25958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3103225958
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.718728556
Short name T1066
Test name
Test status
Simulation time 8419407688 ps
CPU time 7.35 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:28 PM PDT 24
Peak memory 204084 kb
Host smart-a716df64-f525-4da8-a011-256aae159b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71872
8556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.718728556
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4073368656
Short name T193
Test name
Test status
Simulation time 8378426672 ps
CPU time 7.52 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:31 PM PDT 24
Peak memory 204084 kb
Host smart-cfcec730-0962-45c5-861c-968382d26099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40733
68656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4073368656
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1959001639
Short name T923
Test name
Test status
Simulation time 8367205751 ps
CPU time 9.23 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:33 PM PDT 24
Peak memory 204088 kb
Host smart-b4dae382-c9a2-439e-a516-ab70ce8743cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19590
01639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1959001639
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.59569860
Short name T1244
Test name
Test status
Simulation time 37649626 ps
CPU time 0.71 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:24 PM PDT 24
Peak memory 204000 kb
Host smart-6c3132e8-24e5-4ab4-95e7-58621374be77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59569
860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.59569860
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2868260905
Short name T1194
Test name
Test status
Simulation time 20284362913 ps
CPU time 39.32 seconds
Started May 05 03:17:18 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204452 kb
Host smart-327a4f36-5261-4187-a24e-6c268072931c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28682
60905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2868260905
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3734069335
Short name T1218
Test name
Test status
Simulation time 8375974893 ps
CPU time 7.32 seconds
Started May 05 03:17:18 PM PDT 24
Finished May 05 03:17:26 PM PDT 24
Peak memory 204112 kb
Host smart-2464c93d-95e6-4599-9090-99ce926cf4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340
69335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3734069335
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3409484596
Short name T928
Test name
Test status
Simulation time 8486676709 ps
CPU time 10.27 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:31 PM PDT 24
Peak memory 204108 kb
Host smart-c2baca8c-7cc8-403f-8a3f-1b4c85132301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34094
84596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3409484596
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2777769674
Short name T570
Test name
Test status
Simulation time 8407171193 ps
CPU time 7.93 seconds
Started May 05 03:17:19 PM PDT 24
Finished May 05 03:17:28 PM PDT 24
Peak memory 204132 kb
Host smart-78fbf9dc-39fd-4e54-9001-85cdf699336b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27777
69674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2777769674
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2523776298
Short name T878
Test name
Test status
Simulation time 8406453663 ps
CPU time 7.76 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:29 PM PDT 24
Peak memory 204160 kb
Host smart-8258b529-3b26-4b98-a95a-f8ccaadfab20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25237
76298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2523776298
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3437667976
Short name T903
Test name
Test status
Simulation time 8370121288 ps
CPU time 9.38 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:30 PM PDT 24
Peak memory 204108 kb
Host smart-b2067677-76ee-438a-93da-0374bb6ad250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34376
67976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3437667976
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2787400738
Short name T792
Test name
Test status
Simulation time 8476978169 ps
CPU time 8.31 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:28 PM PDT 24
Peak memory 204140 kb
Host smart-266d7299-96fa-49e6-9b83-b939ae049252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27874
00738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2787400738
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1634065400
Short name T730
Test name
Test status
Simulation time 8408063610 ps
CPU time 9.58 seconds
Started May 05 03:17:22 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204132 kb
Host smart-ca71a2aa-44f3-4ea8-b908-9dab3d2da856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
65400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1634065400
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1493641699
Short name T1356
Test name
Test status
Simulation time 8403161832 ps
CPU time 9.33 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:29 PM PDT 24
Peak memory 204084 kb
Host smart-c25b82bb-eb5f-4796-9e9c-be42581d7bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14936
41699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1493641699
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3781008197
Short name T1358
Test name
Test status
Simulation time 8457750268 ps
CPU time 7.69 seconds
Started May 05 03:17:28 PM PDT 24
Finished May 05 03:17:37 PM PDT 24
Peak memory 204088 kb
Host smart-daab96e7-3a77-4b4b-bf80-afb59bdabbc1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3781008197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3781008197
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1824123413
Short name T223
Test name
Test status
Simulation time 8382322635 ps
CPU time 7.82 seconds
Started May 05 03:17:26 PM PDT 24
Finished May 05 03:17:35 PM PDT 24
Peak memory 204088 kb
Host smart-53a8ed8e-6e4f-4314-b572-39e76feec5be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1824123413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1824123413
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.3676946720
Short name T1092
Test name
Test status
Simulation time 8470053935 ps
CPU time 8.83 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204060 kb
Host smart-a597b5ff-1cc8-4876-987a-e3706a7da52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36769
46720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3676946720
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1505519891
Short name T627
Test name
Test status
Simulation time 8378751300 ps
CPU time 7.52 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:28 PM PDT 24
Peak memory 204024 kb
Host smart-e0a8f2b0-c1f4-4795-9b9a-f5c39f30c13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
19891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1505519891
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.3222084414
Short name T1254
Test name
Test status
Simulation time 8378038404 ps
CPU time 7.94 seconds
Started May 05 03:17:24 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204072 kb
Host smart-cf0fc46e-05b9-4080-b9a3-d55e7d03da62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32220
84414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3222084414
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2536786839
Short name T1232
Test name
Test status
Simulation time 120844790 ps
CPU time 1.44 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:26 PM PDT 24
Peak memory 204212 kb
Host smart-e541e834-6737-457b-9407-e3c225fa483b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
86839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2536786839
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1799538750
Short name T157
Test name
Test status
Simulation time 8390280759 ps
CPU time 8.07 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:39 PM PDT 24
Peak memory 204144 kb
Host smart-3e8b2a29-656d-44cc-94c3-bcc5ca18887c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
38750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1799538750
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.4197000689
Short name T1121
Test name
Test status
Simulation time 8365583904 ps
CPU time 8.05 seconds
Started May 05 03:17:28 PM PDT 24
Finished May 05 03:17:37 PM PDT 24
Peak memory 204096 kb
Host smart-59235a60-75b5-4954-83b9-7c43374a8437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
00689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.4197000689
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2095768707
Short name T137
Test name
Test status
Simulation time 8458037600 ps
CPU time 8.06 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204084 kb
Host smart-584e3de1-709a-40e9-9a68-a0de243b2a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20957
68707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2095768707
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1983919705
Short name T930
Test name
Test status
Simulation time 8425074028 ps
CPU time 7.9 seconds
Started May 05 03:17:27 PM PDT 24
Finished May 05 03:17:36 PM PDT 24
Peak memory 204060 kb
Host smart-68d0b7ca-1359-4ab9-af99-76a58d4f7aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
19705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1983919705
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3925902255
Short name T971
Test name
Test status
Simulation time 8383877102 ps
CPU time 7.55 seconds
Started May 05 03:17:25 PM PDT 24
Finished May 05 03:17:33 PM PDT 24
Peak memory 204084 kb
Host smart-5d961691-c601-4d5f-abe3-96a781c58a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
02255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3925902255
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1456913372
Short name T550
Test name
Test status
Simulation time 8450737584 ps
CPU time 7.93 seconds
Started May 05 03:17:24 PM PDT 24
Finished May 05 03:17:33 PM PDT 24
Peak memory 204060 kb
Host smart-155431e4-4384-442d-a521-0a47715cec2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14569
13372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1456913372
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2564646132
Short name T665
Test name
Test status
Simulation time 8398693927 ps
CPU time 7.26 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:27 PM PDT 24
Peak memory 204096 kb
Host smart-9a23536a-b102-4836-bc35-faf2ad5d6a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25646
46132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2564646132
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1533256395
Short name T471
Test name
Test status
Simulation time 8374882376 ps
CPU time 8.23 seconds
Started May 05 03:17:20 PM PDT 24
Finished May 05 03:17:29 PM PDT 24
Peak memory 204108 kb
Host smart-7edda220-599b-4a9c-baaa-dede3f5a57a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15332
56395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1533256395
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.682445992
Short name T887
Test name
Test status
Simulation time 8383992201 ps
CPU time 7.39 seconds
Started May 05 03:17:28 PM PDT 24
Finished May 05 03:17:36 PM PDT 24
Peak memory 204076 kb
Host smart-10f42e94-9bd0-4d98-91da-fd6a8269e3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68244
5992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.682445992
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.770738100
Short name T867
Test name
Test status
Simulation time 8372319032 ps
CPU time 8.72 seconds
Started May 05 03:17:27 PM PDT 24
Finished May 05 03:17:37 PM PDT 24
Peak memory 204104 kb
Host smart-10bcf3e1-e837-4fcf-82aa-55526cb44f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77073
8100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.770738100
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1850548142
Short name T36
Test name
Test status
Simulation time 43360405 ps
CPU time 0.65 seconds
Started May 05 03:17:27 PM PDT 24
Finished May 05 03:17:29 PM PDT 24
Peak memory 203952 kb
Host smart-65f178e7-b7e6-47d3-938b-43a66bc0d8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
48142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1850548142
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.4100803179
Short name T94
Test name
Test status
Simulation time 28927106915 ps
CPU time 57.55 seconds
Started May 05 03:17:25 PM PDT 24
Finished May 05 03:18:23 PM PDT 24
Peak memory 204412 kb
Host smart-811e70ef-64cd-4f65-ad51-87802fd5e7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
03179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.4100803179
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1836530943
Short name T942
Test name
Test status
Simulation time 8396409361 ps
CPU time 7.67 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:31 PM PDT 24
Peak memory 204096 kb
Host smart-b4faa922-acef-4dad-83ef-e7485cb6e060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18365
30943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1836530943
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.654912683
Short name T1255
Test name
Test status
Simulation time 8398511170 ps
CPU time 8.2 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204120 kb
Host smart-c524fac5-df51-43c5-a8bb-c3528a37fcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65491
2683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.654912683
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.2065971100
Short name T721
Test name
Test status
Simulation time 8394017318 ps
CPU time 8.13 seconds
Started May 05 03:17:23 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204064 kb
Host smart-dc19d210-398c-451a-abe8-5e2981476e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659
71100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.2065971100
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.793423228
Short name T674
Test name
Test status
Simulation time 8377995901 ps
CPU time 7.75 seconds
Started May 05 03:17:24 PM PDT 24
Finished May 05 03:17:33 PM PDT 24
Peak memory 204088 kb
Host smart-36f8d004-73ff-4972-b04e-9720c5af608c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79342
3228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.793423228
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.238179735
Short name T692
Test name
Test status
Simulation time 8372237580 ps
CPU time 7.83 seconds
Started May 05 03:17:31 PM PDT 24
Finished May 05 03:17:39 PM PDT 24
Peak memory 204060 kb
Host smart-f1bba713-d6c1-4988-9b1a-58cf408ea7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23817
9735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.238179735
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1160414269
Short name T1306
Test name
Test status
Simulation time 8488382841 ps
CPU time 10.11 seconds
Started May 05 03:17:25 PM PDT 24
Finished May 05 03:17:35 PM PDT 24
Peak memory 204128 kb
Host smart-4bc2a314-5ace-4f9a-94dc-25382d95536a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
14269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1160414269
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2642052446
Short name T602
Test name
Test status
Simulation time 8410015470 ps
CPU time 8.09 seconds
Started May 05 03:17:27 PM PDT 24
Finished May 05 03:17:35 PM PDT 24
Peak memory 204052 kb
Host smart-bd986ffe-8280-426d-9cbf-6380c5f73907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26420
52446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2642052446
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3231904561
Short name T823
Test name
Test status
Simulation time 8402313124 ps
CPU time 7.54 seconds
Started May 05 03:17:29 PM PDT 24
Finished May 05 03:17:37 PM PDT 24
Peak memory 204076 kb
Host smart-53ffd1f5-9557-4d1b-a548-0003fb5cb9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
04561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3231904561
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.889840465
Short name T472
Test name
Test status
Simulation time 8465026240 ps
CPU time 7.77 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204132 kb
Host smart-fbb76eba-bed9-42f6-b4b7-7def3fe0e16e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=889840465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.889840465
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.196580850
Short name T544
Test name
Test status
Simulation time 8404137501 ps
CPU time 8.4 seconds
Started May 05 03:17:32 PM PDT 24
Finished May 05 03:17:41 PM PDT 24
Peak memory 204140 kb
Host smart-a27f4590-0ce5-4bac-a26d-ca9fce3c9be8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=196580850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.196580850
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.2889451948
Short name T294
Test name
Test status
Simulation time 8461482161 ps
CPU time 9.43 seconds
Started May 05 03:17:29 PM PDT 24
Finished May 05 03:17:39 PM PDT 24
Peak memory 204080 kb
Host smart-a7d1cd16-4e88-4fdd-8608-25a1f5105926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
51948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.2889451948
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3128869048
Short name T464
Test name
Test status
Simulation time 8380533704 ps
CPU time 8.05 seconds
Started May 05 03:17:27 PM PDT 24
Finished May 05 03:17:36 PM PDT 24
Peak memory 204128 kb
Host smart-c94768d6-c607-43f6-99d2-bec6bb24d524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31288
69048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3128869048
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.201499431
Short name T805
Test name
Test status
Simulation time 8378003437 ps
CPU time 7.93 seconds
Started May 05 03:17:28 PM PDT 24
Finished May 05 03:17:36 PM PDT 24
Peak memory 204100 kb
Host smart-76b1eaee-4425-4778-96e7-ed84315a1a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20149
9431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.201499431
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2747031896
Short name T1140
Test name
Test status
Simulation time 82509599 ps
CPU time 2.07 seconds
Started May 05 03:17:28 PM PDT 24
Finished May 05 03:17:31 PM PDT 24
Peak memory 204180 kb
Host smart-0108bdb3-7a9d-40b8-837d-356d25322d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
31896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2747031896
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.189240058
Short name T589
Test name
Test status
Simulation time 8414509365 ps
CPU time 8.75 seconds
Started May 05 03:17:33 PM PDT 24
Finished May 05 03:17:42 PM PDT 24
Peak memory 204136 kb
Host smart-2684bb64-b048-4eec-bcf4-78d4e7ee8cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18924
0058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.189240058
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2730961837
Short name T204
Test name
Test status
Simulation time 8373313596 ps
CPU time 9.91 seconds
Started May 05 03:17:32 PM PDT 24
Finished May 05 03:17:43 PM PDT 24
Peak memory 204144 kb
Host smart-02df77b1-9039-4fa3-b0d7-e05921d40e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
61837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2730961837
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.238363000
Short name T1083
Test name
Test status
Simulation time 8422967713 ps
CPU time 8.74 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204100 kb
Host smart-e0fc8ee9-061c-4ede-9b47-1903670329ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
3000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.238363000
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.972020646
Short name T425
Test name
Test status
Simulation time 8428012289 ps
CPU time 8.2 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:39 PM PDT 24
Peak memory 204100 kb
Host smart-86a2af6f-d787-4580-aa68-f9f737d9c707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97202
0646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.972020646
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1376607529
Short name T1096
Test name
Test status
Simulation time 8368649555 ps
CPU time 9.72 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204280 kb
Host smart-dae570d7-b361-4f7e-a141-1a8f5210c138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766
07529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1376607529
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1188879031
Short name T1317
Test name
Test status
Simulation time 8452684893 ps
CPU time 9.78 seconds
Started May 05 03:17:31 PM PDT 24
Finished May 05 03:17:41 PM PDT 24
Peak memory 204148 kb
Host smart-cd6a2c54-88c1-4be6-b787-bbb5e4d6cb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
79031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1188879031
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1920789337
Short name T830
Test name
Test status
Simulation time 8387833387 ps
CPU time 7.63 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204120 kb
Host smart-178ff03e-7aed-45fd-b9d1-131b0d87a4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19207
89337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1920789337
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3099208521
Short name T832
Test name
Test status
Simulation time 8384845631 ps
CPU time 9.05 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:39 PM PDT 24
Peak memory 204128 kb
Host smart-6f200f2c-cdc8-47ad-8edd-516049ae520d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30992
08521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3099208521
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1429940706
Short name T804
Test name
Test status
Simulation time 8415009501 ps
CPU time 8.27 seconds
Started May 05 03:17:31 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204080 kb
Host smart-b8f68cf9-1433-446a-8099-3e8c12e146d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299
40706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1429940706
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1660206395
Short name T8
Test name
Test status
Simulation time 8384141716 ps
CPU time 8.92 seconds
Started May 05 03:17:31 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204120 kb
Host smart-7f5cef97-ec97-4080-a8c5-d9fca5fefc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
06395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1660206395
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.168678833
Short name T1065
Test name
Test status
Simulation time 63529044 ps
CPU time 0.7 seconds
Started May 05 03:17:31 PM PDT 24
Finished May 05 03:17:32 PM PDT 24
Peak memory 204004 kb
Host smart-8e838794-8057-442b-8cc8-dfbebbac8a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
8833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.168678833
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3253700423
Short name T763
Test name
Test status
Simulation time 19977236703 ps
CPU time 39 seconds
Started May 05 03:17:32 PM PDT 24
Finished May 05 03:18:11 PM PDT 24
Peak memory 204392 kb
Host smart-0f8a3acd-3fe5-4848-913d-015ea1f07d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
00423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3253700423
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.269350879
Short name T795
Test name
Test status
Simulation time 8408503547 ps
CPU time 8.6 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:46 PM PDT 24
Peak memory 204116 kb
Host smart-7999465f-ed0f-4653-aaa6-a93bd7ead054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26935
0879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.269350879
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2206692268
Short name T1288
Test name
Test status
Simulation time 8439649221 ps
CPU time 7.8 seconds
Started May 05 03:17:33 PM PDT 24
Finished May 05 03:17:41 PM PDT 24
Peak memory 204076 kb
Host smart-1b4284eb-fcf7-43a5-8b16-5e7a03eaefc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066
92268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2206692268
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1083463734
Short name T346
Test name
Test status
Simulation time 8429606742 ps
CPU time 7.48 seconds
Started May 05 03:17:31 PM PDT 24
Finished May 05 03:17:39 PM PDT 24
Peak memory 204108 kb
Host smart-0530299a-651c-485b-9b80-52575def125c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834
63734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1083463734
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2447925841
Short name T1073
Test name
Test status
Simulation time 8378715764 ps
CPU time 9.21 seconds
Started May 05 03:17:30 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204132 kb
Host smart-dcfe7f33-9b1f-42f7-b6f2-990dbeafe149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24479
25841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2447925841
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4179194053
Short name T324
Test name
Test status
Simulation time 8382917475 ps
CPU time 7.79 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204116 kb
Host smart-7433fef4-1101-48a6-b188-544bd2868433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41791
94053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4179194053
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2619548906
Short name T164
Test name
Test status
Simulation time 8457322057 ps
CPU time 7.69 seconds
Started May 05 03:17:27 PM PDT 24
Finished May 05 03:17:36 PM PDT 24
Peak memory 204140 kb
Host smart-31698c68-e880-4f86-a5e3-8573966bdcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26195
48906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2619548906
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.268451973
Short name T1130
Test name
Test status
Simulation time 8439451517 ps
CPU time 7.94 seconds
Started May 05 03:17:34 PM PDT 24
Finished May 05 03:17:42 PM PDT 24
Peak memory 204052 kb
Host smart-7052323f-dbff-45ec-9426-0b2e42c55b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26845
1973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.268451973
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.583933757
Short name T557
Test name
Test status
Simulation time 8402733889 ps
CPU time 10.2 seconds
Started May 05 03:17:29 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204280 kb
Host smart-1a93e7ac-7b53-40d2-aff3-150b0660ddde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58393
3757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.583933757
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.4170334074
Short name T390
Test name
Test status
Simulation time 8497312621 ps
CPU time 10.2 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:48 PM PDT 24
Peak memory 204024 kb
Host smart-2200a0f5-2b96-448f-bc83-a49844dba801
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4170334074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.4170334074
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.3266728854
Short name T1335
Test name
Test status
Simulation time 8384205786 ps
CPU time 9.38 seconds
Started May 05 03:17:41 PM PDT 24
Finished May 05 03:17:51 PM PDT 24
Peak memory 204064 kb
Host smart-3189fdef-7a56-4bf4-8cb9-549b29548706
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3266728854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.3266728854
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.2139856399
Short name T819
Test name
Test status
Simulation time 8453498437 ps
CPU time 10.04 seconds
Started May 05 03:17:39 PM PDT 24
Finished May 05 03:17:49 PM PDT 24
Peak memory 204052 kb
Host smart-7c03270d-d941-4691-a075-5e9ab7a19b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21398
56399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.2139856399
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2500456790
Short name T714
Test name
Test status
Simulation time 8374659576 ps
CPU time 10.24 seconds
Started May 05 03:17:36 PM PDT 24
Finished May 05 03:17:46 PM PDT 24
Peak memory 204096 kb
Host smart-ade6ab44-872f-4422-ae7b-61aca5528e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
56790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2500456790
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.1845844559
Short name T1100
Test name
Test status
Simulation time 8384675057 ps
CPU time 8.21 seconds
Started May 05 03:17:38 PM PDT 24
Finished May 05 03:17:47 PM PDT 24
Peak memory 204120 kb
Host smart-9b86a152-c101-4c52-a4ed-dd41ee0d58eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18458
44559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1845844559
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3187933673
Short name T1064
Test name
Test status
Simulation time 250734702 ps
CPU time 2.43 seconds
Started May 05 03:17:36 PM PDT 24
Finished May 05 03:17:40 PM PDT 24
Peak memory 204104 kb
Host smart-ed68079d-f7df-435c-adf5-be3c816529d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
33673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3187933673
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.882749223
Short name T855
Test name
Test status
Simulation time 8441912269 ps
CPU time 7.86 seconds
Started May 05 03:17:38 PM PDT 24
Finished May 05 03:17:47 PM PDT 24
Peak memory 204128 kb
Host smart-8488b9eb-8329-4958-b9b8-79223a04643c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88274
9223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.882749223
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.475407032
Short name T1249
Test name
Test status
Simulation time 8369340282 ps
CPU time 8.69 seconds
Started May 05 03:17:38 PM PDT 24
Finished May 05 03:17:47 PM PDT 24
Peak memory 204084 kb
Host smart-1dbb1d5a-c19c-4621-bddf-36874c79cefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47540
7032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.475407032
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.72385128
Short name T593
Test name
Test status
Simulation time 8420198159 ps
CPU time 8.68 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:46 PM PDT 24
Peak memory 204128 kb
Host smart-f23222b7-7727-47ca-87a1-4aaf3fa29dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72385
128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.72385128
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3044338128
Short name T243
Test name
Test status
Simulation time 8416436956 ps
CPU time 7.48 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204120 kb
Host smart-65411e5b-c5f5-46b8-b18d-709ac5acb5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30443
38128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3044338128
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2986410666
Short name T400
Test name
Test status
Simulation time 8375689785 ps
CPU time 7.53 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204060 kb
Host smart-6f980f3d-9129-4e27-a663-e1ab04a0341b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29864
10666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2986410666
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1789907036
Short name T854
Test name
Test status
Simulation time 8412800776 ps
CPU time 7.51 seconds
Started May 05 03:17:35 PM PDT 24
Finished May 05 03:17:43 PM PDT 24
Peak memory 204096 kb
Host smart-cfcab34a-6493-4186-a765-d8a309d48090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17899
07036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1789907036
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1577720159
Short name T663
Test name
Test status
Simulation time 8397363938 ps
CPU time 8.07 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204060 kb
Host smart-4de29ed8-98fc-4a49-823b-8e7fc089faae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
20159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1577720159
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3430553834
Short name T1132
Test name
Test status
Simulation time 8385174043 ps
CPU time 8.34 seconds
Started May 05 03:17:36 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204096 kb
Host smart-615bef42-84cf-4d6d-ae25-0bd7eeaa2d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34305
53834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3430553834
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3931017981
Short name T1201
Test name
Test status
Simulation time 8380303187 ps
CPU time 7.97 seconds
Started May 05 03:17:40 PM PDT 24
Finished May 05 03:17:48 PM PDT 24
Peak memory 204112 kb
Host smart-df8eb7e6-7991-4897-849a-f37eb99d3520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39310
17981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3931017981
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1596958042
Short name T582
Test name
Test status
Simulation time 8385077534 ps
CPU time 7.71 seconds
Started May 05 03:17:40 PM PDT 24
Finished May 05 03:17:49 PM PDT 24
Peak memory 204040 kb
Host smart-031a7f0a-8f5f-46c6-84fb-79b98a5b5b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969
58042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1596958042
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2438606876
Short name T402
Test name
Test status
Simulation time 52884192 ps
CPU time 0.65 seconds
Started May 05 03:17:40 PM PDT 24
Finished May 05 03:17:41 PM PDT 24
Peak memory 203992 kb
Host smart-c4a361e0-5e12-41d8-8989-03cde1a104d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386
06876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2438606876
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.470831483
Short name T857
Test name
Test status
Simulation time 22732652802 ps
CPU time 44.22 seconds
Started May 05 03:17:36 PM PDT 24
Finished May 05 03:18:21 PM PDT 24
Peak memory 204368 kb
Host smart-5b97979a-5717-4720-babf-58560aa944ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47083
1483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.470831483
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.773026940
Short name T371
Test name
Test status
Simulation time 8410224188 ps
CPU time 7.63 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:45 PM PDT 24
Peak memory 204116 kb
Host smart-cc17e40b-b625-4784-aa71-23545869bd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77302
6940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.773026940
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3842176755
Short name T1327
Test name
Test status
Simulation time 8398991793 ps
CPU time 8.36 seconds
Started May 05 03:17:34 PM PDT 24
Finished May 05 03:17:43 PM PDT 24
Peak memory 204096 kb
Host smart-05df6bec-af79-430b-b5aa-3aed54e44447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
76755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3842176755
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2241208344
Short name T1301
Test name
Test status
Simulation time 8405095570 ps
CPU time 7.94 seconds
Started May 05 03:17:38 PM PDT 24
Finished May 05 03:17:46 PM PDT 24
Peak memory 204036 kb
Host smart-80d61056-ff63-45d9-be2a-a01bf0b7f170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
08344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2241208344
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3379921139
Short name T997
Test name
Test status
Simulation time 8386237639 ps
CPU time 8.33 seconds
Started May 05 03:17:40 PM PDT 24
Finished May 05 03:17:49 PM PDT 24
Peak memory 204084 kb
Host smart-4f7ab0b5-598f-463b-9023-d837a0610b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
21139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3379921139
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.706792158
Short name T244
Test name
Test status
Simulation time 8379686680 ps
CPU time 10.12 seconds
Started May 05 03:17:38 PM PDT 24
Finished May 05 03:17:48 PM PDT 24
Peak memory 204104 kb
Host smart-5d699bac-e594-44c6-862b-b077cc9be943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70679
2158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.706792158
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2642343088
Short name T91
Test name
Test status
Simulation time 8449657577 ps
CPU time 8.06 seconds
Started May 05 03:17:37 PM PDT 24
Finished May 05 03:17:46 PM PDT 24
Peak memory 204112 kb
Host smart-b01f4998-36f9-456c-b414-5a6d08176afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26423
43088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2642343088
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2169192203
Short name T741
Test name
Test status
Simulation time 8464093547 ps
CPU time 7.61 seconds
Started May 05 03:17:40 PM PDT 24
Finished May 05 03:17:49 PM PDT 24
Peak memory 204032 kb
Host smart-75ddf3c8-4997-43f3-a53f-813cc8f16e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21691
92203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2169192203
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1725679261
Short name T291
Test name
Test status
Simulation time 8395927818 ps
CPU time 7.61 seconds
Started May 05 03:17:40 PM PDT 24
Finished May 05 03:17:48 PM PDT 24
Peak memory 204104 kb
Host smart-c26362de-61d5-4610-b4fd-aad65d9fdba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
79261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1725679261
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.1598617183
Short name T1168
Test name
Test status
Simulation time 8463714305 ps
CPU time 8.09 seconds
Started May 05 03:17:49 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204132 kb
Host smart-d31d3533-21ea-414f-84c1-8e8e35e95de4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1598617183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.1598617183
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.1157147185
Short name T733
Test name
Test status
Simulation time 8376111170 ps
CPU time 8.09 seconds
Started May 05 03:17:47 PM PDT 24
Finished May 05 03:17:55 PM PDT 24
Peak memory 204148 kb
Host smart-30bd5783-aa70-4d87-9782-abbe7fd6b65f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1157147185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.1157147185
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.378832722
Short name T501
Test name
Test status
Simulation time 8474183353 ps
CPU time 9.63 seconds
Started May 05 03:17:50 PM PDT 24
Finished May 05 03:18:00 PM PDT 24
Peak memory 204124 kb
Host smart-798297f5-b952-44f5-9c67-e5dbc8e00ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37883
2722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.378832722
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2233128644
Short name T345
Test name
Test status
Simulation time 8373233195 ps
CPU time 7.99 seconds
Started May 05 03:17:42 PM PDT 24
Finished May 05 03:17:50 PM PDT 24
Peak memory 204060 kb
Host smart-463b75fd-b5e5-448e-9343-80b23ca3b066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22331
28644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2233128644
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.959061307
Short name T406
Test name
Test status
Simulation time 8373342905 ps
CPU time 8.27 seconds
Started May 05 03:17:43 PM PDT 24
Finished May 05 03:17:51 PM PDT 24
Peak memory 204112 kb
Host smart-dd30eb68-978c-49ed-add2-11e1d4359699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95906
1307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.959061307
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2803588517
Short name T1009
Test name
Test status
Simulation time 268992233 ps
CPU time 2.13 seconds
Started May 05 03:17:48 PM PDT 24
Finished May 05 03:17:50 PM PDT 24
Peak memory 204192 kb
Host smart-49d80e4a-1202-40ad-a07a-2090a646ca33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
88517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2803588517
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3382252231
Short name T1177
Test name
Test status
Simulation time 8405495717 ps
CPU time 8.5 seconds
Started May 05 03:17:49 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204140 kb
Host smart-c23ac076-7b8d-4cf7-a9df-37fa441504e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33822
52231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3382252231
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3053201695
Short name T181
Test name
Test status
Simulation time 8370487720 ps
CPU time 7.58 seconds
Started May 05 03:17:50 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204088 kb
Host smart-d9e5021c-cda1-48a8-b72e-2fe50107bdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
01695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3053201695
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4045977303
Short name T1235
Test name
Test status
Simulation time 8449306168 ps
CPU time 10.29 seconds
Started May 05 03:17:43 PM PDT 24
Finished May 05 03:17:54 PM PDT 24
Peak memory 204128 kb
Host smart-29809302-5ed5-4457-9471-7f003085398b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40459
77303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4045977303
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.646642637
Short name T913
Test name
Test status
Simulation time 8414318243 ps
CPU time 7.95 seconds
Started May 05 03:17:44 PM PDT 24
Finished May 05 03:17:52 PM PDT 24
Peak memory 204128 kb
Host smart-e84ed1f4-7955-45c0-ae3f-531ec64ac138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64664
2637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.646642637
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.601711545
Short name T42
Test name
Test status
Simulation time 8383123841 ps
CPU time 8.07 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:17:54 PM PDT 24
Peak memory 204096 kb
Host smart-f0c9ee51-353f-42c7-b513-9249d84d9e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60171
1545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.601711545
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1711511871
Short name T126
Test name
Test status
Simulation time 8449474909 ps
CPU time 8.18 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:17:53 PM PDT 24
Peak memory 204144 kb
Host smart-b798c3ef-9848-4417-85fa-f96748074576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17115
11871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1711511871
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.4102160051
Short name T411
Test name
Test status
Simulation time 8393364377 ps
CPU time 7.71 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:17:54 PM PDT 24
Peak memory 204084 kb
Host smart-6969f350-773f-431d-a9d8-2418624d6b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41021
60051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.4102160051
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2632327566
Short name T491
Test name
Test status
Simulation time 8382227661 ps
CPU time 8.13 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:17:54 PM PDT 24
Peak memory 204064 kb
Host smart-9ebfc93d-2367-44bc-aacf-8cc4ff8f5efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
27566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2632327566
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1412807549
Short name T1164
Test name
Test status
Simulation time 8405451893 ps
CPU time 7.9 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:17:54 PM PDT 24
Peak memory 204076 kb
Host smart-110343f9-baa8-4b48-909f-4778a7a6b453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
07549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1412807549
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3324486481
Short name T1349
Test name
Test status
Simulation time 8367467766 ps
CPU time 8.92 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:17:55 PM PDT 24
Peak memory 204144 kb
Host smart-e5000b95-f2eb-44a4-8224-05dbf6e69408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33244
86481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3324486481
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2064751119
Short name T578
Test name
Test status
Simulation time 47941043 ps
CPU time 0.67 seconds
Started May 05 03:17:47 PM PDT 24
Finished May 05 03:17:48 PM PDT 24
Peak memory 203924 kb
Host smart-e51445e0-bc0f-4716-b911-834e3e615efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
51119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2064751119
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3794090773
Short name T577
Test name
Test status
Simulation time 16409220110 ps
CPU time 32.1 seconds
Started May 05 03:17:45 PM PDT 24
Finished May 05 03:18:18 PM PDT 24
Peak memory 204368 kb
Host smart-0f88ce5a-cdb2-4a8a-8baa-d6b90d3e3be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
90773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3794090773
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4234806233
Short name T1368
Test name
Test status
Simulation time 8403411013 ps
CPU time 8.29 seconds
Started May 05 03:17:43 PM PDT 24
Finished May 05 03:17:52 PM PDT 24
Peak memory 204280 kb
Host smart-0b715405-7ca7-4b04-9767-4202b2843216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
06233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4234806233
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2378329812
Short name T1166
Test name
Test status
Simulation time 8433387631 ps
CPU time 8.44 seconds
Started May 05 03:17:43 PM PDT 24
Finished May 05 03:17:52 PM PDT 24
Peak memory 204112 kb
Host smart-8880baf1-f749-4989-8485-e51aa481abbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23783
29812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2378329812
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2398776424
Short name T1322
Test name
Test status
Simulation time 8370523226 ps
CPU time 7.51 seconds
Started May 05 03:17:42 PM PDT 24
Finished May 05 03:17:50 PM PDT 24
Peak memory 204128 kb
Host smart-34a40c2f-e4d5-4e28-a93f-d353bd1c5f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23987
76424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2398776424
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.78688947
Short name T1119
Test name
Test status
Simulation time 8412675564 ps
CPU time 10.03 seconds
Started May 05 03:17:46 PM PDT 24
Finished May 05 03:17:57 PM PDT 24
Peak memory 204088 kb
Host smart-850e690f-077c-427b-8a77-64d022b1f913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78688
947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.78688947
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.144011322
Short name T509
Test name
Test status
Simulation time 8374204515 ps
CPU time 7.61 seconds
Started May 05 03:17:43 PM PDT 24
Finished May 05 03:17:51 PM PDT 24
Peak memory 204084 kb
Host smart-8bf9ff9d-e3b9-4fe8-b345-1cd876d78f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401
1322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.144011322
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2882733728
Short name T146
Test name
Test status
Simulation time 8449451471 ps
CPU time 9.61 seconds
Started May 05 03:17:39 PM PDT 24
Finished May 05 03:17:50 PM PDT 24
Peak memory 204056 kb
Host smart-fc128521-4807-4d09-af35-17fb570e6fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28827
33728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2882733728
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1543658301
Short name T678
Test name
Test status
Simulation time 8390340058 ps
CPU time 7.73 seconds
Started May 05 03:17:47 PM PDT 24
Finished May 05 03:17:55 PM PDT 24
Peak memory 204112 kb
Host smart-6e11056e-fc77-4c77-864f-18afb94821d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
58301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1543658301
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2191811833
Short name T1344
Test name
Test status
Simulation time 8390997156 ps
CPU time 9.75 seconds
Started May 05 03:17:43 PM PDT 24
Finished May 05 03:17:53 PM PDT 24
Peak memory 204076 kb
Host smart-97ec7a59-4f69-41fa-8715-3dcaece56e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21918
11833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2191811833
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.780540795
Short name T450
Test name
Test status
Simulation time 8464974246 ps
CPU time 8 seconds
Started May 05 03:17:54 PM PDT 24
Finished May 05 03:18:02 PM PDT 24
Peak memory 204040 kb
Host smart-8dea1b93-00f4-4400-98ed-3b25abda3f13
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=780540795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.780540795
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.3968165220
Short name T412
Test name
Test status
Simulation time 8376313690 ps
CPU time 8.09 seconds
Started May 05 03:17:56 PM PDT 24
Finished May 05 03:18:04 PM PDT 24
Peak memory 204092 kb
Host smart-c7218b71-2ea9-4b6a-b36e-c4787db1e115
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3968165220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3968165220
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.1881133829
Short name T326
Test name
Test status
Simulation time 8390374501 ps
CPU time 8.03 seconds
Started May 05 03:17:56 PM PDT 24
Finished May 05 03:18:04 PM PDT 24
Peak memory 204052 kb
Host smart-a8ccc3d1-6901-4a41-b81d-03c9c2091945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
33829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.1881133829
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1381108868
Short name T370
Test name
Test status
Simulation time 8372696785 ps
CPU time 8.03 seconds
Started May 05 03:17:49 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204116 kb
Host smart-fcbc2e13-5621-43c8-8962-7a3bd14145fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13811
08868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1381108868
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.741252387
Short name T820
Test name
Test status
Simulation time 8390237479 ps
CPU time 9.64 seconds
Started May 05 03:17:47 PM PDT 24
Finished May 05 03:17:57 PM PDT 24
Peak memory 204124 kb
Host smart-015012d5-4af2-4185-af34-3274046064f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74125
2387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.741252387
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2761135686
Short name T1289
Test name
Test status
Simulation time 67112124 ps
CPU time 1.62 seconds
Started May 05 03:17:54 PM PDT 24
Finished May 05 03:17:56 PM PDT 24
Peak memory 204240 kb
Host smart-0520baa9-eeb9-4b41-b59f-ef5e75225f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611
35686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2761135686
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3165529909
Short name T522
Test name
Test status
Simulation time 8417994932 ps
CPU time 8.17 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:18:01 PM PDT 24
Peak memory 204044 kb
Host smart-675d39b4-f2fe-456c-a9d2-cdd2d6387193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31655
29909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3165529909
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.304733614
Short name T704
Test name
Test status
Simulation time 8379114672 ps
CPU time 7.68 seconds
Started May 05 03:17:56 PM PDT 24
Finished May 05 03:18:04 PM PDT 24
Peak memory 204088 kb
Host smart-2903884e-b8d6-454b-9605-dd0cc1d5f209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30473
3614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.304733614
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1552877649
Short name T486
Test name
Test status
Simulation time 8409488593 ps
CPU time 9.66 seconds
Started May 05 03:17:50 PM PDT 24
Finished May 05 03:18:01 PM PDT 24
Peak memory 204112 kb
Host smart-676850ea-95c6-4b4a-a417-4576329914df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15528
77649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1552877649
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3492042320
Short name T1149
Test name
Test status
Simulation time 8417512117 ps
CPU time 7.64 seconds
Started May 05 03:17:50 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204116 kb
Host smart-5b230cf4-8986-4796-b990-e3a6c8d740ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34920
42320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3492042320
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3166507740
Short name T599
Test name
Test status
Simulation time 8378625972 ps
CPU time 8.23 seconds
Started May 05 03:17:49 PM PDT 24
Finished May 05 03:17:58 PM PDT 24
Peak memory 204132 kb
Host smart-9e23480c-a43c-4d30-be38-6b9dca13a089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31665
07740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3166507740
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3320789782
Short name T1115
Test name
Test status
Simulation time 8438164145 ps
CPU time 8.31 seconds
Started May 05 03:17:48 PM PDT 24
Finished May 05 03:17:57 PM PDT 24
Peak memory 204068 kb
Host smart-014258c5-64bc-48bb-b590-662380103b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33207
89782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3320789782
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3178956493
Short name T329
Test name
Test status
Simulation time 8404037841 ps
CPU time 8.75 seconds
Started May 05 03:17:54 PM PDT 24
Finished May 05 03:18:03 PM PDT 24
Peak memory 204064 kb
Host smart-cf53a82d-1146-4988-a720-f071d8920986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31789
56493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3178956493
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2213759342
Short name T986
Test name
Test status
Simulation time 8397265294 ps
CPU time 7.63 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:18:00 PM PDT 24
Peak memory 204004 kb
Host smart-b516062d-519e-484d-b5ec-9663d880b565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22137
59342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2213759342
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3672918387
Short name T174
Test name
Test status
Simulation time 8386366225 ps
CPU time 9.69 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:18:02 PM PDT 24
Peak memory 204072 kb
Host smart-c5fe1e44-c9be-4ea5-a4c4-c197ea1f6b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
18387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3672918387
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3796370387
Short name T595
Test name
Test status
Simulation time 8404027851 ps
CPU time 8.01 seconds
Started May 05 03:17:55 PM PDT 24
Finished May 05 03:18:03 PM PDT 24
Peak memory 204164 kb
Host smart-15658559-1341-4f54-bd7e-1ff8539c7ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963
70387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3796370387
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.161196398
Short name T833
Test name
Test status
Simulation time 80524471 ps
CPU time 0.75 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:17:53 PM PDT 24
Peak memory 204000 kb
Host smart-60c14d84-37ef-4a8f-8ef3-b92a5bb57f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
6398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.161196398
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3425372264
Short name T1195
Test name
Test status
Simulation time 30253149975 ps
CPU time 67.11 seconds
Started May 05 03:17:51 PM PDT 24
Finished May 05 03:18:59 PM PDT 24
Peak memory 204380 kb
Host smart-fb8d5e0e-ea86-4839-8272-1e796ba38eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34253
72264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3425372264
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3193165337
Short name T939
Test name
Test status
Simulation time 8378726926 ps
CPU time 7.94 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:18:01 PM PDT 24
Peak memory 204100 kb
Host smart-30ee49ed-527b-48da-b710-86705fff7bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3193165337
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2757860545
Short name T1031
Test name
Test status
Simulation time 8509451715 ps
CPU time 8.38 seconds
Started May 05 03:17:53 PM PDT 24
Finished May 05 03:18:02 PM PDT 24
Peak memory 204136 kb
Host smart-c3aea713-977b-48e1-9afc-2547eca4f9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
60545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2757860545
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.778893781
Short name T777
Test name
Test status
Simulation time 8392684525 ps
CPU time 8.04 seconds
Started May 05 03:17:53 PM PDT 24
Finished May 05 03:18:01 PM PDT 24
Peak memory 204068 kb
Host smart-a24e1fba-251f-491e-a83f-adcae5ea142a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77889
3781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.778893781
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1596764618
Short name T1155
Test name
Test status
Simulation time 8376328492 ps
CPU time 8.48 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:18:01 PM PDT 24
Peak memory 204128 kb
Host smart-0d1536ca-24d8-4ef1-8ab8-99fe890f7cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
64618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1596764618
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1477642406
Short name T375
Test name
Test status
Simulation time 8371580139 ps
CPU time 9.26 seconds
Started May 05 03:17:53 PM PDT 24
Finished May 05 03:18:03 PM PDT 24
Peak memory 204096 kb
Host smart-4230127d-0e28-4b16-9a5a-b0c27e451bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14776
42406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1477642406
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.471620811
Short name T93
Test name
Test status
Simulation time 8457518071 ps
CPU time 8.21 seconds
Started May 05 03:17:47 PM PDT 24
Finished May 05 03:17:56 PM PDT 24
Peak memory 204096 kb
Host smart-44ef688f-5402-46d5-a811-d67974aa8e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47162
0811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.471620811
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1068580416
Short name T354
Test name
Test status
Simulation time 8379034261 ps
CPU time 8.92 seconds
Started May 05 03:17:53 PM PDT 24
Finished May 05 03:18:02 PM PDT 24
Peak memory 204056 kb
Host smart-06c8ddf7-0b75-40fd-b2bb-1fb44df194fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10685
80416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1068580416
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3953932232
Short name T17
Test name
Test status
Simulation time 8404813736 ps
CPU time 10.03 seconds
Started May 05 03:17:52 PM PDT 24
Finished May 05 03:18:03 PM PDT 24
Peak memory 204124 kb
Host smart-2fbcd7ad-b71a-4880-bda5-8241a2cad98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39539
32232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3953932232
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1085773511
Short name T1295
Test name
Test status
Simulation time 8489281861 ps
CPU time 7.63 seconds
Started May 05 03:12:32 PM PDT 24
Finished May 05 03:12:40 PM PDT 24
Peak memory 204084 kb
Host smart-7c9a21a8-a47f-4ddd-9534-4c9e5f1e22e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1085773511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1085773511
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.2110923197
Short name T981
Test name
Test status
Simulation time 8449350936 ps
CPU time 7.96 seconds
Started May 05 03:12:31 PM PDT 24
Finished May 05 03:12:39 PM PDT 24
Peak memory 204104 kb
Host smart-8e34469b-a977-4522-8ec4-896bd1db3989
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2110923197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.2110923197
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.775918824
Short name T1311
Test name
Test status
Simulation time 8457930670 ps
CPU time 7.44 seconds
Started May 05 03:12:30 PM PDT 24
Finished May 05 03:12:38 PM PDT 24
Peak memory 204100 kb
Host smart-b005c0fa-efac-4acf-b4a4-fea6d947de55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77591
8824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.775918824
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.596177305
Short name T601
Test name
Test status
Simulation time 8377909759 ps
CPU time 7.58 seconds
Started May 05 03:12:23 PM PDT 24
Finished May 05 03:12:31 PM PDT 24
Peak memory 204156 kb
Host smart-155584f2-ceda-476c-9d78-11870839a943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59617
7305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.596177305
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.2862360943
Short name T904
Test name
Test status
Simulation time 8393667188 ps
CPU time 7.58 seconds
Started May 05 03:12:22 PM PDT 24
Finished May 05 03:12:30 PM PDT 24
Peak memory 204048 kb
Host smart-e5d73390-b940-4537-967f-78da51354e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28623
60943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2862360943
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3907261554
Short name T607
Test name
Test status
Simulation time 132118113 ps
CPU time 1.56 seconds
Started May 05 03:12:24 PM PDT 24
Finished May 05 03:12:26 PM PDT 24
Peak memory 204136 kb
Host smart-6ae93f68-4d69-4b9e-bdfe-6f536a6aa7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
61554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3907261554
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.617863077
Short name T543
Test name
Test status
Simulation time 8387137195 ps
CPU time 8.04 seconds
Started May 05 03:12:29 PM PDT 24
Finished May 05 03:12:37 PM PDT 24
Peak memory 204080 kb
Host smart-138ecbec-50e3-487d-8af2-c5370c5d9abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61786
3077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.617863077
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2673889345
Short name T967
Test name
Test status
Simulation time 8364904439 ps
CPU time 8.07 seconds
Started May 05 03:12:27 PM PDT 24
Finished May 05 03:12:36 PM PDT 24
Peak memory 204280 kb
Host smart-1df074f6-cfd7-42be-a000-6f7f0965b032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26738
89345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2673889345
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3729611091
Short name T596
Test name
Test status
Simulation time 8421300481 ps
CPU time 8.02 seconds
Started May 05 03:12:24 PM PDT 24
Finished May 05 03:12:33 PM PDT 24
Peak memory 204100 kb
Host smart-5a678e97-67d7-4b6d-ad37-02fb9bcde374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37296
11091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3729611091
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3734043504
Short name T884
Test name
Test status
Simulation time 8413689147 ps
CPU time 7.92 seconds
Started May 05 03:12:22 PM PDT 24
Finished May 05 03:12:31 PM PDT 24
Peak memory 204088 kb
Host smart-2fb9644f-87a5-468d-af26-3a6141143e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340
43504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3734043504
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2994552894
Short name T1182
Test name
Test status
Simulation time 8370161394 ps
CPU time 7.65 seconds
Started May 05 03:12:23 PM PDT 24
Finished May 05 03:12:32 PM PDT 24
Peak memory 204060 kb
Host smart-bea3326a-4450-4a74-bcfa-8cb3def2a8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
52894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2994552894
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3533853177
Short name T119
Test name
Test status
Simulation time 8448730721 ps
CPU time 9.23 seconds
Started May 05 03:12:22 PM PDT 24
Finished May 05 03:12:32 PM PDT 24
Peak memory 204128 kb
Host smart-357483d9-3415-4c37-a174-480e6d8f6968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338
53177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3533853177
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3294935073
Short name T467
Test name
Test status
Simulation time 8394036759 ps
CPU time 7.33 seconds
Started May 05 03:12:23 PM PDT 24
Finished May 05 03:12:31 PM PDT 24
Peak memory 204076 kb
Host smart-de715574-5a38-4a72-ba1b-fe694527b1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32949
35073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3294935073
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.368017579
Short name T482
Test name
Test status
Simulation time 8402400696 ps
CPU time 8.53 seconds
Started May 05 03:12:21 PM PDT 24
Finished May 05 03:12:30 PM PDT 24
Peak memory 204084 kb
Host smart-16044685-23c0-4b5a-967e-081ea0a5de1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
7579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.368017579
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3865755426
Short name T196
Test name
Test status
Simulation time 8427296647 ps
CPU time 7.95 seconds
Started May 05 03:12:29 PM PDT 24
Finished May 05 03:12:38 PM PDT 24
Peak memory 204092 kb
Host smart-d2ef5d02-bf72-403b-a00a-afb25697c604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
55426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3865755426
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2307772323
Short name T1347
Test name
Test status
Simulation time 8368234114 ps
CPU time 8.67 seconds
Started May 05 03:12:27 PM PDT 24
Finished May 05 03:12:36 PM PDT 24
Peak memory 204100 kb
Host smart-47d455d7-baeb-4278-91e0-d2ce4adbf817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077
72323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2307772323
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2499446149
Short name T492
Test name
Test status
Simulation time 93012986 ps
CPU time 0.72 seconds
Started May 05 03:12:24 PM PDT 24
Finished May 05 03:12:26 PM PDT 24
Peak memory 204012 kb
Host smart-911d2362-3ff2-4de3-968b-dbcdf495f314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24994
46149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2499446149
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1094712782
Short name T221
Test name
Test status
Simulation time 17776819644 ps
CPU time 34.11 seconds
Started May 05 03:12:21 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 204384 kb
Host smart-1f1a1025-c901-4f7c-8553-6dd76c9018de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10947
12782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1094712782
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.4072417129
Short name T1272
Test name
Test status
Simulation time 8406104218 ps
CPU time 8.78 seconds
Started May 05 03:12:26 PM PDT 24
Finished May 05 03:12:36 PM PDT 24
Peak memory 204000 kb
Host smart-daec423b-e6d0-40e2-99b6-75541a08864f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40724
17129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.4072417129
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2877690966
Short name T681
Test name
Test status
Simulation time 8401193878 ps
CPU time 8.13 seconds
Started May 05 03:12:23 PM PDT 24
Finished May 05 03:12:32 PM PDT 24
Peak memory 204100 kb
Host smart-093f3ecf-6611-4d61-866d-8c9c4bc8ad8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
90966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2877690966
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1657231419
Short name T87
Test name
Test status
Simulation time 8400421759 ps
CPU time 7.64 seconds
Started May 05 03:12:25 PM PDT 24
Finished May 05 03:12:33 PM PDT 24
Peak memory 204056 kb
Host smart-036a1799-43b8-487c-8f28-d35398a1566e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572
31419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1657231419
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3196872768
Short name T1144
Test name
Test status
Simulation time 8379507432 ps
CPU time 7.78 seconds
Started May 05 03:12:26 PM PDT 24
Finished May 05 03:12:34 PM PDT 24
Peak memory 204064 kb
Host smart-691b24de-8557-4e79-9728-a08704fdd8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31968
72768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3196872768
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.394231321
Short name T83
Test name
Test status
Simulation time 8392171503 ps
CPU time 8.43 seconds
Started May 05 03:12:26 PM PDT 24
Finished May 05 03:12:35 PM PDT 24
Peak memory 204076 kb
Host smart-5996c10d-706b-4102-8ed7-b414af8f3547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39423
1321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.394231321
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2715288349
Short name T768
Test name
Test status
Simulation time 8432917031 ps
CPU time 8.05 seconds
Started May 05 03:12:24 PM PDT 24
Finished May 05 03:12:33 PM PDT 24
Peak memory 204016 kb
Host smart-356cdc50-e697-49be-bfba-9fbcb96af101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27152
88349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2715288349
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.175291029
Short name T515
Test name
Test status
Simulation time 8396866139 ps
CPU time 8.59 seconds
Started May 05 03:12:34 PM PDT 24
Finished May 05 03:12:44 PM PDT 24
Peak memory 204004 kb
Host smart-0e5b52de-d1f4-4024-ae33-e328d4d6da97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17529
1029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.175291029
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1727085594
Short name T1189
Test name
Test status
Simulation time 8399281623 ps
CPU time 8.09 seconds
Started May 05 03:12:24 PM PDT 24
Finished May 05 03:12:32 PM PDT 24
Peak memory 204024 kb
Host smart-857df45a-6dd3-4f6d-bcd9-f96087fda215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17270
85594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1727085594
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2569200128
Short name T1188
Test name
Test status
Simulation time 8471552347 ps
CPU time 8.97 seconds
Started May 05 03:12:49 PM PDT 24
Finished May 05 03:12:59 PM PDT 24
Peak memory 204016 kb
Host smart-864f7315-c95d-45f6-949b-fab9b0283e2f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2569200128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2569200128
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3258658500
Short name T452
Test name
Test status
Simulation time 8385346077 ps
CPU time 7.6 seconds
Started May 05 03:12:49 PM PDT 24
Finished May 05 03:12:57 PM PDT 24
Peak memory 204016 kb
Host smart-c845a444-25fd-4ee6-a8d7-ab734e200ccd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3258658500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3258658500
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.3138884430
Short name T1291
Test name
Test status
Simulation time 8449910767 ps
CPU time 10.04 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 204112 kb
Host smart-8752d1cd-fec6-42ff-8e28-d3b7bfbeec64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31388
84430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.3138884430
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2340299095
Short name T770
Test name
Test status
Simulation time 8372055746 ps
CPU time 8.06 seconds
Started May 05 03:12:33 PM PDT 24
Finished May 05 03:12:42 PM PDT 24
Peak memory 204120 kb
Host smart-5b9bd75a-51b4-4da8-ba55-63fd992f6224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23402
99095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2340299095
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.3676616821
Short name T548
Test name
Test status
Simulation time 8381744701 ps
CPU time 7.86 seconds
Started May 05 03:12:34 PM PDT 24
Finished May 05 03:12:42 PM PDT 24
Peak memory 204020 kb
Host smart-56e4e4b4-4dc1-4dd0-8ac1-26c1582cbcfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36766
16821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3676616821
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1665225627
Short name T416
Test name
Test status
Simulation time 175439665 ps
CPU time 1.96 seconds
Started May 05 03:12:39 PM PDT 24
Finished May 05 03:12:42 PM PDT 24
Peak memory 204144 kb
Host smart-5670dd8e-0c20-4de7-9069-d612d6a4baa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16652
25627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1665225627
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.104253256
Short name T571
Test name
Test status
Simulation time 8424770818 ps
CPU time 8.31 seconds
Started May 05 03:12:46 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 204104 kb
Host smart-b9851acb-1c18-466e-a3ca-96b3b3dcacb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10425
3256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.104253256
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1132030178
Short name T188
Test name
Test status
Simulation time 8369764248 ps
CPU time 7.21 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:52 PM PDT 24
Peak memory 204108 kb
Host smart-f7332264-412c-41de-9d34-9523e2f27de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
30178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1132030178
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.759915534
Short name T1364
Test name
Test status
Simulation time 8438118973 ps
CPU time 8.04 seconds
Started May 05 03:12:39 PM PDT 24
Finished May 05 03:12:48 PM PDT 24
Peak memory 204000 kb
Host smart-01a1e4d0-375b-4edc-b418-aa31a109e06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75991
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.759915534
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1022398867
Short name T32
Test name
Test status
Simulation time 8444058099 ps
CPU time 7.84 seconds
Started May 05 03:12:39 PM PDT 24
Finished May 05 03:12:48 PM PDT 24
Peak memory 204036 kb
Host smart-c305f894-c469-436f-8cf6-e3df7a7acf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10223
98867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1022398867
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3652802828
Short name T972
Test name
Test status
Simulation time 8367812411 ps
CPU time 10.1 seconds
Started May 05 03:12:35 PM PDT 24
Finished May 05 03:12:46 PM PDT 24
Peak memory 204120 kb
Host smart-cdc61f11-ffe0-454b-bea6-65ba1b6fd556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528
02828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3652802828
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3054452996
Short name T128
Test name
Test status
Simulation time 8447116118 ps
CPU time 7.63 seconds
Started May 05 03:12:36 PM PDT 24
Finished May 05 03:12:44 PM PDT 24
Peak memory 204164 kb
Host smart-732904c0-2520-4b45-9911-2e098edb9f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
52996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3054452996
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.998305096
Short name T633
Test name
Test status
Simulation time 8409546182 ps
CPU time 7.84 seconds
Started May 05 03:12:36 PM PDT 24
Finished May 05 03:12:44 PM PDT 24
Peak memory 204104 kb
Host smart-01cee6f3-2d35-457c-a730-a45abcc7559d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99830
5096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.998305096
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.99799172
Short name T313
Test name
Test status
Simulation time 8417360554 ps
CPU time 7.64 seconds
Started May 05 03:12:37 PM PDT 24
Finished May 05 03:12:45 PM PDT 24
Peak memory 204060 kb
Host smart-3091589f-4420-463d-884b-87ee54d5a946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99799
172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.99799172
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3884110253
Short name T580
Test name
Test status
Simulation time 8388778732 ps
CPU time 8.37 seconds
Started May 05 03:12:45 PM PDT 24
Finished May 05 03:12:54 PM PDT 24
Peak memory 204124 kb
Host smart-4b5fddfd-cfc3-4486-a9be-c0c9f9ea8848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
10253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3884110253
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3141088362
Short name T632
Test name
Test status
Simulation time 8381151136 ps
CPU time 8.71 seconds
Started May 05 03:12:43 PM PDT 24
Finished May 05 03:12:52 PM PDT 24
Peak memory 204112 kb
Host smart-f8dea843-0a57-49a6-9921-3fd7f5765865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31410
88362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3141088362
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.240685025
Short name T1264
Test name
Test status
Simulation time 45218600 ps
CPU time 0.75 seconds
Started May 05 03:12:46 PM PDT 24
Finished May 05 03:12:48 PM PDT 24
Peak memory 203960 kb
Host smart-71b7a7d2-6978-418f-bfb7-c82c7c4dc91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068
5025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.240685025
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.272883671
Short name T1028
Test name
Test status
Simulation time 16979762979 ps
CPU time 30.13 seconds
Started May 05 03:12:40 PM PDT 24
Finished May 05 03:13:10 PM PDT 24
Peak memory 204348 kb
Host smart-afd4154a-75d2-4ffa-93da-0f8611be6d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27288
3671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.272883671
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2453697617
Short name T656
Test name
Test status
Simulation time 8372155848 ps
CPU time 9.32 seconds
Started May 05 03:12:41 PM PDT 24
Finished May 05 03:12:51 PM PDT 24
Peak memory 204088 kb
Host smart-c64c8551-a319-45a0-baef-732ad214d61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24536
97617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2453697617
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1049904967
Short name T1318
Test name
Test status
Simulation time 8389633785 ps
CPU time 8.43 seconds
Started May 05 03:12:39 PM PDT 24
Finished May 05 03:12:48 PM PDT 24
Peak memory 204108 kb
Host smart-b3372e31-0345-4ae3-9a59-feeca27782a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10499
04967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1049904967
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3483361957
Short name T573
Test name
Test status
Simulation time 8412470972 ps
CPU time 9.6 seconds
Started May 05 03:12:38 PM PDT 24
Finished May 05 03:12:48 PM PDT 24
Peak memory 204092 kb
Host smart-d36d6889-9d6a-4452-99f1-3f365e63fc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833
61957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3483361957
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3832818270
Short name T176
Test name
Test status
Simulation time 8383338882 ps
CPU time 7.58 seconds
Started May 05 03:12:43 PM PDT 24
Finished May 05 03:12:51 PM PDT 24
Peak memory 204124 kb
Host smart-5a145f14-fd9e-4df3-ac67-d43c7d088fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38328
18270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3832818270
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.433187725
Short name T1362
Test name
Test status
Simulation time 8369721745 ps
CPU time 8.29 seconds
Started May 05 03:12:45 PM PDT 24
Finished May 05 03:12:54 PM PDT 24
Peak memory 204112 kb
Host smart-b934daad-0b1a-4387-97f4-dc722e2d46d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43318
7725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.433187725
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3748582482
Short name T1211
Test name
Test status
Simulation time 8430367412 ps
CPU time 8.49 seconds
Started May 05 03:12:35 PM PDT 24
Finished May 05 03:12:44 PM PDT 24
Peak memory 204132 kb
Host smart-b1fd1c94-d1d3-486b-aac0-9e153925a3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
82482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3748582482
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3080642779
Short name T707
Test name
Test status
Simulation time 8434353897 ps
CPU time 7.96 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:52 PM PDT 24
Peak memory 204124 kb
Host smart-036f21a1-084c-4672-b0fd-df7e346f9b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
42779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3080642779
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1065811273
Short name T890
Test name
Test status
Simulation time 8369324228 ps
CPU time 7.45 seconds
Started May 05 03:12:37 PM PDT 24
Finished May 05 03:12:45 PM PDT 24
Peak memory 204100 kb
Host smart-b84bb255-a78d-44f9-878e-55be7160023a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10658
11273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1065811273
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1013622973
Short name T1062
Test name
Test status
Simulation time 8466861885 ps
CPU time 9.25 seconds
Started May 05 03:12:53 PM PDT 24
Finished May 05 03:13:03 PM PDT 24
Peak memory 204092 kb
Host smart-0a8e84be-a9e6-4b2f-a59c-6c566c9aacbe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1013622973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1013622973
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2847207864
Short name T886
Test name
Test status
Simulation time 8384563819 ps
CPU time 7.87 seconds
Started May 05 03:12:54 PM PDT 24
Finished May 05 03:13:02 PM PDT 24
Peak memory 204140 kb
Host smart-ac348338-f0b8-4409-8e18-a4f799229d9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2847207864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2847207864
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3166494408
Short name T727
Test name
Test status
Simulation time 8458977735 ps
CPU time 9.27 seconds
Started May 05 03:12:52 PM PDT 24
Finished May 05 03:13:02 PM PDT 24
Peak memory 204124 kb
Host smart-e380136e-7216-4acd-ab3d-49e19e161024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
94408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3166494408
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2284322711
Short name T435
Test name
Test status
Simulation time 8373353048 ps
CPU time 7.84 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:53 PM PDT 24
Peak memory 204108 kb
Host smart-d6cc0ebc-ec58-4967-83bf-2bfec1218202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22843
22711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2284322711
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.1127516567
Short name T289
Test name
Test status
Simulation time 8390782917 ps
CPU time 7.88 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:52 PM PDT 24
Peak memory 204068 kb
Host smart-bbb6be6d-7197-4786-a825-3c190fba454f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11275
16567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1127516567
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.938002084
Short name T919
Test name
Test status
Simulation time 48866099 ps
CPU time 1.17 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:46 PM PDT 24
Peak memory 204180 kb
Host smart-f4fe689d-ef0b-45f6-9a7d-db4933b0d115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93800
2084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.938002084
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3542361477
Short name T881
Test name
Test status
Simulation time 8458094804 ps
CPU time 8.68 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:05 PM PDT 24
Peak memory 204088 kb
Host smart-9293a4c3-e8d1-4308-8f8b-0aa5cc31f66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35423
61477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3542361477
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1688557918
Short name T183
Test name
Test status
Simulation time 8428665899 ps
CPU time 8.08 seconds
Started May 05 03:12:52 PM PDT 24
Finished May 05 03:13:01 PM PDT 24
Peak memory 204076 kb
Host smart-c07abde1-09d4-4396-9694-50121e34d2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16885
57918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1688557918
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.733784771
Short name T1302
Test name
Test status
Simulation time 8428171532 ps
CPU time 8.45 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:53 PM PDT 24
Peak memory 204136 kb
Host smart-128c5b87-cec2-434c-8927-def9dace63b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73378
4771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.733784771
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3424002335
Short name T384
Test name
Test status
Simulation time 8472459964 ps
CPU time 8.81 seconds
Started May 05 03:12:48 PM PDT 24
Finished May 05 03:12:58 PM PDT 24
Peak memory 204084 kb
Host smart-cde085f7-c771-4c08-8675-3422094675a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34240
02335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3424002335
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2753425471
Short name T671
Test name
Test status
Simulation time 8379912129 ps
CPU time 8.16 seconds
Started May 05 03:12:48 PM PDT 24
Finished May 05 03:12:56 PM PDT 24
Peak memory 204136 kb
Host smart-e1ad0727-28c1-4c25-b88d-5f919b41be1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27534
25471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2753425471
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.439808387
Short name T1304
Test name
Test status
Simulation time 8427358383 ps
CPU time 7.89 seconds
Started May 05 03:12:47 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 204064 kb
Host smart-0daf4928-72bf-4d25-a063-f7f53ede987d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43980
8387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.439808387
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1644910939
Short name T1056
Test name
Test status
Simulation time 8387427428 ps
CPU time 7.86 seconds
Started May 05 03:12:48 PM PDT 24
Finished May 05 03:12:56 PM PDT 24
Peak memory 204128 kb
Host smart-52b6b305-d913-460b-99cb-948ee5b12dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
10939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1644910939
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1405205414
Short name T479
Test name
Test status
Simulation time 8394125431 ps
CPU time 8.06 seconds
Started May 05 03:12:47 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 204096 kb
Host smart-7caa00c4-8356-4fa5-8638-e27d24b16c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14052
05414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1405205414
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2913620363
Short name T1006
Test name
Test status
Simulation time 8405070049 ps
CPU time 8.57 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:06 PM PDT 24
Peak memory 204084 kb
Host smart-e08daaa8-07b4-41fe-b8c4-24a18e044deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136
20363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2913620363
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2588071403
Short name T25
Test name
Test status
Simulation time 8366898282 ps
CPU time 9.99 seconds
Started May 05 03:12:54 PM PDT 24
Finished May 05 03:13:04 PM PDT 24
Peak memory 204120 kb
Host smart-e3791d96-fa86-4dbd-8d55-ae4a777cce53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25880
71403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2588071403
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1604664175
Short name T858
Test name
Test status
Simulation time 39565177 ps
CPU time 0.67 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:12:58 PM PDT 24
Peak memory 203952 kb
Host smart-42d4350f-d5ef-40b6-9717-b543d7b96686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16046
64175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1604664175
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1455875638
Short name T250
Test name
Test status
Simulation time 31567384732 ps
CPU time 70.42 seconds
Started May 05 03:12:46 PM PDT 24
Finished May 05 03:13:57 PM PDT 24
Peak memory 204388 kb
Host smart-758461d8-358d-4a16-9fcc-d5f03bd84496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14558
75638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1455875638
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2059736983
Short name T348
Test name
Test status
Simulation time 8391518109 ps
CPU time 8.15 seconds
Started May 05 03:12:47 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 204068 kb
Host smart-f5ed52f5-9b75-4398-baad-2a73b260527a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597
36983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2059736983
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2182159114
Short name T837
Test name
Test status
Simulation time 8450315869 ps
CPU time 8.59 seconds
Started May 05 03:12:48 PM PDT 24
Finished May 05 03:12:57 PM PDT 24
Peak memory 204100 kb
Host smart-b92605bb-ef10-48b5-b799-a1b6bc023625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821
59114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2182159114
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1767850578
Short name T1114
Test name
Test status
Simulation time 8406628183 ps
CPU time 7.9 seconds
Started May 05 03:12:49 PM PDT 24
Finished May 05 03:12:57 PM PDT 24
Peak memory 204112 kb
Host smart-955e9fba-2d2b-4b4b-b1b0-ead7dd93006d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17678
50578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1767850578
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.542790857
Short name T562
Test name
Test status
Simulation time 8378109988 ps
CPU time 8.53 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:05 PM PDT 24
Peak memory 204088 kb
Host smart-65c7dd57-cfdc-491d-8b40-cf9e30682a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54279
0857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.542790857
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3129170389
Short name T1340
Test name
Test status
Simulation time 8378083710 ps
CPU time 7.67 seconds
Started May 05 03:12:52 PM PDT 24
Finished May 05 03:13:00 PM PDT 24
Peak memory 204056 kb
Host smart-b310ae6e-0f1f-42d4-aee5-0ba1cd6d5983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31291
70389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3129170389
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.879935235
Short name T954
Test name
Test status
Simulation time 8396766597 ps
CPU time 7.89 seconds
Started May 05 03:12:44 PM PDT 24
Finished May 05 03:12:52 PM PDT 24
Peak memory 204096 kb
Host smart-ac742b4d-f6d7-4bfa-9914-bad8191d08e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87993
5235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.879935235
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1345044624
Short name T984
Test name
Test status
Simulation time 8387672173 ps
CPU time 7.96 seconds
Started May 05 03:12:52 PM PDT 24
Finished May 05 03:13:01 PM PDT 24
Peak memory 204080 kb
Host smart-c152d145-3aa0-416e-9b5b-401c1955db25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13450
44624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1345044624
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1873423697
Short name T646
Test name
Test status
Simulation time 8389154116 ps
CPU time 7.67 seconds
Started May 05 03:12:46 PM PDT 24
Finished May 05 03:12:54 PM PDT 24
Peak memory 204052 kb
Host smart-89c5ef33-0526-4ca8-9d9d-3bcd01487b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18734
23697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1873423697
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.1161705314
Short name T476
Test name
Test status
Simulation time 8490044846 ps
CPU time 7.86 seconds
Started May 05 03:12:59 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204112 kb
Host smart-72bd386a-7aa6-4598-b11c-f19592f3c154
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1161705314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.1161705314
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.3875484800
Short name T417
Test name
Test status
Simulation time 8378845727 ps
CPU time 7.85 seconds
Started May 05 03:13:00 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204160 kb
Host smart-6b638149-38a0-493f-bf52-8c02c7113879
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3875484800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.3875484800
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.859601284
Short name T553
Test name
Test status
Simulation time 8450021976 ps
CPU time 8.37 seconds
Started May 05 03:13:01 PM PDT 24
Finished May 05 03:13:10 PM PDT 24
Peak memory 204096 kb
Host smart-c2ecfea1-8eac-4191-a7ac-33f4a397ed38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85960
1284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.859601284
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.837966460
Short name T322
Test name
Test status
Simulation time 8377691719 ps
CPU time 7.53 seconds
Started May 05 03:12:52 PM PDT 24
Finished May 05 03:13:00 PM PDT 24
Peak memory 204116 kb
Host smart-10c51fe7-6888-4a63-8fc7-452daac632b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83796
6460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.837966460
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.2064221693
Short name T545
Test name
Test status
Simulation time 8385181572 ps
CPU time 7.83 seconds
Started May 05 03:12:59 PM PDT 24
Finished May 05 03:13:07 PM PDT 24
Peak memory 203992 kb
Host smart-c5c12311-0459-4959-a6ba-4b960a7e5809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20642
21693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2064221693
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.636095799
Short name T1200
Test name
Test status
Simulation time 73377359 ps
CPU time 1.58 seconds
Started May 05 03:12:57 PM PDT 24
Finished May 05 03:13:00 PM PDT 24
Peak memory 204180 kb
Host smart-0c17957b-72b6-4240-864c-cd39bb398dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63609
5799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.636095799
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.149690679
Short name T477
Test name
Test status
Simulation time 8448845478 ps
CPU time 9.58 seconds
Started May 05 03:13:00 PM PDT 24
Finished May 05 03:13:10 PM PDT 24
Peak memory 204120 kb
Host smart-7d1ddfce-ff93-4921-9bc3-5fc740d7668e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
0679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.149690679
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1949921881
Short name T1019
Test name
Test status
Simulation time 8376228372 ps
CPU time 7.85 seconds
Started May 05 03:13:00 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204012 kb
Host smart-792dcce1-f6a6-4ceb-9344-7b60bd6f51ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19499
21881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1949921881
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1199001867
Short name T1030
Test name
Test status
Simulation time 8401759325 ps
CPU time 9.88 seconds
Started May 05 03:12:57 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204060 kb
Host smart-71caf270-f6a8-4f66-8c80-3a8acc82ea29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11990
01867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1199001867
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3905549799
Short name T650
Test name
Test status
Simulation time 8419353802 ps
CPU time 8.39 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:05 PM PDT 24
Peak memory 204148 kb
Host smart-cb7a63e0-1540-4440-b0fa-56970e2123cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39055
49799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3905549799
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1901518492
Short name T927
Test name
Test status
Simulation time 8370308015 ps
CPU time 7.78 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:04 PM PDT 24
Peak memory 204108 kb
Host smart-f585705d-5922-4512-b66f-5f36f1d92d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19015
18492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1901518492
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1361068314
Short name T104
Test name
Test status
Simulation time 8445507877 ps
CPU time 8 seconds
Started May 05 03:12:57 PM PDT 24
Finished May 05 03:13:06 PM PDT 24
Peak memory 204108 kb
Host smart-7cef2703-6ffa-4c73-965d-a31d1d57dc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610
68314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1361068314
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2070961483
Short name T806
Test name
Test status
Simulation time 8380135790 ps
CPU time 9.01 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:06 PM PDT 24
Peak memory 204128 kb
Host smart-a7c784bd-57cb-4b35-b37a-c213e82d2099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20709
61483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2070961483
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1150206445
Short name T367
Test name
Test status
Simulation time 8417744723 ps
CPU time 10.5 seconds
Started May 05 03:12:56 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204084 kb
Host smart-8f0b5d85-6b66-485a-9e47-4a786ee76ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11502
06445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1150206445
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2301601824
Short name T963
Test name
Test status
Simulation time 8393061063 ps
CPU time 8.03 seconds
Started May 05 03:13:02 PM PDT 24
Finished May 05 03:13:10 PM PDT 24
Peak memory 204080 kb
Host smart-d564fb76-e17f-456c-9ebe-497dfa972b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23016
01824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2301601824
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1769711038
Short name T397
Test name
Test status
Simulation time 8377233644 ps
CPU time 7.73 seconds
Started May 05 03:12:57 PM PDT 24
Finished May 05 03:13:06 PM PDT 24
Peak memory 204136 kb
Host smart-c1cbbb44-92e4-447a-a401-6e732633b41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17697
11038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1769711038
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.4169569407
Short name T1072
Test name
Test status
Simulation time 64581947 ps
CPU time 0.67 seconds
Started May 05 03:13:01 PM PDT 24
Finished May 05 03:13:02 PM PDT 24
Peak memory 203876 kb
Host smart-9639818b-e378-4bc3-b351-d9cb32e60573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41695
69407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.4169569407
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.59914804
Short name T268
Test name
Test status
Simulation time 25405646949 ps
CPU time 55.61 seconds
Started May 05 03:12:59 PM PDT 24
Finished May 05 03:13:55 PM PDT 24
Peak memory 204384 kb
Host smart-6028f0cf-6857-4910-8c20-d47d11e66745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59914
804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.59914804
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2812196870
Short name T1150
Test name
Test status
Simulation time 8386892815 ps
CPU time 8.79 seconds
Started May 05 03:12:55 PM PDT 24
Finished May 05 03:13:04 PM PDT 24
Peak memory 204064 kb
Host smart-624bd486-8009-4ae3-8b25-22b2d9895450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28121
96870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2812196870
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2221962578
Short name T1038
Test name
Test status
Simulation time 8466789194 ps
CPU time 9.87 seconds
Started May 05 03:12:57 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204080 kb
Host smart-1e7e478b-0c26-47ff-841c-15fe01f614e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22219
62578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2221962578
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2280822787
Short name T305
Test name
Test status
Simulation time 8402591739 ps
CPU time 8.18 seconds
Started May 05 03:12:58 PM PDT 24
Finished May 05 03:13:06 PM PDT 24
Peak memory 204088 kb
Host smart-426492f9-1d0e-435a-9c6d-07acf8e8d351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
22787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2280822787
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4005988633
Short name T680
Test name
Test status
Simulation time 8373826921 ps
CPU time 7.49 seconds
Started May 05 03:13:00 PM PDT 24
Finished May 05 03:13:09 PM PDT 24
Peak memory 204056 kb
Host smart-1c5eafb2-b1bb-431a-b97a-c058738614ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40059
88633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4005988633
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.73336929
Short name T394
Test name
Test status
Simulation time 8367374670 ps
CPU time 9.5 seconds
Started May 05 03:12:55 PM PDT 24
Finished May 05 03:13:05 PM PDT 24
Peak memory 204080 kb
Host smart-87bb6d10-ef4b-4d97-a79d-9c70e070a616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73336
929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.73336929
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.945711699
Short name T1120
Test name
Test status
Simulation time 8457250252 ps
CPU time 7.9 seconds
Started May 05 03:12:53 PM PDT 24
Finished May 05 03:13:01 PM PDT 24
Peak memory 204092 kb
Host smart-eec4e796-c271-4bec-8f15-570af992facb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94571
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.945711699
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3886089320
Short name T778
Test name
Test status
Simulation time 8395757464 ps
CPU time 8.27 seconds
Started May 05 03:12:59 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 204100 kb
Host smart-89d38d93-3961-4fe4-978b-36cad7b5db25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38860
89320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3886089320
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2184037375
Short name T1363
Test name
Test status
Simulation time 8397455383 ps
CPU time 9.88 seconds
Started May 05 03:12:59 PM PDT 24
Finished May 05 03:13:09 PM PDT 24
Peak memory 203996 kb
Host smart-7b70c3a5-b620-4326-bb8c-871aba31bf83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21840
37375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2184037375
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.1739633610
Short name T756
Test name
Test status
Simulation time 8462970505 ps
CPU time 7.93 seconds
Started May 05 03:13:14 PM PDT 24
Finished May 05 03:13:22 PM PDT 24
Peak memory 204084 kb
Host smart-1011db46-3820-43b0-ae3a-b8fc235e49d1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1739633610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.1739633610
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.2197693073
Short name T386
Test name
Test status
Simulation time 8388842330 ps
CPU time 9.32 seconds
Started May 05 03:13:14 PM PDT 24
Finished May 05 03:13:24 PM PDT 24
Peak memory 204104 kb
Host smart-dc8e19a7-cffc-4669-8fbe-7d4fd1f3dade
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2197693073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.2197693073
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.709509987
Short name T317
Test name
Test status
Simulation time 8440945496 ps
CPU time 8.92 seconds
Started May 05 03:13:13 PM PDT 24
Finished May 05 03:13:23 PM PDT 24
Peak memory 204040 kb
Host smart-888ebdf2-bdef-409a-b933-ce413d133402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70950
9987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.709509987
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2004298694
Short name T1216
Test name
Test status
Simulation time 8377807253 ps
CPU time 8.58 seconds
Started May 05 03:13:01 PM PDT 24
Finished May 05 03:13:10 PM PDT 24
Peak memory 204132 kb
Host smart-aa6551ab-448c-4c71-aa11-af6c63095a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20042
98694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2004298694
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.4269074387
Short name T1152
Test name
Test status
Simulation time 8372022280 ps
CPU time 7.47 seconds
Started May 05 03:13:06 PM PDT 24
Finished May 05 03:13:14 PM PDT 24
Peak memory 204060 kb
Host smart-ef818a26-8a27-4ec4-8384-8fa4c070b109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42690
74387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4269074387
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3845383529
Short name T1266
Test name
Test status
Simulation time 65612812 ps
CPU time 1.67 seconds
Started May 05 03:13:07 PM PDT 24
Finished May 05 03:13:09 PM PDT 24
Peak memory 204200 kb
Host smart-a935e105-eacb-4638-ab33-06709dfd9434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
83529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3845383529
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1785336804
Short name T1207
Test name
Test status
Simulation time 8449278805 ps
CPU time 10.64 seconds
Started May 05 03:13:10 PM PDT 24
Finished May 05 03:13:21 PM PDT 24
Peak memory 204112 kb
Host smart-3d245bc3-1f3e-4a9e-be65-d8d47c440d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
36804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1785336804
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3381937199
Short name T1010
Test name
Test status
Simulation time 8399421194 ps
CPU time 7.8 seconds
Started May 05 03:13:10 PM PDT 24
Finished May 05 03:13:18 PM PDT 24
Peak memory 204076 kb
Host smart-86889258-a826-41d5-9bf1-f0a7f8b6a069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
37199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3381937199
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.226571887
Short name T1091
Test name
Test status
Simulation time 8468507684 ps
CPU time 9.58 seconds
Started May 05 03:13:07 PM PDT 24
Finished May 05 03:13:17 PM PDT 24
Peak memory 204112 kb
Host smart-207f5c9a-dc8d-4622-8b08-d619429c093f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
1887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.226571887
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3568324781
Short name T1005
Test name
Test status
Simulation time 8418138086 ps
CPU time 7.92 seconds
Started May 05 03:13:06 PM PDT 24
Finished May 05 03:13:14 PM PDT 24
Peak memory 204136 kb
Host smart-12277409-5470-4266-be20-3e7a716f6783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35683
24781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3568324781
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1636502743
Short name T334
Test name
Test status
Simulation time 8370251661 ps
CPU time 7.76 seconds
Started May 05 03:13:06 PM PDT 24
Finished May 05 03:13:14 PM PDT 24
Peak memory 204100 kb
Host smart-c86a6e23-f7d4-4754-bead-dba899931117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
02743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1636502743
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1726140089
Short name T111
Test name
Test status
Simulation time 8433723272 ps
CPU time 9.56 seconds
Started May 05 03:13:05 PM PDT 24
Finished May 05 03:13:15 PM PDT 24
Peak memory 204164 kb
Host smart-b4786c6d-90ec-4657-9334-916f0fb3e0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17261
40089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1726140089
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3220743752
Short name T493
Test name
Test status
Simulation time 8423563848 ps
CPU time 9.56 seconds
Started May 05 03:13:04 PM PDT 24
Finished May 05 03:13:14 PM PDT 24
Peak memory 204108 kb
Host smart-1c780ec3-2c15-440d-8cf7-3f91ccb6d01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32207
43752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3220743752
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1931056219
Short name T825
Test name
Test status
Simulation time 8398121747 ps
CPU time 7.6 seconds
Started May 05 03:13:06 PM PDT 24
Finished May 05 03:13:14 PM PDT 24
Peak memory 204064 kb
Host smart-4b5af59f-658a-4f45-b001-e064ce7d2991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
56219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1931056219
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3462087500
Short name T199
Test name
Test status
Simulation time 8391172800 ps
CPU time 7.64 seconds
Started May 05 03:13:10 PM PDT 24
Finished May 05 03:13:18 PM PDT 24
Peak memory 204128 kb
Host smart-468ab8de-4eeb-40ad-be94-e35eaafb8bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620
87500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3462087500
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.685382382
Short name T794
Test name
Test status
Simulation time 8368249488 ps
CPU time 7.99 seconds
Started May 05 03:13:11 PM PDT 24
Finished May 05 03:13:19 PM PDT 24
Peak memory 204136 kb
Host smart-3f50f4d3-5932-4d00-b9db-85ca2722c765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68538
2382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.685382382
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2632198929
Short name T1220
Test name
Test status
Simulation time 174332494 ps
CPU time 0.8 seconds
Started May 05 03:13:11 PM PDT 24
Finished May 05 03:13:12 PM PDT 24
Peak memory 203960 kb
Host smart-f7940bfa-b063-4535-9d57-28a7cf9f0f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26321
98929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2632198929
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.786185079
Short name T1202
Test name
Test status
Simulation time 16934862207 ps
CPU time 29.91 seconds
Started May 05 03:13:06 PM PDT 24
Finished May 05 03:13:37 PM PDT 24
Peak memory 204304 kb
Host smart-b1cd2c3e-0e5c-48a7-a3b8-4163f055efb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78618
5079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.786185079
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2065874816
Short name T811
Test name
Test status
Simulation time 8379178302 ps
CPU time 7.85 seconds
Started May 05 03:13:04 PM PDT 24
Finished May 05 03:13:13 PM PDT 24
Peak memory 204100 kb
Host smart-9c3ff9b2-a4bc-4621-94e8-5628be02819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
74816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2065874816
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.600083727
Short name T38
Test name
Test status
Simulation time 8424372543 ps
CPU time 8.19 seconds
Started May 05 03:13:05 PM PDT 24
Finished May 05 03:13:13 PM PDT 24
Peak memory 204080 kb
Host smart-6f6cb439-2736-46f4-b0ad-48132c092e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60008
3727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.600083727
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.330939034
Short name T1157
Test name
Test status
Simulation time 8402295382 ps
CPU time 7.94 seconds
Started May 05 03:13:11 PM PDT 24
Finished May 05 03:13:20 PM PDT 24
Peak memory 204124 kb
Host smart-310e46ed-60bf-4126-9902-80514e5f90a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
9034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.330939034
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2179521988
Short name T973
Test name
Test status
Simulation time 8380222579 ps
CPU time 7.86 seconds
Started May 05 03:13:08 PM PDT 24
Finished May 05 03:13:17 PM PDT 24
Peak memory 204128 kb
Host smart-af3e49e9-faaf-40f0-b2c5-3bf7db82afe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21795
21988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2179521988
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.971779994
Short name T793
Test name
Test status
Simulation time 8380444001 ps
CPU time 10.6 seconds
Started May 05 03:13:11 PM PDT 24
Finished May 05 03:13:22 PM PDT 24
Peak memory 204092 kb
Host smart-780ebda4-fabc-4bf1-a4e7-bb9de073b78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97177
9994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.971779994
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.807987548
Short name T149
Test name
Test status
Simulation time 8409158185 ps
CPU time 8.18 seconds
Started May 05 03:13:02 PM PDT 24
Finished May 05 03:13:11 PM PDT 24
Peak memory 204068 kb
Host smart-7d332e44-095b-4139-bf7b-e88ff134028c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80798
7548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.807987548
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.835793457
Short name T500
Test name
Test status
Simulation time 8408213063 ps
CPU time 7.59 seconds
Started May 05 03:13:08 PM PDT 24
Finished May 05 03:13:16 PM PDT 24
Peak memory 204060 kb
Host smart-0ab2a11a-1c99-467a-91b2-660238545ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83579
3457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.835793457
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1879765614
Short name T532
Test name
Test status
Simulation time 8428179601 ps
CPU time 9.21 seconds
Started May 05 03:13:09 PM PDT 24
Finished May 05 03:13:19 PM PDT 24
Peak memory 204000 kb
Host smart-d4c16d0c-1eeb-44a5-a71a-6277108f699f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
65614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1879765614
Directory /workspace/9.usbdev_stall_trans/latest
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