Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115707	1		T3	3		T4	2		T5	2
all_values[1]	115707	1		T3	3		T4	2		T5	2
all_values[2]	115707	1		T3	3		T4	2		T5	2
all_values[3]	115707	1		T3	3		T4	2		T5	2
all_values[4]	115707	1		T3	3		T4	2		T5	2
all_values[5]	115707	1		T3	3		T4	2		T5	2
all_values[6]	115707	1		T3	3		T4	2		T5	2
all_values[7]	115707	1		T3	3		T4	2		T5	2
all_values[8]	115707	1		T3	3		T4	2		T5	2
all_values[9]	115707	1		T3	3		T4	2		T5	2
all_values[10]	115707	1		T3	3		T4	2		T5	2
all_values[11]	115707	1		T3	3		T4	2		T5	2
all_values[12]	115707	1		T3	3		T4	2		T5	2
all_values[13]	115707	1		T3	3		T4	2		T5	2
all_values[14]	115707	1		T3	3		T4	2		T5	2
all_values[15]	115707	1		T3	3		T4	2		T5	2
all_values[16]	115707	1		T3	3		T4	2		T5	2
all_values[17]	115707	1		T3	3		T4	2		T5	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2078788	1		T3	54		T4	36		T5	36
auto[1]	3938	1		T10	3		T21	3		T22	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2077830	1		T3	54		T4	36		T5	36
auto[1]	4896	1		T72	118		T73	63		T74	73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114711	1		T3	3		T4	2		T5	2
all_values[0]	auto[0]	auto[1]	112	1		T72	7		T73	1		T75	2
all_values[0]	auto[1]	auto[0]	737	1		T10	3		T21	3		T22	3
all_values[0]	auto[1]	auto[1]	147	1		T72	1		T73	3		T74	4
all_values[1]	auto[0]	auto[0]	115104	1		T3	3		T4	2		T5	2
all_values[1]	auto[0]	auto[1]	134	1		T72	6		T74	3		T75	7
all_values[1]	auto[1]	auto[0]	328	1		T43	3		T53	3		T54	3
all_values[1]	auto[1]	auto[1]	141	1		T72	2		T74	2		T75	1
all_values[2]	auto[0]	auto[0]	115419	1		T3	3		T4	2		T5	2
all_values[2]	auto[0]	auto[1]	123	1		T72	3		T73	5		T74	2
all_values[2]	auto[1]	auto[0]	29	1		T75	2		T77	2		T271	1
all_values[2]	auto[1]	auto[1]	136	1		T72	5		T74	3		T75	2
all_values[3]	auto[0]	auto[0]	115413	1		T3	3		T4	2		T5	2
all_values[3]	auto[0]	auto[1]	147	1		T72	5		T73	4		T74	1
all_values[3]	auto[1]	auto[0]	20	1		T75	1		T76	1		T272	1
all_values[3]	auto[1]	auto[1]	127	1		T72	3		T73	1		T74	4
all_values[4]	auto[0]	auto[0]	115405	1		T3	3		T4	2		T5	2
all_values[4]	auto[0]	auto[1]	137	1		T72	4		T73	3		T75	3
all_values[4]	auto[1]	auto[0]	25	1		T72	2		T74	4		T76	1
all_values[4]	auto[1]	auto[1]	140	1		T72	1		T75	5		T76	3
all_values[5]	auto[0]	auto[0]	115401	1		T3	3		T4	2		T5	2
all_values[5]	auto[0]	auto[1]	142	1		T72	4		T73	3		T74	4
all_values[5]	auto[1]	auto[0]	22	1		T75	1		T273	1		T274	1
all_values[5]	auto[1]	auto[1]	142	1		T72	2		T73	2		T75	5
all_values[6]	auto[0]	auto[0]	115415	1		T3	3		T4	2		T5	2
all_values[6]	auto[0]	auto[1]	119	1		T72	2		T73	5		T75	3
all_values[6]	auto[1]	auto[0]	40	1		T74	1		T273	1		T271	1
all_values[6]	auto[1]	auto[1]	133	1		T72	6		T74	4		T75	5
all_values[7]	auto[0]	auto[0]	115417	1		T3	3		T4	2		T5	2
all_values[7]	auto[0]	auto[1]	148	1		T72	1		T74	5		T75	4
all_values[7]	auto[1]	auto[0]	32	1		T72	2		T73	2		T77	3
all_values[7]	auto[1]	auto[1]	110	1		T72	4		T73	3		T75	2
all_values[8]	auto[0]	auto[0]	115414	1		T3	3		T4	2		T5	2
all_values[8]	auto[0]	auto[1]	143	1		T72	5		T73	4		T75	3
all_values[8]	auto[1]	auto[0]	24	1		T272	2		T275	1		T276	1
all_values[8]	auto[1]	auto[1]	126	1		T72	2		T73	1		T74	5
all_values[9]	auto[0]	auto[0]	115409	1		T3	3		T4	2		T5	2
all_values[9]	auto[0]	auto[1]	150	1		T72	3		T73	3		T74	4
all_values[9]	auto[1]	auto[0]	15	1		T72	1		T75	1		T277	1
all_values[9]	auto[1]	auto[1]	133	1		T72	3		T74	1		T75	3
all_values[10]	auto[0]	auto[0]	115407	1		T3	3		T4	2		T5	2
all_values[10]	auto[0]	auto[1]	131	1		T72	1		T73	4		T75	1
all_values[10]	auto[1]	auto[0]	26	1		T72	3		T74	4		T77	1
all_values[10]	auto[1]	auto[1]	143	1		T72	4		T73	1		T75	7
all_values[11]	auto[0]	auto[0]	115397	1		T3	3		T4	2		T5	2
all_values[11]	auto[0]	auto[1]	151	1		T72	2		T75	5		T76	2
all_values[11]	auto[1]	auto[0]	20	1		T73	1		T74	1		T272	1
all_values[11]	auto[1]	auto[1]	139	1		T72	6		T73	3		T74	4
all_values[12]	auto[0]	auto[0]	115405	1		T3	3		T4	2		T5	2
all_values[12]	auto[0]	auto[1]	122	1		T72	5		T74	5		T75	1
all_values[12]	auto[1]	auto[0]	26	1		T73	1		T75	1		T76	2
all_values[12]	auto[1]	auto[1]	154	1		T72	3		T75	4		T76	5
all_values[13]	auto[0]	auto[0]	115410	1		T3	3		T4	2		T5	2
all_values[13]	auto[0]	auto[1]	137	1		T72	4		T74	3		T75	2
all_values[13]	auto[1]	auto[0]	26	1		T72	2		T76	1		T278	1
all_values[13]	auto[1]	auto[1]	134	1		T72	2		T73	5		T74	2
all_values[14]	auto[0]	auto[0]	115412	1		T3	3		T4	2		T5	2
all_values[14]	auto[0]	auto[1]	127	1		T72	7		T75	3		T76	5
all_values[14]	auto[1]	auto[0]	27	1		T72	1		T73	1		T74	1
all_values[14]	auto[1]	auto[1]	141	1		T74	4		T75	5		T76	3
all_values[15]	auto[0]	auto[0]	115410	1		T3	3		T4	2		T5	2
all_values[15]	auto[0]	auto[1]	134	1		T72	2		T75	5		T76	1
all_values[15]	auto[1]	auto[0]	25	1		T72	1		T75	2		T76	2
all_values[15]	auto[1]	auto[1]	138	1		T72	3		T73	3		T74	3
all_values[16]	auto[0]	auto[0]	115408	1		T3	3		T4	2		T5	2
all_values[16]	auto[0]	auto[1]	140	1		T72	3		T73	1		T75	5
all_values[16]	auto[1]	auto[0]	24	1		T72	3		T272	1		T279	1
all_values[16]	auto[1]	auto[1]	135	1		T73	3		T74	5		T75	2
all_values[17]	auto[0]	auto[0]	115402	1		T3	3		T4	2		T5	2
all_values[17]	auto[0]	auto[1]	132	1		T72	6		T73	3		T74	4
all_values[17]	auto[1]	auto[0]	25	1		T75	1		T280	1		T281	2
all_values[17]	auto[1]	auto[1]	148	1		T72	1		T73	2		T74	1