Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115707	1		T3	3		T4	2		T5	2
all_pins[1]	115707	1		T3	3		T4	2		T5	2
all_pins[2]	115707	1		T3	3		T4	2		T5	2
all_pins[3]	115707	1		T3	3		T4	2		T5	2
all_pins[4]	115707	1		T3	3		T4	2		T5	2
all_pins[5]	115707	1		T3	3		T4	2		T5	2
all_pins[6]	115707	1		T3	3		T4	2		T5	2
all_pins[7]	115707	1		T3	3		T4	2		T5	2
all_pins[8]	115707	1		T3	3		T4	2		T5	2
all_pins[9]	115707	1		T3	3		T4	2		T5	2
all_pins[10]	115707	1		T3	3		T4	2		T5	2
all_pins[11]	115707	1		T3	3		T4	2		T5	2
all_pins[12]	115707	1		T3	3		T4	2		T5	2
all_pins[13]	115707	1		T3	3		T4	2		T5	2
all_pins[14]	115707	1		T3	3		T4	2		T5	2
all_pins[15]	115707	1		T3	3		T4	2		T5	2
all_pins[16]	115707	1		T3	3		T4	2		T5	2
all_pins[17]	115707	1		T3	3		T4	2		T5	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2081394	1		T3	54		T4	36		T5	36
values[0x1]	1332	1		T43	1		T53	1		T54	1
transitions[0x0=>0x1]	1054	1		T43	1		T53	1		T54	1
transitions[0x1=>0x0]	1067	1		T43	1		T53	1		T54	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115557	1		T3	3		T4	2		T5	2
all_pins[0]	values[0x1]	150	1		T55	1		T56	1		T57	1
all_pins[0]	transitions[0x0=>0x1]	139	1		T55	1		T56	1		T57	1
all_pins[0]	transitions[0x1=>0x0]	148	1		T43	1		T53	1		T54	1
all_pins[1]	values[0x0]	115548	1		T3	3		T4	2		T5	2
all_pins[1]	values[0x1]	159	1		T43	1		T53	1		T54	1
all_pins[1]	transitions[0x0=>0x1]	140	1		T43	1		T53	1		T54	1
all_pins[1]	transitions[0x1=>0x0]	53	1		T72	3		T75	1		T77	2
all_pins[2]	values[0x0]	115635	1		T3	3		T4	2		T5	2
all_pins[2]	values[0x1]	72	1		T72	4		T75	2		T77	2
all_pins[2]	transitions[0x0=>0x1]	61	1		T72	3		T75	2		T77	2
all_pins[2]	transitions[0x1=>0x0]	45	1		T72	2		T74	1		T75	1
all_pins[3]	values[0x0]	115651	1		T3	3		T4	2		T5	2
all_pins[3]	values[0x1]	56	1		T72	3		T74	1		T75	1
all_pins[3]	transitions[0x0=>0x1]	42	1		T72	2		T74	1		T75	1
all_pins[3]	transitions[0x1=>0x0]	59	1		T75	2		T76	1		T77	4
all_pins[4]	values[0x0]	115634	1		T3	3		T4	2		T5	2
all_pins[4]	values[0x1]	73	1		T72	1		T75	2		T76	2
all_pins[4]	transitions[0x0=>0x1]	56	1		T72	1		T75	1		T77	3
all_pins[4]	transitions[0x1=>0x0]	46	1		T72	1		T75	1		T76	2
all_pins[5]	values[0x0]	115644	1		T3	3		T4	2		T5	2
all_pins[5]	values[0x1]	63	1		T72	1		T75	2		T76	4
all_pins[5]	transitions[0x0=>0x1]	53	1		T72	1		T76	4		T77	1
all_pins[5]	transitions[0x1=>0x0]	55	1		T72	5		T74	1		T75	2
all_pins[6]	values[0x0]	115642	1		T3	3		T4	2		T5	2
all_pins[6]	values[0x1]	65	1		T72	5		T74	1		T75	4
all_pins[6]	transitions[0x0=>0x1]	48	1		T72	4		T74	1		T75	3
all_pins[6]	transitions[0x1=>0x0]	39	1		T72	1		T73	1		T75	1
all_pins[7]	values[0x0]	115651	1		T3	3		T4	2		T5	2
all_pins[7]	values[0x1]	56	1		T72	2		T73	1		T75	2
all_pins[7]	transitions[0x0=>0x1]	42	1		T72	2		T73	1		T75	2
all_pins[7]	transitions[0x1=>0x0]	37	1		T72	1		T73	1		T74	1
all_pins[8]	values[0x0]	115656	1		T3	3		T4	2		T5	2
all_pins[8]	values[0x1]	51	1		T72	1		T73	1		T74	1
all_pins[8]	transitions[0x0=>0x1]	38	1		T72	1		T73	1		T74	1
all_pins[8]	transitions[0x1=>0x0]	49	1		T74	1		T77	1		T273	1
all_pins[9]	values[0x0]	115645	1		T3	3		T4	2		T5	2
all_pins[9]	values[0x1]	62	1		T74	1		T76	1		T77	2
all_pins[9]	transitions[0x0=>0x1]	47	1		T74	1		T77	2		T273	1
all_pins[9]	transitions[0x1=>0x0]	54	1		T72	3		T73	1		T75	3
all_pins[10]	values[0x0]	115638	1		T3	3		T4	2		T5	2
all_pins[10]	values[0x1]	69	1		T72	3		T73	1		T75	3
all_pins[10]	transitions[0x0=>0x1]	53	1		T72	3		T73	1		T75	3
all_pins[10]	transitions[0x1=>0x0]	40	1		T72	2		T73	2		T74	3
all_pins[11]	values[0x0]	115651	1		T3	3		T4	2		T5	2
all_pins[11]	values[0x1]	56	1		T72	2		T73	2		T74	3
all_pins[11]	transitions[0x0=>0x1]	38	1		T72	1		T73	2		T74	3
all_pins[11]	transitions[0x1=>0x0]	58	1		T72	1		T76	1		T273	1
all_pins[12]	values[0x0]	115631	1		T3	3		T4	2		T5	2
all_pins[12]	values[0x1]	76	1		T72	2		T76	1		T273	1
all_pins[12]	transitions[0x0=>0x1]	57	1		T72	2		T76	1		T273	1
all_pins[12]	transitions[0x1=>0x0]	43	1		T72	1		T73	3		T74	1
all_pins[13]	values[0x0]	115645	1		T3	3		T4	2		T5	2
all_pins[13]	values[0x1]	62	1		T72	1		T73	3		T74	1
all_pins[13]	transitions[0x0=>0x1]	43	1		T72	1		T73	3		T74	1
all_pins[13]	transitions[0x1=>0x0]	49	1		T76	2		T273	3		T271	1
all_pins[14]	values[0x0]	115639	1		T3	3		T4	2		T5	2
all_pins[14]	values[0x1]	68	1		T75	1		T76	2		T77	2
all_pins[14]	transitions[0x0=>0x1]	53	1		T75	1		T76	2		T77	2
all_pins[14]	transitions[0x1=>0x0]	46	1		T72	2		T73	2		T74	2
all_pins[15]	values[0x0]	115646	1		T3	3		T4	2		T5	2
all_pins[15]	values[0x1]	61	1		T72	2		T73	2		T74	2
all_pins[15]	transitions[0x0=>0x1]	47	1		T72	2		T76	1		T278	2
all_pins[15]	transitions[0x1=>0x0]	63	1		T74	2		T75	2		T76	4
all_pins[16]	values[0x0]	115630	1		T3	3		T4	2		T5	2
all_pins[16]	values[0x1]	77	1		T73	2		T74	4		T75	2
all_pins[16]	transitions[0x0=>0x1]	62	1		T73	2		T74	3		T75	1
all_pins[16]	transitions[0x1=>0x0]	41	1		T73	2		T76	1		T273	1
all_pins[17]	values[0x0]	115651	1		T3	3		T4	2		T5	2
all_pins[17]	values[0x1]	56	1		T73	2		T74	1		T75	1
all_pins[17]	transitions[0x0=>0x1]	35	1		T73	1		T75	1		T271	2
all_pins[17]	transitions[0x1=>0x0]	142	1		T55	1		T56	1		T57	1