Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T72	7		T73	4		T74	4
all_values[1]	275	1		T72	7		T73	4		T74	4
all_values[2]	275	1		T72	7		T73	4		T74	4
all_values[3]	275	1		T72	7		T73	4		T74	4
all_values[4]	275	1		T72	7		T73	4		T74	4
all_values[5]	275	1		T72	7		T73	4		T74	4
all_values[6]	275	1		T72	7		T73	4		T74	4
all_values[7]	275	1		T72	7		T73	4		T74	4
all_values[8]	275	1		T72	7		T73	4		T74	4
all_values[9]	275	1		T72	7		T73	4		T74	4
all_values[10]	275	1		T72	7		T73	4		T74	4
all_values[11]	275	1		T72	7		T73	4		T74	4
all_values[12]	275	1		T72	7		T73	4		T74	4
all_values[13]	275	1		T72	7		T73	4		T74	4
all_values[14]	275	1		T72	7		T73	4		T74	4
all_values[15]	275	1		T72	7		T73	4		T74	4
all_values[16]	275	1		T72	7		T73	4		T74	4
all_values[17]	275	1		T72	7		T73	4		T74	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2673	1		T72	79		T73	55		T74	30
auto[1]	2277	1		T72	47		T73	17		T74	42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	892	1		T72	26		T73	24		T74	15
auto[1]	4058	1		T72	100		T73	48		T74	57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2881	1		T72	74		T73	45		T74	45
auto[1]	2069	1		T72	52		T73	27		T74	27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1		T73	1		T74	1		T273	3
all_values[0]	auto[0]	auto[0]	auto[1]	44	1		T72	2		T73	1		T76	2
all_values[0]	auto[0]	auto[1]	auto[0]	20	1		T273	1		T274	1		T280	2
all_values[0]	auto[0]	auto[1]	auto[1]	66	1		T73	1		T74	2		T75	5
all_values[0]	auto[1]	auto[0]	auto[1]	53	1		T72	5		T73	1		T74	1
all_values[0]	auto[1]	auto[1]	auto[1]	53	1		T75	1		T76	4		T271	1
all_values[1]	auto[0]	auto[0]	auto[0]	26	1		T73	3		T76	1		T271	1
all_values[1]	auto[0]	auto[0]	auto[1]	56	1		T72	3		T74	1		T75	3
all_values[1]	auto[0]	auto[1]	auto[0]	21	1		T73	1		T76	2		T77	1
all_values[1]	auto[0]	auto[1]	auto[1]	55	1		T75	1		T77	2		T273	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T72	3		T74	1		T75	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T72	1		T74	2		T75	1
all_values[2]	auto[0]	auto[0]	auto[0]	35	1		T76	1		T273	1		T278	1
all_values[2]	auto[0]	auto[0]	auto[1]	45	1		T72	2		T73	1		T75	2
all_values[2]	auto[0]	auto[1]	auto[0]	26	1		T75	2		T77	2		T280	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1		T72	2		T74	2		T76	2
all_values[2]	auto[1]	auto[0]	auto[1]	64	1		T72	2		T73	3		T74	2
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T72	1		T75	2		T77	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T75	2		T76	1		T272	1
all_values[3]	auto[0]	auto[0]	auto[1]	63	1		T72	1		T73	1		T76	1
all_values[3]	auto[0]	auto[1]	auto[0]	13	1		T75	2		T272	1		T282	1
all_values[3]	auto[0]	auto[1]	auto[1]	56	1		T72	1		T74	3		T75	2
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T72	2		T73	3		T75	1
all_values[3]	auto[1]	auto[1]	auto[1]	46	1		T72	3		T74	1		T76	3
all_values[4]	auto[0]	auto[0]	auto[0]	29	1		T72	3		T73	2		T76	1
all_values[4]	auto[0]	auto[0]	auto[1]	54	1		T72	3		T73	1		T75	1
all_values[4]	auto[0]	auto[1]	auto[0]	16	1		T74	4		T273	3		T278	1
all_values[4]	auto[0]	auto[1]	auto[1]	52	1		T75	2		T76	1		T77	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1		T73	1		T75	2		T76	1
all_values[4]	auto[1]	auto[1]	auto[1]	59	1		T72	1		T75	2		T76	3
all_values[5]	auto[0]	auto[0]	auto[0]	24	1		T72	2		T74	1		T278	1
all_values[5]	auto[0]	auto[0]	auto[1]	61	1		T72	1		T73	1		T74	2
all_values[5]	auto[0]	auto[1]	auto[0]	16	1		T75	1		T273	1		T279	2
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T72	1		T73	2		T75	1
all_values[5]	auto[1]	auto[0]	auto[1]	65	1		T72	2		T73	1		T74	1
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T72	1		T75	3		T76	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1		T77	2		T271	1		T274	1
all_values[6]	auto[0]	auto[0]	auto[1]	53	1		T72	1		T73	2		T75	1
all_values[6]	auto[0]	auto[1]	auto[0]	32	1		T74	1		T273	1		T283	2
all_values[6]	auto[0]	auto[1]	auto[1]	46	1		T72	2		T74	2		T278	2
all_values[6]	auto[1]	auto[0]	auto[1]	47	1		T72	1		T73	2		T76	2
all_values[6]	auto[1]	auto[1]	auto[1]	62	1		T72	3		T74	1		T75	6
all_values[7]	auto[0]	auto[0]	auto[0]	38	1		T72	3		T73	1		T75	2
all_values[7]	auto[0]	auto[0]	auto[1]	62	1		T74	2		T75	1		T76	4
all_values[7]	auto[0]	auto[1]	auto[0]	23	1		T73	1		T77	2		T273	4
all_values[7]	auto[0]	auto[1]	auto[1]	34	1		T72	1		T73	1		T75	1
all_values[7]	auto[1]	auto[0]	auto[1]	68	1		T72	1		T74	2		T75	1
all_values[7]	auto[1]	auto[1]	auto[1]	50	1		T72	2		T73	1		T75	2
all_values[8]	auto[0]	auto[0]	auto[0]	35	1		T72	1		T273	2		T272	1
all_values[8]	auto[0]	auto[0]	auto[1]	53	1		T72	3		T73	1		T75	2
all_values[8]	auto[0]	auto[1]	auto[0]	17	1		T272	2		T275	1		T276	1
all_values[8]	auto[0]	auto[1]	auto[1]	54	1		T74	3		T75	2		T76	3
all_values[8]	auto[1]	auto[0]	auto[1]	79	1		T72	2		T73	3		T75	1
all_values[8]	auto[1]	auto[1]	auto[1]	37	1		T72	1		T74	1		T75	2
all_values[9]	auto[0]	auto[0]	auto[0]	31	1		T72	1		T73	2		T272	3
all_values[9]	auto[0]	auto[0]	auto[1]	63	1		T72	2		T73	1		T74	1
all_values[9]	auto[0]	auto[1]	auto[0]	10	1		T72	1		T75	1		T284	1
all_values[9]	auto[0]	auto[1]	auto[1]	57	1		T72	2		T75	1		T76	1
all_values[9]	auto[1]	auto[0]	auto[1]	58	1		T73	1		T74	3		T75	2
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T72	1		T75	1		T77	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1		T72	1		T74	2		T77	2
all_values[10]	auto[0]	auto[0]	auto[1]	51	1		T73	1		T76	1		T273	1
all_values[10]	auto[0]	auto[1]	auto[0]	15	1		T72	2		T74	2		T271	1
all_values[10]	auto[0]	auto[1]	auto[1]	59	1		T72	1		T75	3		T76	2
all_values[10]	auto[1]	auto[0]	auto[1]	67	1		T72	1		T73	3		T75	2
all_values[10]	auto[1]	auto[1]	auto[1]	50	1		T72	2		T75	2		T76	3
all_values[11]	auto[0]	auto[0]	auto[0]	22	1		T73	2		T76	1		T278	1
all_values[11]	auto[0]	auto[0]	auto[1]	68	1		T75	2		T76	1		T77	1
all_values[11]	auto[0]	auto[1]	auto[0]	13	1		T74	1		T285	2		T286	2
all_values[11]	auto[0]	auto[1]	auto[1]	50	1		T72	4		T73	1		T74	1
all_values[11]	auto[1]	auto[0]	auto[1]	74	1		T72	2		T73	1		T75	2
all_values[11]	auto[1]	auto[1]	auto[1]	48	1		T72	1		T74	2		T75	1
all_values[12]	auto[0]	auto[0]	auto[0]	25	1		T73	2		T75	3		T76	1
all_values[12]	auto[0]	auto[0]	auto[1]	44	1		T72	2		T74	1		T75	1
all_values[12]	auto[0]	auto[1]	auto[0]	20	1		T73	2		T76	2		T77	1
all_values[12]	auto[0]	auto[1]	auto[1]	66	1		T72	2		T75	2		T76	3
all_values[12]	auto[1]	auto[0]	auto[1]	54	1		T72	2		T74	3		T75	1
all_values[12]	auto[1]	auto[1]	auto[1]	66	1		T72	1		T77	1		T273	1
all_values[13]	auto[0]	auto[0]	auto[0]	34	1		T72	1		T76	1		T273	2
all_values[13]	auto[0]	auto[0]	auto[1]	63	1		T72	3		T74	1		T75	2
all_values[13]	auto[0]	auto[1]	auto[0]	17	1		T72	1		T278	1		T283	2
all_values[13]	auto[0]	auto[1]	auto[1]	53	1		T73	2		T75	3		T76	3
all_values[13]	auto[1]	auto[0]	auto[1]	55	1		T73	1		T74	1		T76	1
all_values[13]	auto[1]	auto[1]	auto[1]	53	1		T72	2		T73	1		T74	2
all_values[14]	auto[0]	auto[0]	auto[0]	32	1		T72	1		T73	4		T278	2
all_values[14]	auto[0]	auto[0]	auto[1]	47	1		T72	3		T75	2		T76	1
all_values[14]	auto[0]	auto[1]	auto[0]	19	1		T74	1		T278	2		T283	1
all_values[14]	auto[0]	auto[1]	auto[1]	57	1		T74	2		T75	2		T76	1
all_values[14]	auto[1]	auto[0]	auto[1]	68	1		T72	3		T75	1		T76	5
all_values[14]	auto[1]	auto[1]	auto[1]	52	1		T74	1		T75	2		T77	1
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T72	1		T73	2		T74	2
all_values[15]	auto[0]	auto[0]	auto[1]	48	1		T72	1		T75	2		T76	1
all_values[15]	auto[0]	auto[1]	auto[0]	21	1		T72	2		T75	2		T76	1
all_values[15]	auto[0]	auto[1]	auto[1]	58	1		T72	1		T73	1		T74	1
all_values[15]	auto[1]	auto[0]	auto[1]	69	1		T72	1		T73	1		T75	2
all_values[15]	auto[1]	auto[1]	auto[1]	50	1		T72	1		T74	1		T75	1
all_values[16]	auto[0]	auto[0]	auto[0]	33	1		T72	3		T73	1		T75	1
all_values[16]	auto[0]	auto[0]	auto[1]	59	1		T72	1		T75	3		T77	1
all_values[16]	auto[0]	auto[1]	auto[0]	15	1		T72	2		T279	1		T280	1
all_values[16]	auto[0]	auto[1]	auto[1]	58	1		T73	1		T74	3		T75	1
all_values[16]	auto[1]	auto[0]	auto[1]	58	1		T72	1		T73	2		T75	1
all_values[16]	auto[1]	auto[1]	auto[1]	52	1		T74	1		T75	1		T77	1
all_values[17]	auto[0]	auto[0]	auto[0]	24	1		T72	1		T280	1		T282	2
all_values[17]	auto[0]	auto[0]	auto[1]	48	1		T72	2		T73	1		T74	2
all_values[17]	auto[0]	auto[1]	auto[0]	18	1		T75	1		T281	2		T282	2
all_values[17]	auto[0]	auto[1]	auto[1]	70	1		T72	1		T73	1		T74	1
all_values[17]	auto[1]	auto[0]	auto[1]	61	1		T72	3		T73	1		T76	2
all_values[17]	auto[1]	auto[1]	auto[1]	54	1		T73	1		T74	1		T75	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal