Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.25 96.74 89.94 97.32 51.56 94.63 97.96 96.58


Total test records in report: 1530
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T1502 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3180525916 May 09 02:50:24 PM PDT 24 May 09 02:50:37 PM PDT 24 92866588 ps
T1503 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1621759946 May 09 02:50:28 PM PDT 24 May 09 02:50:42 PM PDT 24 93287106 ps
T1504 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2308820998 May 09 02:50:25 PM PDT 24 May 09 02:50:38 PM PDT 24 299330246 ps
T1505 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1923258561 May 09 02:50:17 PM PDT 24 May 09 02:50:29 PM PDT 24 149391150 ps
T1506 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3463657132 May 09 02:50:18 PM PDT 24 May 09 02:50:30 PM PDT 24 76451895 ps
T1507 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1120330918 May 09 02:50:32 PM PDT 24 May 09 02:50:45 PM PDT 24 36380773 ps
T1508 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.252664706 May 09 02:50:34 PM PDT 24 May 09 02:50:48 PM PDT 24 196087714 ps
T1509 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1420951480 May 09 02:50:16 PM PDT 24 May 09 02:50:29 PM PDT 24 287534221 ps
T1510 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.977897370 May 09 02:50:39 PM PDT 24 May 09 02:50:50 PM PDT 24 39734273 ps
T1511 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2321786296 May 09 02:50:35 PM PDT 24 May 09 02:50:47 PM PDT 24 23891400 ps
T1512 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2622888775 May 09 02:50:31 PM PDT 24 May 09 02:50:44 PM PDT 24 141668126 ps
T1513 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.706152184 May 09 02:50:32 PM PDT 24 May 09 02:50:46 PM PDT 24 86922456 ps
T1514 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3410797278 May 09 02:50:31 PM PDT 24 May 09 02:50:45 PM PDT 24 49951932 ps
T1515 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1016635732 May 09 02:50:35 PM PDT 24 May 09 02:50:47 PM PDT 24 24458693 ps
T1516 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4006098251 May 09 02:50:35 PM PDT 24 May 09 02:50:48 PM PDT 24 158665583 ps
T1517 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2943817184 May 09 02:50:38 PM PDT 24 May 09 02:50:50 PM PDT 24 36138433 ps
T1518 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.737737585 May 09 02:50:17 PM PDT 24 May 09 02:50:29 PM PDT 24 155012669 ps
T1519 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.541595223 May 09 02:50:25 PM PDT 24 May 09 02:50:40 PM PDT 24 820301821 ps
T1520 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2706067957 May 09 02:50:29 PM PDT 24 May 09 02:50:42 PM PDT 24 40590266 ps
T1521 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1012981118 May 09 02:50:26 PM PDT 24 May 09 02:50:38 PM PDT 24 39922944 ps
T1522 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2065695824 May 09 02:50:30 PM PDT 24 May 09 02:50:42 PM PDT 24 43555621 ps
T1523 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3376229243 May 09 02:50:38 PM PDT 24 May 09 02:50:50 PM PDT 24 47674631 ps
T1524 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3023374957 May 09 02:50:27 PM PDT 24 May 09 02:50:41 PM PDT 24 68758031 ps
T1525 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3861418025 May 09 02:50:32 PM PDT 24 May 09 02:50:47 PM PDT 24 172472112 ps
T1526 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2811451169 May 09 02:50:28 PM PDT 24 May 09 02:50:41 PM PDT 24 84019042 ps
T1527 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2826534024 May 09 02:50:35 PM PDT 24 May 09 02:50:47 PM PDT 24 44899531 ps
T1528 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2649636488 May 09 02:50:16 PM PDT 24 May 09 02:50:27 PM PDT 24 185593898 ps
T1529 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3356683425 May 09 02:50:34 PM PDT 24 May 09 02:50:46 PM PDT 24 51628871 ps
T1530 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3952060861 May 09 02:50:24 PM PDT 24 May 09 02:50:36 PM PDT 24 46936307 ps
T2 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2954255185 May 09 02:50:29 PM PDT 24 May 09 02:50:42 PM PDT 24 44903637 ps

Test location /workspace/coverage/default/17.usbdev_in_iso.3045040364
Short name T3
Test name
Test status
Simulation time 8464191892 ps
CPU time 8.25 seconds
Started May 09 02:47:29 PM PDT 24
Finished May 09 02:47:41 PM PDT 24
Peak memory 204564 kb
Host smart-2fc91d43-4d6e-49eb-a006-370b324de26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30450
40364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3045040364
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1576404993
Short name T16
Test name
Test status
Simulation time 15883800755 ps
CPU time 28.77 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:38 PM PDT 24
Peak memory 204840 kb
Host smart-fcf98e6e-c6a2-4f96-b03e-6707495a915d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15764
04993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1576404993
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2990217925
Short name T72
Test name
Test status
Simulation time 44528314 ps
CPU time 0.71 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203192 kb
Host smart-8e22e14a-d23c-4614-a413-540e1233d285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2990217925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2990217925
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1900924589
Short name T215
Test name
Test status
Simulation time 395578056 ps
CPU time 2.92 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 204056 kb
Host smart-71a322b5-2f9e-464a-a10d-daf473a8d5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1900924589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1900924589
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3319417823
Short name T22
Test name
Test status
Simulation time 8374616345 ps
CPU time 8.62 seconds
Started May 09 02:49:12 PM PDT 24
Finished May 09 02:49:28 PM PDT 24
Peak memory 204516 kb
Host smart-3fe83de4-49cf-4ee4-99ec-5249122fa12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
17823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3319417823
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3017451270
Short name T19
Test name
Test status
Simulation time 9479812542 ps
CPU time 12.39 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:44 PM PDT 24
Peak memory 204840 kb
Host smart-50ae733c-b5d3-4020-ab45-2fed0c071873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30174
51270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3017451270
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.758073950
Short name T271
Test name
Test status
Simulation time 40521533 ps
CPU time 0.69 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 202760 kb
Host smart-ae26eb70-c29a-499d-a9af-eb72dbed089a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=758073950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.758073950
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.244775011
Short name T237
Test name
Test status
Simulation time 164469402 ps
CPU time 1.9 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 212284 kb
Host smart-c4b9b309-e186-4d0c-982e-e1c7ce888ce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244775011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.244775011
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3456063056
Short name T66
Test name
Test status
Simulation time 384338007 ps
CPU time 1.27 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:45:56 PM PDT 24
Peak memory 220748 kb
Host smart-8c48cf4c-3294-4794-b75d-15d89a90f8d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3456063056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3456063056
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3505816178
Short name T7
Test name
Test status
Simulation time 8368117489 ps
CPU time 7.91 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204548 kb
Host smart-70fbeef5-fbb2-4d0c-9eba-2dce8cce995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
16178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3505816178
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1271239606
Short name T26
Test name
Test status
Simulation time 8372189841 ps
CPU time 8.12 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204500 kb
Host smart-30342a98-925d-423d-a023-be2ac15047af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12712
39606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1271239606
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3289210181
Short name T33
Test name
Test status
Simulation time 8433777444 ps
CPU time 8.99 seconds
Started May 09 02:47:44 PM PDT 24
Finished May 09 02:47:57 PM PDT 24
Peak memory 204572 kb
Host smart-89894a5a-a0c9-418c-ae6a-3f275851b064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
10181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3289210181
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2954255185
Short name T2
Test name
Test status
Simulation time 44903637 ps
CPU time 0.78 seconds
Started May 09 02:50:29 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 203720 kb
Host smart-3b5eeade-446f-49d9-a6a6-e763949e78a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2954255185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2954255185
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2796249057
Short name T297
Test name
Test status
Simulation time 8377662135 ps
CPU time 7.35 seconds
Started May 09 02:45:39 PM PDT 24
Finished May 09 02:45:49 PM PDT 24
Peak memory 204592 kb
Host smart-c8b1f502-fc18-41ea-9813-fef3ebfce55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27962
49057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2796249057
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.803952438
Short name T52
Test name
Test status
Simulation time 39831768 ps
CPU time 0.67 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:00 PM PDT 24
Peak memory 204516 kb
Host smart-42e6efea-f051-44ae-b2ce-29c820eafd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80395
2438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.803952438
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1173114796
Short name T93
Test name
Test status
Simulation time 79094831 ps
CPU time 1.91 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204708 kb
Host smart-4753908f-d8ac-4a82-a93f-2809b4503374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
14796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1173114796
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3274142863
Short name T286
Test name
Test status
Simulation time 46785188 ps
CPU time 0.68 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203184 kb
Host smart-4aa9d41f-58df-4858-bdde-4c06c02d82cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3274142863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3274142863
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3751507695
Short name T71
Test name
Test status
Simulation time 68181753 ps
CPU time 1.01 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 203756 kb
Host smart-741b6424-56e2-4a13-a4d1-01b27bde1a24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3751507695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3751507695
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3739177149
Short name T53
Test name
Test status
Simulation time 8428376692 ps
CPU time 9.61 seconds
Started May 09 02:47:29 PM PDT 24
Finished May 09 02:47:43 PM PDT 24
Peak memory 204504 kb
Host smart-3c57fdf7-c6e4-47d1-a2a8-635de53308ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37391
77149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3739177149
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1923979944
Short name T278
Test name
Test status
Simulation time 41488308 ps
CPU time 0.69 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 202500 kb
Host smart-2b04be60-7d80-4d9e-bfe7-94592659e5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1923979944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1923979944
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2959538752
Short name T235
Test name
Test status
Simulation time 310281676 ps
CPU time 3.16 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 204092 kb
Host smart-be598bc9-9bdc-4f60-9a77-88d9b49e3db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2959538752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2959538752
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/default/38.usbdev_smoke.108131824
Short name T138
Test name
Test status
Simulation time 8425712367 ps
CPU time 7.71 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204520 kb
Host smart-ba090ffd-af87-4a12-b868-536535e76684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10813
1824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.108131824
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2306140790
Short name T239
Test name
Test status
Simulation time 641351487 ps
CPU time 4.77 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 204032 kb
Host smart-2f603dd1-e751-4859-be25-521e42ebe2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2306140790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2306140790
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1131153076
Short name T272
Test name
Test status
Simulation time 28801407 ps
CPU time 0.65 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 02:50:51 PM PDT 24
Peak memory 203076 kb
Host smart-e5262463-8679-4528-8db9-e99e3ef3a00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1131153076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1131153076
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_enable.2931030354
Short name T336
Test name
Test status
Simulation time 8371454478 ps
CPU time 7.51 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204556 kb
Host smart-5b825984-04a2-479a-8eb2-48dbac8ed667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
30354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2931030354
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.384927654
Short name T292
Test name
Test status
Simulation time 728448871 ps
CPU time 5.25 seconds
Started May 09 02:50:33 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 204000 kb
Host smart-27872eef-4cba-4cd8-a965-c5e52af01119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=384927654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.384927654
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.398740904
Short name T15
Test name
Test status
Simulation time 5108647802 ps
CPU time 129.62 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204744 kb
Host smart-857b2423-4683-4005-8087-d4e7e7dc000e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39874
0904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.398740904
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.289182089
Short name T18
Test name
Test status
Simulation time 21554733212 ps
CPU time 38.89 seconds
Started May 09 02:46:03 PM PDT 24
Finished May 09 02:46:45 PM PDT 24
Peak memory 204704 kb
Host smart-3dee0253-ab70-4d36-a870-c54a9efc703e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28918
2089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.289182089
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2042823834
Short name T1
Test name
Test status
Simulation time 62193538 ps
CPU time 0.91 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 203788 kb
Host smart-f6e1d7e1-b0cf-46a3-9b10-78f52ff9803a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2042823834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2042823834
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.820818204
Short name T273
Test name
Test status
Simulation time 30704832 ps
CPU time 0.66 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 203264 kb
Host smart-6f25c440-f4e7-4486-a460-e80343fe6a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=820818204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.820818204
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3721466980
Short name T220
Test name
Test status
Simulation time 406752774 ps
CPU time 4.12 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 203984 kb
Host smart-23e533da-6e71-48ca-b653-fc9ce9bb19f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3721466980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3721466980
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1621759946
Short name T1503
Test name
Test status
Simulation time 93287106 ps
CPU time 2.46 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 204040 kb
Host smart-351e9acf-34fb-403c-9f98-fa204692699c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1621759946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1621759946
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2011995265
Short name T20
Test name
Test status
Simulation time 9588886844 ps
CPU time 13.34 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204832 kb
Host smart-0d0208a4-ffa3-4699-bbd5-6b5c5f718834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119
95265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2011995265
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2539265200
Short name T49
Test name
Test status
Simulation time 47111517 ps
CPU time 0.67 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204444 kb
Host smart-a49291a6-703b-41ed-bf9c-8e9aaddaf101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392
65200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2539265200
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2853243062
Short name T965
Test name
Test status
Simulation time 8475513009 ps
CPU time 7.86 seconds
Started May 09 02:45:49 PM PDT 24
Finished May 09 02:46:01 PM PDT 24
Peak memory 204576 kb
Host smart-59a6f97c-c090-4d60-bc5f-48360c238916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28532
43062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2853243062
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.768007196
Short name T189
Test name
Test status
Simulation time 8421409380 ps
CPU time 7.59 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204588 kb
Host smart-b8dd3e5a-5b24-403e-853a-54a5eb002ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76800
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.768007196
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2127526517
Short name T1089
Test name
Test status
Simulation time 8461854617 ps
CPU time 7.59 seconds
Started May 09 02:46:47 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204580 kb
Host smart-abe8701d-5e24-46b9-afba-6bb87829d697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
26517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2127526517
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.660557274
Short name T211
Test name
Test status
Simulation time 8391830073 ps
CPU time 7.73 seconds
Started May 09 02:47:01 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204588 kb
Host smart-07843796-cf77-4c54-a81d-74c93683fdd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66055
7274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.660557274
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1793940497
Short name T149
Test name
Test status
Simulation time 8440646500 ps
CPU time 8.22 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204512 kb
Host smart-4b970cdc-57db-44f7-b87a-d3310d3e3a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17939
40497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1793940497
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.201576059
Short name T85
Test name
Test status
Simulation time 9762559973 ps
CPU time 13.97 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:24 PM PDT 24
Peak memory 204780 kb
Host smart-c8a97fb7-0d55-4026-a195-f09508586926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20157
6059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.201576059
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4187647405
Short name T192
Test name
Test status
Simulation time 8412911202 ps
CPU time 10.25 seconds
Started May 09 02:47:19 PM PDT 24
Finished May 09 02:47:32 PM PDT 24
Peak memory 204564 kb
Host smart-e683376a-0d25-4630-9db6-7ceb22237914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41876
47405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4187647405
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3574890570
Short name T530
Test name
Test status
Simulation time 8406294760 ps
CPU time 8.41 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:03 PM PDT 24
Peak memory 204508 kb
Host smart-91bec64c-7707-4de7-8354-b2db0da60e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35748
90570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3574890570
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3036207640
Short name T180
Test name
Test status
Simulation time 8405883256 ps
CPU time 8.64 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204608 kb
Host smart-3b332813-6ef6-4711-a18c-ff88f3267bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
07640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3036207640
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2283325430
Short name T176
Test name
Test status
Simulation time 8390932657 ps
CPU time 7.85 seconds
Started May 09 02:46:13 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 204568 kb
Host smart-be4d115a-a659-4a4b-9c11-3745b3f4b22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833
25430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2283325430
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2203042174
Short name T640
Test name
Test status
Simulation time 8409102795 ps
CPU time 9.17 seconds
Started May 09 02:47:04 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204580 kb
Host smart-5a55be89-8310-4345-b190-37f5efca89c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22030
42174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2203042174
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.667167319
Short name T106
Test name
Test status
Simulation time 8429869544 ps
CPU time 7.59 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:45:40 PM PDT 24
Peak memory 204544 kb
Host smart-21e0ad3f-4efe-4da8-af1e-4a875edfb1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66716
7319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.667167319
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4148299644
Short name T1264
Test name
Test status
Simulation time 8392014452 ps
CPU time 7.46 seconds
Started May 09 02:45:37 PM PDT 24
Finished May 09 02:45:46 PM PDT 24
Peak memory 204564 kb
Host smart-ac939f36-0ed5-40cf-9c62-017883e56984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41482
99644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4148299644
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.892838123
Short name T160
Test name
Test status
Simulation time 8433189129 ps
CPU time 7.48 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 204520 kb
Host smart-48340ea0-11c9-4f42-8554-0f8eb55a0f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89283
8123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.892838123
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1352593005
Short name T143
Test name
Test status
Simulation time 8467310398 ps
CPU time 7.76 seconds
Started May 09 02:45:39 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 204564 kb
Host smart-edc7e486-da24-45ff-9f52-ec70c1c029df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13525
93005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1352593005
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1279910267
Short name T586
Test name
Test status
Simulation time 8447030705 ps
CPU time 8.35 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204576 kb
Host smart-c32a9c78-3e33-42c1-b54e-516a22ef3465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12799
10267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1279910267
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2817676017
Short name T187
Test name
Test status
Simulation time 8377565430 ps
CPU time 7.85 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204568 kb
Host smart-4581abdd-329d-443e-9c93-9a2b67e0c23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28176
76017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2817676017
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.726574869
Short name T1430
Test name
Test status
Simulation time 8386297095 ps
CPU time 7.77 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204556 kb
Host smart-34dcf923-65a6-4667-a89a-7c11bd103dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72657
4869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.726574869
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1759610385
Short name T195
Test name
Test status
Simulation time 9400512255 ps
CPU time 13.23 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204860 kb
Host smart-314109aa-453c-4a3f-9e03-777a92a0bab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17596
10385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1759610385
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.713466452
Short name T139
Test name
Test status
Simulation time 8431040234 ps
CPU time 8.61 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204592 kb
Host smart-7282153e-9641-48ec-b6f1-29cdb20752ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71346
6452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.713466452
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3305418370
Short name T102
Test name
Test status
Simulation time 8444785640 ps
CPU time 7.42 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204584 kb
Host smart-f2475af0-e462-4b85-b45b-206bbd7d9661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33054
18370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3305418370
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3526591032
Short name T992
Test name
Test status
Simulation time 8427038082 ps
CPU time 7.75 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204528 kb
Host smart-8b05ba0b-6aea-4b45-9983-1f728860a376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265
91032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3526591032
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2206750859
Short name T115
Test name
Test status
Simulation time 8462500407 ps
CPU time 7.9 seconds
Started May 09 02:47:01 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204588 kb
Host smart-6d06f2df-83f1-470d-88af-1d1e1b8dca51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22067
50859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2206750859
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3174680478
Short name T714
Test name
Test status
Simulation time 8370192094 ps
CPU time 8.03 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204524 kb
Host smart-4ed818ef-aa82-4700-aeba-b3fff364b978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
80478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3174680478
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3258282489
Short name T110
Test name
Test status
Simulation time 8402629200 ps
CPU time 8 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204572 kb
Host smart-acb63220-e5b2-45d8-82e2-f47c8b0c2076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32582
82489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3258282489
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3126521486
Short name T788
Test name
Test status
Simulation time 8415627990 ps
CPU time 8.12 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204568 kb
Host smart-b0b5cf3d-3c98-4f88-9a86-e3c61a743843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
21486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3126521486
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1222342181
Short name T1344
Test name
Test status
Simulation time 8406792494 ps
CPU time 7.94 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:39 PM PDT 24
Peak memory 204556 kb
Host smart-2d0cd03c-42d6-4e6e-9a91-eeabf4054232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12223
42181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1222342181
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.645472050
Short name T27
Test name
Test status
Simulation time 8387576267 ps
CPU time 8.4 seconds
Started May 09 02:47:39 PM PDT 24
Finished May 09 02:47:50 PM PDT 24
Peak memory 204540 kb
Host smart-29adfe5e-c896-45b1-8cf7-528d63d3da30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64547
2050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.645472050
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3828381100
Short name T117
Test name
Test status
Simulation time 8421711739 ps
CPU time 7.73 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204388 kb
Host smart-2f10ef87-0ff3-4ae7-bf3f-caa3f17f5e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38283
81100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3828381100
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1160318010
Short name T99
Test name
Test status
Simulation time 8446185834 ps
CPU time 8.8 seconds
Started May 09 02:47:57 PM PDT 24
Finished May 09 02:48:10 PM PDT 24
Peak memory 204524 kb
Host smart-267edad6-3bc1-4c76-b408-96b30d759bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11603
18010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1160318010
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.478996431
Short name T1086
Test name
Test status
Simulation time 8372869827 ps
CPU time 8.49 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204560 kb
Host smart-0b81d11c-8ca2-442f-8833-9a9b4b9b20d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47899
6431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.478996431
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4239155921
Short name T125
Test name
Test status
Simulation time 8426375654 ps
CPU time 7.68 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204572 kb
Host smart-f1160570-5c19-4b08-969c-23e84d3687f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
55921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4239155921
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.979433624
Short name T104
Test name
Test status
Simulation time 8393470685 ps
CPU time 7.92 seconds
Started May 09 02:48:09 PM PDT 24
Finished May 09 02:48:22 PM PDT 24
Peak memory 204596 kb
Host smart-8e6487cc-c984-44bf-834a-017d3553f1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97943
3624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.979433624
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3534421475
Short name T768
Test name
Test status
Simulation time 8672507831 ps
CPU time 12.17 seconds
Started May 09 02:48:28 PM PDT 24
Finished May 09 02:48:47 PM PDT 24
Peak memory 204804 kb
Host smart-246a2300-a389-4434-a85f-f9e8818cde8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
21475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3534421475
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3169636468
Short name T120
Test name
Test status
Simulation time 8497359360 ps
CPU time 8.15 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:00 PM PDT 24
Peak memory 204580 kb
Host smart-6d83952a-ade3-4017-9ffe-6ff0bc49e87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31696
36468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3169636468
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.737737585
Short name T1518
Test name
Test status
Simulation time 155012669 ps
CPU time 3.23 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 204008 kb
Host smart-ef612284-7b3c-45b5-bf9f-6fb85aaee625
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=737737585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.737737585
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2260354202
Short name T262
Test name
Test status
Simulation time 462971751 ps
CPU time 4.24 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:30 PM PDT 24
Peak memory 203988 kb
Host smart-d0fb121b-c326-47f1-923a-ad5ea96ed541
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2260354202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2260354202
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.902163398
Short name T1433
Test name
Test status
Simulation time 62302681 ps
CPU time 0.78 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 203712 kb
Host smart-98142be1-98f9-45f4-8761-76d4586652ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=902163398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.902163398
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.129767318
Short name T1487
Test name
Test status
Simulation time 81529252 ps
CPU time 2.19 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 212324 kb
Host smart-2d0f66b8-8046-4759-8c4c-69556bcad5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129767318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.129767318
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.864699132
Short name T259
Test name
Test status
Simulation time 53890507 ps
CPU time 0.94 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 203948 kb
Host smart-3fe370c7-a94b-45b5-829e-6b99960bfa20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=864699132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.864699132
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3102951587
Short name T1484
Test name
Test status
Simulation time 96007651 ps
CPU time 1.5 seconds
Started May 09 02:50:19 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 212156 kb
Host smart-08e472f2-f805-4241-a12c-a4b3d52f373b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3102951587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3102951587
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1351180785
Short name T1457
Test name
Test status
Simulation time 160379602 ps
CPU time 2.31 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 203900 kb
Host smart-6cfead7d-f957-481f-8b4e-3b9a97143a20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1351180785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1351180785
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2376612052
Short name T1445
Test name
Test status
Simulation time 46652239 ps
CPU time 1.06 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:22 PM PDT 24
Peak memory 204004 kb
Host smart-b4055e6f-b553-4089-8863-770ca181f99a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2376612052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2376612052
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1923258561
Short name T1505
Test name
Test status
Simulation time 149391150 ps
CPU time 2.18 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 204280 kb
Host smart-61911a09-b5d7-40eb-b89c-c33aa1010563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1923258561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1923258561
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.506160412
Short name T288
Test name
Test status
Simulation time 341026125 ps
CPU time 3.14 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:22 PM PDT 24
Peak memory 204044 kb
Host smart-b505a2e7-cbaf-46a2-8634-9998a77d6ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=506160412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.506160412
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4054342841
Short name T260
Test name
Test status
Simulation time 354039578 ps
CPU time 3.57 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 204012 kb
Host smart-8d0ce448-82f1-435a-a40f-2d419a0a1c14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4054342841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4054342841
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.761953615
Short name T69
Test name
Test status
Simulation time 580701525 ps
CPU time 7.26 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 203928 kb
Host smart-4769f2fa-b69e-4445-9b21-ee788c482ece
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=761953615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.761953615
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2630093632
Short name T1478
Test name
Test status
Simulation time 115625818 ps
CPU time 1.81 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:21 PM PDT 24
Peak memory 212192 kb
Host smart-3f615a4d-91ed-4280-9b39-2301d5300dc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630093632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2630093632
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.439309359
Short name T212
Test name
Test status
Simulation time 39343618 ps
CPU time 0.8 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 203748 kb
Host smart-e951685d-2e64-4958-abbf-a6d6c57da817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=439309359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.439309359
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2174079052
Short name T261
Test name
Test status
Simulation time 199166433 ps
CPU time 2.35 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 212212 kb
Host smart-ceace352-250b-432a-a493-9c38c098c7de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2174079052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2174079052
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3794154560
Short name T1452
Test name
Test status
Simulation time 155833619 ps
CPU time 3.87 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:28 PM PDT 24
Peak memory 203900 kb
Host smart-6e9d756c-5e49-4f40-9885-381d4c32aa23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3794154560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3794154560
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2952835111
Short name T1435
Test name
Test status
Simulation time 150457046 ps
CPU time 1.59 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:22 PM PDT 24
Peak memory 204048 kb
Host smart-37263f53-1632-4a16-ad84-d8a81b00d39a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2952835111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2952835111
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3016660036
Short name T232
Test name
Test status
Simulation time 207734654 ps
CPU time 2.26 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 204048 kb
Host smart-e6d87c56-4ef4-413a-955a-a5e030ca54fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3016660036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3016660036
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.768347018
Short name T1447
Test name
Test status
Simulation time 85128933 ps
CPU time 1.28 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 212236 kb
Host smart-c48c9af2-6c9c-46b7-a6bc-1974d4eeb6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768347018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.768347018
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2039421497
Short name T1490
Test name
Test status
Simulation time 61067395 ps
CPU time 0.84 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203732 kb
Host smart-44d56499-a1d8-446c-9f0b-6445c1a6a380
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2039421497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2039421497
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3633496867
Short name T1449
Test name
Test status
Simulation time 68166530 ps
CPU time 1.04 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 204036 kb
Host smart-d1744c4f-1f1e-4856-b2ca-5f9795e47848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3633496867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3633496867
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2714806420
Short name T1465
Test name
Test status
Simulation time 270947898 ps
CPU time 2.77 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 203956 kb
Host smart-6a380307-ca45-4684-905c-6dd475330940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2714806420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2714806420
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3218132351
Short name T1460
Test name
Test status
Simulation time 50046785 ps
CPU time 1.36 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 212296 kb
Host smart-032dc9f0-39a2-44f3-bf46-935dbc680dbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218132351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3218132351
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1296424467
Short name T1494
Test name
Test status
Simulation time 42959745 ps
CPU time 1 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 203984 kb
Host smart-cc2c3378-f86d-4153-be04-7401583ccf1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1296424467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1296424467
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1016635732
Short name T1515
Test name
Test status
Simulation time 24458693 ps
CPU time 0.66 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203224 kb
Host smart-3d02d0b2-fb1a-4099-98b9-54627158f9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016635732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1016635732
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3218994795
Short name T1481
Test name
Test status
Simulation time 159437722 ps
CPU time 1.58 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:44 PM PDT 24
Peak memory 204044 kb
Host smart-2ab2adff-986f-42b3-b6b7-21b4e079af84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3218994795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3218994795
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3861418025
Short name T1525
Test name
Test status
Simulation time 172472112 ps
CPU time 2.26 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203928 kb
Host smart-cb53839c-6835-4304-abe7-33871eada6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3861418025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3861418025
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4173992790
Short name T293
Test name
Test status
Simulation time 338239047 ps
CPU time 2.7 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203996 kb
Host smart-d01c3804-b998-47e3-b93f-121affd07f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4173992790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4173992790
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.706152184
Short name T1513
Test name
Test status
Simulation time 86922456 ps
CPU time 1.22 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 212120 kb
Host smart-8a609f27-fce6-45e6-9e9c-e43dee42be65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706152184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.706152184
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2979381867
Short name T263
Test name
Test status
Simulation time 93881886 ps
CPU time 1.06 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 204016 kb
Host smart-8bc84759-bd6e-4f51-af1e-c2d635f26a79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2979381867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2979381867
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2065695824
Short name T1522
Test name
Test status
Simulation time 43555621 ps
CPU time 0.66 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 203280 kb
Host smart-eddcc178-1d4e-463a-bc35-27f9919b2248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065695824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2065695824
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3270022067
Short name T1439
Test name
Test status
Simulation time 58106824 ps
CPU time 1.01 seconds
Started May 09 02:50:33 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203948 kb
Host smart-c9f7ceeb-3f7f-441a-bb7e-6d40db6e7db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3270022067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3270022067
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.700522745
Short name T233
Test name
Test status
Simulation time 133232203 ps
CPU time 1.62 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 203992 kb
Host smart-95e53237-e68a-4078-b364-e93c1f77f13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=700522745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.700522745
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1774483135
Short name T1464
Test name
Test status
Simulation time 304082948 ps
CPU time 4.2 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:51 PM PDT 24
Peak memory 204012 kb
Host smart-1e711b3f-63ef-4511-8a21-14621954526f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1774483135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1774483135
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2996726494
Short name T1499
Test name
Test status
Simulation time 94285836 ps
CPU time 1.4 seconds
Started May 09 02:50:29 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 212252 kb
Host smart-b492e8d1-a774-477f-bb1e-930cb55af7b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996726494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2996726494
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3771941351
Short name T265
Test name
Test status
Simulation time 48566237 ps
CPU time 0.88 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203552 kb
Host smart-3374f02e-4793-4684-b446-3ca5f818826b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3771941351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3771941351
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2274063344
Short name T1488
Test name
Test status
Simulation time 36953864 ps
CPU time 0.67 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 203124 kb
Host smart-125de0ed-08f4-4cc6-ad79-fd5c7aedcd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2274063344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2274063344
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2666789218
Short name T213
Test name
Test status
Simulation time 131439375 ps
CPU time 1.11 seconds
Started May 09 02:50:33 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203948 kb
Host smart-6e2cf896-0376-4377-8e6a-651c779e512a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2666789218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2666789218
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.836630837
Short name T1469
Test name
Test status
Simulation time 356584047 ps
CPU time 3.6 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 204088 kb
Host smart-6c9040a8-03ce-47b9-b2e3-7ac24731fa3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=836630837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.836630837
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4139431205
Short name T1466
Test name
Test status
Simulation time 150763300 ps
CPU time 2.03 seconds
Started May 09 02:50:29 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 212216 kb
Host smart-22ebaa61-6983-4180-be08-66fca0a98a69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139431205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.4139431205
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3961274543
Short name T264
Test name
Test status
Simulation time 32174382 ps
CPU time 0.79 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203764 kb
Host smart-c96cba87-f87a-4552-8ecd-2e2cae078580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3961274543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3961274543
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4176942726
Short name T1467
Test name
Test status
Simulation time 41936365 ps
CPU time 0.69 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203152 kb
Host smart-0de0bcdd-378e-4dcc-8eef-06f227d02609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4176942726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.4176942726
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2363293740
Short name T1462
Test name
Test status
Simulation time 205265251 ps
CPU time 1.2 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 204036 kb
Host smart-4c63502a-208f-455d-a977-6592539ee7b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2363293740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2363293740
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1040379911
Short name T221
Test name
Test status
Simulation time 214030419 ps
CPU time 2.88 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 203960 kb
Host smart-bbc871b7-d909-4a3d-a556-43268e34c129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1040379911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1040379911
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.223905070
Short name T1495
Test name
Test status
Simulation time 304082891 ps
CPU time 2.71 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 204024 kb
Host smart-e5c79fbf-ab13-4aaf-8295-5df1a02f05f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=223905070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.223905070
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.644047403
Short name T1436
Test name
Test status
Simulation time 81484925 ps
CPU time 1.81 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 212260 kb
Host smart-b149c82a-8f70-49c5-85ad-286237dcefc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644047403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.644047403
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4293469142
Short name T258
Test name
Test status
Simulation time 52133307 ps
CPU time 0.93 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 204004 kb
Host smart-ef0ada70-2e73-4209-9c78-5e9fc040bd89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4293469142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4293469142
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1120330918
Short name T1507
Test name
Test status
Simulation time 36380773 ps
CPU time 0.66 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 203104 kb
Host smart-55813b85-fc5a-49ed-88b1-bfb253f2d581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1120330918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1120330918
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2346512547
Short name T1434
Test name
Test status
Simulation time 48832129 ps
CPU time 0.97 seconds
Started May 09 02:50:33 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203956 kb
Host smart-1c9e7d74-933f-46f8-b5e7-0224e8b5fd70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2346512547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2346512547
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1457955259
Short name T1468
Test name
Test status
Simulation time 152679373 ps
CPU time 1.82 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203976 kb
Host smart-581295e6-0842-4383-9206-4d8da07febf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1457955259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1457955259
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4192610876
Short name T291
Test name
Test status
Simulation time 780654222 ps
CPU time 3.14 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 204028 kb
Host smart-fd590086-4d73-4682-a53e-4405de298ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4192610876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.4192610876
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1995847660
Short name T216
Test name
Test status
Simulation time 112243047 ps
CPU time 2.38 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 02:50:52 PM PDT 24
Peak memory 212244 kb
Host smart-be0f249d-b616-47ed-aeda-c23e1dba2b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995847660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1995847660
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1032321582
Short name T1480
Test name
Test status
Simulation time 91390025 ps
CPU time 1.16 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 204036 kb
Host smart-f16e0f8f-056a-4358-9c80-93bc02df57d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1032321582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1032321582
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1024455317
Short name T231
Test name
Test status
Simulation time 62671221 ps
CPU time 1.78 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 203988 kb
Host smart-5d44d62d-189f-4347-ad77-9b0d670fb48f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1024455317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1024455317
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1695875496
Short name T236
Test name
Test status
Simulation time 662914279 ps
CPU time 4.88 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:51 PM PDT 24
Peak memory 204032 kb
Host smart-89acf154-134a-4943-84f2-42232fe96f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1695875496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1695875496
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3410797278
Short name T1514
Test name
Test status
Simulation time 49951932 ps
CPU time 1.23 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 212164 kb
Host smart-b7f21a76-8bf7-4b78-8786-7d8a564eee79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410797278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3410797278
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.246995410
Short name T256
Test name
Test status
Simulation time 29704655 ps
CPU time 0.82 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 203688 kb
Host smart-6d314d55-a2d0-4cb4-b327-f423155bc426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=246995410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.246995410
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3433537074
Short name T281
Test name
Test status
Simulation time 46739926 ps
CPU time 0.64 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 02:50:51 PM PDT 24
Peak memory 203140 kb
Host smart-bd832f59-1644-4eea-9c43-22845c99d8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3433537074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3433537074
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2465926489
Short name T214
Test name
Test status
Simulation time 96137970 ps
CPU time 1.1 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 204056 kb
Host smart-022b9d4e-e97d-4ce5-84e4-a3ea606c0e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2465926489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2465926489
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2622888775
Short name T1512
Test name
Test status
Simulation time 141668126 ps
CPU time 1.53 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:44 PM PDT 24
Peak memory 204068 kb
Host smart-83b8f122-726c-4c80-acb4-64f23ef26996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2622888775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2622888775
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2630118978
Short name T64
Test name
Test status
Simulation time 1136027399 ps
CPU time 3.25 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 02:50:53 PM PDT 24
Peak memory 203992 kb
Host smart-39ddeb71-4108-44f4-992f-af1ea37cffbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2630118978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2630118978
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1424399613
Short name T1479
Test name
Test status
Simulation time 100292278 ps
CPU time 1.31 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:44 PM PDT 24
Peak memory 212244 kb
Host smart-b6f124b4-42dd-4d26-8c01-c2a02aab2293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424399613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1424399613
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2811451169
Short name T1526
Test name
Test status
Simulation time 84019042 ps
CPU time 1.03 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 203992 kb
Host smart-0f799375-3e07-407b-bd12-9b489796c100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2811451169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2811451169
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2725410425
Short name T275
Test name
Test status
Simulation time 33136526 ps
CPU time 0.68 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203188 kb
Host smart-1162a1b0-039d-4c80-9599-09a906092b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2725410425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2725410425
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2550757765
Short name T270
Test name
Test status
Simulation time 98672554 ps
CPU time 1.09 seconds
Started May 09 02:50:30 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 204132 kb
Host smart-2c71828f-553a-4601-9977-fe157eb6d456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2550757765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2550757765
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.98937899
Short name T287
Test name
Test status
Simulation time 892193286 ps
CPU time 5.24 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 204080 kb
Host smart-5970b0cd-db94-436a-8349-5f61c0667218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=98937899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.98937899
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.347530807
Short name T1486
Test name
Test status
Simulation time 107802684 ps
CPU time 2.55 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 212276 kb
Host smart-10b06ca0-f454-45dc-9fa0-0f2404fdeedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347530807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.347530807
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1206583041
Short name T1440
Test name
Test status
Simulation time 35295034 ps
CPU time 0.79 seconds
Started May 09 02:50:32 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 203532 kb
Host smart-3d1ac1a0-8f55-4054-bcd9-fe619aa941f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1206583041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1206583041
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2465805117
Short name T285
Test name
Test status
Simulation time 32564932 ps
CPU time 0.7 seconds
Started May 09 02:50:33 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203188 kb
Host smart-95fca03c-06ce-4756-90a3-6638595ad532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2465805117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2465805117
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4006098251
Short name T1516
Test name
Test status
Simulation time 158665583 ps
CPU time 1.6 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 203984 kb
Host smart-1d191319-1d8e-4ee4-881c-5e16297a6822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4006098251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4006098251
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3010451411
Short name T65
Test name
Test status
Simulation time 175630505 ps
CPU time 2.25 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 212236 kb
Host smart-88def6fe-3a68-4690-8226-f071a1963d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010451411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3010451411
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.801359638
Short name T290
Test name
Test status
Simulation time 270606559 ps
CPU time 2.53 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 204008 kb
Host smart-e46d27a6-362d-478b-b455-4813a5e46d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=801359638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.801359638
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1420951480
Short name T1509
Test name
Test status
Simulation time 287534221 ps
CPU time 3.43 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 203988 kb
Host smart-cdc65e50-171c-4663-b177-d7e8a1a58ad5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1420951480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1420951480
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1092186245
Short name T257
Test name
Test status
Simulation time 544651193 ps
CPU time 4.28 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 203932 kb
Host smart-e55ae54e-d51f-4ce0-83ad-e6aa6d1c94d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1092186245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1092186245
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.169816988
Short name T70
Test name
Test status
Simulation time 198401365 ps
CPU time 1.05 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:26 PM PDT 24
Peak memory 203700 kb
Host smart-51f8fdd5-efb4-4f1d-95f3-b22634dd1135
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=169816988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.169816988
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2649636488
Short name T1528
Test name
Test status
Simulation time 185593898 ps
CPU time 2.02 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 212304 kb
Host smart-17336475-0778-4b20-84be-c1539ca7bd7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649636488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2649636488
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.964717913
Short name T1493
Test name
Test status
Simulation time 60564077 ps
CPU time 0.82 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 203304 kb
Host smart-9b050794-44bf-41d8-a302-db34816dae7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=964717913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.964717913
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3916042957
Short name T74
Test name
Test status
Simulation time 40452112 ps
CPU time 0.65 seconds
Started May 09 02:50:19 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 203192 kb
Host smart-498adb45-40c3-4bf7-8095-05126c5add4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3916042957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3916042957
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.668342374
Short name T250
Test name
Test status
Simulation time 173185913 ps
CPU time 2.27 seconds
Started May 09 02:50:19 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 212160 kb
Host smart-c011018d-4593-4db4-ad2a-6c06e7122c19
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=668342374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.668342374
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3034749724
Short name T1432
Test name
Test status
Simulation time 482430851 ps
CPU time 4.42 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:19 PM PDT 24
Peak memory 203912 kb
Host smart-cde5639e-588e-4b34-b1c3-047334778f4b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3034749724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3034749724
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2703012262
Short name T1482
Test name
Test status
Simulation time 125716012 ps
CPU time 1.09 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 204060 kb
Host smart-9417bd2f-daa6-4439-bd49-ffe14eea933a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2703012262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2703012262
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3303323191
Short name T230
Test name
Test status
Simulation time 130725648 ps
CPU time 3.22 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 212232 kb
Host smart-9de45322-fd25-4027-b40a-c5d047992457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3303323191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3303323191
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2771780942
Short name T217
Test name
Test status
Simulation time 592066741 ps
CPU time 4.7 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 203996 kb
Host smart-267d4a68-6117-4941-9db2-ef32ac6e9627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2771780942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2771780942
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1964420049
Short name T1501
Test name
Test status
Simulation time 33551805 ps
CPU time 0.66 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203124 kb
Host smart-f10caa76-38e5-420b-bea1-637c5a041d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1964420049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1964420049
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2406456990
Short name T73
Test name
Test status
Simulation time 25765922 ps
CPU time 0.64 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203240 kb
Host smart-e7710f71-124d-4701-81bc-5bf450bf1fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406456990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2406456990
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3602863739
Short name T75
Test name
Test status
Simulation time 34575512 ps
CPU time 0.67 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 203260 kb
Host smart-a42e6619-aa99-43ad-9ae8-e2b5d421fa4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3602863739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3602863739
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1532787910
Short name T1483
Test name
Test status
Simulation time 33548996 ps
CPU time 0.66 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203180 kb
Host smart-e464c0e5-7bbc-4e2a-a9aa-446bba049faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532787910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1532787910
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.375815120
Short name T284
Test name
Test status
Simulation time 26759692 ps
CPU time 0.67 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 203200 kb
Host smart-79b74614-f91c-430a-b2da-ab8cbd2c27f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375815120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.375815120
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1857967881
Short name T1477
Test name
Test status
Simulation time 31998143 ps
CPU time 0.66 seconds
Started May 09 02:50:33 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203160 kb
Host smart-302d2341-b87f-46cf-9ce4-bfa29a9fff07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1857967881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1857967881
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.387740625
Short name T279
Test name
Test status
Simulation time 59332562 ps
CPU time 0.72 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 202716 kb
Host smart-aafebc5c-ef95-4f88-9de7-de370df5a3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=387740625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.387740625
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.977897370
Short name T1510
Test name
Test status
Simulation time 39734273 ps
CPU time 0.68 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203252 kb
Host smart-e4ef07fa-d65d-47a4-86d3-0cb9388ba6be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=977897370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.977897370
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2943817184
Short name T1517
Test name
Test status
Simulation time 36138433 ps
CPU time 0.65 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203180 kb
Host smart-92579c6a-2596-4ff7-b5c5-405041473e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2943817184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2943817184
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2321786296
Short name T1511
Test name
Test status
Simulation time 23891400 ps
CPU time 0.63 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203196 kb
Host smart-56d669c9-d879-403f-878c-6e8b389a752f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321786296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2321786296
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3199379059
Short name T254
Test name
Test status
Simulation time 301146192 ps
CPU time 3.43 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203900 kb
Host smart-00319485-d4b7-4e32-ae18-dc9869522a6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3199379059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3199379059
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1564325125
Short name T1456
Test name
Test status
Simulation time 538931403 ps
CPU time 4.67 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 203940 kb
Host smart-0afdf917-3ac2-4c7f-897e-3cd199d8cec3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1564325125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1564325125
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4120335163
Short name T1454
Test name
Test status
Simulation time 30850399 ps
CPU time 0.78 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 203784 kb
Host smart-c479f932-8159-4694-9d1a-e8709e9f6508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4120335163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4120335163
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1754820115
Short name T1437
Test name
Test status
Simulation time 107621158 ps
CPU time 0.74 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 203176 kb
Host smart-b5136f76-cd70-41ad-9ecf-7742407cb049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1754820115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1754820115
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1433235216
Short name T255
Test name
Test status
Simulation time 110847647 ps
CPU time 1.44 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 212220 kb
Host smart-2f2ac522-484e-4ed6-9871-fbc9ade88200
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1433235216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1433235216
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1676495995
Short name T1496
Test name
Test status
Simulation time 106747602 ps
CPU time 2.31 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 203892 kb
Host smart-a7986bf9-50b1-4431-b265-ac324fad6728
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1676495995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1676495995
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1137053250
Short name T1461
Test name
Test status
Simulation time 67030421 ps
CPU time 1.09 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 204032 kb
Host smart-3af0d6d4-4826-4a87-810e-4dbab5ac760b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1137053250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1137053250
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3463657132
Short name T1506
Test name
Test status
Simulation time 76451895 ps
CPU time 1.93 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:30 PM PDT 24
Peak memory 203996 kb
Host smart-5e5a84f5-2912-4a24-a797-898cc4c424a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3463657132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3463657132
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3810359069
Short name T1470
Test name
Test status
Simulation time 439090963 ps
CPU time 2.96 seconds
Started May 09 02:50:23 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 204092 kb
Host smart-a51037a4-f493-43d5-be78-c864da82d7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3810359069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3810359069
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1615951000
Short name T1471
Test name
Test status
Simulation time 42738823 ps
CPU time 0.66 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203156 kb
Host smart-8e1b6513-c6dd-4325-8bee-7429636bef8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1615951000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1615951000
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3929890970
Short name T1491
Test name
Test status
Simulation time 22673228 ps
CPU time 0.65 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203180 kb
Host smart-f82c27b5-7739-4ddf-9c37-3ccf2998a46a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3929890970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3929890970
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2149679751
Short name T280
Test name
Test status
Simulation time 20749220 ps
CPU time 0.68 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203168 kb
Host smart-65e5d43f-f5dc-43b7-9140-245f6db7a804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149679751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2149679751
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2631517265
Short name T76
Test name
Test status
Simulation time 34119807 ps
CPU time 0.68 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203136 kb
Host smart-3214ac2e-c1ee-4c8e-8f69-35f3a632cc2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2631517265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2631517265
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1347046104
Short name T1475
Test name
Test status
Simulation time 28256394 ps
CPU time 0.63 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203188 kb
Host smart-c2a35748-8fc8-4573-8081-f305d972d32e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1347046104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1347046104
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3410790479
Short name T1446
Test name
Test status
Simulation time 38132866 ps
CPU time 0.64 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:50:57 PM PDT 24
Peak memory 203204 kb
Host smart-0ef0388e-cac4-4f4e-b1d6-8c23359b1503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3410790479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3410790479
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3134339636
Short name T276
Test name
Test status
Simulation time 31908219 ps
CPU time 0.64 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203196 kb
Host smart-8e8fc8cf-728a-4ec5-8685-f7487098c9e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3134339636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3134339636
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2826534024
Short name T1527
Test name
Test status
Simulation time 44899531 ps
CPU time 0.71 seconds
Started May 09 02:50:35 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203216 kb
Host smart-3f68486a-a45c-444e-8e65-971c9c25fafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2826534024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2826534024
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.582236622
Short name T282
Test name
Test status
Simulation time 35614704 ps
CPU time 0.65 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203160 kb
Host smart-4a79aab6-94d0-4d69-a31c-980b37a5b0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=582236622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.582236622
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3023374957
Short name T1524
Test name
Test status
Simulation time 68758031 ps
CPU time 1.97 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 203928 kb
Host smart-d502fc51-a629-4137-ac43-7474bcf4c3cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3023374957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3023374957
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.520472218
Short name T1438
Test name
Test status
Simulation time 2444908296 ps
CPU time 13.11 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 204020 kb
Host smart-cce8b73c-5dd2-4a4e-a02b-747b7b774ae7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=520472218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.520472218
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2918205590
Short name T1472
Test name
Test status
Simulation time 53103751 ps
CPU time 0.8 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 203704 kb
Host smart-ab6527cb-1f03-4492-92f7-70515342fa1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2918205590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2918205590
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1581353580
Short name T1458
Test name
Test status
Simulation time 82088966 ps
CPU time 1.19 seconds
Started May 09 02:50:29 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 212228 kb
Host smart-287d3880-0fab-45dc-b007-1cbd73f18213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581353580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1581353580
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3356683425
Short name T1529
Test name
Test status
Simulation time 51628871 ps
CPU time 0.81 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:46 PM PDT 24
Peak memory 203748 kb
Host smart-875f87ad-cfc2-494b-bdea-04fb72872dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3356683425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3356683425
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3952060861
Short name T1530
Test name
Test status
Simulation time 46936307 ps
CPU time 0.67 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 203264 kb
Host smart-c65a4ecd-a50e-4d28-9911-60411d9e4e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3952060861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3952060861
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2604817223
Short name T252
Test name
Test status
Simulation time 136869464 ps
CPU time 2.32 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 211576 kb
Host smart-9f6450ab-b492-45b3-bc5b-15a969f3a0c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2604817223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2604817223
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4086589605
Short name T1453
Test name
Test status
Simulation time 370638160 ps
CPU time 2.61 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 203960 kb
Host smart-8bb561c4-26f1-4a73-b868-4159c01a945b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4086589605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4086589605
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2706067957
Short name T1520
Test name
Test status
Simulation time 40590266 ps
CPU time 1.01 seconds
Started May 09 02:50:29 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 204024 kb
Host smart-14e22ea2-60d0-41ed-8e17-a45cdebd3cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2706067957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2706067957
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3625977509
Short name T1459
Test name
Test status
Simulation time 132271876 ps
CPU time 2.19 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 204020 kb
Host smart-8fedebc8-e3c6-486a-a8e0-f9e3daf9a05f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3625977509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3625977509
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4019187396
Short name T269
Test name
Test status
Simulation time 438741094 ps
CPU time 2.94 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 204016 kb
Host smart-de662915-41bc-413c-8bd6-adb1b2994329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4019187396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.4019187396
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2231792449
Short name T1455
Test name
Test status
Simulation time 48707903 ps
CPU time 0.69 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203256 kb
Host smart-a0e3e5a5-f37d-4374-8c50-b2933283c3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2231792449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2231792449
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3345652224
Short name T1474
Test name
Test status
Simulation time 36369713 ps
CPU time 0.68 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 203172 kb
Host smart-eb6d6190-2044-408d-98d5-6337b55cf8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3345652224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3345652224
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3376229243
Short name T1523
Test name
Test status
Simulation time 47674631 ps
CPU time 0.68 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203184 kb
Host smart-a0ae62bd-d263-40f0-b402-ea592967a95d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3376229243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3376229243
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2383889253
Short name T1485
Test name
Test status
Simulation time 43958950 ps
CPU time 0.7 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203256 kb
Host smart-41e459d7-07a6-4910-97bc-8914446de220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2383889253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2383889253
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2322779438
Short name T1476
Test name
Test status
Simulation time 35823859 ps
CPU time 0.69 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203284 kb
Host smart-3350b96c-be76-4a4b-a5fc-618aaeafb67e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2322779438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2322779438
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2157742927
Short name T1497
Test name
Test status
Simulation time 34279391 ps
CPU time 0.67 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:50:49 PM PDT 24
Peak memory 203220 kb
Host smart-3b4c879b-6b59-4f2e-81c4-dfdf3126279c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2157742927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2157742927
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3421357571
Short name T1489
Test name
Test status
Simulation time 23758125 ps
CPU time 0.62 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:50:57 PM PDT 24
Peak memory 203204 kb
Host smart-d3da1601-2fd1-4bc2-8545-edece2230bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3421357571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3421357571
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.617443409
Short name T77
Test name
Test status
Simulation time 52397898 ps
CPU time 0.67 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:47 PM PDT 24
Peak memory 203180 kb
Host smart-9b6748ba-63ce-477c-9076-22588fca49b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617443409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.617443409
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.762179454
Short name T274
Test name
Test status
Simulation time 26073550 ps
CPU time 0.7 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:50:50 PM PDT 24
Peak memory 203128 kb
Host smart-968d16c5-7da7-441c-94df-5681f9ffb735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=762179454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.762179454
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.869661029
Short name T1451
Test name
Test status
Simulation time 131660533 ps
CPU time 1.34 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 212196 kb
Host smart-282bdfe4-9e71-4091-8936-b7062a499776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869661029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.869661029
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.171453034
Short name T219
Test name
Test status
Simulation time 54638250 ps
CPU time 0.96 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 203992 kb
Host smart-8e37ae31-ccb1-457c-a572-6857ae22e876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=171453034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.171453034
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2743665682
Short name T1441
Test name
Test status
Simulation time 38985129 ps
CPU time 0.7 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 203204 kb
Host smart-7a9ad279-e68d-4fc6-9f78-762b42caf6b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2743665682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2743665682
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.500664651
Short name T266
Test name
Test status
Simulation time 134910479 ps
CPU time 1.59 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203984 kb
Host smart-b287d923-5b60-4a8e-886f-14539e51a5f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=500664651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.500664651
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.467610420
Short name T1448
Test name
Test status
Simulation time 135672001 ps
CPU time 1.84 seconds
Started May 09 02:50:22 PM PDT 24
Finished May 09 02:50:35 PM PDT 24
Peak memory 204008 kb
Host smart-14a9f521-0b0b-445c-8e06-1dad4d0f92f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=467610420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.467610420
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.541595223
Short name T1519
Test name
Test status
Simulation time 820301821 ps
CPU time 3.85 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 204084 kb
Host smart-6d9396a5-4739-409a-82d3-6f7716f1da56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=541595223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.541595223
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1769490680
Short name T234
Test name
Test status
Simulation time 152468108 ps
CPU time 1.7 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 215472 kb
Host smart-b043a1e4-f654-41af-882a-2686977f6a2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769490680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1769490680
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.221660490
Short name T251
Test name
Test status
Simulation time 43177458 ps
CPU time 0.89 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 203712 kb
Host smart-eb9b5f88-0c03-4d0a-89a0-98d931332d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=221660490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.221660490
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.743014469
Short name T283
Test name
Test status
Simulation time 58534899 ps
CPU time 0.69 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 203248 kb
Host smart-13d03f66-0efd-4bd1-9cc9-670955a00b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=743014469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.743014469
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2308820998
Short name T1504
Test name
Test status
Simulation time 299330246 ps
CPU time 2.19 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 204076 kb
Host smart-feada5f2-146d-446b-89cb-2655e5293cd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2308820998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2308820998
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2050162186
Short name T63
Test name
Test status
Simulation time 151857412 ps
CPU time 1.97 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 204024 kb
Host smart-501711b8-0ac5-4628-9c2f-5d8fef19c56c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2050162186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2050162186
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.306207237
Short name T289
Test name
Test status
Simulation time 302973399 ps
CPU time 2.87 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:39 PM PDT 24
Peak memory 204028 kb
Host smart-2c560c30-c4dd-4784-a225-c9d5b6094847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=306207237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.306207237
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3180525916
Short name T1502
Test name
Test status
Simulation time 92866588 ps
CPU time 1.25 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 212232 kb
Host smart-742de6ba-ccf3-44c1-8048-7e834deaf054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180525916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3180525916
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1611252946
Short name T253
Test name
Test status
Simulation time 56263896 ps
CPU time 0.82 seconds
Started May 09 02:50:27 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203636 kb
Host smart-5e400993-1231-4299-8337-fd490434c3b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1611252946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1611252946
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1851292105
Short name T1463
Test name
Test status
Simulation time 29462385 ps
CPU time 0.65 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 203108 kb
Host smart-518a90fd-73f1-4969-8c4f-ddf5b3955055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1851292105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1851292105
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3159592461
Short name T1442
Test name
Test status
Simulation time 138328721 ps
CPU time 1.56 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:45 PM PDT 24
Peak memory 204088 kb
Host smart-aa65c83f-ccdc-4347-aa28-c5f506608fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3159592461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3159592461
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3629006550
Short name T1473
Test name
Test status
Simulation time 360982276 ps
CPU time 4.12 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 204108 kb
Host smart-30582567-85bd-4c61-a32a-223e3f81ffcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3629006550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3629006550
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3288277903
Short name T238
Test name
Test status
Simulation time 138598539 ps
CPU time 1.96 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 216092 kb
Host smart-2b10231b-5b9d-445f-b548-20f6837a7a5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288277903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3288277903
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4074437647
Short name T1443
Test name
Test status
Simulation time 83342242 ps
CPU time 0.87 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:40 PM PDT 24
Peak memory 203704 kb
Host smart-7f69e709-b6bf-46c5-9a81-77e03a42cc8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4074437647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4074437647
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2136472321
Short name T277
Test name
Test status
Simulation time 28108198 ps
CPU time 0.68 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 202472 kb
Host smart-518a688b-d74b-496f-b314-422b8b0da650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2136472321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2136472321
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.140939494
Short name T1498
Test name
Test status
Simulation time 92453690 ps
CPU time 1.08 seconds
Started May 09 02:50:24 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 204040 kb
Host smart-c1ac1677-8537-404a-884f-bbe5c4e3f217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=140939494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.140939494
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1288183378
Short name T1450
Test name
Test status
Simulation time 52782365 ps
CPU time 1.51 seconds
Started May 09 02:50:25 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 204012 kb
Host smart-3088e785-cbb6-49b9-9dbe-22368bb807db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1288183378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1288183378
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3980700355
Short name T1492
Test name
Test status
Simulation time 299558225 ps
CPU time 2.82 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:42 PM PDT 24
Peak memory 204056 kb
Host smart-c9700331-575c-4ee6-8316-318095be1dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3980700355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3980700355
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2380140509
Short name T1444
Test name
Test status
Simulation time 50074276 ps
CPU time 1.31 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 212216 kb
Host smart-614643b4-68a9-48ec-bd5d-c5d86dd53d07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380140509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2380140509
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1012981118
Short name T1521
Test name
Test status
Simulation time 39922944 ps
CPU time 0.96 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 203972 kb
Host smart-5997e0b2-a174-4554-90d9-61a8a495b640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1012981118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1012981118
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3741054299
Short name T1500
Test name
Test status
Simulation time 38795498 ps
CPU time 0.66 seconds
Started May 09 02:50:26 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 203108 kb
Host smart-3b150564-9eeb-4d17-803e-e128e0cbf18c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3741054299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3741054299
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4150654639
Short name T218
Test name
Test status
Simulation time 90798909 ps
CPU time 1.17 seconds
Started May 09 02:50:28 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 204052 kb
Host smart-79a6c9e6-ee49-44b9-b75c-6cbfee67721a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4150654639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.4150654639
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.252664706
Short name T1508
Test name
Test status
Simulation time 196087714 ps
CPU time 2.45 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:50:48 PM PDT 24
Peak memory 203996 kb
Host smart-9cfae26a-d779-4808-99b7-01dba60dee47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=252664706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.252664706
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.33538548
Short name T347
Test name
Test status
Simulation time 8488878063 ps
CPU time 7.7 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:46:05 PM PDT 24
Peak memory 204516 kb
Host smart-efadf6e2-4b24-4b19-8c59-1cc5ca773378
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=33538548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.33538548
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.655906756
Short name T870
Test name
Test status
Simulation time 8372679406 ps
CPU time 7.43 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 204536 kb
Host smart-44b60591-cf9d-450d-a8cc-be80234176b7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=655906756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.655906756
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.438153574
Short name T890
Test name
Test status
Simulation time 8423769737 ps
CPU time 7.64 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 204524 kb
Host smart-0fdab2ee-4db4-490c-8d5f-7d38d3d517fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43815
3574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.438153574
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1020707682
Short name T1358
Test name
Test status
Simulation time 8384678234 ps
CPU time 7.97 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:45:41 PM PDT 24
Peak memory 204400 kb
Host smart-9388fe38-afae-4f39-b2ad-73afd9fd06d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
07682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1020707682
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.1356928503
Short name T993
Test name
Test status
Simulation time 8375594213 ps
CPU time 7.68 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:40 PM PDT 24
Peak memory 204568 kb
Host smart-28e23d35-931b-4960-9881-4d20e0e37b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13569
28503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1356928503
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2688162075
Short name T958
Test name
Test status
Simulation time 66642323 ps
CPU time 1.7 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:45:35 PM PDT 24
Peak memory 204764 kb
Host smart-bbe511c5-b1a7-4da1-8cd0-d2f1dc8020e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26881
62075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2688162075
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1183146405
Short name T760
Test name
Test status
Simulation time 8387033767 ps
CPU time 7.75 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 204508 kb
Host smart-e3d028c1-dbb3-43b5-867f-8794e32c7c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11831
46405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1183146405
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.645223273
Short name T831
Test name
Test status
Simulation time 8373989849 ps
CPU time 7.59 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 204520 kb
Host smart-f1dd2893-aef1-4ec0-8b8b-b762868e4724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64522
3273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.645223273
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.764172320
Short name T1279
Test name
Test status
Simulation time 8461161763 ps
CPU time 7.37 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:45:41 PM PDT 24
Peak memory 204604 kb
Host smart-c40e0fc3-d95a-47e4-9d5b-7617e56298d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76417
2320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.764172320
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1457291914
Short name T940
Test name
Test status
Simulation time 8459647690 ps
CPU time 7.72 seconds
Started May 09 02:45:28 PM PDT 24
Finished May 09 02:45:38 PM PDT 24
Peak memory 204568 kb
Host smart-59225364-4a7e-4411-825d-2999b30bd10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14572
91914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1457291914
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2324328618
Short name T767
Test name
Test status
Simulation time 8372950363 ps
CPU time 7.78 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:45:41 PM PDT 24
Peak memory 204516 kb
Host smart-dbb98687-13a7-4dc9-a013-71fccf9367da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23243
28618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2324328618
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3690192577
Short name T511
Test name
Test status
Simulation time 8414716302 ps
CPU time 9 seconds
Started May 09 02:45:32 PM PDT 24
Finished May 09 02:45:44 PM PDT 24
Peak memory 204588 kb
Host smart-da15a164-d204-4ebb-988d-a05d80f89f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36901
92577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3690192577
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.413135047
Short name T1357
Test name
Test status
Simulation time 8411600358 ps
CPU time 7.48 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:40 PM PDT 24
Peak memory 204624 kb
Host smart-5e662285-2236-4c4c-acb4-9e624472a7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41313
5047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.413135047
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3012155523
Short name T1324
Test name
Test status
Simulation time 8380028536 ps
CPU time 7.72 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:49 PM PDT 24
Peak memory 204568 kb
Host smart-4e9ebb49-64e3-4216-a71f-22a51a1c7c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
55523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3012155523
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3296936123
Short name T985
Test name
Test status
Simulation time 45079368 ps
CPU time 0.67 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:41 PM PDT 24
Peak memory 204512 kb
Host smart-391049a6-1991-437c-a21d-d613128ed800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
36123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3296936123
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.965912092
Short name T1409
Test name
Test status
Simulation time 16434025022 ps
CPU time 30.74 seconds
Started May 09 02:45:39 PM PDT 24
Finished May 09 02:46:12 PM PDT 24
Peak memory 204756 kb
Host smart-10b9512c-da9e-4e45-bd2d-a6a0babcd1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96591
2092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.965912092
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1480736206
Short name T967
Test name
Test status
Simulation time 8435205432 ps
CPU time 8.7 seconds
Started May 09 02:45:40 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 204588 kb
Host smart-32b02c34-b67b-478f-9fbd-877913ffd585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14807
36206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1480736206
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1477702731
Short name T222
Test name
Test status
Simulation time 8396345822 ps
CPU time 9.56 seconds
Started May 09 02:45:40 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 204528 kb
Host smart-f4175da6-af6a-4d22-845a-7cc776007314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
02731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1477702731
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3012590279
Short name T68
Test name
Test status
Simulation time 360261247 ps
CPU time 1.21 seconds
Started May 09 02:45:43 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 221944 kb
Host smart-9c7413c6-0cc8-4407-af20-3cb162ecdc09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3012590279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3012590279
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2401586004
Short name T1015
Test name
Test status
Simulation time 8409590623 ps
CPU time 8.78 seconds
Started May 09 02:45:39 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 204572 kb
Host smart-73f58933-6688-4c2d-b52e-0fbd22ab417f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
86004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2401586004
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3487617171
Short name T1112
Test name
Test status
Simulation time 8382231881 ps
CPU time 7.79 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 204576 kb
Host smart-7ca46258-ae73-4350-a2a5-3f67607cc07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34876
17171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3487617171
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3199983867
Short name T1284
Test name
Test status
Simulation time 8445622601 ps
CPU time 8.11 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:45:42 PM PDT 24
Peak memory 204512 kb
Host smart-7b6a1323-86d3-4933-a8da-d8258b216169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
83867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3199983867
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1885538063
Short name T1187
Test name
Test status
Simulation time 8407724840 ps
CPU time 8.16 seconds
Started May 09 02:45:43 PM PDT 24
Finished May 09 02:45:54 PM PDT 24
Peak memory 204576 kb
Host smart-b32bed1b-bbb9-42d5-ad52-f6f0808cad6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855
38063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1885538063
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.930898799
Short name T1149
Test name
Test status
Simulation time 8408493539 ps
CPU time 7.54 seconds
Started May 09 02:45:43 PM PDT 24
Finished May 09 02:45:54 PM PDT 24
Peak memory 204612 kb
Host smart-75d2c5be-b11c-4f2b-96de-9cf15cbdd7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93089
8799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.930898799
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3275489803
Short name T1177
Test name
Test status
Simulation time 8468540551 ps
CPU time 8.4 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204568 kb
Host smart-5e09cfd9-fe9b-4bda-84e3-6621ddf333e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3275489803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3275489803
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3190661008
Short name T1421
Test name
Test status
Simulation time 8380216436 ps
CPU time 7.64 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204460 kb
Host smart-3fe4a1d7-f0a2-4750-82d8-991fe7971a53
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3190661008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3190661008
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1087430599
Short name T1295
Test name
Test status
Simulation time 8461180190 ps
CPU time 7.36 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204548 kb
Host smart-64966fa7-ce19-4d9f-95ba-be6b14929c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
30599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1087430599
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.623204789
Short name T1256
Test name
Test status
Simulation time 8480258670 ps
CPU time 7.63 seconds
Started May 09 02:45:39 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 204400 kb
Host smart-00077c37-8a53-435a-810f-18d470483ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62320
4789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.623204789
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3467521723
Short name T554
Test name
Test status
Simulation time 8677493396 ps
CPU time 12.86 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:54 PM PDT 24
Peak memory 204808 kb
Host smart-5435f3d6-4693-4161-9186-e57ff004a603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675
21723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3467521723
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_enable.1084496278
Short name T516
Test name
Test status
Simulation time 8374354065 ps
CPU time 8.36 seconds
Started May 09 02:45:49 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204540 kb
Host smart-e26b1a7c-2a27-445a-bf45-b0baf6dd7fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10844
96278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1084496278
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1887254071
Short name T1379
Test name
Test status
Simulation time 43281886 ps
CPU time 1.19 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:45:59 PM PDT 24
Peak memory 204364 kb
Host smart-eb976e62-8685-4170-9128-d1aab8833bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18872
54071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1887254071
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2747811452
Short name T1037
Test name
Test status
Simulation time 8454926660 ps
CPU time 10.13 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:06 PM PDT 24
Peak memory 204560 kb
Host smart-a2f5d66c-9601-4046-be33-f8be2ede8570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27478
11452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2747811452
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3258635636
Short name T473
Test name
Test status
Simulation time 8379906622 ps
CPU time 8.23 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204628 kb
Host smart-69dce051-dcbf-4668-94ec-2ac590a21eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32586
35636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3258635636
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.4232815384
Short name T1070
Test name
Test status
Simulation time 8399267360 ps
CPU time 8.75 seconds
Started May 09 02:45:43 PM PDT 24
Finished May 09 02:45:55 PM PDT 24
Peak memory 204628 kb
Host smart-547ca04c-4198-4cb0-8e65-6a599a9802de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42328
15384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.4232815384
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1557117111
Short name T1355
Test name
Test status
Simulation time 8446557647 ps
CPU time 7.86 seconds
Started May 09 02:45:40 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 204528 kb
Host smart-8d7a31ee-1d09-46da-8565-c58624e26246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15571
17111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1557117111
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.974675197
Short name T340
Test name
Test status
Simulation time 8367769714 ps
CPU time 7.76 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 204608 kb
Host smart-4a74b357-0789-48cf-b3b0-3d35491ceee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97467
5197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.974675197
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2028743423
Short name T108
Test name
Test status
Simulation time 8437460758 ps
CPU time 7.75 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 204540 kb
Host smart-ccced878-b19c-47cb-abf8-da67677ea9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20287
43423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2028743423
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2458092022
Short name T947
Test name
Test status
Simulation time 8420046288 ps
CPU time 8.44 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:49 PM PDT 24
Peak memory 204512 kb
Host smart-35470579-2ce1-496c-82a5-427f9f2e1e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24580
92022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2458092022
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.905255088
Short name T1129
Test name
Test status
Simulation time 8393633201 ps
CPU time 7.8 seconds
Started May 09 02:45:40 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 204576 kb
Host smart-1c46ec2c-65aa-4cd3-b199-9192ef763ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90525
5088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.905255088
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1425456738
Short name T1006
Test name
Test status
Simulation time 8366825538 ps
CPU time 10.29 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:46:08 PM PDT 24
Peak memory 204248 kb
Host smart-4956d1c2-d925-4bb7-9671-70db3e7865f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
56738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1425456738
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1941294950
Short name T87
Test name
Test status
Simulation time 64299170 ps
CPU time 0.68 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:45:57 PM PDT 24
Peak memory 204512 kb
Host smart-927eae2f-2e70-4e7e-876e-5b01f15928eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19412
94950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1941294950
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3073073596
Short name T537
Test name
Test status
Simulation time 17986556599 ps
CPU time 32.85 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:29 PM PDT 24
Peak memory 204732 kb
Host smart-5e06b526-dcae-47ee-94af-5e19bcb6cf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30730
73596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3073073596
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2403552182
Short name T482
Test name
Test status
Simulation time 8385035833 ps
CPU time 7.98 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 204552 kb
Host smart-899ace51-e34e-4ae8-be40-eba17661da0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
52182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2403552182
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.2799012145
Short name T793
Test name
Test status
Simulation time 8403705955 ps
CPU time 7.71 seconds
Started May 09 02:45:40 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 204392 kb
Host smart-dc5d1a43-9a96-4f1e-bfe7-8ae2c3423f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27990
12145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.2799012145
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.291166774
Short name T1214
Test name
Test status
Simulation time 8370830018 ps
CPU time 8.28 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204512 kb
Host smart-47a401a3-152b-402f-98bd-3c5cc6d5a932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29116
6774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.291166774
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3173755170
Short name T1178
Test name
Test status
Simulation time 8372810875 ps
CPU time 8.21 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:05 PM PDT 24
Peak memory 204524 kb
Host smart-2d8bf55e-ef1f-4d35-a9ad-e3e187c89aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
55170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3173755170
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3570608793
Short name T1260
Test name
Test status
Simulation time 8432080109 ps
CPU time 8.1 seconds
Started May 09 02:45:41 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 204556 kb
Host smart-fda8e075-8a78-4dbb-8d21-95f64cc55952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35706
08793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3570608793
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1631147767
Short name T898
Test name
Test status
Simulation time 8414270520 ps
CPU time 7.68 seconds
Started May 09 02:45:38 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 204568 kb
Host smart-a8240b42-234f-4e8d-a205-2495fc88879a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311
47767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1631147767
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.267004700
Short name T1162
Test name
Test status
Simulation time 8515815411 ps
CPU time 7.88 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204580 kb
Host smart-7d47a481-f0ba-4e6d-a72c-5e41bdb8b27a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=267004700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.267004700
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.1060130037
Short name T970
Test name
Test status
Simulation time 8451089127 ps
CPU time 9.99 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:07 PM PDT 24
Peak memory 204548 kb
Host smart-c6e6ea3e-f986-44c4-b292-2a18914e0390
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1060130037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.1060130037
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.3875910358
Short name T1273
Test name
Test status
Simulation time 8397301112 ps
CPU time 10.1 seconds
Started May 09 02:46:47 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204620 kb
Host smart-8d53f635-e01a-40f6-b35b-b900095a7ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38759
10358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.3875910358
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.353487002
Short name T1245
Test name
Test status
Simulation time 8398386123 ps
CPU time 7.59 seconds
Started May 09 02:46:47 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204564 kb
Host smart-604ae144-818a-4564-8f8a-d6a1c24b7d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35348
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.353487002
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2179058885
Short name T543
Test name
Test status
Simulation time 8495537699 ps
CPU time 12.17 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204800 kb
Host smart-81007cb1-03b7-4a0c-ba20-b326b3bd9431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21790
58885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2179058885
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_enable.2850757763
Short name T448
Test name
Test status
Simulation time 8380280692 ps
CPU time 8.94 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204552 kb
Host smart-c2db0787-36c9-4d6a-9837-aa7807a34ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28507
57763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2850757763
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1755462826
Short name T360
Test name
Test status
Simulation time 72702620 ps
CPU time 1.21 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:46:56 PM PDT 24
Peak memory 204748 kb
Host smart-cf9a43b4-788b-470c-8841-4771830547ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17554
62826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1755462826
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.616757163
Short name T154
Test name
Test status
Simulation time 8450809393 ps
CPU time 8.64 seconds
Started May 09 02:46:54 PM PDT 24
Finished May 09 02:47:07 PM PDT 24
Peak memory 204592 kb
Host smart-fa5b2457-50fc-44cc-8ce6-98743a55e694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61675
7163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.616757163
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3244261429
Short name T1007
Test name
Test status
Simulation time 8424021808 ps
CPU time 8.09 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204512 kb
Host smart-babe2726-0491-428f-9e89-e4257d93f7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32442
61429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3244261429
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2069758819
Short name T421
Test name
Test status
Simulation time 8372887974 ps
CPU time 7.63 seconds
Started May 09 02:46:46 PM PDT 24
Finished May 09 02:46:57 PM PDT 24
Peak memory 204528 kb
Host smart-f4591ba4-06ec-4106-9a31-698db68627d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20697
58819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2069758819
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2378805745
Short name T380
Test name
Test status
Simulation time 8435525920 ps
CPU time 8.07 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204456 kb
Host smart-3ba0119e-585d-416d-b521-fbcf0abad5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23788
05745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2378805745
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2333921480
Short name T1046
Test name
Test status
Simulation time 8400885928 ps
CPU time 7.83 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204608 kb
Host smart-1acbc015-4c7a-43f4-a1eb-ff621d4621c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23339
21480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2333921480
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.862509649
Short name T579
Test name
Test status
Simulation time 8390737769 ps
CPU time 7.46 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:02 PM PDT 24
Peak memory 204544 kb
Host smart-aae0d467-ab0c-46dc-a223-55c3f3d6db78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86250
9649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.862509649
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1016869877
Short name T1127
Test name
Test status
Simulation time 36276572 ps
CPU time 0.68 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:46:57 PM PDT 24
Peak memory 204524 kb
Host smart-9ebb7e33-b620-439b-8a3c-ea8d7793250c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10168
69877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1016869877
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2403564583
Short name T917
Test name
Test status
Simulation time 28758317546 ps
CPU time 55 seconds
Started May 09 02:46:54 PM PDT 24
Finished May 09 02:47:53 PM PDT 24
Peak memory 204820 kb
Host smart-1cca0ab3-efb2-4f6e-b961-0085d571b965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
64583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2403564583
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.646408088
Short name T423
Test name
Test status
Simulation time 8371014316 ps
CPU time 7.98 seconds
Started May 09 02:46:46 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204608 kb
Host smart-c61c261a-0709-4b31-bcb4-b786e00f6875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64640
8088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.646408088
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3747068657
Short name T1231
Test name
Test status
Simulation time 8396964261 ps
CPU time 7.58 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:02 PM PDT 24
Peak memory 204464 kb
Host smart-15e2181d-b331-4030-b75b-053fe46059c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37470
68657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3747068657
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3651284206
Short name T1118
Test name
Test status
Simulation time 8408960449 ps
CPU time 7.95 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204568 kb
Host smart-47d22368-7058-4d2e-9f45-142856d3c21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
84206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3651284206
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2223866697
Short name T1263
Test name
Test status
Simulation time 8378028674 ps
CPU time 7.7 seconds
Started May 09 02:46:53 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204532 kb
Host smart-34785405-f121-45c6-a449-c1413657ad70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
66697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2223866697
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3325694584
Short name T1061
Test name
Test status
Simulation time 8372656182 ps
CPU time 7.68 seconds
Started May 09 02:46:47 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204500 kb
Host smart-9313e5fe-646f-41ee-bec4-98d32a79440b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33256
94584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3325694584
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3998280638
Short name T310
Test name
Test status
Simulation time 8373028432 ps
CPU time 8.24 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204516 kb
Host smart-53dd4c5f-d615-47d1-8cd9-815e09f8c60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39982
80638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3998280638
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3934722908
Short name T1163
Test name
Test status
Simulation time 8445558323 ps
CPU time 7.42 seconds
Started May 09 02:46:53 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204572 kb
Host smart-138729fa-efe3-4564-b007-c17c948fe5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39347
22908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3934722908
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3535141285
Short name T1160
Test name
Test status
Simulation time 8475392668 ps
CPU time 8.84 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:11 PM PDT 24
Peak memory 204552 kb
Host smart-9a7d1235-3d43-4bc4-9837-6cda000d427b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3535141285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3535141285
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1645161635
Short name T1157
Test name
Test status
Simulation time 8398474758 ps
CPU time 8.4 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204536 kb
Host smart-f29e3c25-ca9c-4b75-a8f6-4f281f829ff4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1645161635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1645161635
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.2661640071
Short name T941
Test name
Test status
Simulation time 8508663417 ps
CPU time 9.01 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204540 kb
Host smart-e994c4f2-3aee-4c66-a0c2-bfe1a538e499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26616
40071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.2661640071
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3830808273
Short name T1290
Test name
Test status
Simulation time 8372542955 ps
CPU time 7.39 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204568 kb
Host smart-107ea0b7-5601-4731-8607-3cd4ee9364e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
08273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3830808273
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.716646214
Short name T229
Test name
Test status
Simulation time 147193361 ps
CPU time 1.38 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204656 kb
Host smart-c5ef85f2-5fb9-4f51-97f9-b281aa27ad06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71664
6214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.716646214
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2470578966
Short name T918
Test name
Test status
Simulation time 8381578317 ps
CPU time 7.88 seconds
Started May 09 02:46:56 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204524 kb
Host smart-61c7a0d3-0105-4d8b-bcda-c79559aa6217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24705
78966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2470578966
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3740021876
Short name T1151
Test name
Test status
Simulation time 8366461237 ps
CPU time 8.09 seconds
Started May 09 02:46:56 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204824 kb
Host smart-405fa4ef-2005-45ed-8542-9d48b77755d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37400
21876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3740021876
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4265574204
Short name T545
Test name
Test status
Simulation time 8424659271 ps
CPU time 7.84 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204604 kb
Host smart-e26e0b10-a135-4df2-b593-8c72ab4c2127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
74204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4265574204
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2553864431
Short name T1182
Test name
Test status
Simulation time 8398186514 ps
CPU time 7.74 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204596 kb
Host smart-f030f61f-1bf2-41af-8caa-2850bf2edda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25538
64431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2553864431
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3116971695
Short name T428
Test name
Test status
Simulation time 8376601517 ps
CPU time 7.85 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204588 kb
Host smart-72085c93-0e44-4408-aab0-30629165c245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
71695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3116971695
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1242746144
Short name T678
Test name
Test status
Simulation time 8435328865 ps
CPU time 8.29 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204596 kb
Host smart-ae0e42c2-b0c9-4b59-bcba-8145a9717312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427
46144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1242746144
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2569704334
Short name T1361
Test name
Test status
Simulation time 8392580525 ps
CPU time 7.93 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204508 kb
Host smart-8d54aeb7-f4fe-4b42-acde-b8b0266ff4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25697
04334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2569704334
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.844369501
Short name T517
Test name
Test status
Simulation time 8381956669 ps
CPU time 8.18 seconds
Started May 09 02:46:56 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204592 kb
Host smart-5745252b-9b6e-47c8-ac93-03cf8739b344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84436
9501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.844369501
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3974198486
Short name T1410
Test name
Test status
Simulation time 49714220 ps
CPU time 0.69 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:12 PM PDT 24
Peak memory 204492 kb
Host smart-908cfa2c-1593-45a3-8998-759c08219165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39741
98486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3974198486
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1081388893
Short name T268
Test name
Test status
Simulation time 18860500391 ps
CPU time 33.18 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:28 PM PDT 24
Peak memory 204748 kb
Host smart-06a21f48-2c30-421c-a781-2f47f9411aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10813
88893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1081388893
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.4116413965
Short name T1319
Test name
Test status
Simulation time 8385274017 ps
CPU time 7.72 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:02 PM PDT 24
Peak memory 204596 kb
Host smart-71543bf4-b133-447f-8715-292f13f157c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
13965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.4116413965
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3584013343
Short name T436
Test name
Test status
Simulation time 8467257837 ps
CPU time 8.5 seconds
Started May 09 02:46:56 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 204556 kb
Host smart-65f58867-b284-49d4-aad0-48219aee199f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35840
13343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3584013343
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1987255063
Short name T727
Test name
Test status
Simulation time 8382474606 ps
CPU time 8.18 seconds
Started May 09 02:46:55 PM PDT 24
Finished May 09 02:47:07 PM PDT 24
Peak memory 204612 kb
Host smart-cdda8a43-72f9-4260-84eb-d013b45f8291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19872
55063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1987255063
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2310459554
Short name T638
Test name
Test status
Simulation time 8374798413 ps
CPU time 7.67 seconds
Started May 09 02:46:56 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204820 kb
Host smart-a9cfaa3d-a4d2-469c-826d-590c35787e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23104
59554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2310459554
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2159836274
Short name T1289
Test name
Test status
Simulation time 8368018282 ps
CPU time 7.39 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204540 kb
Host smart-71241ec8-7e84-4b88-9d08-dd7c13b77975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21598
36274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2159836274
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3432630096
Short name T182
Test name
Test status
Simulation time 8555217007 ps
CPU time 9.25 seconds
Started May 09 02:46:53 PM PDT 24
Finished May 09 02:47:06 PM PDT 24
Peak memory 204588 kb
Host smart-d7e9e16f-91aa-443e-bf8f-52c0f0d6ac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326
30096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3432630096
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1296590006
Short name T702
Test name
Test status
Simulation time 8407201021 ps
CPU time 7.88 seconds
Started May 09 02:46:59 PM PDT 24
Finished May 09 02:47:11 PM PDT 24
Peak memory 204600 kb
Host smart-be64b2cd-d5d5-4b6e-91d3-0a4c60ab64cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12965
90006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1296590006
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.522627637
Short name T1080
Test name
Test status
Simulation time 8378160678 ps
CPU time 7.62 seconds
Started May 09 02:46:59 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204556 kb
Host smart-efba915c-c30b-45a5-b287-7202c766f7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52262
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.522627637
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.4289746654
Short name T453
Test name
Test status
Simulation time 8467703688 ps
CPU time 7.83 seconds
Started May 09 02:47:04 PM PDT 24
Finished May 09 02:47:16 PM PDT 24
Peak memory 204516 kb
Host smart-ba03235d-a16c-4ef4-a0fc-61b1a1dc3233
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4289746654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.4289746654
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.1423758241
Short name T1027
Test name
Test status
Simulation time 8386642563 ps
CPU time 9.58 seconds
Started May 09 02:47:05 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204568 kb
Host smart-868b4c22-eadd-45e7-bc11-2146c5242550
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1423758241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.1423758241
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.381211431
Short name T480
Test name
Test status
Simulation time 8484461642 ps
CPU time 8.02 seconds
Started May 09 02:47:04 PM PDT 24
Finished May 09 02:47:16 PM PDT 24
Peak memory 204560 kb
Host smart-3014216a-b2b2-424a-a854-3eb978a8538a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38121
1431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.381211431
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3455745843
Short name T318
Test name
Test status
Simulation time 8370802902 ps
CPU time 9.8 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 204576 kb
Host smart-eb1de725-44da-49e5-8872-1f14ad4cb6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34557
45843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3455745843
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3098771574
Short name T704
Test name
Test status
Simulation time 8468849485 ps
CPU time 11.46 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204736 kb
Host smart-e9c199c8-e451-4280-a480-38dd2771f747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
71574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3098771574
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_enable.997782689
Short name T547
Test name
Test status
Simulation time 8379746387 ps
CPU time 7.88 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204604 kb
Host smart-ff45679c-fb48-4f56-88e3-fd821a340a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99778
2689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.997782689
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3458750304
Short name T693
Test name
Test status
Simulation time 97919695 ps
CPU time 1.13 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:08 PM PDT 24
Peak memory 204664 kb
Host smart-dc49baae-67dd-45d5-a53d-e823257c2637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34587
50304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3458750304
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3984727223
Short name T193
Test name
Test status
Simulation time 8367756535 ps
CPU time 8.19 seconds
Started May 09 02:47:00 PM PDT 24
Finished May 09 02:47:12 PM PDT 24
Peak memory 204504 kb
Host smart-a6dc4d56-2971-4adc-9b54-d838628bd42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39847
27223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3984727223
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.4039376407
Short name T1010
Test name
Test status
Simulation time 8433904120 ps
CPU time 9.92 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:11 PM PDT 24
Peak memory 204536 kb
Host smart-32e5aeaa-d5c0-48db-8986-13868fbda6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40393
76407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.4039376407
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.615252270
Short name T1388
Test name
Test status
Simulation time 8421066400 ps
CPU time 9.05 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 204556 kb
Host smart-6e389e18-197e-40d0-92b1-3d1b893a025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61525
2270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.615252270
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.463004310
Short name T871
Test name
Test status
Simulation time 8372445834 ps
CPU time 8.06 seconds
Started May 09 02:47:00 PM PDT 24
Finished May 09 02:47:12 PM PDT 24
Peak memory 204608 kb
Host smart-0f55c411-911e-4c8f-b023-b6e703d2b5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46300
4310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.463004310
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2086590366
Short name T986
Test name
Test status
Simulation time 8399622311 ps
CPU time 7.5 seconds
Started May 09 02:47:01 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204588 kb
Host smart-57ef8434-e5b0-4f37-b239-2fd6b16a3670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20865
90366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2086590366
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2935010182
Short name T1168
Test name
Test status
Simulation time 8392014857 ps
CPU time 8.04 seconds
Started May 09 02:47:00 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204608 kb
Host smart-b441f96e-19cc-4989-b2e7-dcd73ef65092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29350
10182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2935010182
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3266915995
Short name T508
Test name
Test status
Simulation time 43642374 ps
CPU time 0.66 seconds
Started May 09 02:47:00 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204460 kb
Host smart-1939390e-9349-4214-b743-efb53143563a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32669
15995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3266915995
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2727663725
Short name T896
Test name
Test status
Simulation time 25808586673 ps
CPU time 55.82 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:57 PM PDT 24
Peak memory 204752 kb
Host smart-581a0259-870b-462d-96c0-e9073d0a3956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
63725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2727663725
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.226799924
Short name T706
Test name
Test status
Simulation time 8408183961 ps
CPU time 7.64 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 204528 kb
Host smart-36bac958-0014-49be-83e1-50fa24dcfa74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22679
9924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.226799924
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3373642697
Short name T135
Test name
Test status
Simulation time 8464004609 ps
CPU time 9.08 seconds
Started May 09 02:47:00 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204604 kb
Host smart-5bcfba28-063b-448f-94e1-fdc86eeb77ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33736
42697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3373642697
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2450677759
Short name T443
Test name
Test status
Simulation time 8438534187 ps
CPU time 7.61 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204576 kb
Host smart-d130c53b-5b14-4fc1-9f49-4e64cf97184a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24506
77759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2450677759
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2813377441
Short name T1119
Test name
Test status
Simulation time 8380093760 ps
CPU time 7.73 seconds
Started May 09 02:46:55 PM PDT 24
Finished May 09 02:47:07 PM PDT 24
Peak memory 204544 kb
Host smart-873dc488-486f-4d7b-a13d-f0d09fef3c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28133
77441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2813377441
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.601947755
Short name T1024
Test name
Test status
Simulation time 8383235072 ps
CPU time 7.77 seconds
Started May 09 02:47:00 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204584 kb
Host smart-a9963cef-2308-429b-ac69-cece04b75708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60194
7755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.601947755
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2902811215
Short name T674
Test name
Test status
Simulation time 8428019485 ps
CPU time 9.99 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 204524 kb
Host smart-cc88aa07-5a39-4045-bccb-db518028dce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29028
11215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2902811215
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1331939494
Short name T241
Test name
Test status
Simulation time 8399245112 ps
CPU time 9.38 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 204556 kb
Host smart-5cdba870-b5e7-49ae-b620-231ebc90f915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
39494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1331939494
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.1949247885
Short name T803
Test name
Test status
Simulation time 8461229778 ps
CPU time 7.77 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204516 kb
Host smart-e6168e60-5b02-430b-8683-d57ceadff3a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1949247885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.1949247885
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.834061092
Short name T652
Test name
Test status
Simulation time 8398695004 ps
CPU time 7.9 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204596 kb
Host smart-daf24320-be1a-4170-b4df-aac51d4fb646
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=834061092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.834061092
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2050291110
Short name T602
Test name
Test status
Simulation time 8415261627 ps
CPU time 7.64 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204508 kb
Host smart-5cedeedf-4134-4415-a547-8d3708887157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20502
91110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2050291110
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3208184052
Short name T820
Test name
Test status
Simulation time 8397571253 ps
CPU time 7.73 seconds
Started May 09 02:47:07 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204576 kb
Host smart-2d73ac8b-3d64-4355-b348-277763123f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32081
84052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3208184052
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3403758965
Short name T1036
Test name
Test status
Simulation time 8900142741 ps
CPU time 13.39 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:15 PM PDT 24
Peak memory 204804 kb
Host smart-b43db062-e972-4731-ba23-d0def210135a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
58965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3403758965
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_enable.3587680011
Short name T1193
Test name
Test status
Simulation time 8369740911 ps
CPU time 7.28 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204400 kb
Host smart-08645a79-5232-4c66-bb4b-55208c2e68dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35876
80011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3587680011
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.969716086
Short name T911
Test name
Test status
Simulation time 81266776 ps
CPU time 2 seconds
Started May 09 02:46:56 PM PDT 24
Finished May 09 02:47:02 PM PDT 24
Peak memory 204700 kb
Host smart-56364c96-3f81-471b-aecb-001764bf2d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96971
6086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.969716086
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1388784859
Short name T351
Test name
Test status
Simulation time 8445930379 ps
CPU time 7.86 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204524 kb
Host smart-f4dfd0a5-47b2-4778-88f7-d6abcb8093c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13887
84859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1388784859
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4264334836
Short name T1090
Test name
Test status
Simulation time 8398956528 ps
CPU time 7.66 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 204552 kb
Host smart-2ab6af5b-0f76-4dee-ae26-c2b834e1406c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42643
34836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4264334836
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2106147284
Short name T1371
Test name
Test status
Simulation time 8443159458 ps
CPU time 8.09 seconds
Started May 09 02:46:57 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 204540 kb
Host smart-b6513fec-2691-4b29-8b0b-6e9b7da80644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21061
47284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2106147284
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1419143854
Short name T1108
Test name
Test status
Simulation time 8404684238 ps
CPU time 9.42 seconds
Started May 09 02:47:01 PM PDT 24
Finished May 09 02:47:15 PM PDT 24
Peak memory 204388 kb
Host smart-49c9c75e-d434-4fc8-8efc-dc8c0bccaaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191
43854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1419143854
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1634561344
Short name T1320
Test name
Test status
Simulation time 8413062355 ps
CPU time 7.62 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204512 kb
Host smart-e1586f32-fd72-43e8-b2e5-07f4797c55dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16345
61344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1634561344
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1436624024
Short name T1328
Test name
Test status
Simulation time 8388716635 ps
CPU time 7.57 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204488 kb
Host smart-d7672f50-f3d1-46b2-b243-c2b297fa22f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14366
24024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1436624024
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3177718467
Short name T1173
Test name
Test status
Simulation time 8419816829 ps
CPU time 7.93 seconds
Started May 09 02:47:02 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 204564 kb
Host smart-b79cac91-8a1d-4c13-9b4c-e8db931eb89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777
18467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3177718467
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1990542637
Short name T1376
Test name
Test status
Simulation time 8372323101 ps
CPU time 9.11 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204532 kb
Host smart-72156835-7077-4f63-a7bb-2527425b3552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19905
42637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1990542637
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2376587622
Short name T782
Test name
Test status
Simulation time 116858556 ps
CPU time 0.7 seconds
Started May 09 02:47:07 PM PDT 24
Finished May 09 02:47:11 PM PDT 24
Peak memory 204448 kb
Host smart-e701532d-ef32-46ed-854d-419d08d4f5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23765
87622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2376587622
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2503234701
Short name T841
Test name
Test status
Simulation time 18426737632 ps
CPU time 30.41 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204728 kb
Host smart-2653e2fb-6846-4dd2-94c1-5af58ed9897d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25032
34701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2503234701
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.342750422
Short name T698
Test name
Test status
Simulation time 8422021542 ps
CPU time 7.77 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:10 PM PDT 24
Peak memory 204604 kb
Host smart-4b1360be-5a46-4588-9f65-60bd23900680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
0422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.342750422
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1073695451
Short name T1258
Test name
Test status
Simulation time 8414905584 ps
CPU time 8.95 seconds
Started May 09 02:47:07 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204528 kb
Host smart-df036ce4-2212-451e-95d1-78f5b092a838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10736
95451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1073695451
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.787680528
Short name T662
Test name
Test status
Simulation time 8385164787 ps
CPU time 8.09 seconds
Started May 09 02:46:59 PM PDT 24
Finished May 09 02:47:11 PM PDT 24
Peak memory 204616 kb
Host smart-be16dba8-6b38-4f37-9c60-0721d6874d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78768
0528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.787680528
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1319490253
Short name T568
Test name
Test status
Simulation time 8374426760 ps
CPU time 7.35 seconds
Started May 09 02:47:01 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204600 kb
Host smart-5718a214-094c-46d8-b427-7cb9a9995f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13194
90253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1319490253
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3020973820
Short name T325
Test name
Test status
Simulation time 8366149589 ps
CPU time 10.29 seconds
Started May 09 02:46:58 PM PDT 24
Finished May 09 02:47:12 PM PDT 24
Peak memory 204500 kb
Host smart-41b2171d-7b8f-4a2f-a007-1bb0fc16a73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30209
73820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3020973820
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3903621705
Short name T153
Test name
Test status
Simulation time 8454858191 ps
CPU time 7.81 seconds
Started May 09 02:47:04 PM PDT 24
Finished May 09 02:47:16 PM PDT 24
Peak memory 204540 kb
Host smart-289c7cb0-aac8-470d-b519-d48276ac6c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39036
21705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3903621705
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3113873720
Short name T397
Test name
Test status
Simulation time 8385282617 ps
CPU time 8.35 seconds
Started May 09 02:47:03 PM PDT 24
Finished May 09 02:47:15 PM PDT 24
Peak memory 204384 kb
Host smart-f256ab94-6397-4cef-918b-ed8e67432ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
73720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3113873720
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2088090763
Short name T311
Test name
Test status
Simulation time 8401196052 ps
CPU time 8.09 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204524 kb
Host smart-b35f4c9b-bfee-4b73-8fba-35db229451ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
90763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2088090763
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.4156815022
Short name T639
Test name
Test status
Simulation time 8498672350 ps
CPU time 8.14 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204548 kb
Host smart-9e450a24-1918-4249-9bcc-7fa08f9bb23d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4156815022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.4156815022
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.3936055598
Short name T515
Test name
Test status
Simulation time 8381664791 ps
CPU time 7.49 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:17 PM PDT 24
Peak memory 204572 kb
Host smart-7d2699f7-770f-45a5-8b53-39ef8cd370b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3936055598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.3936055598
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.247956878
Short name T607
Test name
Test status
Simulation time 8432894738 ps
CPU time 9.69 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 204528 kb
Host smart-842e72a7-4149-49bf-9fbd-afc5ef42f12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.247956878
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3531683282
Short name T84
Test name
Test status
Simulation time 8381624494 ps
CPU time 7.57 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204580 kb
Host smart-23284f9f-c88f-4ff3-a73a-19c4129717e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35316
83282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3531683282
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.885404217
Short name T541
Test name
Test status
Simulation time 8382159719 ps
CPU time 7.48 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204520 kb
Host smart-f4bd4d2e-3fa2-4aad-91b8-0b4e68bc5fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88540
4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.885404217
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1578689573
Short name T641
Test name
Test status
Simulation time 86768670 ps
CPU time 1.09 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:15 PM PDT 24
Peak memory 204624 kb
Host smart-75cdfecf-14c0-41b6-952a-0eb8341ef8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786
89573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1578689573
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1914112169
Short name T1154
Test name
Test status
Simulation time 8521670813 ps
CPU time 9.34 seconds
Started May 09 02:47:05 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204532 kb
Host smart-91467f18-707f-440b-968f-5a89f0f4f144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19141
12169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1914112169
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2515736836
Short name T605
Test name
Test status
Simulation time 8424832831 ps
CPU time 8.84 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204456 kb
Host smart-418503da-d7ce-4000-8d40-0c744a2ab678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25157
36836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2515736836
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.515602952
Short name T805
Test name
Test status
Simulation time 8417211378 ps
CPU time 8.87 seconds
Started May 09 02:47:10 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 204596 kb
Host smart-dc3125a9-6da1-4bd8-a571-32a9130d9f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51560
2952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.515602952
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1471566877
Short name T705
Test name
Test status
Simulation time 8375500450 ps
CPU time 7.64 seconds
Started May 09 02:47:10 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204580 kb
Host smart-14aa73ad-ed16-4293-a7d0-c517ce10c26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
66877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1471566877
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3646376803
Short name T920
Test name
Test status
Simulation time 8451699142 ps
CPU time 8.42 seconds
Started May 09 02:47:07 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204580 kb
Host smart-a269f6ae-082d-4c01-81af-90d0bb82bd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36463
76803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3646376803
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.773929415
Short name T1342
Test name
Test status
Simulation time 8392869059 ps
CPU time 8.31 seconds
Started May 09 02:47:05 PM PDT 24
Finished May 09 02:47:17 PM PDT 24
Peak memory 204548 kb
Host smart-0357b729-c230-4d36-b359-e598d0329629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77392
9415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.773929415
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.965475281
Short name T394
Test name
Test status
Simulation time 8399103253 ps
CPU time 8.56 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204556 kb
Host smart-013f84ce-eadc-4e20-8371-612f8ac8a0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96547
5281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.965475281
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3384995459
Short name T587
Test name
Test status
Simulation time 8371143056 ps
CPU time 7.65 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 203992 kb
Host smart-256c460c-ee4d-4421-943f-d3c358397865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
95459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3384995459
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.4066319585
Short name T387
Test name
Test status
Simulation time 56435545 ps
CPU time 0.65 seconds
Started May 09 02:47:14 PM PDT 24
Finished May 09 02:47:17 PM PDT 24
Peak memory 204448 kb
Host smart-490d53e3-3fa0-437d-9652-a2e50dc508a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663
19585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.4066319585
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.594483966
Short name T1329
Test name
Test status
Simulation time 8394027597 ps
CPU time 7.47 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:19 PM PDT 24
Peak memory 204604 kb
Host smart-d56a905d-fc1a-4fa5-8ed4-aea42c9ad885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59448
3966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.594483966
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.157098318
Short name T747
Test name
Test status
Simulation time 8421066142 ps
CPU time 8.18 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204540 kb
Host smart-d0800365-5d30-4965-be01-492727fe82f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15709
8318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.157098318
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.295220415
Short name T804
Test name
Test status
Simulation time 8415674060 ps
CPU time 8.23 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204552 kb
Host smart-1051f677-bf80-48a7-b88f-4ede1be09f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29522
0415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.295220415
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3102394198
Short name T505
Test name
Test status
Simulation time 8403467409 ps
CPU time 7.88 seconds
Started May 09 02:47:07 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204384 kb
Host smart-c11271ab-b87b-499e-a1c4-766f6ed929ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31023
94198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3102394198
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3079906515
Short name T303
Test name
Test status
Simulation time 8368886112 ps
CPU time 7.99 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:23 PM PDT 24
Peak memory 204532 kb
Host smart-be91ea2f-d379-4601-9de0-b893800bf1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30799
06515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3079906515
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2374352517
Short name T1303
Test name
Test status
Simulation time 8404911956 ps
CPU time 8.2 seconds
Started May 09 02:47:10 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 204576 kb
Host smart-62236edb-5979-44cf-99c8-a36fa37bb7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
52517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2374352517
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3618773918
Short name T800
Test name
Test status
Simulation time 8371100348 ps
CPU time 7.99 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204588 kb
Host smart-f994946a-a1b2-471c-b4ab-1403d94ed8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36187
73918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3618773918
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3729460711
Short name T761
Test name
Test status
Simulation time 8397676542 ps
CPU time 7.92 seconds
Started May 09 02:47:06 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204556 kb
Host smart-059f3366-562b-472c-89f9-4cef12be7a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37294
60711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3729460711
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.29443081
Short name T850
Test name
Test status
Simulation time 8466129345 ps
CPU time 7.64 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204512 kb
Host smart-2d69a956-c082-4ee4-9fcd-31533ae278dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=29443081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.29443081
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.3523188830
Short name T657
Test name
Test status
Simulation time 8378744761 ps
CPU time 9.86 seconds
Started May 09 02:47:20 PM PDT 24
Finished May 09 02:47:32 PM PDT 24
Peak memory 204532 kb
Host smart-2b7d2a8a-1782-4b7b-a862-e45599b3d7bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3523188830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.3523188830
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2847130165
Short name T362
Test name
Test status
Simulation time 8404804558 ps
CPU time 7.9 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204536 kb
Host smart-5bbd04bf-5ee3-4460-8cde-95018a713ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28471
30165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2847130165
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2979551899
Short name T1386
Test name
Test status
Simulation time 8400647989 ps
CPU time 9.11 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:30 PM PDT 24
Peak memory 204576 kb
Host smart-25006274-abcc-420a-a8d2-c908581b0a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
51899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2979551899
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1115195552
Short name T1408
Test name
Test status
Simulation time 8888678521 ps
CPU time 13.31 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:27 PM PDT 24
Peak memory 204820 kb
Host smart-bd847873-0f7b-4294-a43a-33ee30ce0c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11151
95552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1115195552
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_enable.1052636877
Short name T950
Test name
Test status
Simulation time 8391747534 ps
CPU time 8.56 seconds
Started May 09 02:47:12 PM PDT 24
Finished May 09 02:47:23 PM PDT 24
Peak memory 204576 kb
Host smart-6c164f5d-cb5a-4836-95b1-eb81e81b1656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
36877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1052636877
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2620606474
Short name T467
Test name
Test status
Simulation time 77645926 ps
CPU time 2.03 seconds
Started May 09 02:47:10 PM PDT 24
Finished May 09 02:47:15 PM PDT 24
Peak memory 204740 kb
Host smart-2527d7f6-d5c5-47c8-b228-c5cda7ee0e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26206
06474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2620606474
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1724334530
Short name T915
Test name
Test status
Simulation time 8450998171 ps
CPU time 7.96 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:27 PM PDT 24
Peak memory 204600 kb
Host smart-bc115bff-1755-4216-90ad-1eaf3fc2ba7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
34530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1724334530
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3756353181
Short name T756
Test name
Test status
Simulation time 8375273488 ps
CPU time 9.93 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 204524 kb
Host smart-7ca642cf-f499-4a1c-a3ac-d4041fa330f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37563
53181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3756353181
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3882884413
Short name T455
Test name
Test status
Simulation time 8419507143 ps
CPU time 7.69 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 204576 kb
Host smart-738e7094-b09a-45d7-87b0-37f78be3d902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38828
84413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3882884413
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1757618141
Short name T367
Test name
Test status
Simulation time 8370945282 ps
CPU time 9 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:23 PM PDT 24
Peak memory 204540 kb
Host smart-b2c15446-6567-4c93-a223-06520d17d74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
18141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1757618141
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.773986696
Short name T694
Test name
Test status
Simulation time 8414693686 ps
CPU time 7.84 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 204560 kb
Host smart-d1fa328a-2193-43db-86d6-5f8f005f9383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77398
6696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.773986696
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1753059493
Short name T315
Test name
Test status
Simulation time 8400839980 ps
CPU time 9.22 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 203776 kb
Host smart-0897cf62-e66a-4c53-b3d7-9229f9a41116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
59493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1753059493
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3071581082
Short name T343
Test name
Test status
Simulation time 8400384555 ps
CPU time 7.92 seconds
Started May 09 02:47:09 PM PDT 24
Finished May 09 02:47:21 PM PDT 24
Peak memory 204524 kb
Host smart-2990a6ba-1a11-4172-8a97-e8cb1c588c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30715
81082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3071581082
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2692385919
Short name T1243
Test name
Test status
Simulation time 8391152358 ps
CPU time 10.3 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:32 PM PDT 24
Peak memory 204508 kb
Host smart-8e3b6810-f5c9-4bbe-a3b8-66c8efe7575a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
85919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2692385919
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.433259354
Short name T813
Test name
Test status
Simulation time 8382171205 ps
CPU time 7.91 seconds
Started May 09 02:47:12 PM PDT 24
Finished May 09 02:47:23 PM PDT 24
Peak memory 204564 kb
Host smart-7c6d34fa-df31-4132-ab67-69c75af5fce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43325
9354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.433259354
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3366933073
Short name T1292
Test name
Test status
Simulation time 48996826 ps
CPU time 0.67 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:20 PM PDT 24
Peak memory 204308 kb
Host smart-5651c760-05c0-43b6-be3b-1b8d681f46c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33669
33073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3366933073
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.4209486820
Short name T1141
Test name
Test status
Simulation time 31257908541 ps
CPU time 66.57 seconds
Started May 09 02:47:14 PM PDT 24
Finished May 09 02:48:22 PM PDT 24
Peak memory 204792 kb
Host smart-98ddaea3-8710-4e3b-9a70-1ff4a75f845b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42094
86820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.4209486820
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2963043379
Short name T675
Test name
Test status
Simulation time 8423957135 ps
CPU time 7.48 seconds
Started May 09 02:47:08 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204612 kb
Host smart-4dddcd04-c54f-40d2-b237-7ef2d8e16469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
43379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2963043379
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1237806889
Short name T552
Test name
Test status
Simulation time 8397448769 ps
CPU time 7.58 seconds
Started May 09 02:47:11 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 204560 kb
Host smart-afb128aa-3dd7-4761-80c4-9a487aa8bf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
06889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1237806889
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2439570012
Short name T1183
Test name
Test status
Simulation time 8438895286 ps
CPU time 8.98 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:30 PM PDT 24
Peak memory 204572 kb
Host smart-d99a92a6-44aa-47e0-9ae1-5e586e9fee29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395
70012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2439570012
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.9435038
Short name T696
Test name
Test status
Simulation time 8385566082 ps
CPU time 7.9 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 204564 kb
Host smart-03274b2f-f055-43eb-90e9-d7acda64c44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94350
38 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.9435038
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1328801666
Short name T853
Test name
Test status
Simulation time 8374796887 ps
CPU time 7.45 seconds
Started May 09 02:47:12 PM PDT 24
Finished May 09 02:47:22 PM PDT 24
Peak memory 204556 kb
Host smart-725e681d-34dc-48ce-a5b5-56bdf26b103f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
01666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1328801666
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2406432642
Short name T633
Test name
Test status
Simulation time 8456084254 ps
CPU time 8.23 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 204576 kb
Host smart-770464dc-823b-497b-9cb6-0acd3e75e3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
32642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2406432642
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.4093673774
Short name T496
Test name
Test status
Simulation time 8411794357 ps
CPU time 9 seconds
Started May 09 02:47:12 PM PDT 24
Finished May 09 02:47:23 PM PDT 24
Peak memory 204564 kb
Host smart-b26b9507-fbf0-4b84-bc6f-e4f19a12566f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40936
73774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.4093673774
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3769147710
Short name T389
Test name
Test status
Simulation time 8454813587 ps
CPU time 8.3 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:30 PM PDT 24
Peak memory 204544 kb
Host smart-9a27316a-f9ac-411f-8edf-a60261ceba86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
47710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3769147710
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.1651173106
Short name T684
Test name
Test status
Simulation time 8460070271 ps
CPU time 8.56 seconds
Started May 09 02:47:15 PM PDT 24
Finished May 09 02:47:25 PM PDT 24
Peak memory 204588 kb
Host smart-5fb2fe8a-1a12-47d8-a73f-74275641dda7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1651173106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.1651173106
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2846433453
Short name T46
Test name
Test status
Simulation time 8381525580 ps
CPU time 8.93 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 204568 kb
Host smart-fe62a3f1-acb9-4455-bc9b-41b45ac3da56
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2846433453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2846433453
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2934221563
Short name T1191
Test name
Test status
Simulation time 8458933698 ps
CPU time 7.99 seconds
Started May 09 02:47:25 PM PDT 24
Finished May 09 02:47:34 PM PDT 24
Peak memory 204556 kb
Host smart-d04524c0-dd64-423c-9e22-c6316a4901c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
21563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2934221563
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1174521281
Short name T1297
Test name
Test status
Simulation time 8377126548 ps
CPU time 7.85 seconds
Started May 09 02:47:20 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 204580 kb
Host smart-92065441-4f48-4997-ae7a-a8df9729ebc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745
21281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1174521281
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2270398785
Short name T226
Test name
Test status
Simulation time 8817796897 ps
CPU time 12.28 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:34 PM PDT 24
Peak memory 204832 kb
Host smart-cc9778cf-17cf-467e-b8b1-49cd56a746b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
98785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2270398785
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_enable.1853106726
Short name T1012
Test name
Test status
Simulation time 8372632452 ps
CPU time 7.49 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204532 kb
Host smart-08551d7a-87bb-47c1-828a-16119c20ea36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18531
06726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1853106726
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3012357351
Short name T224
Test name
Test status
Simulation time 72676988 ps
CPU time 1.56 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:32 PM PDT 24
Peak memory 204632 kb
Host smart-6ec9c034-5afd-4e9c-a258-2e7a4f7cb63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30123
57351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3012357351
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1608800670
Short name T1138
Test name
Test status
Simulation time 8404586371 ps
CPU time 9.88 seconds
Started May 09 02:47:21 PM PDT 24
Finished May 09 02:47:33 PM PDT 24
Peak memory 204456 kb
Host smart-2a484c0a-6150-4333-9df0-9ea6b55a92d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
00670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1608800670
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2481627428
Short name T785
Test name
Test status
Simulation time 8372253028 ps
CPU time 8.13 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:47:25 PM PDT 24
Peak memory 204504 kb
Host smart-e4a0179f-bf69-4426-8f35-f173b69123ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
27428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2481627428
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.718909601
Short name T553
Test name
Test status
Simulation time 8482713962 ps
CPU time 8.77 seconds
Started May 09 02:47:19 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 204532 kb
Host smart-ac653c98-12ae-416d-995b-808b961ab45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71890
9601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.718909601
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3026740860
Short name T875
Test name
Test status
Simulation time 8420198074 ps
CPU time 7.65 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:47:26 PM PDT 24
Peak memory 204556 kb
Host smart-25770a55-06be-46d6-b9b6-7740e58442ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267
40860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3026740860
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3494178116
Short name T486
Test name
Test status
Simulation time 8371825516 ps
CPU time 8.51 seconds
Started May 09 02:47:20 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 204580 kb
Host smart-fae30f2d-7401-4c91-b1f3-8da12243dfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
78116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3494178116
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3459395334
Short name T919
Test name
Test status
Simulation time 8428368482 ps
CPU time 7.44 seconds
Started May 09 02:47:26 PM PDT 24
Finished May 09 02:47:34 PM PDT 24
Peak memory 204560 kb
Host smart-c203a0d6-4908-42f7-915a-28fc8ee5664b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593
95334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3459395334
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4150892250
Short name T452
Test name
Test status
Simulation time 8390753637 ps
CPU time 8.74 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:47:27 PM PDT 24
Peak memory 204532 kb
Host smart-94474745-282a-4358-9706-e1d58495ac69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41508
92250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4150892250
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.155721788
Short name T352
Test name
Test status
Simulation time 8390388018 ps
CPU time 10.01 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 204516 kb
Host smart-8066b4e8-4cdf-43d6-a0ed-ee9f5e527006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
1788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.155721788
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.709782525
Short name T1189
Test name
Test status
Simulation time 8369916719 ps
CPU time 9.45 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 204560 kb
Host smart-578330ec-f90a-4184-86a8-714fbea85867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70978
2525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.709782525
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3771886658
Short name T551
Test name
Test status
Simulation time 76665041 ps
CPU time 0.69 seconds
Started May 09 02:47:29 PM PDT 24
Finished May 09 02:47:34 PM PDT 24
Peak memory 204472 kb
Host smart-935ca1c3-3d54-4116-ab11-d953cf056857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37718
86658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3771886658
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3304925538
Short name T246
Test name
Test status
Simulation time 21745552224 ps
CPU time 42.79 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:48:01 PM PDT 24
Peak memory 204884 kb
Host smart-0f23b06a-19d1-4ef2-931d-17c05f79bbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33049
25538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3304925538
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3429805890
Short name T666
Test name
Test status
Simulation time 8405455682 ps
CPU time 8.94 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:30 PM PDT 24
Peak memory 204636 kb
Host smart-b3c34df9-8212-4184-b2bc-067f40388a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34298
05890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3429805890
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1690647759
Short name T157
Test name
Test status
Simulation time 8436800839 ps
CPU time 7.81 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:28 PM PDT 24
Peak memory 204504 kb
Host smart-a47d8c31-275b-4d07-94d6-3c0c92994e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
47759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1690647759
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1385742606
Short name T242
Test name
Test status
Simulation time 8397021118 ps
CPU time 9.06 seconds
Started May 09 02:47:19 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 204524 kb
Host smart-081e3c8b-80f2-44da-b230-aae218b5534f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857
42606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1385742606
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1968042225
Short name T181
Test name
Test status
Simulation time 8446065964 ps
CPU time 8.11 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204532 kb
Host smart-a6db6ff2-3d30-4166-9154-3d07f3d5e780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19680
42225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1968042225
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3985558826
Short name T730
Test name
Test status
Simulation time 8367974486 ps
CPU time 7.98 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:47:26 PM PDT 24
Peak memory 204552 kb
Host smart-6000a76e-3688-4e40-a46c-c37ff18f3a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39855
58826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3985558826
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.406115000
Short name T133
Test name
Test status
Simulation time 8485714644 ps
CPU time 8.17 seconds
Started May 09 02:47:17 PM PDT 24
Finished May 09 02:47:28 PM PDT 24
Peak memory 204612 kb
Host smart-5fe1b200-df3a-464d-8ddb-86546e59e306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40611
5000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.406115000
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1009084900
Short name T1307
Test name
Test status
Simulation time 8419146146 ps
CPU time 7.4 seconds
Started May 09 02:47:18 PM PDT 24
Finished May 09 02:47:28 PM PDT 24
Peak memory 204576 kb
Host smart-31d76564-7c98-4889-9fe4-9e00f86c048d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
84900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1009084900
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2539802020
Short name T502
Test name
Test status
Simulation time 8389981147 ps
CPU time 8.14 seconds
Started May 09 02:47:19 PM PDT 24
Finished May 09 02:47:30 PM PDT 24
Peak memory 204576 kb
Host smart-a444d863-6bae-4fab-9b82-e1a3921a648b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25398
02020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2539802020
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2023353010
Short name T726
Test name
Test status
Simulation time 8466032599 ps
CPU time 7.73 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204568 kb
Host smart-14121ad4-1634-4584-b5b6-8bf18177fcd6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2023353010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2023353010
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.3927698779
Short name T1069
Test name
Test status
Simulation time 8446140001 ps
CPU time 8.16 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204504 kb
Host smart-a15ad955-b953-43f9-a773-d6d95d0fb3f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3927698779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.3927698779
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3863698598
Short name T789
Test name
Test status
Simulation time 8421145059 ps
CPU time 7.67 seconds
Started May 09 02:47:29 PM PDT 24
Finished May 09 02:47:41 PM PDT 24
Peak memory 204592 kb
Host smart-e27afdf9-314f-4367-bc74-2074db5fbbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
98598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3863698598
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1572121691
Short name T1003
Test name
Test status
Simulation time 8393506933 ps
CPU time 7.47 seconds
Started May 09 02:47:16 PM PDT 24
Finished May 09 02:47:25 PM PDT 24
Peak memory 204564 kb
Host smart-bfe08fd2-6f9c-4509-a354-f867018318c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
21691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1572121691
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2367088798
Short name T225
Test name
Test status
Simulation time 8626222698 ps
CPU time 12.35 seconds
Started May 09 02:47:21 PM PDT 24
Finished May 09 02:47:36 PM PDT 24
Peak memory 204712 kb
Host smart-51d4f618-80a0-40f7-83c1-e4295c50ca1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23670
88798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2367088798
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_enable.1225401551
Short name T57
Test name
Test status
Simulation time 8377545156 ps
CPU time 8.16 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204620 kb
Host smart-b97c125a-0225-4b1b-b71f-b1cfe7c002a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12254
01551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1225401551
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1798125776
Short name T370
Test name
Test status
Simulation time 109065177 ps
CPU time 1.75 seconds
Started May 09 02:47:31 PM PDT 24
Finished May 09 02:47:37 PM PDT 24
Peak memory 204612 kb
Host smart-d35a4639-e6b7-40e8-b641-4dcf8cd329ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
25776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1798125776
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.491823492
Short name T489
Test name
Test status
Simulation time 8393655016 ps
CPU time 8.17 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:39 PM PDT 24
Peak memory 204520 kb
Host smart-511a8465-4559-4c53-9d5e-2912f7d22fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49182
3492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.491823492
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.4089689828
Short name T589
Test name
Test status
Simulation time 8445775584 ps
CPU time 9.89 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:44 PM PDT 24
Peak memory 204512 kb
Host smart-19ef853b-300c-4a0c-a257-c0d2747a9b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
89828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.4089689828
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3614088392
Short name T606
Test name
Test status
Simulation time 8371152382 ps
CPU time 8.29 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204604 kb
Host smart-fe89b844-f78d-4734-adff-53ca2836d7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36140
88392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3614088392
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.983769733
Short name T122
Test name
Test status
Simulation time 8442371470 ps
CPU time 8.66 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:39 PM PDT 24
Peak memory 204824 kb
Host smart-585bc509-56cf-477e-bfa0-de1807e77c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98376
9733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.983769733
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.720998793
Short name T972
Test name
Test status
Simulation time 8395909209 ps
CPU time 8.91 seconds
Started May 09 02:47:31 PM PDT 24
Finished May 09 02:47:44 PM PDT 24
Peak memory 204516 kb
Host smart-93065faa-49fd-4f4c-bad7-0d5073914aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72099
8793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.720998793
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.405257678
Short name T1229
Test name
Test status
Simulation time 8423512253 ps
CPU time 7.73 seconds
Started May 09 02:47:32 PM PDT 24
Finished May 09 02:47:43 PM PDT 24
Peak memory 204576 kb
Host smart-40061ac4-7a6f-4d48-8850-01fdc6f6eccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
7678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.405257678
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.764573504
Short name T169
Test name
Test status
Simulation time 8381750903 ps
CPU time 9.37 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:41 PM PDT 24
Peak memory 204520 kb
Host smart-d6d0da9e-a953-4faf-a971-4d8d3311c480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76457
3504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.764573504
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2404321905
Short name T1246
Test name
Test status
Simulation time 8365347456 ps
CPU time 8.34 seconds
Started May 09 02:47:32 PM PDT 24
Finished May 09 02:47:44 PM PDT 24
Peak memory 204560 kb
Host smart-7c345106-5b6f-49dd-a9e0-4a4d6862f388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
21905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2404321905
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1325006112
Short name T1360
Test name
Test status
Simulation time 45150469 ps
CPU time 0.67 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:35 PM PDT 24
Peak memory 204524 kb
Host smart-ad90b4c6-f5ca-488c-a2e3-b3a045fe3970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13250
06112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1325006112
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2145079998
Short name T95
Test name
Test status
Simulation time 30613911258 ps
CPU time 57.82 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:48:27 PM PDT 24
Peak memory 204812 kb
Host smart-46eff008-bbcf-41c1-9677-9c8e3e06f4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
79998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2145079998
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3052109512
Short name T1337
Test name
Test status
Simulation time 8415292775 ps
CPU time 7.66 seconds
Started May 09 02:47:29 PM PDT 24
Finished May 09 02:47:41 PM PDT 24
Peak memory 204572 kb
Host smart-70886cc4-eac8-4a93-9902-87871be53162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30521
09512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3052109512
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.4138203960
Short name T1142
Test name
Test status
Simulation time 8401560188 ps
CPU time 8.47 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:38 PM PDT 24
Peak memory 204592 kb
Host smart-8eeb3652-e6fd-4e8e-9218-be8826f64839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
03960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.4138203960
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.4134748986
Short name T14
Test name
Test status
Simulation time 8389558877 ps
CPU time 8.47 seconds
Started May 09 02:47:36 PM PDT 24
Finished May 09 02:47:46 PM PDT 24
Peak memory 204536 kb
Host smart-e27526ea-c883-4d14-a926-579260795b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41347
48986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.4134748986
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1681534250
Short name T1254
Test name
Test status
Simulation time 8374969035 ps
CPU time 7.86 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:37 PM PDT 24
Peak memory 204572 kb
Host smart-39f376bb-2ba3-41e8-b7ba-6c114806ebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
34250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1681534250
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2035525863
Short name T539
Test name
Test status
Simulation time 8371553180 ps
CPU time 7.95 seconds
Started May 09 02:47:30 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 204564 kb
Host smart-8294a991-c836-4b17-855f-3a340f15c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20355
25863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2035525863
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3585668354
Short name T1255
Test name
Test status
Simulation time 8412449446 ps
CPU time 8.12 seconds
Started May 09 02:47:20 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 204528 kb
Host smart-13f7ebe2-46cf-4ddc-ab4d-ee8f36c7ea22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
68354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3585668354
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3767298062
Short name T438
Test name
Test status
Simulation time 8398315821 ps
CPU time 9.43 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204528 kb
Host smart-bbbb2503-3a6b-4529-87ae-638f2c2dc7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37672
98062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3767298062
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3283210320
Short name T818
Test name
Test status
Simulation time 8462327034 ps
CPU time 8.56 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:39 PM PDT 24
Peak memory 204572 kb
Host smart-81aa4cd0-c33d-4948-a2b8-b9d3f4adea12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32832
10320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3283210320
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.60937858
Short name T1066
Test name
Test status
Simulation time 8501575146 ps
CPU time 9 seconds
Started May 09 02:47:44 PM PDT 24
Finished May 09 02:47:56 PM PDT 24
Peak memory 204564 kb
Host smart-f0710174-6ec3-446f-908c-dbd974d5652a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=60937858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.60937858
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.3048889905
Short name T1210
Test name
Test status
Simulation time 8396353585 ps
CPU time 8.75 seconds
Started May 09 02:47:39 PM PDT 24
Finished May 09 02:47:50 PM PDT 24
Peak memory 204524 kb
Host smart-275c53c1-e390-4415-88f8-b2efed2a70bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3048889905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.3048889905
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.4281434855
Short name T321
Test name
Test status
Simulation time 8469664685 ps
CPU time 8.35 seconds
Started May 09 02:47:43 PM PDT 24
Finished May 09 02:47:55 PM PDT 24
Peak memory 204540 kb
Host smart-3be7addc-17be-4192-89b2-1f5440909311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814
34855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.4281434855
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2167522541
Short name T945
Test name
Test status
Simulation time 8391109768 ps
CPU time 7.61 seconds
Started May 09 02:47:31 PM PDT 24
Finished May 09 02:47:43 PM PDT 24
Peak memory 204532 kb
Host smart-04c9a3b5-e793-4c34-a893-5b04ff673a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21675
22541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2167522541
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.4098787041
Short name T378
Test name
Test status
Simulation time 9249366574 ps
CPU time 12.55 seconds
Started May 09 02:47:29 PM PDT 24
Finished May 09 02:47:45 PM PDT 24
Peak memory 204800 kb
Host smart-80a447aa-5745-4927-88ed-2b2a92c0f9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987
87041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.4098787041
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_enable.3745842562
Short name T679
Test name
Test status
Simulation time 8380545676 ps
CPU time 9.26 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204580 kb
Host smart-317080f1-7b7d-4dd6-8434-5baacfacbea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37458
42562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3745842562
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3309140080
Short name T1067
Test name
Test status
Simulation time 38364970 ps
CPU time 1.02 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:33 PM PDT 24
Peak memory 204688 kb
Host smart-c294cacd-db4f-47d9-b11c-5853c126d8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33091
40080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3309140080
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.938504568
Short name T786
Test name
Test status
Simulation time 8420860647 ps
CPU time 8.31 seconds
Started May 09 02:47:44 PM PDT 24
Finished May 09 02:47:56 PM PDT 24
Peak memory 204572 kb
Host smart-ff48bca6-b4d5-49e3-88cb-4795433ef7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93850
4568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.938504568
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2377612398
Short name T999
Test name
Test status
Simulation time 8362698901 ps
CPU time 7.63 seconds
Started May 09 02:47:41 PM PDT 24
Finished May 09 02:47:52 PM PDT 24
Peak memory 204572 kb
Host smart-d9ca9451-c324-4693-8d14-daf04ee4b4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
12398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2377612398
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1868588349
Short name T1384
Test name
Test status
Simulation time 8425900920 ps
CPU time 8.47 seconds
Started May 09 02:47:31 PM PDT 24
Finished May 09 02:47:44 PM PDT 24
Peak memory 204516 kb
Host smart-86dd5a7b-7237-424a-a6c5-d79654e6fd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
88349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1868588349
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.882306282
Short name T1205
Test name
Test status
Simulation time 8419050899 ps
CPU time 8.27 seconds
Started May 09 02:47:28 PM PDT 24
Finished May 09 02:47:39 PM PDT 24
Peak memory 204508 kb
Host smart-8aaf3c83-a6ba-4ea2-bbe7-cf46ea4334e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88230
6282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.882306282
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1517675953
Short name T534
Test name
Test status
Simulation time 8372075115 ps
CPU time 10.15 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:40 PM PDT 24
Peak memory 204576 kb
Host smart-d17a0853-e6bc-4a47-b693-934392fe9aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15176
75953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1517675953
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1805187993
Short name T294
Test name
Test status
Simulation time 8400731775 ps
CPU time 7.83 seconds
Started May 09 02:47:27 PM PDT 24
Finished May 09 02:47:38 PM PDT 24
Peak memory 204508 kb
Host smart-c571095e-cc60-42c0-9d1e-1b955e4c3206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18051
87993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1805187993
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2894941312
Short name T1213
Test name
Test status
Simulation time 8412631487 ps
CPU time 7.77 seconds
Started May 09 02:47:47 PM PDT 24
Finished May 09 02:47:57 PM PDT 24
Peak memory 204372 kb
Host smart-43121317-89d6-44f5-b7ed-4d0fbebd1718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
41312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2894941312
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3423580605
Short name T1331
Test name
Test status
Simulation time 8382043626 ps
CPU time 9.65 seconds
Started May 09 02:47:44 PM PDT 24
Finished May 09 02:47:57 PM PDT 24
Peak memory 204572 kb
Host smart-997a91c4-a5fe-445a-88c4-7ea508a5735d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
80605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3423580605
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2711507518
Short name T365
Test name
Test status
Simulation time 45761936 ps
CPU time 0.66 seconds
Started May 09 02:47:41 PM PDT 24
Finished May 09 02:47:45 PM PDT 24
Peak memory 204516 kb
Host smart-5572eebe-4d64-4f2c-8a59-b47d2cfc0d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27115
07518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2711507518
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.577539659
Short name T249
Test name
Test status
Simulation time 28521981904 ps
CPU time 59.9 seconds
Started May 09 02:47:39 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204808 kb
Host smart-44e31656-607c-4c36-a4f3-d8e02aa1c288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57753
9659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.577539659
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.828734741
Short name T1175
Test name
Test status
Simulation time 8399661334 ps
CPU time 8.48 seconds
Started May 09 02:47:42 PM PDT 24
Finished May 09 02:47:54 PM PDT 24
Peak memory 204620 kb
Host smart-d9be40f4-6522-4889-a06f-27b666466802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82873
4741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.828734741
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4068183105
Short name T141
Test name
Test status
Simulation time 8418516866 ps
CPU time 9.67 seconds
Started May 09 02:47:41 PM PDT 24
Finished May 09 02:47:54 PM PDT 24
Peak memory 204504 kb
Host smart-2f1855db-990d-4817-9720-14cf009b2bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
83105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4068183105
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1990318514
Short name T472
Test name
Test status
Simulation time 8445373553 ps
CPU time 8.04 seconds
Started May 09 02:47:45 PM PDT 24
Finished May 09 02:47:57 PM PDT 24
Peak memory 204508 kb
Host smart-f11923e3-0644-4b58-a254-10c056c4c827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19903
18514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1990318514
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1791743234
Short name T435
Test name
Test status
Simulation time 8384790709 ps
CPU time 7.52 seconds
Started May 09 02:47:40 PM PDT 24
Finished May 09 02:47:51 PM PDT 24
Peak memory 204540 kb
Host smart-4e5ede74-afc9-4a02-b5ee-cd5523362cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
43234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1791743234
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.107624789
Short name T735
Test name
Test status
Simulation time 8377181798 ps
CPU time 7.66 seconds
Started May 09 02:47:44 PM PDT 24
Finished May 09 02:47:55 PM PDT 24
Peak memory 204556 kb
Host smart-42238b38-39bb-4085-a093-9d05abd35172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
4789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.107624789
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1128942065
Short name T1339
Test name
Test status
Simulation time 8464274697 ps
CPU time 7.93 seconds
Started May 09 02:47:31 PM PDT 24
Finished May 09 02:47:43 PM PDT 24
Peak memory 204512 kb
Host smart-6f810978-aee8-4597-875c-12bd264f0b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
42065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1128942065
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2631306200
Short name T572
Test name
Test status
Simulation time 8378942456 ps
CPU time 7.67 seconds
Started May 09 02:47:42 PM PDT 24
Finished May 09 02:47:53 PM PDT 24
Peak memory 204604 kb
Host smart-e62ef950-12c2-4a9f-afe6-5f6689b447ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26313
06200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2631306200
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.567833447
Short name T566
Test name
Test status
Simulation time 8380084282 ps
CPU time 7.69 seconds
Started May 09 02:47:47 PM PDT 24
Finished May 09 02:47:58 PM PDT 24
Peak memory 204608 kb
Host smart-62852180-1b76-4b0c-bda0-63a8f6b00f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56783
3447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.567833447
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.2440055690
Short name T809
Test name
Test status
Simulation time 8471978452 ps
CPU time 8.37 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204552 kb
Host smart-814bd586-c941-43aa-94ca-bfa738e9c1a2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2440055690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.2440055690
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2918124454
Short name T1428
Test name
Test status
Simulation time 8397958554 ps
CPU time 9.5 seconds
Started May 09 02:47:51 PM PDT 24
Finished May 09 02:48:03 PM PDT 24
Peak memory 204560 kb
Host smart-5b11d996-73c5-4349-9dab-3654d7a280de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2918124454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2918124454
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.3891637879
Short name T924
Test name
Test status
Simulation time 8429642000 ps
CPU time 7.65 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 204516 kb
Host smart-8e007d56-8516-4910-aa8c-012b40ce608a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38916
37879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3891637879
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1169406116
Short name T559
Test name
Test status
Simulation time 8395505760 ps
CPU time 10.44 seconds
Started May 09 02:47:40 PM PDT 24
Finished May 09 02:47:53 PM PDT 24
Peak memory 204520 kb
Host smart-7ee06b60-71ce-4215-b440-c3493e588ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
06116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1169406116
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.4268769690
Short name T188
Test name
Test status
Simulation time 9060293962 ps
CPU time 12.39 seconds
Started May 09 02:47:43 PM PDT 24
Finished May 09 02:47:59 PM PDT 24
Peak memory 204780 kb
Host smart-43c7006f-e92b-47a6-a800-96546686829b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42687
69690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.4268769690
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_enable.3849625139
Short name T1188
Test name
Test status
Simulation time 8416840679 ps
CPU time 9.13 seconds
Started May 09 02:47:40 PM PDT 24
Finished May 09 02:47:53 PM PDT 24
Peak memory 204520 kb
Host smart-d39589fb-543d-4235-bbba-51b252a99f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
25139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3849625139
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2599915243
Short name T687
Test name
Test status
Simulation time 171145086 ps
CPU time 1.6 seconds
Started May 09 02:47:44 PM PDT 24
Finished May 09 02:47:49 PM PDT 24
Peak memory 204736 kb
Host smart-b4639904-3e0e-4706-af44-edea8e7b280e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25999
15243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2599915243
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2490555791
Short name T1020
Test name
Test status
Simulation time 8401339154 ps
CPU time 8.82 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204504 kb
Host smart-9541963c-a620-4c13-8e2d-ea70ff533a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24905
55791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2490555791
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.659274741
Short name T8
Test name
Test status
Simulation time 8369123343 ps
CPU time 10.18 seconds
Started May 09 02:47:51 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204548 kb
Host smart-f52f2663-5c0f-4082-ac2c-a694f30033d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65927
4741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.659274741
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1746175158
Short name T1309
Test name
Test status
Simulation time 8403944335 ps
CPU time 9.22 seconds
Started May 09 02:47:46 PM PDT 24
Finished May 09 02:47:58 PM PDT 24
Peak memory 204556 kb
Host smart-ba167cf8-eb2d-45a7-9c4e-54e441f967e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17461
75158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1746175158
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2091681101
Short name T1111
Test name
Test status
Simulation time 8427509223 ps
CPU time 8.56 seconds
Started May 09 02:47:41 PM PDT 24
Finished May 09 02:47:53 PM PDT 24
Peak memory 204568 kb
Host smart-36ab966c-2e23-43de-81dd-026eb9fc680f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20916
81101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2091681101
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2774215610
Short name T342
Test name
Test status
Simulation time 8371360492 ps
CPU time 8.27 seconds
Started May 09 02:47:43 PM PDT 24
Finished May 09 02:47:54 PM PDT 24
Peak memory 204580 kb
Host smart-612e8d9f-f2b6-4853-9324-f514618017e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27742
15610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2774215610
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2181395858
Short name T298
Test name
Test status
Simulation time 8418475530 ps
CPU time 10.1 seconds
Started May 09 02:47:43 PM PDT 24
Finished May 09 02:47:56 PM PDT 24
Peak memory 204612 kb
Host smart-af4a3fae-fc63-4bf0-84b7-76033e538c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
95858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2181395858
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.100051037
Short name T475
Test name
Test status
Simulation time 8380440835 ps
CPU time 8.19 seconds
Started May 09 02:47:40 PM PDT 24
Finished May 09 02:47:52 PM PDT 24
Peak memory 204580 kb
Host smart-16285a5c-cd07-48ae-8703-6b52d0aa67e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
1037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.100051037
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2726376630
Short name T852
Test name
Test status
Simulation time 8421125918 ps
CPU time 8.81 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204372 kb
Host smart-9e7c0303-3882-4b25-b951-2ddf3e9858ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
76630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2726376630
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.585406688
Short name T536
Test name
Test status
Simulation time 8405634290 ps
CPU time 8.36 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204568 kb
Host smart-85e523e5-5da1-4baa-9ae6-e02bde3c0c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58540
6688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.585406688
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3842604686
Short name T1043
Test name
Test status
Simulation time 24532390707 ps
CPU time 45.97 seconds
Started May 09 02:47:41 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204696 kb
Host smart-9cea04bc-d6d5-4313-8c87-7408101d0bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38426
04686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3842604686
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3966454874
Short name T1148
Test name
Test status
Simulation time 8406200638 ps
CPU time 7.82 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:03 PM PDT 24
Peak memory 204520 kb
Host smart-8deaeda4-cd12-4ae5-8a96-d90ae129f8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
54874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3966454874
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1630417113
Short name T476
Test name
Test status
Simulation time 8410245567 ps
CPU time 8.05 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204592 kb
Host smart-4da6112e-a31f-4841-a47c-d3478f74cc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16304
17113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1630417113
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.365852412
Short name T369
Test name
Test status
Simulation time 8440215174 ps
CPU time 8.12 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204524 kb
Host smart-5f97721a-ff94-4d15-845e-b82e6ddeac15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36585
2412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.365852412
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1226717870
Short name T795
Test name
Test status
Simulation time 8371641612 ps
CPU time 8.05 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:06 PM PDT 24
Peak memory 204596 kb
Host smart-97b634c2-04eb-407c-b852-7e3568bd7512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12267
17870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1226717870
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.766301652
Short name T503
Test name
Test status
Simulation time 8367231312 ps
CPU time 9.15 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204380 kb
Host smart-cde419b2-cf7d-4ab8-aa37-8102cfabe641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76630
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.766301652
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1313420188
Short name T1153
Test name
Test status
Simulation time 8445159499 ps
CPU time 8.1 seconds
Started May 09 02:47:41 PM PDT 24
Finished May 09 02:47:53 PM PDT 24
Peak memory 204464 kb
Host smart-7bd17b77-4f57-449b-b362-bf836b83a000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
20188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1313420188
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.609551184
Short name T240
Test name
Test status
Simulation time 8431150665 ps
CPU time 10.3 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 204528 kb
Host smart-16ad33ef-c1b4-4e14-8128-7a0aac49916d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60955
1184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.609551184
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3430993828
Short name T451
Test name
Test status
Simulation time 8394514247 ps
CPU time 7.77 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204584 kb
Host smart-93974a17-d232-41ea-a3ba-eba6c69d19df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
93828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3430993828
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.1123403593
Short name T130
Test name
Test status
Simulation time 8523653035 ps
CPU time 8.26 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:46:06 PM PDT 24
Peak memory 204512 kb
Host smart-e416984d-2be9-45fe-a8d8-b6b261ba04d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1123403593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.1123403593
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3231804054
Short name T720
Test name
Test status
Simulation time 8401809708 ps
CPU time 8.08 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204528 kb
Host smart-e6f9e063-a609-442b-ac14-af3dcbf23737
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3231804054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3231804054
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.1087439606
Short name T457
Test name
Test status
Simulation time 8493462848 ps
CPU time 7.7 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:46:05 PM PDT 24
Peak memory 204568 kb
Host smart-6ba78df4-2701-4173-ac98-163a376a7a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
39606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.1087439606
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3560853409
Short name T1135
Test name
Test status
Simulation time 8376147515 ps
CPU time 9.43 seconds
Started May 09 02:45:49 PM PDT 24
Finished May 09 02:46:02 PM PDT 24
Peak memory 204580 kb
Host smart-f95cc163-9d00-4ff3-ac6f-6ba9a55d1e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35608
53409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3560853409
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1438843242
Short name T960
Test name
Test status
Simulation time 8649579964 ps
CPU time 12.45 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:09 PM PDT 24
Peak memory 204820 kb
Host smart-1774bb19-67df-45e0-b83c-8e1c7d11dd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
43242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1438843242
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_enable.230396029
Short name T1372
Test name
Test status
Simulation time 8379869651 ps
CPU time 7.9 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204564 kb
Host smart-69155b7f-d16e-4979-80c0-922f581f7968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
6029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.230396029
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.4081948424
Short name T670
Test name
Test status
Simulation time 295920555 ps
CPU time 2.33 seconds
Started May 09 02:45:53 PM PDT 24
Finished May 09 02:46:00 PM PDT 24
Peak memory 204716 kb
Host smart-bb89f669-825e-4722-84e8-55ee3074b2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819
48424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.4081948424
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.406436719
Short name T1310
Test name
Test status
Simulation time 8382813013 ps
CPU time 9.45 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204556 kb
Host smart-48f40629-4788-4463-8717-c07d4929a9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40643
6719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.406436719
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1342947346
Short name T205
Test name
Test status
Simulation time 8377754340 ps
CPU time 7.43 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204524 kb
Host smart-a6ef70af-cbaf-4be1-ad35-5338a793fed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429
47346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1342947346
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1540693821
Short name T492
Test name
Test status
Simulation time 8471301902 ps
CPU time 8.17 seconds
Started May 09 02:45:49 PM PDT 24
Finished May 09 02:46:02 PM PDT 24
Peak memory 204548 kb
Host smart-75f2ed2a-6b07-44f6-bff1-c73a438b4a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15406
93821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1540693821
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.329149845
Short name T86
Test name
Test status
Simulation time 8418941514 ps
CPU time 8.2 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204596 kb
Host smart-e74e2a58-f757-4cd5-9c77-557bb7dc499c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
9845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.329149845
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.4122922655
Short name T939
Test name
Test status
Simulation time 8383337409 ps
CPU time 8.25 seconds
Started May 09 02:45:49 PM PDT 24
Finished May 09 02:46:02 PM PDT 24
Peak memory 204604 kb
Host smart-4edcd193-d7be-4b0d-9efa-01fa566defa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41229
22655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.4122922655
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3885421422
Short name T1250
Test name
Test status
Simulation time 8376614787 ps
CPU time 7.96 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204592 kb
Host smart-98b6dfd5-650b-4793-8cdd-034f151e267b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38854
21422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3885421422
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3150241943
Short name T355
Test name
Test status
Simulation time 8401669717 ps
CPU time 7.87 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204584 kb
Host smart-e5ddef44-1338-4ea0-adc2-b645d40167ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
41943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3150241943
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.877730530
Short name T576
Test name
Test status
Simulation time 8401773348 ps
CPU time 8.38 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204584 kb
Host smart-4bf9d230-e936-4a51-aebc-a79fe8fe7b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87773
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.877730530
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3123295017
Short name T961
Test name
Test status
Simulation time 8369070729 ps
CPU time 8.49 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204592 kb
Host smart-ee92bc99-8d39-493e-9e54-e9bac8b542fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31232
95017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3123295017
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2143574623
Short name T398
Test name
Test status
Simulation time 62240874 ps
CPU time 0.67 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:45:57 PM PDT 24
Peak memory 204544 kb
Host smart-db8cf155-c6ef-48ee-be8b-d3847d917798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
74623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2143574623
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1321654898
Short name T471
Test name
Test status
Simulation time 16085550958 ps
CPU time 27.87 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 204800 kb
Host smart-361890e2-9cd3-484a-8f8f-fb2223edebec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13216
54898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1321654898
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2121942809
Short name T56
Test name
Test status
Simulation time 8426860112 ps
CPU time 8.01 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204540 kb
Host smart-71cf0350-2bed-4570-82c6-514bed95850d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21219
42809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2121942809
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.329328582
Short name T404
Test name
Test status
Simulation time 8448674923 ps
CPU time 8.11 seconds
Started May 09 02:45:53 PM PDT 24
Finished May 09 02:46:06 PM PDT 24
Peak memory 204588 kb
Host smart-842ed548-8086-4900-a3be-46557cef43fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32932
8582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.329328582
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.2658039261
Short name T860
Test name
Test status
Simulation time 8416290780 ps
CPU time 8.49 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204572 kb
Host smart-e22e6e76-31e7-47b7-9d8d-3527cdea95f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26580
39261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.2658039261
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1876389204
Short name T67
Test name
Test status
Simulation time 349487449 ps
CPU time 1.21 seconds
Started May 09 02:45:49 PM PDT 24
Finished May 09 02:45:55 PM PDT 24
Peak memory 221840 kb
Host smart-6b147328-a4e0-401b-b313-e87bac60ae8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1876389204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1876389204
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.730438159
Short name T1165
Test name
Test status
Simulation time 8381228042 ps
CPU time 7.65 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:46:05 PM PDT 24
Peak memory 204580 kb
Host smart-ed480846-03ab-4628-bc8d-63cb658ad4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73043
8159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.730438159
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2894514301
Short name T21
Test name
Test status
Simulation time 8378016433 ps
CPU time 8 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204552 kb
Host smart-153b5bf8-f034-4638-9368-5a718387f56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28945
14301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2894514301
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1035064228
Short name T1351
Test name
Test status
Simulation time 8480096864 ps
CPU time 7.9 seconds
Started May 09 02:45:51 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 204608 kb
Host smart-7699a6cc-b6dc-4051-919b-dea6ba86bbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10350
64228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1035064228
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2136615065
Short name T771
Test name
Test status
Simulation time 8449740273 ps
CPU time 8.67 seconds
Started May 09 02:45:50 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 204544 kb
Host smart-d4b48d7c-1fa5-414a-a2c8-b8152e1ab2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21366
15065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2136615065
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1070521327
Short name T1103
Test name
Test status
Simulation time 8398369436 ps
CPU time 8.27 seconds
Started May 09 02:45:52 PM PDT 24
Finished May 09 02:46:06 PM PDT 24
Peak memory 204532 kb
Host smart-c44ec497-6889-4dd3-823b-9daeb5bc7462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
21327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1070521327
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.420227569
Short name T1041
Test name
Test status
Simulation time 8474880718 ps
CPU time 8.36 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204392 kb
Host smart-86f44a55-e98d-4ef8-bc8e-95424540fe24
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=420227569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.420227569
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.3465882702
Short name T466
Test name
Test status
Simulation time 8434883274 ps
CPU time 8.09 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204548 kb
Host smart-e7b4b461-643a-45b2-8740-f8902c105d3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3465882702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.3465882702
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.464470740
Short name T904
Test name
Test status
Simulation time 8414478273 ps
CPU time 7.69 seconds
Started May 09 02:47:51 PM PDT 24
Finished May 09 02:48:01 PM PDT 24
Peak memory 204524 kb
Host smart-04ce7e2c-7bec-4d18-a6cf-5a095c406985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46447
0740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.464470740
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2807721360
Short name T571
Test name
Test status
Simulation time 8389879728 ps
CPU time 7.65 seconds
Started May 09 03:01:53 PM PDT 24
Finished May 09 03:02:03 PM PDT 24
Peak memory 204560 kb
Host smart-fd26c9a1-0b2c-4854-84b7-5f32eaea0b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28077
21360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2807721360
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1768445359
Short name T625
Test name
Test status
Simulation time 8681497384 ps
CPU time 13.25 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204808 kb
Host smart-b89d9604-3353-4cf5-a0bc-2b2abe2568d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
45359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1768445359
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_enable.1628835606
Short name T680
Test name
Test status
Simulation time 8422568332 ps
CPU time 9.47 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204552 kb
Host smart-b06aef29-ae67-4ece-8077-8998d204f863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16288
35606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1628835606
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3481470643
Short name T1223
Test name
Test status
Simulation time 63051512 ps
CPU time 1.22 seconds
Started May 09 02:47:51 PM PDT 24
Finished May 09 02:47:55 PM PDT 24
Peak memory 204616 kb
Host smart-e4c322f3-c475-491a-a662-1e3cdc9cd808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
70643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3481470643
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2976393503
Short name T1000
Test name
Test status
Simulation time 8435298041 ps
CPU time 9.58 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204592 kb
Host smart-5bba27b5-aa3f-4efa-ba02-ec528e281354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
93503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2976393503
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2465234497
Short name T197
Test name
Test status
Simulation time 8386475255 ps
CPU time 8.38 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204552 kb
Host smart-aacdf33b-ec74-4d0f-a28d-7ed33241d956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652
34497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2465234497
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2803554507
Short name T692
Test name
Test status
Simulation time 8415829236 ps
CPU time 7.69 seconds
Started May 09 02:47:50 PM PDT 24
Finished May 09 02:48:00 PM PDT 24
Peak memory 204512 kb
Host smart-98e5dc47-f6fc-4df7-960b-8654fb9e790d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
54507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2803554507
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.323136216
Short name T1013
Test name
Test status
Simulation time 8412604958 ps
CPU time 8.56 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:06 PM PDT 24
Peak memory 204512 kb
Host smart-9d9270ea-393c-4bba-86f0-3f1a3beaf4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32313
6216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.323136216
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.893108613
Short name T677
Test name
Test status
Simulation time 8371583716 ps
CPU time 9.89 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204608 kb
Host smart-af6018a1-a527-4112-be3a-832b7926b17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89310
8613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.893108613
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.59589989
Short name T832
Test name
Test status
Simulation time 8439185799 ps
CPU time 10.47 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:06 PM PDT 24
Peak memory 204620 kb
Host smart-73b6bf8d-a466-4e29-8ee2-a33677c47db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59589
989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.59589989
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.291691095
Short name T525
Test name
Test status
Simulation time 8369381083 ps
CPU time 8.07 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204388 kb
Host smart-28787f25-cdbb-486e-8d0d-4d836f97c273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
1095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.291691095
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.882665366
Short name T900
Test name
Test status
Simulation time 8399988489 ps
CPU time 7.72 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 204592 kb
Host smart-46000a2c-d388-4269-9492-fed524cca679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88266
5366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.882665366
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1198769189
Short name T937
Test name
Test status
Simulation time 8383139090 ps
CPU time 9.43 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204564 kb
Host smart-c9be31de-3149-48c5-b7ba-198022ed3cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11987
69189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1198769189
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1038782543
Short name T40
Test name
Test status
Simulation time 49235506 ps
CPU time 0.67 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:47:56 PM PDT 24
Peak memory 204528 kb
Host smart-73f4472e-ef12-41c6-a3e0-f3b94c7aca32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10387
82543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1038782543
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1973963116
Short name T227
Test name
Test status
Simulation time 17141377804 ps
CPU time 31.17 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204700 kb
Host smart-67e22d26-4f5d-4fa0-9153-72eedcfa438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19739
63116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1973963116
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1475515959
Short name T1244
Test name
Test status
Simulation time 8387528151 ps
CPU time 8.29 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204500 kb
Host smart-f4a4e440-5a30-4677-84a7-3246e1b28a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14755
15959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1475515959
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.623350534
Short name T839
Test name
Test status
Simulation time 8395076059 ps
CPU time 7.8 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 204624 kb
Host smart-1058ed58-e00f-4e3b-8153-7414f5f3b8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62335
0534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.623350534
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.1701574627
Short name T433
Test name
Test status
Simulation time 8382643804 ps
CPU time 8.82 seconds
Started May 09 02:47:51 PM PDT 24
Finished May 09 02:48:02 PM PDT 24
Peak memory 204572 kb
Host smart-a62e978b-271c-48db-84c8-433ec6607fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17015
74627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.1701574627
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3276629423
Short name T979
Test name
Test status
Simulation time 8375344207 ps
CPU time 7.6 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204572 kb
Host smart-c690e8d1-334a-4d77-a880-fd99911155de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32766
29423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3276629423
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3660870152
Short name T296
Test name
Test status
Simulation time 8361512751 ps
CPU time 7.49 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204600 kb
Host smart-226ffd82-fb8c-4201-9341-f04890cd52f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608
70152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3660870152
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1347117935
Short name T1362
Test name
Test status
Simulation time 8461005228 ps
CPU time 9.68 seconds
Started May 09 02:47:50 PM PDT 24
Finished May 09 02:48:01 PM PDT 24
Peak memory 204540 kb
Host smart-b9d0cb6b-2739-44b0-ac30-5ffa4927dfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13471
17935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1347117935
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1670034752
Short name T877
Test name
Test status
Simulation time 8390664106 ps
CPU time 7.81 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:03 PM PDT 24
Peak memory 204572 kb
Host smart-69d43d0f-5b76-40fa-8ba2-a4420c5837b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16700
34752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1670034752
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1202617970
Short name T302
Test name
Test status
Simulation time 8389963059 ps
CPU time 9.85 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204588 kb
Host smart-08fe5ad3-ed8a-4ec4-8d36-dc249493f9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12026
17970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1202617970
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3428976950
Short name T309
Test name
Test status
Simulation time 8461533369 ps
CPU time 7.88 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204580 kb
Host smart-6255ffb5-40ba-48d4-85a7-c63ee81317b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3428976950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3428976950
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2695287654
Short name T635
Test name
Test status
Simulation time 8376238584 ps
CPU time 7.66 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:06 PM PDT 24
Peak memory 204496 kb
Host smart-3a341040-fbda-4992-a2df-98b355f61804
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2695287654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2695287654
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3877969866
Short name T754
Test name
Test status
Simulation time 8419363090 ps
CPU time 7.75 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204568 kb
Host smart-d0d190c8-bd5a-4e6b-8b35-d9e3c3b42f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779
69866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3877969866
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.4165587865
Short name T729
Test name
Test status
Simulation time 8375117811 ps
CPU time 7.94 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204588 kb
Host smart-760db5f9-9086-4d79-bb2a-82eb8df6dcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655
87865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.4165587865
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.4222682828
Short name T766
Test name
Test status
Simulation time 8383195317 ps
CPU time 7.85 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204400 kb
Host smart-0dd4fb0b-01c9-4546-9188-a2ef9670a45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42226
82828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.4222682828
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.4186402645
Short name T755
Test name
Test status
Simulation time 182650164 ps
CPU time 1.63 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:01 PM PDT 24
Peak memory 204720 kb
Host smart-5b26b784-01d9-4ec8-8660-4fdcae03133e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41864
02645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.4186402645
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1523400787
Short name T851
Test name
Test status
Simulation time 8410773599 ps
CPU time 9.31 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204576 kb
Host smart-8e4e483d-641c-4e09-ad3e-6636455377c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15234
00787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1523400787
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1607390162
Short name T1402
Test name
Test status
Simulation time 8380978267 ps
CPU time 7.4 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:06 PM PDT 24
Peak memory 204580 kb
Host smart-87c5ab7e-3b29-4005-9511-cd7fbbdddf62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16073
90162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1607390162
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.269035030
Short name T565
Test name
Test status
Simulation time 8399921914 ps
CPU time 8.33 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204552 kb
Host smart-87765217-e84e-4b9d-b0a9-68855af1e81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
5030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.269035030
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2954245075
Short name T1248
Test name
Test status
Simulation time 8413430129 ps
CPU time 8.55 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 204616 kb
Host smart-e9777bfc-bf89-4791-94fc-518f63462845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542
45075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2954245075
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.224216733
Short name T1354
Test name
Test status
Simulation time 8375353886 ps
CPU time 8.31 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204544 kb
Host smart-16bca915-bad8-4fa8-a02a-5918fac8fa8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22421
6733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.224216733
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2725574733
Short name T1323
Test name
Test status
Simulation time 8409506653 ps
CPU time 9.97 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:11 PM PDT 24
Peak memory 204524 kb
Host smart-208fbf87-ca5f-4339-a9ca-36aa6055a72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
74733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2725574733
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2037435074
Short name T1369
Test name
Test status
Simulation time 8376339942 ps
CPU time 7.77 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204580 kb
Host smart-392f09d3-35b6-440f-a3a1-978adcded716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20374
35074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2037435074
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.277332243
Short name T1385
Test name
Test status
Simulation time 8405057443 ps
CPU time 7.73 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204328 kb
Host smart-28c1e1fc-efb6-44b1-bf4e-231636ab5935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27733
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.277332243
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2267866530
Short name T13
Test name
Test status
Simulation time 8408101918 ps
CPU time 8.72 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204588 kb
Host smart-80720349-9e56-4421-9557-100d639dfcdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22678
66530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2267866530
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2090675948
Short name T411
Test name
Test status
Simulation time 115111393 ps
CPU time 0.75 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:00 PM PDT 24
Peak memory 204448 kb
Host smart-bcc1b490-522a-40bb-9978-64c1cf949246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20906
75948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2090675948
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3161011239
Short name T244
Test name
Test status
Simulation time 18207804241 ps
CPU time 33.01 seconds
Started May 09 02:47:57 PM PDT 24
Finished May 09 02:48:34 PM PDT 24
Peak memory 204724 kb
Host smart-7e72c920-98a9-40f1-a6e2-cd88770a9c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
11239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3161011239
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1650905244
Short name T858
Test name
Test status
Simulation time 8416136792 ps
CPU time 7.54 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204596 kb
Host smart-5b0e41d7-bd1b-4709-bf27-cba444f36c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16509
05244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1650905244
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.531507035
Short name T1056
Test name
Test status
Simulation time 8421481412 ps
CPU time 8.69 seconds
Started May 09 02:47:57 PM PDT 24
Finished May 09 02:48:10 PM PDT 24
Peak memory 204520 kb
Host smart-252570cf-effd-4bc3-8200-4e9fe49d03a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53150
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.531507035
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.3207222673
Short name T375
Test name
Test status
Simulation time 8401554179 ps
CPU time 9.28 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204584 kb
Host smart-31584f7c-65a3-4dc5-8ce0-f947f74445c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
22673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.3207222673
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.342259421
Short name T174
Test name
Test status
Simulation time 8466902204 ps
CPU time 8.19 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204608 kb
Host smart-15a5a1d3-d9ac-422c-92fc-0fee14a41b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34225
9421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.342259421
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1372199657
Short name T10
Test name
Test status
Simulation time 8370842597 ps
CPU time 8.25 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204356 kb
Host smart-fe279632-7244-4cad-83e2-9debe2834de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13721
99657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1372199657
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.360726472
Short name T1280
Test name
Test status
Simulation time 8464865094 ps
CPU time 8.4 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:05 PM PDT 24
Peak memory 204836 kb
Host smart-e388bba3-d21c-4dfd-a0e0-83177f6c0940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
6472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.360726472
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1708349952
Short name T546
Test name
Test status
Simulation time 8415699251 ps
CPU time 8.79 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204496 kb
Host smart-e92967e9-1afd-44ab-8a0a-64b4909cf65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17083
49952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1708349952
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1715858522
Short name T1170
Test name
Test status
Simulation time 8421014808 ps
CPU time 8.31 seconds
Started May 09 02:47:57 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204580 kb
Host smart-327d4359-5a67-4623-ac34-3993b822fe63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
58522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1715858522
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.669685150
Short name T58
Test name
Test status
Simulation time 8473427287 ps
CPU time 7.9 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204588 kb
Host smart-32c64b4a-a525-4e5d-96dd-7102671cd786
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=669685150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.669685150
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.1690557593
Short name T1252
Test name
Test status
Simulation time 8422129451 ps
CPU time 8.36 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204544 kb
Host smart-b55e9f31-c9a5-4a2b-908a-d5fa338f29b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1690557593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.1690557593
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.791554418
Short name T372
Test name
Test status
Simulation time 8447308506 ps
CPU time 8.43 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204588 kb
Host smart-0ece653d-0612-4daf-918a-0dcd9e233588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79155
4418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.791554418
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3210820448
Short name T1327
Test name
Test status
Simulation time 8378061410 ps
CPU time 8.3 seconds
Started May 09 02:47:58 PM PDT 24
Finished May 09 02:48:10 PM PDT 24
Peak memory 204596 kb
Host smart-0c8e0305-2593-4814-9bde-ae041ab4e653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32108
20448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3210820448
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3617683031
Short name T609
Test name
Test status
Simulation time 9332166182 ps
CPU time 13.24 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204836 kb
Host smart-d3062647-130f-4631-92fd-3ac8c35affcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36176
83031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3617683031
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_enable.703635440
Short name T461
Test name
Test status
Simulation time 8444447608 ps
CPU time 8.71 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204556 kb
Host smart-0d38b90d-319e-40fb-8087-eb6234a31d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70363
5440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.703635440
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1396604542
Short name T62
Test name
Test status
Simulation time 77699465 ps
CPU time 2.11 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:02 PM PDT 24
Peak memory 204736 kb
Host smart-7851a701-55fa-48c0-b184-7a892d174dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
04542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1396604542
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1547939344
Short name T712
Test name
Test status
Simulation time 8436011052 ps
CPU time 7.65 seconds
Started May 09 02:48:04 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 204508 kb
Host smart-e6d6559b-fd0a-4c20-bea4-6b7ef5168baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
39344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1547939344
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2112198845
Short name T490
Test name
Test status
Simulation time 8443402421 ps
CPU time 8.06 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204556 kb
Host smart-ce291106-1fb1-415d-9bb9-9e0e5849d050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21121
98845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2112198845
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1905623537
Short name T1345
Test name
Test status
Simulation time 8420494304 ps
CPU time 8.35 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204544 kb
Host smart-0f32f048-d5a8-4e06-b358-a75e4f3de5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19056
23537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1905623537
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.453899934
Short name T1334
Test name
Test status
Simulation time 8385287082 ps
CPU time 8.62 seconds
Started May 09 02:47:56 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204560 kb
Host smart-6a8e951d-5b1a-4df4-a068-42b89c4cb988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45389
9934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.453899934
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3628278410
Short name T101
Test name
Test status
Simulation time 8439147721 ps
CPU time 7.59 seconds
Started May 09 02:47:53 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204560 kb
Host smart-881710aa-aa04-42c1-80a1-ce30f560d720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
78410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3628278410
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2697266615
Short name T584
Test name
Test status
Simulation time 8403123339 ps
CPU time 8.91 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:14 PM PDT 24
Peak memory 204600 kb
Host smart-92d9af70-b08e-4858-ab62-b4900015aaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972
66615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2697266615
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2740897152
Short name T314
Test name
Test status
Simulation time 8416168799 ps
CPU time 7.91 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:06 PM PDT 24
Peak memory 204544 kb
Host smart-70f6c42a-4b3d-4646-bb51-a4ce7c70fa94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27408
97152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2740897152
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3596970804
Short name T80
Test name
Test status
Simulation time 8372697552 ps
CPU time 7.86 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204572 kb
Host smart-e429954e-0f01-4a58-af94-81b05835bcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35969
70804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3596970804
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1175153762
Short name T879
Test name
Test status
Simulation time 8370987352 ps
CPU time 7.85 seconds
Started May 09 02:47:57 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204568 kb
Host smart-37c3e50a-1bd0-4b22-bfd2-0695fcede076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11751
53762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1175153762
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3342878312
Short name T1053
Test name
Test status
Simulation time 31932030 ps
CPU time 0.66 seconds
Started May 09 02:48:00 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204544 kb
Host smart-073e68ca-93c7-4afb-b698-99ccf04bb5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33428
78312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3342878312
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1805992791
Short name T844
Test name
Test status
Simulation time 14674432752 ps
CPU time 23.6 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204816 kb
Host smart-be5a3aba-3672-4715-a2b9-88ead1a70c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18059
92791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1805992791
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1703371773
Short name T549
Test name
Test status
Simulation time 8399694649 ps
CPU time 9.27 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204512 kb
Host smart-3f6d1be8-b188-4fa6-9668-f4922946f7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
71773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1703371773
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1038231624
Short name T152
Test name
Test status
Simulation time 8459582844 ps
CPU time 8.41 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204488 kb
Host smart-6e13bc59-642d-45e4-9504-291aa353f181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382
31624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1038231624
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1206050805
Short name T507
Test name
Test status
Simulation time 8379095798 ps
CPU time 7.48 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:07 PM PDT 24
Peak memory 204600 kb
Host smart-fdf8f5b2-f422-4b1f-b17b-c22594fc5e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
50805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1206050805
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3751305929
Short name T1123
Test name
Test status
Simulation time 8379945391 ps
CPU time 7.62 seconds
Started May 09 02:47:52 PM PDT 24
Finished May 09 02:48:04 PM PDT 24
Peak memory 204820 kb
Host smart-a16069a6-cda6-44c1-9b6d-6a5502f0f411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513
05929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3751305929
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1957491143
Short name T366
Test name
Test status
Simulation time 8369852155 ps
CPU time 8.02 seconds
Started May 09 02:47:58 PM PDT 24
Finished May 09 02:48:09 PM PDT 24
Peak memory 204572 kb
Host smart-b981ad28-8fbf-46d4-97a5-45855357d327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19574
91143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1957491143
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4246626205
Short name T477
Test name
Test status
Simulation time 8451353147 ps
CPU time 9.17 seconds
Started May 09 02:47:54 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204372 kb
Host smart-ce5cf96a-e85c-4649-b61f-338c2d28dbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42466
26205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4246626205
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2120045110
Short name T854
Test name
Test status
Simulation time 8410380509 ps
CPU time 9.72 seconds
Started May 09 02:47:55 PM PDT 24
Finished May 09 02:48:10 PM PDT 24
Peak memory 204560 kb
Host smart-6e729f56-c5f4-4132-b397-ed647a67667c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21200
45110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2120045110
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2251027993
Short name T1016
Test name
Test status
Simulation time 8385686249 ps
CPU time 7.92 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:12 PM PDT 24
Peak memory 204608 kb
Host smart-81125e1b-a2d7-47c0-83cb-c6c1dcba000a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
27993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2251027993
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1657535760
Short name T349
Test name
Test status
Simulation time 8463980334 ps
CPU time 8.48 seconds
Started May 09 02:48:09 PM PDT 24
Finished May 09 02:48:23 PM PDT 24
Peak memory 204560 kb
Host smart-befdb53b-0e13-4632-b754-6c9e2b54d1d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1657535760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1657535760
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.2655738697
Short name T881
Test name
Test status
Simulation time 8380796627 ps
CPU time 7.34 seconds
Started May 09 02:48:06 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204560 kb
Host smart-35011c57-443c-49dd-828a-ff61b02e2aa6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2655738697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.2655738697
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.4163445528
Short name T299
Test name
Test status
Simulation time 8433077182 ps
CPU time 7.95 seconds
Started May 09 02:48:06 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204372 kb
Host smart-3e1089b8-ca64-454b-a059-240f55349c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41634
45528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.4163445528
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2991591948
Short name T1219
Test name
Test status
Simulation time 8378182109 ps
CPU time 8.62 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:21 PM PDT 24
Peak memory 204576 kb
Host smart-9acce165-596b-4d8e-9413-ceede52e9d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
91948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2991591948
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3825524982
Short name T1306
Test name
Test status
Simulation time 8603909309 ps
CPU time 11.59 seconds
Started May 09 02:48:08 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204820 kb
Host smart-89b9ab5c-9589-4f12-9eb1-62a5003201d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
24982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3825524982
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_enable.3003699649
Short name T1023
Test name
Test status
Simulation time 8378407824 ps
CPU time 7.56 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204520 kb
Host smart-3382711f-4749-44f9-92d8-e87e38ec35a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
99649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3003699649
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.4011631535
Short name T145
Test name
Test status
Simulation time 8445549570 ps
CPU time 8.73 seconds
Started May 09 02:48:03 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 204532 kb
Host smart-4ee5b404-057d-4b4f-9c3e-743425c7f9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40116
31535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.4011631535
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2019606773
Short name T724
Test name
Test status
Simulation time 8369699452 ps
CPU time 7.58 seconds
Started May 09 02:48:04 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 204596 kb
Host smart-af4b564e-e9cb-4131-90a6-40f50493c53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20196
06773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2019606773
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.326059354
Short name T1222
Test name
Test status
Simulation time 8454225395 ps
CPU time 8.28 seconds
Started May 09 02:48:04 PM PDT 24
Finished May 09 02:48:17 PM PDT 24
Peak memory 204604 kb
Host smart-82ba73b7-78e9-4163-8820-40de3b53ff89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32605
9354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.326059354
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3938334330
Short name T425
Test name
Test status
Simulation time 8455920112 ps
CPU time 7.66 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:11 PM PDT 24
Peak memory 204616 kb
Host smart-18d5f60a-0f6b-4d51-9135-8135ad8366ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39383
34330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3938334330
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2189922543
Short name T1145
Test name
Test status
Simulation time 8393021165 ps
CPU time 9.56 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:21 PM PDT 24
Peak memory 204572 kb
Host smart-92504fb1-37eb-47d6-9932-9c52eed76f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21899
22543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2189922543
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.786995300
Short name T38
Test name
Test status
Simulation time 8391902378 ps
CPU time 10.07 seconds
Started May 09 02:48:08 PM PDT 24
Finished May 09 02:48:23 PM PDT 24
Peak memory 204548 kb
Host smart-557b53b5-3713-4dc6-928d-a8e3fe75d8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78699
5300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.786995300
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.489258725
Short name T358
Test name
Test status
Simulation time 8379559628 ps
CPU time 8.41 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204512 kb
Host smart-534ca914-7ab4-4ac2-bd72-161eaed3c8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48925
8725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.489258725
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4064623591
Short name T1109
Test name
Test status
Simulation time 8385507544 ps
CPU time 7.71 seconds
Started May 09 02:48:04 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 204508 kb
Host smart-72b2b946-d158-4f89-83a2-bb6fa9ef7ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40646
23591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4064623591
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.104721681
Short name T954
Test name
Test status
Simulation time 8364863208 ps
CPU time 8.63 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204572 kb
Host smart-a57148cf-74bb-4503-912e-06bfef2f52cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
1681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.104721681
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2834208927
Short name T1131
Test name
Test status
Simulation time 36444265 ps
CPU time 0.65 seconds
Started May 09 02:48:08 PM PDT 24
Finished May 09 02:48:15 PM PDT 24
Peak memory 204516 kb
Host smart-0eae98b2-d3df-45d3-89d3-4a18c7af7f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342
08927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2834208927
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2762618949
Short name T995
Test name
Test status
Simulation time 25183542956 ps
CPU time 49.94 seconds
Started May 09 02:48:01 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204656 kb
Host smart-18e29748-97aa-41de-b63e-95a2cdfa5b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27626
18949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2762618949
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.747557409
Short name T1380
Test name
Test status
Simulation time 8418553885 ps
CPU time 8.01 seconds
Started May 09 02:48:04 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 204568 kb
Host smart-ed99e84a-449a-41be-8bc3-a1571003c59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74755
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.747557409
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1704388992
Short name T1235
Test name
Test status
Simulation time 8414803424 ps
CPU time 9.51 seconds
Started May 09 02:48:09 PM PDT 24
Finished May 09 02:48:24 PM PDT 24
Peak memory 204560 kb
Host smart-eb854c3d-0b23-45e8-a471-adabc1428400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17043
88992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1704388992
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.896532183
Short name T327
Test name
Test status
Simulation time 8413084038 ps
CPU time 8.69 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:14 PM PDT 24
Peak memory 204516 kb
Host smart-184e4df6-95b9-471a-ba60-b7af55187c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89653
2183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.896532183
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2367501911
Short name T171
Test name
Test status
Simulation time 8373183630 ps
CPU time 7.48 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:17 PM PDT 24
Peak memory 204540 kb
Host smart-69938418-b15e-4b45-ba29-59fa2662873d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
01911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2367501911
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2526986747
Short name T504
Test name
Test status
Simulation time 8372228015 ps
CPU time 8.6 seconds
Started May 09 02:48:06 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204536 kb
Host smart-7c5f57e3-7135-4de3-b96b-7818ee56a717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25269
86747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2526986747
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1618418065
Short name T777
Test name
Test status
Simulation time 8449402374 ps
CPU time 7.73 seconds
Started May 09 02:48:02 PM PDT 24
Finished May 09 02:48:13 PM PDT 24
Peak memory 204480 kb
Host smart-708c9ebe-da6d-4fb8-984c-f2bf03fd4bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16184
18065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1618418065
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1161840557
Short name T544
Test name
Test status
Simulation time 8401341793 ps
CPU time 8.06 seconds
Started May 09 02:48:08 PM PDT 24
Finished May 09 02:48:21 PM PDT 24
Peak memory 204560 kb
Host smart-67e0f947-6fa6-4d4e-a909-ed5638012478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11618
40557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1161840557
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2885522736
Short name T929
Test name
Test status
Simulation time 8409182791 ps
CPU time 7.76 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204524 kb
Host smart-9e615909-f011-411e-8471-169c9bcd4066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28855
22736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2885522736
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.2222915103
Short name T501
Test name
Test status
Simulation time 8482922219 ps
CPU time 8.15 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:25 PM PDT 24
Peak memory 204548 kb
Host smart-6b6da711-029b-4fbb-95ba-cf3b583a29d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2222915103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.2222915103
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3998373507
Short name T334
Test name
Test status
Simulation time 8395092534 ps
CPU time 8.93 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204544 kb
Host smart-f06c4b2a-4300-4a01-9740-35d2ebf5ce04
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3998373507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3998373507
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.4135616540
Short name T316
Test name
Test status
Simulation time 8477099887 ps
CPU time 10.04 seconds
Started May 09 02:48:03 PM PDT 24
Finished May 09 02:48:16 PM PDT 24
Peak memory 204560 kb
Host smart-a89cf6ff-ff54-4b38-8eb0-1ba1bdaa1d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41356
16540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.4135616540
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1864607037
Short name T791
Test name
Test status
Simulation time 8406994663 ps
CPU time 7.7 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:24 PM PDT 24
Peak memory 204608 kb
Host smart-f097fa20-140f-48cb-b42c-0c16903408f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18646
07037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1864607037
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2981076686
Short name T392
Test name
Test status
Simulation time 8788519028 ps
CPU time 12.83 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:22 PM PDT 24
Peak memory 204816 kb
Host smart-16327c74-bce4-4825-b2d7-a2acd206a8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29810
76686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2981076686
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_enable.2283331739
Short name T1274
Test name
Test status
Simulation time 8391251283 ps
CPU time 8.69 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204400 kb
Host smart-c00e61cf-85ce-4afc-8966-23f02cd6f9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833
31739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2283331739
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1865564238
Short name T1063
Test name
Test status
Simulation time 96046258 ps
CPU time 1.19 seconds
Started May 09 02:48:06 PM PDT 24
Finished May 09 02:48:11 PM PDT 24
Peak memory 204544 kb
Host smart-fe337ddb-8c6a-4e6e-9e1e-ed859d28385e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18655
64238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1865564238
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.475133939
Short name T780
Test name
Test status
Simulation time 8446946175 ps
CPU time 8.25 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204548 kb
Host smart-df0d2cfd-0afb-4dd2-b4e9-f625d005b400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47513
3939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.475133939
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1657395293
Short name T857
Test name
Test status
Simulation time 8364763214 ps
CPU time 8.85 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204556 kb
Host smart-220e8a4c-ba33-4744-b153-74ec7402f183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16573
95293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1657395293
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3440497169
Short name T1033
Test name
Test status
Simulation time 8479015377 ps
CPU time 10.04 seconds
Started May 09 02:48:09 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204596 kb
Host smart-c70625c6-09cf-4038-9248-0f476e494a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34404
97169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3440497169
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2027532950
Short name T1176
Test name
Test status
Simulation time 8417242663 ps
CPU time 8.05 seconds
Started May 09 02:48:06 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 204572 kb
Host smart-a0b09195-4759-434c-b364-3900abbaa08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
32950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2027532950
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1334388074
Short name T1097
Test name
Test status
Simulation time 8370824336 ps
CPU time 8.02 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:24 PM PDT 24
Peak memory 204596 kb
Host smart-3528d325-7fa9-4819-aabc-4da54ced934c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
88074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1334388074
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3460854565
Short name T1082
Test name
Test status
Simulation time 8480655072 ps
CPU time 7.69 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:17 PM PDT 24
Peak memory 204560 kb
Host smart-fa6ad2a7-1619-4431-9b21-1ae08b25f026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
54565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3460854565
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1578515098
Short name T739
Test name
Test status
Simulation time 8405441161 ps
CPU time 8 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:24 PM PDT 24
Peak memory 204592 kb
Host smart-c5a846e7-08d5-4765-93a7-b5e5d15ecf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15785
15098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1578515098
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2499826139
Short name T163
Test name
Test status
Simulation time 8407776171 ps
CPU time 8.2 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:25 PM PDT 24
Peak memory 204552 kb
Host smart-08b60646-11f3-49e1-b8e7-661b6fb84b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24998
26139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2499826139
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3680129629
Short name T561
Test name
Test status
Simulation time 66447809 ps
CPU time 0.68 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204500 kb
Host smart-94ca6223-586b-4bff-b0db-ffb8eaeed519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
29629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3680129629
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1551193824
Short name T1341
Test name
Test status
Simulation time 19728143937 ps
CPU time 38.75 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:58 PM PDT 24
Peak memory 204764 kb
Host smart-9e4a8ea4-47d7-4f4f-8c57-5046cc5c0326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15511
93824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1551193824
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4182388158
Short name T815
Test name
Test status
Simulation time 8403851245 ps
CPU time 9.66 seconds
Started May 09 02:48:05 PM PDT 24
Finished May 09 02:48:19 PM PDT 24
Peak memory 204588 kb
Host smart-959a93e9-5c2c-4734-bc17-1bb1285be2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41823
88158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4182388158
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3463712391
Short name T510
Test name
Test status
Simulation time 8409929761 ps
CPU time 8.88 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204560 kb
Host smart-821ace37-9134-4cf2-9031-dc4691bdca6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
12391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3463712391
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2407325110
Short name T395
Test name
Test status
Simulation time 8415789092 ps
CPU time 8.76 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:25 PM PDT 24
Peak memory 204628 kb
Host smart-be49ebd0-b973-4bae-bfe7-574f42f9a8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
25110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2407325110
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.765876474
Short name T1332
Test name
Test status
Simulation time 8368746821 ps
CPU time 7.59 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:27 PM PDT 24
Peak memory 204568 kb
Host smart-4146b7f5-3a82-4582-b372-8fccef23085a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76587
6474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.765876474
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.322736123
Short name T1158
Test name
Test status
Simulation time 8387139482 ps
CPU time 9.62 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204548 kb
Host smart-fb91403e-52c8-48c3-ade5-66a15263875d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32273
6123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.322736123
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.550043239
Short name T667
Test name
Test status
Simulation time 8475125161 ps
CPU time 8.19 seconds
Started May 09 02:48:08 PM PDT 24
Finished May 09 02:48:21 PM PDT 24
Peak memory 204584 kb
Host smart-6ecccbb9-c3c3-4f4a-a624-062657a5a3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55004
3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.550043239
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2854556426
Short name T1035
Test name
Test status
Simulation time 8423684719 ps
CPU time 7.94 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204564 kb
Host smart-42c212c6-b88f-490d-899c-e9dc93f13a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
56426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2854556426
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2797971752
Short name T308
Test name
Test status
Simulation time 8396803826 ps
CPU time 7.79 seconds
Started May 09 02:48:07 PM PDT 24
Finished May 09 02:48:19 PM PDT 24
Peak memory 204576 kb
Host smart-13bdd845-aa51-4132-b4f8-7c61604c85e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27979
71752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2797971752
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.1347312632
Short name T868
Test name
Test status
Simulation time 8506057807 ps
CPU time 7.65 seconds
Started May 09 02:48:15 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204552 kb
Host smart-c42bf435-c3fe-4db6-aef5-2221b11f29df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1347312632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.1347312632
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.3067638438
Short name T817
Test name
Test status
Simulation time 8381494565 ps
CPU time 8.28 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204548 kb
Host smart-dd11f088-b613-4352-955d-9f18727b5d56
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3067638438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.3067638438
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.3781828304
Short name T779
Test name
Test status
Simulation time 8389984494 ps
CPU time 8.27 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204576 kb
Host smart-5c03ed6e-d467-4218-9f9b-c047dbb13a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37818
28304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.3781828304
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2136878993
Short name T1377
Test name
Test status
Simulation time 8379153106 ps
CPU time 8.09 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 203736 kb
Host smart-c520a921-4e9f-4a0d-8ad4-b2190793ebc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21368
78993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2136878993
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1304937085
Short name T629
Test name
Test status
Simulation time 9187276382 ps
CPU time 12.83 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:33 PM PDT 24
Peak memory 204840 kb
Host smart-bc73fee1-872c-4f77-8ff6-b22a8ff552c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
37085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1304937085
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_enable.1408259139
Short name T520
Test name
Test status
Simulation time 8387126739 ps
CPU time 7.63 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204588 kb
Host smart-5de882d0-f78e-446a-be21-b4953fdfa9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14082
59139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1408259139
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1887560480
Short name T610
Test name
Test status
Simulation time 78968734 ps
CPU time 1.11 seconds
Started May 09 02:48:03 PM PDT 24
Finished May 09 02:48:08 PM PDT 24
Peak memory 204752 kb
Host smart-566a7901-f92d-4b5c-9803-6eedded63130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18875
60480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1887560480
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2761689380
Short name T1417
Test name
Test status
Simulation time 8399524817 ps
CPU time 8.54 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204576 kb
Host smart-b63e0a40-c7df-4b7b-90c3-5e9865da234f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27616
89380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2761689380
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1709328568
Short name T1139
Test name
Test status
Simulation time 8367931259 ps
CPU time 7.43 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204524 kb
Host smart-62a32d14-978b-4a81-b233-d2b8ea1635e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
28568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1709328568
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2209183941
Short name T599
Test name
Test status
Simulation time 8436408011 ps
CPU time 8.66 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204580 kb
Host smart-1e06a8b9-7cbf-4a0d-a11d-c0d64e03d709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
83941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2209183941
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2806235800
Short name T1287
Test name
Test status
Simulation time 8419657670 ps
CPU time 8.07 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204596 kb
Host smart-429b0cdc-efab-42a8-9d44-f02602bb6b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28062
35800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2806235800
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3756201687
Short name T798
Test name
Test status
Simulation time 8369032040 ps
CPU time 7.48 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204424 kb
Host smart-3c32b1fc-b7b9-431d-99c0-5402beb5d6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
01687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3756201687
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2387390761
Short name T126
Test name
Test status
Simulation time 8444647291 ps
CPU time 7.5 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204536 kb
Host smart-96244c2f-a631-4393-b027-a14431defa1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
90761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2387390761
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2268816716
Short name T1349
Test name
Test status
Simulation time 8409444604 ps
CPU time 7.64 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:27 PM PDT 24
Peak memory 204540 kb
Host smart-032d7329-efa8-4ab0-8bb9-c5febae13c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22688
16716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2268816716
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2082209919
Short name T656
Test name
Test status
Simulation time 8475308181 ps
CPU time 8.84 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204576 kb
Host smart-9d01bf34-277f-4d9f-ac6f-38bc44dbdf99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
09919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2082209919
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2903596871
Short name T32
Test name
Test status
Simulation time 8413073228 ps
CPU time 7.59 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:25 PM PDT 24
Peak memory 204568 kb
Host smart-2c2aa032-30ce-4c92-99a3-b656d418b141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035
96871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2903596871
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1679114654
Short name T1169
Test name
Test status
Simulation time 8371430845 ps
CPU time 7.58 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204336 kb
Host smart-c990cafc-2ff8-494c-845a-28e6ffa46bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16791
14654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1679114654
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3196004408
Short name T364
Test name
Test status
Simulation time 193094221 ps
CPU time 0.84 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:20 PM PDT 24
Peak memory 204468 kb
Host smart-c4b556eb-a005-495d-86b5-10b4663da09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31960
04408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3196004408
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3454174118
Short name T1200
Test name
Test status
Simulation time 21139438617 ps
CPU time 38.22 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204740 kb
Host smart-172af08d-d25e-4d9b-b24b-40325050ee26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34541
74118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3454174118
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2787081077
Short name T914
Test name
Test status
Simulation time 8390495282 ps
CPU time 8.4 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:27 PM PDT 24
Peak memory 204564 kb
Host smart-b308fecf-e3da-4a77-8b1d-509b1772fcc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27870
81077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2787081077
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.47646352
Short name T1058
Test name
Test status
Simulation time 8452941281 ps
CPU time 7.46 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 203616 kb
Host smart-cc3c9e6c-e903-4241-8eaf-da72e758481a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47646
352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.47646352
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.3633864362
Short name T736
Test name
Test status
Simulation time 8406021463 ps
CPU time 9.7 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204556 kb
Host smart-816b14d4-9f28-4019-bf79-22f706f0db59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338
64362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.3633864362
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1504992424
Short name T1299
Test name
Test status
Simulation time 8390564014 ps
CPU time 7.43 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204544 kb
Host smart-2b8f9cb0-7f8d-4471-9f63-58de3b839c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15049
92424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1504992424
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.760889975
Short name T591
Test name
Test status
Simulation time 8376185056 ps
CPU time 9.05 seconds
Started May 09 02:48:04 PM PDT 24
Finished May 09 02:48:17 PM PDT 24
Peak memory 204516 kb
Host smart-d3a7f178-e869-4e84-aba8-927484cb1a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76088
9975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.760889975
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2571629979
Short name T1240
Test name
Test status
Simulation time 8487431735 ps
CPU time 8.92 seconds
Started May 09 02:48:10 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204568 kb
Host smart-70693732-3d63-4fae-b981-ec127a806754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25716
29979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2571629979
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2244865661
Short name T862
Test name
Test status
Simulation time 8412623749 ps
CPU time 8.2 seconds
Started May 09 02:48:12 PM PDT 24
Finished May 09 02:48:27 PM PDT 24
Peak memory 204544 kb
Host smart-caec998a-208a-4fb4-93e3-5eb787461b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
65661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2244865661
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1473975593
Short name T1049
Test name
Test status
Simulation time 8431833037 ps
CPU time 7.89 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204540 kb
Host smart-213a7b89-4b14-4cc6-a6b5-a70bb0af57be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
75593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1473975593
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3437898793
Short name T485
Test name
Test status
Simulation time 8470889632 ps
CPU time 9.15 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204484 kb
Host smart-4c03fbe7-9f9f-4eb1-aa9a-09d9734c3dea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3437898793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3437898793
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.321961045
Short name T676
Test name
Test status
Simulation time 8380484040 ps
CPU time 7.69 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 204492 kb
Host smart-5924be90-fe23-4a87-a772-ea65bb8e549c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=321961045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.321961045
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.1839771611
Short name T952
Test name
Test status
Simulation time 8447377095 ps
CPU time 8.19 seconds
Started May 09 02:48:15 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204524 kb
Host smart-95a611ac-10b1-49db-9414-4407c8d2ac1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18397
71611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.1839771611
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.372669205
Short name T400
Test name
Test status
Simulation time 8378639711 ps
CPU time 7.7 seconds
Started May 09 02:48:11 PM PDT 24
Finished May 09 02:48:26 PM PDT 24
Peak memory 204568 kb
Host smart-af02855c-2ca6-4ffb-b966-8181baa34b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
9205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.372669205
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3596469388
Short name T199
Test name
Test status
Simulation time 9150173097 ps
CPU time 13.53 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:35 PM PDT 24
Peak memory 204764 kb
Host smart-ed09ba8f-0c01-42b5-859e-0298355afd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35964
69388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3596469388
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_enable.229550190
Short name T1348
Test name
Test status
Simulation time 8388076068 ps
CPU time 7.99 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204560 kb
Host smart-9f5c6927-4441-488b-b66d-f91b0b67f514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22955
0190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.229550190
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.4010636867
Short name T1390
Test name
Test status
Simulation time 166959659 ps
CPU time 1.77 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:23 PM PDT 24
Peak memory 204712 kb
Host smart-71b3ee29-a105-44e0-9480-bfac2c86c18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40106
36867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.4010636867
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.817444964
Short name T1059
Test name
Test status
Simulation time 8432888981 ps
CPU time 7.54 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 204488 kb
Host smart-88ff4fb6-b2d5-4031-813c-d67394d21dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81744
4964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.817444964
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.34674251
Short name T742
Test name
Test status
Simulation time 8383033163 ps
CPU time 9.29 seconds
Started May 09 02:48:26 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204488 kb
Host smart-3efa8daa-83be-478e-8140-bcc1127639fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674
251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.34674251
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3469480397
Short name T596
Test name
Test status
Simulation time 8391636636 ps
CPU time 8.13 seconds
Started May 09 02:48:13 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 204504 kb
Host smart-ce8fe477-0324-4bdc-861a-4f32d1e59879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34694
80397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3469480397
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3126576446
Short name T1220
Test name
Test status
Simulation time 8421608583 ps
CPU time 7.91 seconds
Started May 09 02:48:15 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204592 kb
Host smart-3bbb88a2-d61a-4e22-86c9-4f7872d7f30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
76446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3126576446
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3957662943
Short name T989
Test name
Test status
Simulation time 8374506267 ps
CPU time 10.17 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:33 PM PDT 24
Peak memory 204560 kb
Host smart-714b82a2-2aef-45b8-9a35-90d426cd3918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39576
62943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3957662943
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2051697526
Short name T964
Test name
Test status
Simulation time 8444822521 ps
CPU time 8.13 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204576 kb
Host smart-3fca3bd5-5011-46fc-aaf2-4557d42783af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20516
97526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2051697526
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.530770210
Short name T223
Test name
Test status
Simulation time 8439963506 ps
CPU time 10.15 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204584 kb
Host smart-9fba234e-19a5-4d3c-b488-8993fd41fe54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53077
0210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.530770210
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1691401900
Short name T823
Test name
Test status
Simulation time 8384461181 ps
CPU time 7.31 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204560 kb
Host smart-92d961a3-5ee9-4205-b720-2105c29a2051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
01900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1691401900
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.287898011
Short name T186
Test name
Test status
Simulation time 8472161790 ps
CPU time 7.68 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:39 PM PDT 24
Peak memory 204488 kb
Host smart-64303ae9-c609-4fb3-ba03-c610a5c3c3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
8011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.287898011
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1449003108
Short name T406
Test name
Test status
Simulation time 8372248704 ps
CPU time 7.71 seconds
Started May 09 02:48:18 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204540 kb
Host smart-21531a73-2eb2-4432-84c4-c310888548bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14490
03108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1449003108
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1678021687
Short name T41
Test name
Test status
Simulation time 49620208 ps
CPU time 0.73 seconds
Started May 09 02:48:17 PM PDT 24
Finished May 09 02:48:23 PM PDT 24
Peak memory 204524 kb
Host smart-2d37edca-0acd-455e-924d-ae9a5c246db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780
21687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1678021687
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1305476837
Short name T17
Test name
Test status
Simulation time 18864013601 ps
CPU time 34.26 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204720 kb
Host smart-77488e59-1485-410b-b38b-da9e7ab331fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13054
76837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1305476837
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1660491495
Short name T1208
Test name
Test status
Simulation time 8381029999 ps
CPU time 7.96 seconds
Started May 09 02:48:18 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204568 kb
Host smart-f0beed9f-d471-475c-9bb1-2ee7d10a4d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16604
91495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1660491495
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1739455660
Short name T751
Test name
Test status
Simulation time 8445174955 ps
CPU time 8.03 seconds
Started May 09 02:48:17 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204556 kb
Host smart-9b42a846-9166-4ef0-af3b-7a909d746f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17394
55660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1739455660
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.1616711354
Short name T509
Test name
Test status
Simulation time 8510422063 ps
CPU time 8.9 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204464 kb
Host smart-c0bd7e5a-c4ab-41ab-89ea-2216e247afba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16167
11354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.1616711354
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2720023641
Short name T837
Test name
Test status
Simulation time 8432218622 ps
CPU time 9.62 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204820 kb
Host smart-6b7c2d7a-2c7a-4a1a-90e4-13649de1e8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27200
23641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2720023641
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3055815341
Short name T969
Test name
Test status
Simulation time 8368680122 ps
CPU time 7.98 seconds
Started May 09 02:48:19 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204532 kb
Host smart-0a41efe9-09f3-426e-8f83-d17fc796ce20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30558
15341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3055815341
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.86665321
Short name T1085
Test name
Test status
Simulation time 8447064351 ps
CPU time 9.27 seconds
Started May 09 02:48:17 PM PDT 24
Finished May 09 02:48:32 PM PDT 24
Peak memory 204576 kb
Host smart-cd827f79-eeaa-4fea-837e-cfe541caf5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86665
321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.86665321
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1172191047
Short name T1241
Test name
Test status
Simulation time 8417287468 ps
CPU time 8.83 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204592 kb
Host smart-4a098cba-8267-40db-bab7-b2d424eaadbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11721
91047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1172191047
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2345159909
Short name T424
Test name
Test status
Simulation time 8484056610 ps
CPU time 7.79 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:29 PM PDT 24
Peak memory 204540 kb
Host smart-41e3b02e-7601-4053-928c-cc0492b843e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
59909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2345159909
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.2271335690
Short name T843
Test name
Test status
Simulation time 8472809072 ps
CPU time 9.26 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204520 kb
Host smart-ba635359-a95a-403e-8dac-f87e8f0a9346
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2271335690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.2271335690
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.377094594
Short name T1336
Test name
Test status
Simulation time 8380893595 ps
CPU time 7.61 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:37 PM PDT 24
Peak memory 204576 kb
Host smart-0f5e57d3-049d-4183-ad33-85053a991441
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=377094594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.377094594
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.1165647747
Short name T728
Test name
Test status
Simulation time 8395986540 ps
CPU time 7.92 seconds
Started May 09 02:48:26 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204580 kb
Host smart-0590f929-9606-4176-bdee-1d4c5cb617de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
47747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.1165647747
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3878170075
Short name T523
Test name
Test status
Simulation time 8382071897 ps
CPU time 7.5 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:39 PM PDT 24
Peak memory 204504 kb
Host smart-7f573c5b-be2f-4ccd-be82-27a12dae0eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
70075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3878170075
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3239942970
Short name T1415
Test name
Test status
Simulation time 9116038796 ps
CPU time 12.32 seconds
Started May 09 02:48:15 PM PDT 24
Finished May 09 02:48:34 PM PDT 24
Peak memory 204776 kb
Host smart-a4f3b8a0-834e-496a-a649-b7b8977db13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32399
42970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3239942970
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_enable.2694814899
Short name T1126
Test name
Test status
Simulation time 8371165863 ps
CPU time 8.25 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:39 PM PDT 24
Peak memory 204504 kb
Host smart-20d2afe1-3972-448c-9603-4eaa3fbbd98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
14899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2694814899
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2434937600
Short name T5
Test name
Test status
Simulation time 99242763 ps
CPU time 1.25 seconds
Started May 09 02:48:14 PM PDT 24
Finished May 09 02:48:22 PM PDT 24
Peak memory 204740 kb
Host smart-fc6bde00-fe9a-4d4b-b0bd-8283d04f90b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24349
37600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2434937600
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2039973347
Short name T1267
Test name
Test status
Simulation time 8405989547 ps
CPU time 8.11 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:39 PM PDT 24
Peak memory 204508 kb
Host smart-9622d14c-d2c0-4dd9-8934-8fa163f193f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20399
73347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2039973347
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.828363584
Short name T206
Test name
Test status
Simulation time 8372840399 ps
CPU time 8.05 seconds
Started May 09 02:48:26 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204572 kb
Host smart-f6cc0bad-bf86-473e-be2a-3ac7a710b4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82836
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.828363584
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1640420645
Short name T1076
Test name
Test status
Simulation time 8413580997 ps
CPU time 8.05 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204572 kb
Host smart-ad1642a3-b883-4881-b013-c74209f74faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
20645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1640420645
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1973358406
Short name T1322
Test name
Test status
Simulation time 8418260149 ps
CPU time 7.98 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204508 kb
Host smart-723172fe-9406-4598-81bb-30f6e58b8941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19733
58406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1973358406
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1689387446
Short name T642
Test name
Test status
Simulation time 8442882860 ps
CPU time 8.54 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204608 kb
Host smart-224e2bd8-2741-4ec3-9bc6-1411b2878ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
87446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1689387446
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2154008344
Short name T129
Test name
Test status
Simulation time 8422772983 ps
CPU time 8.21 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204524 kb
Host smart-f2a2c127-e77e-43ca-8e8b-c2ab9fab6bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
08344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2154008344
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.4077676442
Short name T892
Test name
Test status
Simulation time 8405345886 ps
CPU time 8.09 seconds
Started May 09 02:48:16 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204576 kb
Host smart-490f5b14-eabc-4e73-babc-d8cc73ecab4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
76442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.4077676442
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1457667999
Short name T577
Test name
Test status
Simulation time 8399210247 ps
CPU time 10.35 seconds
Started May 09 02:48:15 PM PDT 24
Finished May 09 02:48:32 PM PDT 24
Peak memory 204536 kb
Host smart-4886b687-2730-4c51-a990-5c97ddc7617f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14576
67999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1457667999
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.874937777
Short name T709
Test name
Test status
Simulation time 8410543686 ps
CPU time 8.43 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:37 PM PDT 24
Peak memory 204508 kb
Host smart-f4219486-f684-48a1-b1ac-1c69d8d86efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87493
7777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.874937777
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3151126131
Short name T1068
Test name
Test status
Simulation time 8413313292 ps
CPU time 8.93 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:37 PM PDT 24
Peak memory 204560 kb
Host smart-f2aa77dd-bec1-4ed2-8eb6-241bffb71728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31511
26131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3151126131
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3534662230
Short name T42
Test name
Test status
Simulation time 58981943 ps
CPU time 0.69 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204544 kb
Host smart-ac905113-955a-47ba-a82f-21bae1a0444e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346
62230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3534662230
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.758219967
Short name T1079
Test name
Test status
Simulation time 14267526809 ps
CPU time 25.02 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204792 kb
Host smart-c721dc79-11a0-48d7-a660-a31a23733ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75821
9967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.758219967
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2280648979
Short name T1350
Test name
Test status
Simulation time 8399607324 ps
CPU time 8.69 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204604 kb
Host smart-9bcfcade-a312-41cb-b9cd-4ce5ce91b2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22806
48979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2280648979
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.841743997
Short name T765
Test name
Test status
Simulation time 8485121792 ps
CPU time 8.38 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204592 kb
Host smart-2354e59a-7268-4b27-a871-89ace0c3c754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84174
3997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.841743997
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2663343276
Short name T864
Test name
Test status
Simulation time 8414650383 ps
CPU time 9.19 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 204576 kb
Host smart-21887610-5b6a-45b9-b841-6a36aceba6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26633
43276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2663343276
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.478129863
Short name T81
Test name
Test status
Simulation time 8413143907 ps
CPU time 9.9 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204528 kb
Host smart-311c8e15-8953-4c62-b636-0d309b760992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47812
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.478129863
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.304343218
Short name T938
Test name
Test status
Simulation time 8375926988 ps
CPU time 8 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:37 PM PDT 24
Peak memory 204616 kb
Host smart-23120592-0f47-41ea-a645-af1f368bc0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30434
3218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.304343218
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1956929515
Short name T759
Test name
Test status
Simulation time 8462891638 ps
CPU time 8.19 seconds
Started May 09 02:48:15 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 204620 kb
Host smart-7fb2b504-e35c-449e-a6ce-6eea01293a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569
29515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1956929515
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3656197416
Short name T371
Test name
Test status
Simulation time 8396283493 ps
CPU time 8.26 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204604 kb
Host smart-2800a5cd-af8d-4ebc-b8ec-845f6b4dd977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36561
97416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3656197416
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.4127757752
Short name T1230
Test name
Test status
Simulation time 8408608489 ps
CPU time 8.21 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204544 kb
Host smart-03d21ae1-ff59-4cad-8443-35a42677934d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41277
57752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.4127757752
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1909904980
Short name T796
Test name
Test status
Simulation time 8487480344 ps
CPU time 8.15 seconds
Started May 09 02:48:29 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204444 kb
Host smart-d27fcd5f-e423-4cb9-a65b-3e2a075637d1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1909904980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1909904980
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.436621718
Short name T1190
Test name
Test status
Simulation time 8389524518 ps
CPU time 9.12 seconds
Started May 09 02:48:28 PM PDT 24
Finished May 09 02:48:44 PM PDT 24
Peak memory 204456 kb
Host smart-0a96510d-6dcf-4ed8-bf05-53da22b52356
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=436621718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.436621718
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.3673107037
Short name T313
Test name
Test status
Simulation time 8459208402 ps
CPU time 8.55 seconds
Started May 09 02:48:31 PM PDT 24
Finished May 09 02:48:44 PM PDT 24
Peak memory 204496 kb
Host smart-d8b48cf2-f273-4cb0-91eb-2951b73fa3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731
07037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.3673107037
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3929953689
Short name T593
Test name
Test status
Simulation time 8374636529 ps
CPU time 8.7 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204588 kb
Host smart-51198105-42e2-4f5c-aebd-af8b85b79097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39299
53689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3929953689
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.2107836902
Short name T1233
Test name
Test status
Simulation time 8378404959 ps
CPU time 8.35 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204600 kb
Host smart-42b971c0-b105-49e9-a4b5-3deca05c3f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21078
36902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2107836902
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3528187313
Short name T1194
Test name
Test status
Simulation time 303192455 ps
CPU time 2.41 seconds
Started May 09 02:48:23 PM PDT 24
Finished May 09 02:48:31 PM PDT 24
Peak memory 204644 kb
Host smart-af856b85-ff5a-45ff-b309-befabe5fa750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
87313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3528187313
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2227892602
Short name T1052
Test name
Test status
Simulation time 8434897418 ps
CPU time 8.4 seconds
Started May 09 02:48:28 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204496 kb
Host smart-21b44f6f-763e-43af-9431-b3d205a92a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22278
92602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2227892602
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1664759782
Short name T201
Test name
Test status
Simulation time 8369321805 ps
CPU time 8.81 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 204524 kb
Host smart-9939b42a-a90f-427f-86db-3f600fc4f614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647
59782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1664759782
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4294034856
Short name T1311
Test name
Test status
Simulation time 8415693066 ps
CPU time 7.68 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204504 kb
Host smart-ae0a95a5-31ac-4b61-a484-718ae49de6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42940
34856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4294034856
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.986877046
Short name T1378
Test name
Test status
Simulation time 8416912299 ps
CPU time 8 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204536 kb
Host smart-7c662216-463d-43db-9e7a-eeec3e67aa82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98687
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.986877046
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1893753430
Short name T1150
Test name
Test status
Simulation time 8369386637 ps
CPU time 9.1 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:42 PM PDT 24
Peak memory 204604 kb
Host smart-1b5246c6-8bda-409c-b0b6-24d4fe06b2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18937
53430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1893753430
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3218254860
Short name T107
Test name
Test status
Simulation time 8402966549 ps
CPU time 8.49 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 204576 kb
Host smart-0a689a71-126b-431e-af0c-fcb3c73c0059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32182
54860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3218254860
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.4077495820
Short name T849
Test name
Test status
Simulation time 8432853446 ps
CPU time 8.3 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 204568 kb
Host smart-84bedce7-6080-4afa-aba0-9e49a3fbf5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
95820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.4077495820
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2187100064
Short name T891
Test name
Test status
Simulation time 8401556434 ps
CPU time 8.73 seconds
Started May 09 02:48:27 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204572 kb
Host smart-565ecf40-0adf-4bfc-a356-e1f965e81d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21871
00064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2187100064
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1050030119
Short name T707
Test name
Test status
Simulation time 8479913375 ps
CPU time 7.87 seconds
Started May 09 02:48:28 PM PDT 24
Finished May 09 02:48:42 PM PDT 24
Peak memory 204568 kb
Host smart-d8e36e2d-acd5-4899-b6b3-538ded6aabdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10500
30119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1050030119
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.893249640
Short name T1185
Test name
Test status
Simulation time 8375326262 ps
CPU time 9.04 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204608 kb
Host smart-c4ff2fe2-6e28-427c-aab7-8ea7f73a8094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89324
9640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.893249640
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3598595440
Short name T1234
Test name
Test status
Simulation time 37305525 ps
CPU time 0.68 seconds
Started May 09 02:48:31 PM PDT 24
Finished May 09 02:48:36 PM PDT 24
Peak memory 204444 kb
Host smart-1c866ba5-3f0e-4601-aeca-0bf4ef667ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35985
95440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3598595440
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2549050342
Short name T581
Test name
Test status
Simulation time 28867536619 ps
CPU time 55.49 seconds
Started May 09 02:48:26 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204764 kb
Host smart-57c04e95-b386-49b3-bc7d-69e16aa4718f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25490
50342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2549050342
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.210420487
Short name T491
Test name
Test status
Simulation time 8409336726 ps
CPU time 7.66 seconds
Started May 09 02:48:27 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204604 kb
Host smart-c494f993-f162-4203-98fa-c47abd8d43dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
0487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.210420487
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3398625523
Short name T161
Test name
Test status
Simulation time 8464643127 ps
CPU time 7.85 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 204564 kb
Host smart-71589cbd-2a4e-458b-961d-e8e4f56fbb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33986
25523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3398625523
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.1083080694
Short name T1144
Test name
Test status
Simulation time 8432280914 ps
CPU time 8.99 seconds
Started May 09 02:48:24 PM PDT 24
Finished May 09 02:48:39 PM PDT 24
Peak memory 204576 kb
Host smart-d33e841f-f099-41ea-b568-ec99fc96e518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10830
80694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.1083080694
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.4168080183
Short name T177
Test name
Test status
Simulation time 8368178675 ps
CPU time 10.13 seconds
Started May 09 02:48:29 PM PDT 24
Finished May 09 02:48:45 PM PDT 24
Peak memory 204580 kb
Host smart-4b36da5d-19c3-4eb1-93fa-2753963a19ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
80183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.4168080183
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3186339003
Short name T631
Test name
Test status
Simulation time 8375012648 ps
CPU time 7.93 seconds
Started May 09 02:48:27 PM PDT 24
Finished May 09 02:48:42 PM PDT 24
Peak memory 204536 kb
Host smart-9f2d42f3-6859-4146-b393-724d4aaa5d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31863
39003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3186339003
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2370711461
Short name T470
Test name
Test status
Simulation time 8424573722 ps
CPU time 9.7 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:41 PM PDT 24
Peak memory 204584 kb
Host smart-ee8ac2ea-6f29-497e-95f1-62bfc06ee246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23707
11461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2370711461
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.504446564
Short name T590
Test name
Test status
Simulation time 8457804002 ps
CPU time 8.36 seconds
Started May 09 02:48:26 PM PDT 24
Finished May 09 02:48:42 PM PDT 24
Peak memory 204572 kb
Host smart-6a973a0c-5c98-430b-b772-1aeb82e7e437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50444
6564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.504446564
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.843374382
Short name T386
Test name
Test status
Simulation time 8417859656 ps
CPU time 9.04 seconds
Started May 09 02:48:28 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204564 kb
Host smart-70a4bdc1-e75e-494a-bcba-32ce8846825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84337
4382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.843374382
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.2283339547
Short name T774
Test name
Test status
Simulation time 8465218651 ps
CPU time 7.88 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:49 PM PDT 24
Peak memory 204516 kb
Host smart-f7e9abd0-35a2-4c7b-9ab0-77e4b0d26b30
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2283339547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.2283339547
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.3358816823
Short name T1224
Test name
Test status
Simulation time 8387764941 ps
CPU time 7.68 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:51 PM PDT 24
Peak memory 204556 kb
Host smart-0c2d2e09-1698-4ac1-8265-61a734a187f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3358816823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.3358816823
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.4101063074
Short name T903
Test name
Test status
Simulation time 8407489178 ps
CPU time 8.31 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:48:48 PM PDT 24
Peak memory 204588 kb
Host smart-32c5869b-fd8a-4dea-b28b-d1b41eded626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41010
63074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.4101063074
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2933661739
Short name T460
Test name
Test status
Simulation time 8389731143 ps
CPU time 9.32 seconds
Started May 09 02:48:30 PM PDT 24
Finished May 09 02:48:45 PM PDT 24
Peak memory 204468 kb
Host smart-5dd1b8de-1c90-40c7-a1c5-bca4d021893f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29336
61739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2933661739
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2330325666
Short name T1164
Test name
Test status
Simulation time 8835783231 ps
CPU time 12.49 seconds
Started May 09 02:48:25 PM PDT 24
Finished May 09 02:48:45 PM PDT 24
Peak memory 204844 kb
Host smart-c4a81aca-298e-4dc9-8ac6-eddb08fa6744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
25666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2330325666
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_enable.864527514
Short name T951
Test name
Test status
Simulation time 8401556203 ps
CPU time 8.45 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:48:47 PM PDT 24
Peak memory 204568 kb
Host smart-9705723b-5cc1-459d-9d1f-8d698dee93de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86452
7514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.864527514
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2868285845
Short name T412
Test name
Test status
Simulation time 198940877 ps
CPU time 2.3 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:44 PM PDT 24
Peak memory 204688 kb
Host smart-266cd469-dcca-408a-a3c1-23438f184f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28682
85845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2868285845
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3249173856
Short name T1338
Test name
Test status
Simulation time 8549235345 ps
CPU time 7.62 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204584 kb
Host smart-239ff896-627c-48d1-b848-5bb44b31548e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32491
73856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3249173856
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1559122131
Short name T953
Test name
Test status
Simulation time 8370485998 ps
CPU time 7.59 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204540 kb
Host smart-194953ee-4186-41f8-8d89-1e25d12e6bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591
22131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1559122131
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.676795295
Short name T1104
Test name
Test status
Simulation time 8436617325 ps
CPU time 7.53 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:51 PM PDT 24
Peak memory 204056 kb
Host smart-6cf25de8-ec96-4943-b17e-b596090611e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67679
5295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.676795295
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.424435534
Short name T811
Test name
Test status
Simulation time 8422247835 ps
CPU time 8.33 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204596 kb
Host smart-01411c44-c918-4ee0-a845-7044be9f6117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42443
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.424435534
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.743713064
Short name T527
Test name
Test status
Simulation time 8367288219 ps
CPU time 8.08 seconds
Started May 09 02:48:42 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204556 kb
Host smart-7f37ca9e-03ad-405c-9ead-a1d0ae7b4d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74371
3064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.743713064
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1757037863
Short name T114
Test name
Test status
Simulation time 8410910031 ps
CPU time 7.57 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:49 PM PDT 24
Peak memory 204608 kb
Host smart-afba5072-302b-4369-a923-d891db9ebc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17570
37863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1757037863
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2858183159
Short name T468
Test name
Test status
Simulation time 8398196823 ps
CPU time 10.19 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204540 kb
Host smart-57bb16a1-24ef-4fb1-9895-53ac96d65f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28581
83159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2858183159
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3045952915
Short name T1028
Test name
Test status
Simulation time 8416871168 ps
CPU time 8.7 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:48:48 PM PDT 24
Peak memory 204524 kb
Host smart-b68e3c80-c1c9-4445-8b76-165f7a115a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30459
52915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3045952915
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.624279661
Short name T542
Test name
Test status
Simulation time 8390961855 ps
CPU time 8.89 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:51 PM PDT 24
Peak memory 204508 kb
Host smart-c41ec07a-d103-4d55-995e-62b261934c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62427
9661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.624279661
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3562041757
Short name T1216
Test name
Test status
Simulation time 88382757 ps
CPU time 0.76 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204496 kb
Host smart-eb7e4896-9df5-4ae1-8948-035f918d3c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35620
41757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3562041757
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2062654675
Short name T555
Test name
Test status
Simulation time 19255244860 ps
CPU time 35.78 seconds
Started May 09 02:48:39 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204800 kb
Host smart-25f47386-30b0-4c60-ac0d-f42e9a46b9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
54675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2062654675
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1430310169
Short name T1002
Test name
Test status
Simulation time 8418870386 ps
CPU time 7.9 seconds
Started May 09 02:48:34 PM PDT 24
Finished May 09 02:48:46 PM PDT 24
Peak memory 204536 kb
Host smart-2c4929aa-84fa-4d55-b2b3-4b42e29c5073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
10169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1430310169
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.759993756
Short name T131
Test name
Test status
Simulation time 8427246046 ps
CPU time 8.9 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204604 kb
Host smart-9a50d67b-1274-4044-ae5f-0c849d93d68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75999
3756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.759993756
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2226714696
Short name T611
Test name
Test status
Simulation time 8417471749 ps
CPU time 7.65 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:50 PM PDT 24
Peak memory 204612 kb
Host smart-8c8dd6a2-f113-4108-9601-f636cdd6fea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
14696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2226714696
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3299398529
Short name T167
Test name
Test status
Simulation time 8378024105 ps
CPU time 7.56 seconds
Started May 09 02:48:46 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204528 kb
Host smart-d9c1e781-421d-4c58-821f-14ccc9f0b6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
98529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3299398529
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.353609646
Short name T790
Test name
Test status
Simulation time 8371624240 ps
CPU time 9.36 seconds
Started May 09 02:48:39 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204300 kb
Host smart-8135ad1a-025f-463d-abbd-9f4139dfc88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35360
9646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.353609646
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.622430804
Short name T1403
Test name
Test status
Simulation time 8413624621 ps
CPU time 8.19 seconds
Started May 09 02:48:30 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204552 kb
Host smart-30f2284b-7aa6-4780-9056-c2cf8bde8f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62243
0804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.622430804
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2622674574
Short name T725
Test name
Test status
Simulation time 8387796852 ps
CPU time 8.11 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204500 kb
Host smart-c228dc8a-460b-440d-8a7b-a067c82bf982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26226
74574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2622674574
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.425677544
Short name T1084
Test name
Test status
Simulation time 8373064492 ps
CPU time 8.79 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:48:48 PM PDT 24
Peak memory 204496 kb
Host smart-9b661b45-0934-47d8-b32c-30ddab5cffe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.425677544
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1817442357
Short name T388
Test name
Test status
Simulation time 8475447954 ps
CPU time 9.17 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204824 kb
Host smart-6dd72b0c-546c-4246-953f-c0f3cb08eca9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1817442357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1817442357
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2011430454
Short name T1302
Test name
Test status
Simulation time 8389902770 ps
CPU time 7.66 seconds
Started May 09 02:46:05 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204564 kb
Host smart-7570fb60-9ea3-4ee0-8ff5-c63ba2732942
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2011430454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2011430454
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.179536361
Short name T368
Test name
Test status
Simulation time 8440396365 ps
CPU time 8.87 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204540 kb
Host smart-f8922ed1-f68b-41fa-b585-d5695410ae91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17953
6361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.179536361
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2001107941
Short name T326
Test name
Test status
Simulation time 8376171056 ps
CPU time 8.22 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:10 PM PDT 24
Peak memory 204564 kb
Host smart-2cd2115c-1357-486d-9662-8e4d719412e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011
07941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2001107941
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1769953669
Short name T144
Test name
Test status
Simulation time 9027084064 ps
CPU time 11.69 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204784 kb
Host smart-aa3b73d3-bff3-4f54-8413-9cf52edc1884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17699
53669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1769953669
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_enable.898888908
Short name T341
Test name
Test status
Simulation time 8391893436 ps
CPU time 7.76 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204556 kb
Host smart-12772287-6032-46ec-8120-c8be252794b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89888
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.898888908
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.126886911
Short name T575
Test name
Test status
Simulation time 144343749 ps
CPU time 1.31 seconds
Started May 09 02:45:58 PM PDT 24
Finished May 09 02:46:02 PM PDT 24
Peak memory 204728 kb
Host smart-a0517654-052d-4d4d-8d20-272f2c2e806f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12688
6911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.126886911
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3645893883
Short name T159
Test name
Test status
Simulation time 8465484870 ps
CPU time 8.23 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204508 kb
Host smart-572c7149-a331-46eb-89ba-d77a60be4379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36458
93883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3645893883
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.825759747
Short name T792
Test name
Test status
Simulation time 8363907303 ps
CPU time 7.69 seconds
Started May 09 02:46:03 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 204492 kb
Host smart-7fdf23d9-a15b-48ea-97ca-d18747af9208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82575
9747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.825759747
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1065739483
Short name T1363
Test name
Test status
Simulation time 8463102849 ps
CPU time 10.06 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204604 kb
Host smart-22825fca-4cbb-4437-9676-75daec4a0cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10657
39483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1065739483
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.658015718
Short name T721
Test name
Test status
Simulation time 8412808108 ps
CPU time 7.79 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204576 kb
Host smart-ab505e11-1421-450a-88aa-2c83535e10b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65801
5718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.658015718
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2670227798
Short name T1071
Test name
Test status
Simulation time 8375131871 ps
CPU time 8.22 seconds
Started May 09 02:46:04 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204560 kb
Host smart-e8c0c359-889d-42e2-86eb-ca793e77ebd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26702
27798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2670227798
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.151098185
Short name T127
Test name
Test status
Simulation time 8415515716 ps
CPU time 7.64 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204596 kb
Host smart-3973431d-38a6-479e-91d7-1ba50de059b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15109
8185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.151098185
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.880357741
Short name T1393
Test name
Test status
Simulation time 8387258220 ps
CPU time 10.06 seconds
Started May 09 02:45:59 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204576 kb
Host smart-9bd2c545-e178-4bf0-b6a9-45f457e40391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88035
7741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.880357741
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2901613819
Short name T743
Test name
Test status
Simulation time 8378411651 ps
CPU time 8.42 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204544 kb
Host smart-6939bbf5-fd3f-48ff-887f-f067d7bded83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29016
13819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2901613819
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3895592281
Short name T737
Test name
Test status
Simulation time 8403850167 ps
CPU time 8.34 seconds
Started May 09 02:46:04 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204540 kb
Host smart-33afff13-7248-44e6-ad06-40b307198ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
92281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3895592281
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1637627300
Short name T710
Test name
Test status
Simulation time 8392606555 ps
CPU time 8.21 seconds
Started May 09 02:46:03 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 204588 kb
Host smart-6e0e7468-311c-4bdd-a503-0eb4f43418db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16376
27300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1637627300
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.230151606
Short name T1405
Test name
Test status
Simulation time 8391237313 ps
CPU time 9.87 seconds
Started May 09 02:46:07 PM PDT 24
Finished May 09 02:46:19 PM PDT 24
Peak memory 204596 kb
Host smart-f46bd1f9-1402-496c-98aa-8f6feb224de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23015
1606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.230151606
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.281317575
Short name T784
Test name
Test status
Simulation time 8467758128 ps
CPU time 9.93 seconds
Started May 09 02:46:03 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 204492 kb
Host smart-7f496d9e-200c-4c21-a780-a7b97fdc1274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28131
7575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.281317575
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3361936038
Short name T9
Test name
Test status
Simulation time 8409357190 ps
CPU time 8.9 seconds
Started May 09 02:46:03 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 204544 kb
Host smart-600ff41e-008c-4429-a76d-2a93a87bac72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33619
36038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3361936038
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1119385358
Short name T79
Test name
Test status
Simulation time 367623706 ps
CPU time 1.22 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 221916 kb
Host smart-56e52d95-822d-4f1b-bea7-8e82afef755c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1119385358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1119385358
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2640277448
Short name T184
Test name
Test status
Simulation time 8379747329 ps
CPU time 9.2 seconds
Started May 09 02:46:05 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 204580 kb
Host smart-1ce94acb-24d0-4a65-bcca-40b93b7d2b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26402
77448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2640277448
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2806460682
Short name T783
Test name
Test status
Simulation time 8392713214 ps
CPU time 8.58 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 204548 kb
Host smart-4e0a4d45-e998-4389-88fc-a74edc9118b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
60682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2806460682
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3903328077
Short name T1374
Test name
Test status
Simulation time 8402284932 ps
CPU time 7.61 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204584 kb
Host smart-b3e9cd38-48a3-45e5-b090-e55294ed16de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39033
28077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3903328077
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.4215850185
Short name T361
Test name
Test status
Simulation time 8397532164 ps
CPU time 7.72 seconds
Started May 09 02:46:08 PM PDT 24
Finished May 09 02:46:17 PM PDT 24
Peak memory 204520 kb
Host smart-4f1948d8-cd16-4737-a778-2be930f4701a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42158
50185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.4215850185
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2227060241
Short name T1026
Test name
Test status
Simulation time 8374684449 ps
CPU time 10.43 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 204824 kb
Host smart-aab394dc-cc8e-418b-b597-bb8239eb43c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
60241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2227060241
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1784580625
Short name T622
Test name
Test status
Simulation time 8505691030 ps
CPU time 7.91 seconds
Started May 09 02:48:45 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204512 kb
Host smart-53c90edf-b297-4e71-8c17-393ebafc806d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1784580625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1784580625
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.793422861
Short name T574
Test name
Test status
Simulation time 8380834444 ps
CPU time 8.05 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:48:47 PM PDT 24
Peak memory 204388 kb
Host smart-2293b207-fc4e-485b-a49f-b64853d85386
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=793422861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.793422861
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3203477547
Short name T518
Test name
Test status
Simulation time 8413910322 ps
CPU time 7.81 seconds
Started May 09 02:48:40 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204592 kb
Host smart-ff153d10-f8b6-43d8-bcb2-f12e125d57de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32034
77547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3203477547
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2839667124
Short name T1268
Test name
Test status
Simulation time 8471318426 ps
CPU time 7.95 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:50 PM PDT 24
Peak memory 204580 kb
Host smart-731150b2-e1f4-4851-96f8-b89b99a2e5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28396
67124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2839667124
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3086198018
Short name T207
Test name
Test status
Simulation time 9159949671 ps
CPU time 15.58 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204828 kb
Host smart-a3d7d45d-f348-44ef-a284-c9aea41bde6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30861
98018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3086198018
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_enable.1790787914
Short name T442
Test name
Test status
Simulation time 8372028862 ps
CPU time 7.57 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:50 PM PDT 24
Peak memory 204584 kb
Host smart-02b8c2b8-bea6-4afd-879f-537d0cd5ccc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17907
87914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1790787914
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2481623822
Short name T592
Test name
Test status
Simulation time 287567520 ps
CPU time 2.24 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:45 PM PDT 24
Peak memory 204616 kb
Host smart-da2f5e22-5ecd-47e9-9ab6-abde65fca183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
23822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2481623822
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1432890464
Short name T381
Test name
Test status
Simulation time 8407719676 ps
CPU time 8.25 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:50 PM PDT 24
Peak memory 204568 kb
Host smart-ffe14406-3f36-4240-8728-e0e58eea98d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14328
90464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1432890464
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3654496658
Short name T1038
Test name
Test status
Simulation time 8380942171 ps
CPU time 7.87 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:48:48 PM PDT 24
Peak memory 204388 kb
Host smart-d35f8793-ae8c-4853-ba01-577b9b9e41a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
96658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3654496658
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2661750415
Short name T1031
Test name
Test status
Simulation time 8489241111 ps
CPU time 9.34 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204572 kb
Host smart-18d12e19-5e80-4902-8f86-dcaca751767b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617
50415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2661750415
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4023077485
Short name T337
Test name
Test status
Simulation time 8410414990 ps
CPU time 8.96 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204568 kb
Host smart-4c94ebd3-1a65-4032-93cd-f5b2715381c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
77485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4023077485
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.378653722
Short name T758
Test name
Test status
Simulation time 8370150649 ps
CPU time 8.03 seconds
Started May 09 02:48:44 PM PDT 24
Finished May 09 02:48:56 PM PDT 24
Peak memory 204560 kb
Host smart-6547b9d3-9c43-426c-a2f1-ef89cafa78e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37865
3722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.378653722
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.4033255730
Short name T103
Test name
Test status
Simulation time 8417992571 ps
CPU time 9.24 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204496 kb
Host smart-25b3054a-093b-4bd0-8465-c400ddd80d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40332
55730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.4033255730
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2340301026
Short name T732
Test name
Test status
Simulation time 8404911385 ps
CPU time 9.18 seconds
Started May 09 02:48:39 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204280 kb
Host smart-75de53b0-431b-4ac6-b477-7602317ef0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23403
01026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2340301026
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3942129351
Short name T1092
Test name
Test status
Simulation time 8419140701 ps
CPU time 8.69 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204560 kb
Host smart-79373a5d-bbbe-4027-8b08-d5ff5ee9c496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39421
29351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3942129351
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2173277675
Short name T848
Test name
Test status
Simulation time 8426339391 ps
CPU time 8.61 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204608 kb
Host smart-e012da54-c283-4bde-94d2-e12b4b4f7682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21732
77675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2173277675
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3285835429
Short name T1179
Test name
Test status
Simulation time 8373090633 ps
CPU time 9.03 seconds
Started May 09 02:48:41 PM PDT 24
Finished May 09 02:48:55 PM PDT 24
Peak memory 204576 kb
Host smart-5e89ffbd-11e4-4d32-8139-5ca427639ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32858
35429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3285835429
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3742409876
Short name T47
Test name
Test status
Simulation time 41521966 ps
CPU time 0.64 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:43 PM PDT 24
Peak memory 204480 kb
Host smart-26a997dc-4cbf-45c9-a6da-cbc8d2601b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37424
09876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3742409876
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1438939949
Short name T1398
Test name
Test status
Simulation time 24902513091 ps
CPU time 51.98 seconds
Started May 09 02:48:35 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204844 kb
Host smart-f879069d-7fa5-4849-93fd-e58d4c9a0b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
39949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1438939949
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3815145900
Short name T905
Test name
Test status
Simulation time 8378685445 ps
CPU time 8.9 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204548 kb
Host smart-9148dc2a-5ab5-4ef0-bcab-7bddecfb4fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38151
45900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3815145900
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3770625076
Short name T1029
Test name
Test status
Simulation time 8423401203 ps
CPU time 8.16 seconds
Started May 09 02:48:43 PM PDT 24
Finished May 09 02:48:55 PM PDT 24
Peak memory 204556 kb
Host smart-6fd5e291-1595-4561-afec-9c07e4da17fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706
25076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3770625076
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3612120169
Short name T319
Test name
Test status
Simulation time 8378878079 ps
CPU time 9.54 seconds
Started May 09 02:48:41 PM PDT 24
Finished May 09 02:48:55 PM PDT 24
Peak memory 204584 kb
Host smart-13ee1416-6a0c-4aa6-9e6d-dba252946341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36121
20169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3612120169
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.521949153
Short name T164
Test name
Test status
Simulation time 8376553977 ps
CPU time 8.44 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204560 kb
Host smart-cbe1d174-70dd-45ab-bd65-8c87b705c6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52194
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.521949153
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2106146088
Short name T829
Test name
Test status
Simulation time 8375956432 ps
CPU time 7.51 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:51 PM PDT 24
Peak memory 203996 kb
Host smart-c6b80cc1-c0fa-4fb2-af6d-a3f0cc4dfc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21061
46088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2106146088
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1597604105
Short name T155
Test name
Test status
Simulation time 8457524931 ps
CPU time 8.08 seconds
Started May 09 02:48:36 PM PDT 24
Finished May 09 02:48:50 PM PDT 24
Peak memory 204556 kb
Host smart-97d07e91-3241-4eee-8f56-fc6ff30ae3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15976
04105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1597604105
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.751120660
Short name T330
Test name
Test status
Simulation time 8451823490 ps
CPU time 8.1 seconds
Started May 09 02:48:37 PM PDT 24
Finished May 09 02:48:50 PM PDT 24
Peak memory 204520 kb
Host smart-4707f16f-8f09-4289-9eb8-929b5c9dcc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75112
0660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.751120660
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.4107284931
Short name T531
Test name
Test status
Simulation time 8461490617 ps
CPU time 8.13 seconds
Started May 09 02:48:41 PM PDT 24
Finished May 09 02:48:54 PM PDT 24
Peak memory 204584 kb
Host smart-d5410b56-e2c5-4e0f-aeda-4af49f4340a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072
84931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.4107284931
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.3173850841
Short name T1401
Test name
Test status
Simulation time 8464245765 ps
CPU time 7.66 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204540 kb
Host smart-a4ddc351-7079-45b5-95f3-fdd79170efe6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3173850841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.3173850841
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.96763734
Short name T348
Test name
Test status
Simulation time 8373743958 ps
CPU time 8.95 seconds
Started May 09 02:48:47 PM PDT 24
Finished May 09 02:48:59 PM PDT 24
Peak memory 204584 kb
Host smart-cd642ad8-dd8c-4fcf-8e5d-849af3867172
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=96763734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.96763734
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.1119577108
Short name T1180
Test name
Test status
Simulation time 8469301492 ps
CPU time 9.02 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204508 kb
Host smart-1ac202f2-0e24-4cc4-8b42-cd56e9b453df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11195
77108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.1119577108
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3458468246
Short name T1382
Test name
Test status
Simulation time 8392145141 ps
CPU time 8.81 seconds
Started May 09 02:48:43 PM PDT 24
Finished May 09 02:48:56 PM PDT 24
Peak memory 204572 kb
Host smart-8f73220a-f564-4b7b-8364-ac72fe685ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
68246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3458468246
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3935379953
Short name T649
Test name
Test status
Simulation time 8872036332 ps
CPU time 14.31 seconds
Started May 09 02:48:45 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204772 kb
Host smart-6b5801e7-b230-4893-88a5-4556ce77914e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
79953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3935379953
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_enable.1898348962
Short name T1271
Test name
Test status
Simulation time 8375053206 ps
CPU time 7.85 seconds
Started May 09 02:48:39 PM PDT 24
Finished May 09 02:48:53 PM PDT 24
Peak memory 204480 kb
Host smart-ca911961-25da-483d-94d5-2b09977f03a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983
48962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1898348962
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.90119251
Short name T1394
Test name
Test status
Simulation time 138641257 ps
CPU time 1.69 seconds
Started May 09 02:48:42 PM PDT 24
Finished May 09 02:48:48 PM PDT 24
Peak memory 204716 kb
Host smart-588e6793-d224-443c-80a0-aa6b90da3391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90119
251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.90119251
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2786619024
Short name T1065
Test name
Test status
Simulation time 8392864537 ps
CPU time 9.79 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204608 kb
Host smart-46562e00-5428-4223-a97f-d3dadc15bc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27866
19024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2786619024
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2475694833
Short name T208
Test name
Test status
Simulation time 8367952379 ps
CPU time 7.54 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204536 kb
Host smart-aea3ca2b-9543-4088-afda-379923828735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24756
94833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2475694833
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.639137269
Short name T1146
Test name
Test status
Simulation time 8399193533 ps
CPU time 7.76 seconds
Started May 09 02:48:45 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204532 kb
Host smart-e6c98968-d9c3-4981-be84-05e907b25638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63913
7269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.639137269
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3883955228
Short name T1137
Test name
Test status
Simulation time 8415425262 ps
CPU time 8.33 seconds
Started May 09 02:48:45 PM PDT 24
Finished May 09 02:48:56 PM PDT 24
Peak memory 204528 kb
Host smart-8e6b6462-52cd-4e8b-8b8f-f415cfec5a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
55228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3883955228
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3709333612
Short name T1325
Test name
Test status
Simulation time 8371222259 ps
CPU time 7.69 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:00 PM PDT 24
Peak memory 204560 kb
Host smart-53af4efa-589b-4647-b7b1-d0fc244426d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37093
33612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3709333612
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2905246394
Short name T686
Test name
Test status
Simulation time 8395359215 ps
CPU time 8.88 seconds
Started May 09 02:48:48 PM PDT 24
Finished May 09 02:49:01 PM PDT 24
Peak memory 204524 kb
Host smart-a5d59bf9-ac52-4958-b2de-aaf557a44d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29052
46394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2905246394
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3300503151
Short name T567
Test name
Test status
Simulation time 8404788744 ps
CPU time 9.7 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:02 PM PDT 24
Peak memory 204584 kb
Host smart-6577524d-adc2-439e-9010-c11a9847e39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
03151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3300503151
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.294419374
Short name T165
Test name
Test status
Simulation time 8388529614 ps
CPU time 8.82 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:02 PM PDT 24
Peak memory 204572 kb
Host smart-22b26505-3d1a-4841-95ac-fd4d6e26df03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
9374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.294419374
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.249424407
Short name T1288
Test name
Test status
Simulation time 8370151613 ps
CPU time 8.1 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:04 PM PDT 24
Peak memory 204500 kb
Host smart-c7874a2e-e5b4-46dd-ba74-88ab221b9def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24942
4407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.249424407
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1425732716
Short name T413
Test name
Test status
Simulation time 74820899 ps
CPU time 0.66 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:48:56 PM PDT 24
Peak memory 204472 kb
Host smart-893b4e75-fa27-44a1-883c-5422ff53f20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14257
32716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1425732716
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3994738866
Short name T1050
Test name
Test status
Simulation time 18815961768 ps
CPU time 35.06 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204836 kb
Host smart-0e95a58a-2d45-442b-8085-e2e51a5728a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39947
38866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3994738866
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1243463767
Short name T690
Test name
Test status
Simulation time 8387625539 ps
CPU time 7.95 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204596 kb
Host smart-c0aea8b3-75ba-44a7-a3b7-e65bdbba8126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
63767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1243463767
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2054743131
Short name T1054
Test name
Test status
Simulation time 8444054485 ps
CPU time 8.3 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204596 kb
Host smart-510bfd4d-24e3-4b75-98e3-e26ffd906faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20547
43131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2054743131
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.551686591
Short name T634
Test name
Test status
Simulation time 8417557633 ps
CPU time 7.48 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204596 kb
Host smart-30d10cbf-03b5-4629-bde0-8e24446957c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55168
6591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.551686591
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1044691749
Short name T616
Test name
Test status
Simulation time 8382969080 ps
CPU time 9.86 seconds
Started May 09 02:48:47 PM PDT 24
Finished May 09 02:49:00 PM PDT 24
Peak memory 204616 kb
Host smart-e4fdd49e-66dd-49b0-adf2-d9661c924d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10446
91749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1044691749
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2117310797
Short name T1128
Test name
Test status
Simulation time 8408034800 ps
CPU time 7.7 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204564 kb
Host smart-33601638-27b7-4901-b573-ac3c727f9dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21173
10797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2117310797
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.4139563196
Short name T150
Test name
Test status
Simulation time 8473778048 ps
CPU time 7.41 seconds
Started May 09 02:48:38 PM PDT 24
Finished May 09 02:48:52 PM PDT 24
Peak memory 204596 kb
Host smart-02e33b39-e5ef-4885-9701-d93dfda65ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41395
63196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.4139563196
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.316437243
Short name T481
Test name
Test status
Simulation time 8390601842 ps
CPU time 7.52 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:02 PM PDT 24
Peak memory 204548 kb
Host smart-c9e924c2-77cd-4d69-93ba-3fb7f6b7d8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31643
7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.316437243
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1065713409
Short name T1275
Test name
Test status
Simulation time 8423669133 ps
CPU time 7.88 seconds
Started May 09 02:48:48 PM PDT 24
Finished May 09 02:49:00 PM PDT 24
Peak memory 204516 kb
Host smart-58b4b6c9-3d47-40d0-b981-4b17fe29ea55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10657
13409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1065713409
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1935460362
Short name T1005
Test name
Test status
Simulation time 8465777867 ps
CPU time 8.89 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204516 kb
Host smart-8dd9be78-e4aa-42ec-8fdc-ea2b52d52e99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1935460362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1935460362
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1556962936
Short name T44
Test name
Test status
Simulation time 8383987450 ps
CPU time 8.17 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:02 PM PDT 24
Peak memory 204600 kb
Host smart-0a7a5e36-f96b-40fb-9f26-bb220338f18e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1556962936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1556962936
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1484218570
Short name T487
Test name
Test status
Simulation time 8433348746 ps
CPU time 10.33 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204528 kb
Host smart-4fc8bf63-09cc-4e35-a9c9-79f9154a1fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
18570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1484218570
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2649957043
Short name T973
Test name
Test status
Simulation time 8458453382 ps
CPU time 9.14 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204604 kb
Host smart-ed9658dc-bc15-4610-974c-916785d223f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26499
57043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2649957043
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1357881055
Short name T456
Test name
Test status
Simulation time 8886674646 ps
CPU time 15.08 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:10 PM PDT 24
Peak memory 204812 kb
Host smart-3ab89de9-97dc-412b-ab63-72733e3b6478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13578
81055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1357881055
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_enable.2751546745
Short name T643
Test name
Test status
Simulation time 8376425948 ps
CPU time 8.81 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204544 kb
Host smart-f9df8ac8-1ffb-4e83-a540-9c38f261fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515
46745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2751546745
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2009492317
Short name T931
Test name
Test status
Simulation time 66281541 ps
CPU time 1.59 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204684 kb
Host smart-7b0ac909-f403-4029-af88-3cf46519cbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
92317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2009492317
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.483636803
Short name T617
Test name
Test status
Simulation time 8447723137 ps
CPU time 8.89 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204556 kb
Host smart-e360f313-2713-4ac4-9414-cfdd61667619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48363
6803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.483636803
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3905559133
Short name T1298
Test name
Test status
Simulation time 8368608962 ps
CPU time 8.27 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:02 PM PDT 24
Peak memory 204600 kb
Host smart-d2b6e153-4a59-439f-8389-80e80820c80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39055
59133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3905559133
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3005950950
Short name T977
Test name
Test status
Simulation time 8419119359 ps
CPU time 8.55 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204496 kb
Host smart-da02c251-a0d0-4f49-aa31-758c30e1c483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30059
50950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3005950950
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2657471826
Short name T1039
Test name
Test status
Simulation time 8416917723 ps
CPU time 8.81 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204572 kb
Host smart-3065fcaa-7386-40f9-9f76-729407945ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26574
71826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2657471826
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3162511610
Short name T1125
Test name
Test status
Simulation time 8366498130 ps
CPU time 8.35 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204560 kb
Host smart-99408edf-057f-4c33-814f-9215694c24ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31625
11610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3162511610
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2960140563
Short name T1034
Test name
Test status
Simulation time 8409268539 ps
CPU time 7.57 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204564 kb
Host smart-67159cbc-fb5c-4f6d-888b-4bee61a0affa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
40563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2960140563
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1496086209
Short name T869
Test name
Test status
Simulation time 8396459785 ps
CPU time 8.68 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:02 PM PDT 24
Peak memory 204584 kb
Host smart-b6988cfa-3acb-4382-bfa7-a23bf7d7b7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
86209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1496086209
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1116160352
Short name T957
Test name
Test status
Simulation time 8397449936 ps
CPU time 8.46 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204616 kb
Host smart-fba95ca4-26d3-46ce-bcf4-7f2d51aef8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
60352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1116160352
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2232388864
Short name T168
Test name
Test status
Simulation time 8407882109 ps
CPU time 8.29 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204520 kb
Host smart-0d87dfab-b130-42ca-882a-7bd446a39941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323
88864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2232388864
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.956486358
Short name T1047
Test name
Test status
Simulation time 8361360529 ps
CPU time 8.08 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204576 kb
Host smart-7bdf5654-ff64-412f-be4b-fa19ca9cd5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95648
6358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.956486358
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3772628561
Short name T949
Test name
Test status
Simulation time 36490150 ps
CPU time 0.69 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:48:57 PM PDT 24
Peak memory 204528 kb
Host smart-d286a032-bca5-4567-9ade-6afe32484004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37726
28561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3772628561
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3206582864
Short name T1048
Test name
Test status
Simulation time 26449548933 ps
CPU time 47.82 seconds
Started May 09 02:48:49 PM PDT 24
Finished May 09 02:49:40 PM PDT 24
Peak memory 204760 kb
Host smart-aac4b0d5-edc2-49c8-9803-bb14a8b05fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
82864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3206582864
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.927650434
Short name T855
Test name
Test status
Simulation time 8406560425 ps
CPU time 9.29 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204600 kb
Host smart-9442f6ba-5dd8-4f30-995c-79d250950baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92765
0434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.927650434
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1070218972
Short name T713
Test name
Test status
Simulation time 8472008004 ps
CPU time 10.27 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204560 kb
Host smart-31f402b6-790d-4b2f-b0c4-5784b0bb91a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
18972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1070218972
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3262754074
Short name T359
Test name
Test status
Simulation time 8455834312 ps
CPU time 8.79 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:04 PM PDT 24
Peak memory 204616 kb
Host smart-63bfa823-7217-4cab-84b2-bd5ce1e1dd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32627
54074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3262754074
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3450743620
Short name T750
Test name
Test status
Simulation time 8395912687 ps
CPU time 7.77 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204572 kb
Host smart-718e9558-029e-47c9-84b6-e176a49e64ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34507
43620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3450743620
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1477869560
Short name T955
Test name
Test status
Simulation time 8372264759 ps
CPU time 8.15 seconds
Started May 09 02:48:48 PM PDT 24
Finished May 09 02:48:59 PM PDT 24
Peak memory 204556 kb
Host smart-b37c0fe8-6c16-4f47-bca3-3910b3a6a52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
69560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1477869560
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2122320647
Short name T1143
Test name
Test status
Simulation time 8472518935 ps
CPU time 8.02 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 204572 kb
Host smart-3f6eaf22-0e6b-4b4b-97ff-f8a455160226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21223
20647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2122320647
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1040719760
Short name T1172
Test name
Test status
Simulation time 8401063042 ps
CPU time 8.06 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204544 kb
Host smart-607c0005-66c8-4d50-b67d-73f3010db3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10407
19760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1040719760
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3430070758
Short name T1389
Test name
Test status
Simulation time 8434013173 ps
CPU time 10.27 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204588 kb
Host smart-ec61d0a1-d6ab-49ec-99b8-01b054e7492a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300
70758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3430070758
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.2644708259
Short name T320
Test name
Test status
Simulation time 8460767127 ps
CPU time 8.03 seconds
Started May 09 02:49:04 PM PDT 24
Finished May 09 02:49:15 PM PDT 24
Peak memory 204492 kb
Host smart-30e267c6-eb33-40e6-81fd-4bcd54fc467a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2644708259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.2644708259
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.656602358
Short name T1077
Test name
Test status
Simulation time 8380143296 ps
CPU time 8.14 seconds
Started May 09 02:48:53 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204608 kb
Host smart-23c01a55-2fb1-49ac-aba6-075f4cbd5284
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=656602358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.656602358
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.791880668
Short name T846
Test name
Test status
Simulation time 8416128510 ps
CPU time 9.11 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:04 PM PDT 24
Peak memory 204524 kb
Host smart-37f7cccb-b60e-442f-ba4f-77bc4b82b721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79188
0668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.791880668
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3527164214
Short name T374
Test name
Test status
Simulation time 8373415845 ps
CPU time 7.58 seconds
Started May 09 02:48:53 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204520 kb
Host smart-9e600612-f8e2-44d0-b171-b6efbc15615e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35271
64214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3527164214
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2354406530
Short name T402
Test name
Test status
Simulation time 9387625353 ps
CPU time 12.96 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:10 PM PDT 24
Peak memory 204848 kb
Host smart-572a6181-a084-4686-8d67-a0f064893ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544
06530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2354406530
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_enable.1653152169
Short name T623
Test name
Test status
Simulation time 8462228368 ps
CPU time 8.27 seconds
Started May 09 02:48:54 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204540 kb
Host smart-eaf2caf8-4da0-4149-b139-d4f0411285f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16531
52169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1653152169
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1645625652
Short name T94
Test name
Test status
Simulation time 86929905 ps
CPU time 1.77 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:48:58 PM PDT 24
Peak memory 204732 kb
Host smart-91d6393f-5c50-46e9-b829-1616b3775b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456
25652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1645625652
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2927471234
Short name T137
Test name
Test status
Simulation time 8461214440 ps
CPU time 7.52 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204560 kb
Host smart-68a8b531-eb8c-4308-a07e-caa532b85972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29274
71234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2927471234
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.238622195
Short name T806
Test name
Test status
Simulation time 8378577179 ps
CPU time 9.89 seconds
Started May 09 02:48:53 PM PDT 24
Finished May 09 02:49:09 PM PDT 24
Peak memory 204624 kb
Host smart-50148971-6907-478a-9f16-f375ccce7f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23862
2195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.238622195
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.590825971
Short name T1266
Test name
Test status
Simulation time 8452467266 ps
CPU time 7.83 seconds
Started May 09 02:48:53 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204624 kb
Host smart-578f3a3d-e642-45ed-85ed-0aa1a06e8197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59082
5971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.590825971
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2255321738
Short name T332
Test name
Test status
Simulation time 8443237373 ps
CPU time 7.99 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204608 kb
Host smart-9ff8c008-9c85-4674-a8f0-eda02e677ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
21738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2255321738
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3707150666
Short name T922
Test name
Test status
Simulation time 8375627272 ps
CPU time 7.92 seconds
Started May 09 02:48:54 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204504 kb
Host smart-63e86208-cd97-4b64-bf93-51eb2c4eba48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37071
50666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3707150666
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1985356609
Short name T124
Test name
Test status
Simulation time 8445229896 ps
CPU time 9.71 seconds
Started May 09 02:48:54 PM PDT 24
Finished May 09 02:49:09 PM PDT 24
Peak memory 204508 kb
Host smart-464e9ca5-5b36-4bdb-aa27-3ad88a586a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
56609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1985356609
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1022776125
Short name T393
Test name
Test status
Simulation time 8380520169 ps
CPU time 8.91 seconds
Started May 09 02:48:54 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204548 kb
Host smart-375ae70b-b99e-452e-98cd-e4d5f51e60d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10227
76125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1022776125
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.735481037
Short name T35
Test name
Test status
Simulation time 8407144514 ps
CPU time 8.24 seconds
Started May 09 02:48:54 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204508 kb
Host smart-49113ba6-45d2-4232-a104-0c71356da18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73548
1037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.735481037
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1760896398
Short name T190
Test name
Test status
Simulation time 8401520139 ps
CPU time 7.83 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204464 kb
Host smart-eb7c6a89-ada0-4dbc-8397-384896f08677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17608
96398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1760896398
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.358376700
Short name T1147
Test name
Test status
Simulation time 8368507600 ps
CPU time 8.14 seconds
Started May 09 02:48:55 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204552 kb
Host smart-98d15265-821c-49a4-9604-d8ebbff6aa31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35837
6700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.358376700
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.4257469936
Short name T787
Test name
Test status
Simulation time 76666610 ps
CPU time 0.71 seconds
Started May 09 02:48:55 PM PDT 24
Finished May 09 02:49:01 PM PDT 24
Peak memory 204536 kb
Host smart-d7c04183-abc1-4215-8efb-dbf745a501f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574
69936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.4257469936
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.815834939
Short name T1426
Test name
Test status
Simulation time 15731338431 ps
CPU time 26.79 seconds
Started May 09 02:48:50 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204776 kb
Host smart-78323ea7-d888-42a9-aefb-c9c9a4524f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81583
4939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.815834939
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1682379334
Short name T1093
Test name
Test status
Simulation time 8404602504 ps
CPU time 8.22 seconds
Started May 09 02:48:54 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204524 kb
Host smart-f1aa17df-ffc0-4ccd-a066-1185ab6307d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16823
79334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1682379334
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.4294458960
Short name T1081
Test name
Test status
Simulation time 8413197291 ps
CPU time 8.75 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204580 kb
Host smart-c5965212-7e7c-453e-bc78-07d690b15a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42944
58960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.4294458960
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1303137604
Short name T1195
Test name
Test status
Simulation time 8398207939 ps
CPU time 7.59 seconds
Started May 09 02:48:51 PM PDT 24
Finished May 09 02:49:05 PM PDT 24
Peak memory 204592 kb
Host smart-0fc99bb8-d718-4ccc-84d8-4ec44f68ccc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13031
37604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1303137604
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3668000312
Short name T548
Test name
Test status
Simulation time 8398177134 ps
CPU time 9.04 seconds
Started May 09 02:48:55 PM PDT 24
Finished May 09 02:49:09 PM PDT 24
Peak memory 204596 kb
Host smart-65ad445f-4c52-4a48-a0b4-3380291f441e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36680
00312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3668000312
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.677841077
Short name T691
Test name
Test status
Simulation time 8386616388 ps
CPU time 7.95 seconds
Started May 09 02:48:55 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204548 kb
Host smart-00d32d3c-4827-4ed3-a117-8a8b35e44265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67784
1077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.677841077
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1757857969
Short name T1124
Test name
Test status
Simulation time 8450476910 ps
CPU time 7.71 seconds
Started May 09 02:48:53 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204612 kb
Host smart-647894e7-139c-4a89-9cfe-3a543d367a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17578
57969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1757857969
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.204697607
Short name T1340
Test name
Test status
Simulation time 8415610322 ps
CPU time 9.36 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:07 PM PDT 24
Peak memory 204580 kb
Host smart-664761c4-61c9-4144-a795-060680ebb79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20469
7607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.204697607
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.962170476
Short name T1352
Test name
Test status
Simulation time 8405019997 ps
CPU time 9.65 seconds
Started May 09 02:48:53 PM PDT 24
Finished May 09 02:49:09 PM PDT 24
Peak memory 204608 kb
Host smart-51d2b1f5-3f0c-4180-86d9-0c9fea46fa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96217
0476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.962170476
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2871982290
Short name T763
Test name
Test status
Simulation time 8463716913 ps
CPU time 7.89 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204504 kb
Host smart-70710fbc-8d93-4966-b47a-becfe7aaacbf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2871982290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2871982290
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3982116398
Short name T719
Test name
Test status
Simulation time 8466848027 ps
CPU time 8.19 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204536 kb
Host smart-b69e3c1c-64c5-49f9-b15e-41523ced33de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3982116398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3982116398
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.295219334
Short name T934
Test name
Test status
Simulation time 8379381716 ps
CPU time 8.22 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204528 kb
Host smart-9f5463f7-1d75-4775-bcb6-28d0ac12c8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29521
9334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.295219334
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3930806334
Short name T350
Test name
Test status
Simulation time 8379259291 ps
CPU time 8.79 seconds
Started May 09 02:49:00 PM PDT 24
Finished May 09 02:49:12 PM PDT 24
Peak memory 204536 kb
Host smart-d5112f50-3d73-4924-84f1-684bb302e7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39308
06334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3930806334
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2346563387
Short name T36
Test name
Test status
Simulation time 8768127296 ps
CPU time 14.72 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:36 PM PDT 24
Peak memory 204784 kb
Host smart-3a606d35-0e2c-4dd6-be02-72ddfda67c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
63387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2346563387
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_enable.2067000783
Short name T821
Test name
Test status
Simulation time 8376092397 ps
CPU time 7.4 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204584 kb
Host smart-bea6529d-ded0-480d-96b4-87a5786d6315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20670
00783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2067000783
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3856173717
Short name T1110
Test name
Test status
Simulation time 192777763 ps
CPU time 1.75 seconds
Started May 09 02:49:02 PM PDT 24
Finished May 09 02:49:06 PM PDT 24
Peak memory 204680 kb
Host smart-0420e0bc-19f2-4bf6-9a72-c06edacb1127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38561
73717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3856173717
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1471910564
Short name T1270
Test name
Test status
Simulation time 8418892927 ps
CPU time 8.02 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204528 kb
Host smart-a26989c9-259c-4e90-9628-212bc5b8a58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14719
10564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1471910564
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.107256926
Short name T1242
Test name
Test status
Simulation time 8382439665 ps
CPU time 7.74 seconds
Started May 09 02:49:03 PM PDT 24
Finished May 09 02:49:14 PM PDT 24
Peak memory 204604 kb
Host smart-b2258f80-5bd0-4151-8da6-9d0d2b71b2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10725
6926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.107256926
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1329054666
Short name T825
Test name
Test status
Simulation time 8419077777 ps
CPU time 7.99 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204568 kb
Host smart-d1f34626-13c5-4254-8c28-103b92e9d5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13290
54666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1329054666
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2541767017
Short name T927
Test name
Test status
Simulation time 8415253131 ps
CPU time 8.79 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:19 PM PDT 24
Peak memory 204572 kb
Host smart-de4ead98-9a0a-4eed-8b44-4179e420e508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25417
67017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2541767017
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4143512449
Short name T1064
Test name
Test status
Simulation time 8384498496 ps
CPU time 7.74 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:18 PM PDT 24
Peak memory 204284 kb
Host smart-bb102221-ddb8-4b98-ad2f-60e103369eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41435
12449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4143512449
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.4141667122
Short name T105
Test name
Test status
Simulation time 8449580006 ps
CPU time 8.29 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204572 kb
Host smart-61e9a4a2-b903-4d32-be38-6053c34e4e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
67122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.4141667122
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2848400701
Short name T1420
Test name
Test status
Simulation time 8383738433 ps
CPU time 7.91 seconds
Started May 09 02:49:02 PM PDT 24
Finished May 09 02:49:13 PM PDT 24
Peak memory 204540 kb
Host smart-ac6210fb-7dd1-486b-aaa2-2fcd7e3c47ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484
00701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2848400701
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1085612365
Short name T932
Test name
Test status
Simulation time 8397156714 ps
CPU time 8.41 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204548 kb
Host smart-d6bf8216-b8ed-4cd2-abd0-1925f797528a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10856
12365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1085612365
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1247662648
Short name T886
Test name
Test status
Simulation time 8401925448 ps
CPU time 7.38 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:18 PM PDT 24
Peak memory 204824 kb
Host smart-ef3027da-23bb-4f35-b152-cb038d6cd232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12476
62648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1247662648
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2961740003
Short name T608
Test name
Test status
Simulation time 8364294589 ps
CPU time 7.59 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 204548 kb
Host smart-fd875872-ff12-45b0-a07e-5796b5d8ea97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29617
40003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2961740003
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.411802500
Short name T419
Test name
Test status
Simulation time 81333182 ps
CPU time 0.69 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204448 kb
Host smart-6fae6c71-e902-457a-abdf-2e824798f790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
2500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.411802500
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1010025520
Short name T1042
Test name
Test status
Simulation time 29560182772 ps
CPU time 57.49 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204740 kb
Host smart-7b0a16e3-8444-42cd-92c7-d8c298dce1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10100
25520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1010025520
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2387582228
Short name T345
Test name
Test status
Simulation time 8389430988 ps
CPU time 8.91 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 204596 kb
Host smart-de8d3283-fca6-45de-9629-2e63e9779034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23875
82228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2387582228
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.761996080
Short name T1088
Test name
Test status
Simulation time 8467751492 ps
CPU time 8.02 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204524 kb
Host smart-c94bb54b-0b2b-440c-9ef5-247e6570334c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76199
6080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.761996080
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1544572330
Short name T444
Test name
Test status
Simulation time 8426631957 ps
CPU time 9.09 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204832 kb
Host smart-19b5a774-7303-4103-969a-ca58a4987bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15445
72330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1544572330
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.424112790
Short name T636
Test name
Test status
Simulation time 8375214892 ps
CPU time 8 seconds
Started May 09 02:49:03 PM PDT 24
Finished May 09 02:49:14 PM PDT 24
Peak memory 204580 kb
Host smart-ecdf7d4d-7990-4247-9527-fb95e0504166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42411
2790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.424112790
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3686104480
Short name T1293
Test name
Test status
Simulation time 8369629958 ps
CPU time 7.98 seconds
Started May 09 02:49:11 PM PDT 24
Finished May 09 02:49:27 PM PDT 24
Peak memory 204532 kb
Host smart-cad275a2-0b49-4380-8de9-aac503e2d57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
04480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3686104480
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.4143035255
Short name T1017
Test name
Test status
Simulation time 8436837529 ps
CPU time 8.37 seconds
Started May 09 02:49:11 PM PDT 24
Finished May 09 02:49:26 PM PDT 24
Peak memory 204552 kb
Host smart-d1f31f1c-3cf0-4f97-a408-5c50fbd06703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
35255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.4143035255
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.546459031
Short name T772
Test name
Test status
Simulation time 8408553168 ps
CPU time 7.99 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:24 PM PDT 24
Peak memory 204544 kb
Host smart-5215d4be-6d00-42f8-abfc-5562a0a592ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54645
9031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.546459031
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3376309650
Short name T493
Test name
Test status
Simulation time 8383208422 ps
CPU time 7.74 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 204584 kb
Host smart-d51b02be-60be-4b75-b82e-a31cfdf0f620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33763
09650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3376309650
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2415822607
Short name T1427
Test name
Test status
Simulation time 8487733363 ps
CPU time 7.58 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204540 kb
Host smart-48f0a424-8edb-4deb-a9f0-aef84399d0b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2415822607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2415822607
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2493123703
Short name T1171
Test name
Test status
Simulation time 8378737863 ps
CPU time 9.32 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:24 PM PDT 24
Peak memory 204540 kb
Host smart-ee4c50e3-ba3a-4fba-a014-1654eb2b5bf8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2493123703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2493123703
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.1833545823
Short name T819
Test name
Test status
Simulation time 8408359076 ps
CPU time 7.98 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 204532 kb
Host smart-2854f086-1d8f-461c-a4dd-61e54d911402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18335
45823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1833545823
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1568441331
Short name T863
Test name
Test status
Simulation time 8381952837 ps
CPU time 8.52 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204584 kb
Host smart-69d0c299-aea0-4586-a96c-6e3f764304e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15684
41331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1568441331
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.679326013
Short name T462
Test name
Test status
Simulation time 8951965900 ps
CPU time 12.74 seconds
Started May 09 02:49:04 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204884 kb
Host smart-114f2b82-71c6-4486-b3d2-ce836ab8539b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67932
6013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.679326013
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_enable.3713872944
Short name T585
Test name
Test status
Simulation time 8378909105 ps
CPU time 9.22 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204608 kb
Host smart-ab67c888-39d5-48a7-808c-dd64ea67725b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
72944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3713872944
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.150023994
Short name T910
Test name
Test status
Simulation time 244643845 ps
CPU time 1.82 seconds
Started May 09 02:49:09 PM PDT 24
Finished May 09 02:49:18 PM PDT 24
Peak memory 204696 kb
Host smart-15353fd9-a466-4e05-b343-e22a7aa0b544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
3994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.150023994
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2770270923
Short name T1206
Test name
Test status
Simulation time 8422383795 ps
CPU time 7.49 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204596 kb
Host smart-c45fc7d9-521a-41f9-a73c-00ab3c258b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
70923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2770270923
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.41614647
Short name T210
Test name
Test status
Simulation time 8386366395 ps
CPU time 9.38 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:49:26 PM PDT 24
Peak memory 204540 kb
Host smart-8038d330-e905-4285-919b-bb619b7ba0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41614
647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.41614647
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3773371795
Short name T142
Test name
Test status
Simulation time 8410901202 ps
CPU time 7.95 seconds
Started May 09 02:49:02 PM PDT 24
Finished May 09 02:49:13 PM PDT 24
Peak memory 204504 kb
Host smart-e2f43bd0-e782-4609-aff2-85949719fd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
71795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3773371795
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1866017259
Short name T1404
Test name
Test status
Simulation time 8444100954 ps
CPU time 8.12 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204576 kb
Host smart-1de973d5-985e-43a2-b1d5-6746a92245ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18660
17259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1866017259
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2128133170
Short name T978
Test name
Test status
Simulation time 8387147421 ps
CPU time 10.04 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204572 kb
Host smart-8e9f1a7d-d9a1-47c6-961d-2be17f6b3cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
33170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2128133170
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.612258648
Short name T1199
Test name
Test status
Simulation time 8455702550 ps
CPU time 8.52 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204556 kb
Host smart-ee5f5461-546f-46de-81ec-de4b80efdb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61225
8648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.612258648
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3077295091
Short name T1265
Test name
Test status
Simulation time 8380705298 ps
CPU time 8.85 seconds
Started May 09 02:49:09 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204208 kb
Host smart-a6348184-5f6d-4c47-82b9-0bc11ce1cdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30772
95091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3077295091
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1546554535
Short name T1121
Test name
Test status
Simulation time 8395800164 ps
CPU time 8.89 seconds
Started May 09 02:49:02 PM PDT 24
Finished May 09 02:49:14 PM PDT 24
Peak memory 204548 kb
Host smart-c5d04b89-744f-49e0-a9da-e6949068f237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
54535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1546554535
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3273328332
Short name T715
Test name
Test status
Simulation time 8433477231 ps
CPU time 9.73 seconds
Started May 09 02:49:08 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204572 kb
Host smart-d4ab7203-2bc4-4ed2-96b1-384ee71fb163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
28332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3273328332
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.100077846
Short name T11
Test name
Test status
Simulation time 8382788222 ps
CPU time 7.5 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204560 kb
Host smart-93e6045e-acbd-444e-8ebc-d2ee359fb525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10007
7846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.100077846
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.228491649
Short name T990
Test name
Test status
Simulation time 39214183 ps
CPU time 0.66 seconds
Started May 09 02:49:04 PM PDT 24
Finished May 09 02:49:08 PM PDT 24
Peak memory 204416 kb
Host smart-8f5e9174-8b4c-4437-85e8-aee276da4dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22849
1649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.228491649
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1304611114
Short name T1346
Test name
Test status
Simulation time 25592493508 ps
CPU time 47.05 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:50:00 PM PDT 24
Peak memory 204784 kb
Host smart-4d70a6dc-07c9-4c41-a423-664aa5ac6743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13046
11114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1304611114
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2735461923
Short name T644
Test name
Test status
Simulation time 8392568641 ps
CPU time 7.41 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:18 PM PDT 24
Peak memory 204832 kb
Host smart-6c2042d4-ebe3-435d-8f2d-2a406aa4d435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27354
61923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2735461923
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2595905042
Short name T494
Test name
Test status
Simulation time 8456658720 ps
CPU time 7.47 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204504 kb
Host smart-705d37db-87f3-4221-aa70-73720665724c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25959
05042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2595905042
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2096422838
Short name T324
Test name
Test status
Simulation time 8428292915 ps
CPU time 8.62 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:19 PM PDT 24
Peak memory 204608 kb
Host smart-7e0de91c-24a5-4cc2-90e1-c9927ff0387a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20964
22838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2096422838
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2208258839
Short name T1227
Test name
Test status
Simulation time 8375900294 ps
CPU time 8.49 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204524 kb
Host smart-8854f977-6a09-49c6-87b0-4cec1a48305b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22082
58839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2208258839
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.4044640102
Short name T933
Test name
Test status
Simulation time 8369784399 ps
CPU time 7.68 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204500 kb
Host smart-49afdd12-b62b-4180-be96-54ee81be9cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
40102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.4044640102
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.779849727
Short name T1399
Test name
Test status
Simulation time 8463700034 ps
CPU time 7.84 seconds
Started May 09 02:49:01 PM PDT 24
Finished May 09 02:49:12 PM PDT 24
Peak memory 204576 kb
Host smart-20dbd266-eaa4-45f1-b9a6-d395fe33a5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77984
9727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.779849727
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3056770133
Short name T1335
Test name
Test status
Simulation time 8401537664 ps
CPU time 8 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204584 kb
Host smart-43207395-1000-440c-8bc6-fbd4fa1a23bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
70133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3056770133
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.748758524
Short name T322
Test name
Test status
Simulation time 8400241950 ps
CPU time 7.94 seconds
Started May 09 02:49:04 PM PDT 24
Finished May 09 02:49:15 PM PDT 24
Peak memory 204620 kb
Host smart-266f0255-a826-40f4-9111-3a7612cdba9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74875
8524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.748758524
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.2062362933
Short name T1113
Test name
Test status
Simulation time 8465621994 ps
CPU time 8.92 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204820 kb
Host smart-ee8e0b47-5c82-4c22-b26a-b946a8f33600
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2062362933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.2062362933
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.4116807843
Short name T514
Test name
Test status
Simulation time 8399455344 ps
CPU time 10.05 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204572 kb
Host smart-c5bd2d18-82f9-4439-be26-eba9df60fd89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4116807843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.4116807843
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.1040193528
Short name T151
Test name
Test status
Simulation time 8427246362 ps
CPU time 7.9 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204524 kb
Host smart-86ceaeff-19ce-47e4-8068-1890aea73761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401
93528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.1040193528
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3341895379
Short name T434
Test name
Test status
Simulation time 8403258432 ps
CPU time 9.06 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204572 kb
Host smart-f2017712-1ecc-4fe6-8a46-42f9651da2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33418
95379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3341895379
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3329925796
Short name T773
Test name
Test status
Simulation time 8868267772 ps
CPU time 12.45 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204828 kb
Host smart-876908c8-33d3-447a-9964-c7d329126bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
25796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3329925796
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_enable.3261683210
Short name T417
Test name
Test status
Simulation time 8389590996 ps
CPU time 8.62 seconds
Started May 09 02:49:10 PM PDT 24
Finished May 09 02:49:25 PM PDT 24
Peak memory 204560 kb
Host smart-d723ba01-537c-4280-b887-7b0ef79fcafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32616
83210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3261683210
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2224243317
Short name T1075
Test name
Test status
Simulation time 143632456 ps
CPU time 1.65 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:16 PM PDT 24
Peak memory 204700 kb
Host smart-bfd76a28-1383-4688-ba03-05d6642b5310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
43317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2224243317
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1504381881
Short name T382
Test name
Test status
Simulation time 8459328092 ps
CPU time 7.75 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204824 kb
Host smart-24b97197-70f2-4639-a180-fe625f00728f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15043
81881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1504381881
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1013140693
Short name T203
Test name
Test status
Simulation time 8362883123 ps
CPU time 8.55 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204572 kb
Host smart-891fae8e-fdbf-4fb7-8ac0-88f0826bd728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10131
40693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1013140693
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1138090733
Short name T620
Test name
Test status
Simulation time 8451654547 ps
CPU time 10.14 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:24 PM PDT 24
Peak memory 204584 kb
Host smart-a769eaa6-c51f-4b6f-9612-3e9641af3db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11380
90733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1138090733
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3674261824
Short name T323
Test name
Test status
Simulation time 8434390165 ps
CPU time 7.62 seconds
Started May 09 02:49:04 PM PDT 24
Finished May 09 02:49:15 PM PDT 24
Peak memory 204588 kb
Host smart-0ff526c0-efef-425f-b9b1-bf179f87e480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
61824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3674261824
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3593996312
Short name T697
Test name
Test status
Simulation time 8369315883 ps
CPU time 9.76 seconds
Started May 09 02:49:02 PM PDT 24
Finished May 09 02:49:15 PM PDT 24
Peak memory 204496 kb
Host smart-3317a4cb-2c9f-44ab-8a4b-d342b69ab4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35939
96312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3593996312
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1947573975
Short name T116
Test name
Test status
Simulation time 8415258016 ps
CPU time 9.18 seconds
Started May 09 02:49:05 PM PDT 24
Finished May 09 02:49:19 PM PDT 24
Peak memory 204356 kb
Host smart-c7f50bbe-3858-4564-9eb9-f6c7ca7a7a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19475
73975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1947573975
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.4104980490
Short name T1391
Test name
Test status
Simulation time 8373944746 ps
CPU time 8.74 seconds
Started May 09 02:49:07 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 204596 kb
Host smart-b2f58a87-fa90-4105-990a-847729767cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049
80490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.4104980490
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2226782052
Short name T383
Test name
Test status
Simulation time 8387718949 ps
CPU time 8.32 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204584 kb
Host smart-76636bd5-5731-4069-bdc4-15eba9f293bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
82052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2226782052
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2150176458
Short name T196
Test name
Test status
Simulation time 8431991414 ps
CPU time 7.57 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204596 kb
Host smart-eef3853e-9a1c-41ba-8aa9-ce30b683a1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21501
76458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2150176458
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.486465182
Short name T1094
Test name
Test status
Simulation time 8365055684 ps
CPU time 8.51 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204456 kb
Host smart-fb2d238f-b19a-42a8-938e-0f0ac172e78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48646
5182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.486465182
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1592563140
Short name T50
Test name
Test status
Simulation time 41357748 ps
CPU time 0.62 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:23 PM PDT 24
Peak memory 204444 kb
Host smart-33e3f73d-d8d0-4c4f-a723-6199ed990509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
63140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1592563140
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3940448027
Short name T799
Test name
Test status
Simulation time 24267405609 ps
CPU time 45 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:50:07 PM PDT 24
Peak memory 204864 kb
Host smart-30af140c-7d32-481c-bad0-2d28805bf252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39404
48027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3940448027
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2366207608
Short name T588
Test name
Test status
Simulation time 8406208705 ps
CPU time 7.5 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:28 PM PDT 24
Peak memory 204536 kb
Host smart-33c045f9-b5b8-45e7-a5bc-4a641a88843b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
07608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2366207608
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3107122571
Short name T942
Test name
Test status
Simulation time 8435940416 ps
CPU time 7.35 seconds
Started May 09 02:49:12 PM PDT 24
Finished May 09 02:49:27 PM PDT 24
Peak memory 204552 kb
Host smart-b15e971f-8e82-4cfc-a6ef-cd82cab64e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31071
22571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3107122571
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.3786324849
Short name T88
Test name
Test status
Simulation time 8397038440 ps
CPU time 10.43 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204616 kb
Host smart-80563e17-bce0-4b9f-acff-13d576f598b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
24849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.3786324849
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.546616726
Short name T718
Test name
Test status
Simulation time 8386505214 ps
CPU time 7.85 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204528 kb
Host smart-1e9d6b2a-a181-4c41-9d45-3a511fb7a70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54661
6726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.546616726
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1286993898
Short name T1115
Test name
Test status
Simulation time 8449821750 ps
CPU time 8.51 seconds
Started May 09 02:49:06 PM PDT 24
Finished May 09 02:49:21 PM PDT 24
Peak memory 204576 kb
Host smart-39275d29-aaa5-4f94-882b-d2f5827faade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
93898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1286993898
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1492172795
Short name T1203
Test name
Test status
Simulation time 8416146140 ps
CPU time 7.98 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204572 kb
Host smart-77a86aba-dff2-4281-a75e-ab83507fc415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14921
72795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1492172795
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.4289372140
Short name T469
Test name
Test status
Simulation time 8376666395 ps
CPU time 8.56 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204492 kb
Host smart-c136e309-cdd8-404f-99c5-9d7136273387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42893
72140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.4289372140
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3440210454
Short name T959
Test name
Test status
Simulation time 8511554314 ps
CPU time 7.88 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204548 kb
Host smart-ced37a5e-39bd-4de0-8f05-0c94c1d4e550
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3440210454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3440210454
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2827042805
Short name T1366
Test name
Test status
Simulation time 8382513287 ps
CPU time 9.69 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204560 kb
Host smart-a0dfb49f-e16a-42df-982a-8181b941e89c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2827042805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2827042805
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.3351721818
Short name T708
Test name
Test status
Simulation time 8433318745 ps
CPU time 8 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204580 kb
Host smart-66f01c8c-422e-44da-a2c3-bf18e17ad717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33517
21818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.3351721818
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.865658590
Short name T672
Test name
Test status
Simulation time 8405351311 ps
CPU time 7.91 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204540 kb
Host smart-2e72144e-db3e-4860-a598-c72338b0076f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86565
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.865658590
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2199977839
Short name T495
Test name
Test status
Simulation time 8763846813 ps
CPU time 11.77 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:34 PM PDT 24
Peak memory 204788 kb
Host smart-1a4e4340-fff1-43f1-a4cd-44d46fb0ec1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
77839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2199977839
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_enable.2355265888
Short name T55
Test name
Test status
Simulation time 8377892997 ps
CPU time 8.66 seconds
Started May 09 02:49:17 PM PDT 24
Finished May 09 02:49:33 PM PDT 24
Peak memory 204560 kb
Host smart-d11820ae-953b-4101-b227-2717281e700b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23552
65888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2355265888
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2790957599
Short name T1272
Test name
Test status
Simulation time 127442316 ps
CPU time 1.2 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204644 kb
Host smart-3088f039-8b04-477b-aefc-87e55b8a75d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27909
57599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2790957599
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3522603811
Short name T521
Test name
Test status
Simulation time 8466117972 ps
CPU time 7.85 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204556 kb
Host smart-a8b0c379-f9f6-4c06-96d4-d10ac434261e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35226
03811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3522603811
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3555778790
Short name T1373
Test name
Test status
Simulation time 8382360369 ps
CPU time 7.6 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204556 kb
Host smart-7e20d3e4-b410-4721-ad84-d78a1f9aa4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
78790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3555778790
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.126433136
Short name T1117
Test name
Test status
Simulation time 8421330491 ps
CPU time 7.67 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204556 kb
Host smart-a1eb4e9e-424a-4347-9ba0-b098423ca6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12643
3136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.126433136
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1434276568
Short name T637
Test name
Test status
Simulation time 8441231852 ps
CPU time 8.2 seconds
Started May 09 02:49:22 PM PDT 24
Finished May 09 02:49:38 PM PDT 24
Peak memory 204564 kb
Host smart-4d6afda9-5f8f-4269-bea6-9df86b8d6a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14342
76568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1434276568
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3241812291
Short name T1259
Test name
Test status
Simulation time 8369932596 ps
CPU time 8.48 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204540 kb
Host smart-8e41d3f0-5c03-47c7-99c4-10cfbc220db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
12291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3241812291
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1640418232
Short name T113
Test name
Test status
Simulation time 8431044603 ps
CPU time 7.47 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204460 kb
Host smart-04032b70-4b37-4ae6-a872-19d2b6278e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
18232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1640418232
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1081941081
Short name T734
Test name
Test status
Simulation time 8404533302 ps
CPU time 7.69 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:28 PM PDT 24
Peak memory 204500 kb
Host smart-6e690fe4-927f-4964-870c-32d1c5830442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
41081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1081941081
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2365510398
Short name T621
Test name
Test status
Simulation time 8381266126 ps
CPU time 9.72 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204468 kb
Host smart-4ce01956-83a5-49f2-be92-bba4b2d18dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23655
10398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2365510398
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.791675288
Short name T835
Test name
Test status
Simulation time 8411381323 ps
CPU time 8.67 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204564 kb
Host smart-f2cecd38-2985-4e29-a072-18fc5f4ac54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79167
5288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.791675288
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1271105997
Short name T1159
Test name
Test status
Simulation time 8367987108 ps
CPU time 8.26 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204488 kb
Host smart-e1d3d7f0-1c32-4f42-897e-2130f9d2a350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
05997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1271105997
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.134528165
Short name T484
Test name
Test status
Simulation time 54398414 ps
CPU time 0.67 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:22 PM PDT 24
Peak memory 204444 kb
Host smart-d4f3d45f-2f7a-4ab2-9d2d-7760cc612c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
8165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.134528165
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.361979339
Short name T824
Test name
Test status
Simulation time 19078395358 ps
CPU time 35.33 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204732 kb
Host smart-0c610e10-339a-4c86-8f26-61f0d4a076df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
9339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.361979339
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.4293160890
Short name T532
Test name
Test status
Simulation time 8389306132 ps
CPU time 9.29 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204480 kb
Host smart-3cf74130-dfff-4b94-8a75-dc3c3bf87451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42931
60890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.4293160890
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3917771370
Short name T808
Test name
Test status
Simulation time 8407476494 ps
CPU time 9.27 seconds
Started May 09 02:49:20 PM PDT 24
Finished May 09 02:49:37 PM PDT 24
Peak memory 204560 kb
Host smart-a606e250-329f-4735-bf06-8b6cf4d1c3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39177
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3917771370
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2765549292
Short name T1364
Test name
Test status
Simulation time 8386537627 ps
CPU time 10.3 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:34 PM PDT 24
Peak memory 204584 kb
Host smart-8555b3ad-7ad4-47e7-b69d-bb77854e486d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27655
49292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2765549292
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1816275163
Short name T31
Test name
Test status
Simulation time 8376629231 ps
CPU time 8 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204552 kb
Host smart-39785c5c-620c-4412-807c-525171975c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
75163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1816275163
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.817630711
Short name T409
Test name
Test status
Simulation time 8359759245 ps
CPU time 8.63 seconds
Started May 09 02:49:20 PM PDT 24
Finished May 09 02:49:36 PM PDT 24
Peak memory 204576 kb
Host smart-d8a2ae4a-5555-4e51-8aad-48930b132976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81763
0711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.817630711
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1111105317
Short name T660
Test name
Test status
Simulation time 8431320970 ps
CPU time 7.91 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204520 kb
Host smart-6c414140-96f1-4d10-a3a8-91ab6dcfda31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111
05317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1111105317
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3100794977
Short name T1247
Test name
Test status
Simulation time 8411967410 ps
CPU time 7.94 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204604 kb
Host smart-40bcc856-7c01-4536-afef-34e1a7ce932a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31007
94977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3100794977
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2769598150
Short name T564
Test name
Test status
Simulation time 8402640057 ps
CPU time 7.3 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204480 kb
Host smart-7b13d26f-07ba-4849-a69d-965dc32fe0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27695
98150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2769598150
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.2464929912
Short name T613
Test name
Test status
Simulation time 8468745847 ps
CPU time 8.43 seconds
Started May 09 02:49:22 PM PDT 24
Finished May 09 02:49:38 PM PDT 24
Peak memory 204548 kb
Host smart-1b4a70ba-c57b-4d78-97de-64f6cfbce4ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2464929912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.2464929912
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.4260587436
Short name T403
Test name
Test status
Simulation time 8417308245 ps
CPU time 7.63 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:38 PM PDT 24
Peak memory 204548 kb
Host smart-44aaef3e-d1c1-4af2-957b-c2d94c347554
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4260587436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.4260587436
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.4290751481
Short name T1431
Test name
Test status
Simulation time 8423694186 ps
CPU time 9.84 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204568 kb
Host smart-1eea2599-bb8f-4fe6-9884-5959cb29c34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42907
51481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.4290751481
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.880707670
Short name T912
Test name
Test status
Simulation time 8377390648 ps
CPU time 8.21 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:43 PM PDT 24
Peak memory 204568 kb
Host smart-37c868b8-ac95-4f68-ba94-7892797979e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88070
7670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.880707670
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3477036535
Short name T597
Test name
Test status
Simulation time 8906533834 ps
CPU time 12.28 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:34 PM PDT 24
Peak memory 204816 kb
Host smart-47c4680d-8a5a-4dd9-9106-ec30bbd77d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34770
36535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3477036535
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_enable.1695046577
Short name T1207
Test name
Test status
Simulation time 8373947442 ps
CPU time 7.58 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204508 kb
Host smart-92a6bc59-61a5-416c-ba0e-5989d4e30c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
46577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1695046577
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1522052404
Short name T474
Test name
Test status
Simulation time 81343374 ps
CPU time 1.57 seconds
Started May 09 02:49:11 PM PDT 24
Finished May 09 02:49:20 PM PDT 24
Peak memory 204700 kb
Host smart-8d4dabb5-25c2-43d0-ac13-c42ede6d2e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
52404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1522052404
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2357899889
Short name T557
Test name
Test status
Simulation time 8441814786 ps
CPU time 9.29 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204604 kb
Host smart-8554fb14-7b30-4a29-9785-de0de2bb32e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23578
99889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2357899889
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3076104700
Short name T1001
Test name
Test status
Simulation time 8381862207 ps
CPU time 9.96 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:40 PM PDT 24
Peak memory 204548 kb
Host smart-bd137aa2-0c04-477b-a562-cd34bc649f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30761
04700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3076104700
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3336786678
Short name T908
Test name
Test status
Simulation time 8426068618 ps
CPU time 10.21 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204588 kb
Host smart-222e4f78-af9f-487a-b6fe-bea906bc50fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33367
86678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3336786678
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3932586273
Short name T866
Test name
Test status
Simulation time 8410728888 ps
CPU time 7.79 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204560 kb
Host smart-246407b7-3aba-42e0-a5be-f728f3a70d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39325
86273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3932586273
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2423016832
Short name T673
Test name
Test status
Simulation time 8363211783 ps
CPU time 7.6 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204544 kb
Host smart-3eaf9a1f-a93e-46d4-b7b0-70da7c451c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24230
16832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2423016832
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2161467186
Short name T111
Test name
Test status
Simulation time 8411109545 ps
CPU time 8.09 seconds
Started May 09 02:49:12 PM PDT 24
Finished May 09 02:49:27 PM PDT 24
Peak memory 204544 kb
Host smart-9d479bdc-5201-46f8-9335-4f9baeea118d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21614
67186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2161467186
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2347419946
Short name T301
Test name
Test status
Simulation time 8398017246 ps
CPU time 7.33 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:28 PM PDT 24
Peak memory 204600 kb
Host smart-89cc4c40-2271-49df-90f7-ac7b71d94e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23474
19946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2347419946
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.4226030032
Short name T1101
Test name
Test status
Simulation time 8394438602 ps
CPU time 8.42 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204576 kb
Host smart-adb33458-1601-482a-b9ef-c85fd7047b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
30032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.4226030032
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.945076150
Short name T1395
Test name
Test status
Simulation time 8447397036 ps
CPU time 8.06 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204548 kb
Host smart-d3c8fe0f-e38a-4178-bc07-733ea8177743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94507
6150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.945076150
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2945540242
Short name T935
Test name
Test status
Simulation time 8375809752 ps
CPU time 7.39 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204560 kb
Host smart-d296a4f4-408a-44f2-8a29-fa3a06c81637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
40242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2945540242
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3851873999
Short name T717
Test name
Test status
Simulation time 65195462 ps
CPU time 0.68 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:24 PM PDT 24
Peak memory 204500 kb
Host smart-223916d3-c7f5-4ecf-98e3-2fd630e65195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38518
73999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3851873999
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1263073330
Short name T1045
Test name
Test status
Simulation time 18256908210 ps
CPU time 37.26 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:59 PM PDT 24
Peak memory 204832 kb
Host smart-0ff33ce3-3fb7-46fd-902a-00c80f887620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12630
73330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1263073330
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.4212196801
Short name T984
Test name
Test status
Simulation time 8409757811 ps
CPU time 8.01 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204536 kb
Host smart-f2f17b91-731b-4679-970e-59ef374ec025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42121
96801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.4212196801
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2423752882
Short name T54
Test name
Test status
Simulation time 8461782665 ps
CPU time 8.53 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204504 kb
Host smart-2af3e7d5-2810-4568-ad6d-29de5248f34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24237
52882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2423752882
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.553186946
Short name T1236
Test name
Test status
Simulation time 8394473115 ps
CPU time 7.66 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204628 kb
Host smart-fa48a1e4-ffea-4178-b0b1-874a74bc6f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55318
6946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.553186946
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3981172703
Short name T646
Test name
Test status
Simulation time 8375737687 ps
CPU time 7.74 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204620 kb
Host smart-aa004b5f-e7d5-4f64-a0e3-78a47fb47096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39811
72703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3981172703
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3539472673
Short name T971
Test name
Test status
Simulation time 8378593762 ps
CPU time 7.95 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204548 kb
Host smart-3a4a666e-b443-4587-9cea-9a88d8107530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35394
72673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3539472673
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1292647271
Short name T1406
Test name
Test status
Simulation time 8389472703 ps
CPU time 7.62 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204576 kb
Host smart-3b5506d9-5afc-46cf-864c-d9d84e69587b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926
47271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1292647271
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2042488258
Short name T39
Test name
Test status
Simulation time 8369461353 ps
CPU time 7.95 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:31 PM PDT 24
Peak memory 204620 kb
Host smart-ebb93c8f-3a9f-47f5-8244-866ffe7ae245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20424
88258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2042488258
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1387754284
Short name T991
Test name
Test status
Simulation time 8467859845 ps
CPU time 8 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204568 kb
Host smart-0272cdd3-3660-46cb-a68e-866b1ba321ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1387754284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1387754284
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1236932345
Short name T1411
Test name
Test status
Simulation time 8395010125 ps
CPU time 10.1 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204556 kb
Host smart-79ccbb69-d527-48c2-b8cd-d31897466765
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1236932345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1236932345
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.3855946007
Short name T1156
Test name
Test status
Simulation time 8409320020 ps
CPU time 7.74 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204560 kb
Host smart-b42114e0-7a41-43be-8cfa-8f7404b41b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38559
46007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.3855946007
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.362850507
Short name T573
Test name
Test status
Simulation time 8377342024 ps
CPU time 8.29 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:32 PM PDT 24
Peak memory 204548 kb
Host smart-419fbd6e-610b-4848-b872-362f8c1287ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36285
0507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.362850507
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1814310948
Short name T464
Test name
Test status
Simulation time 9461085773 ps
CPU time 12.38 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:46 PM PDT 24
Peak memory 204740 kb
Host smart-3ad73b89-d3f6-4618-aaa4-bc5d36ba092c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
10948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1814310948
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_enable.1610217741
Short name T522
Test name
Test status
Simulation time 8393781073 ps
CPU time 7.8 seconds
Started May 09 02:49:13 PM PDT 24
Finished May 09 02:49:28 PM PDT 24
Peak memory 204508 kb
Host smart-ff8b83cd-62c8-478d-bd67-ac7d886d9483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
17741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1610217741
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1283292779
Short name T569
Test name
Test status
Simulation time 45008719 ps
CPU time 1 seconds
Started May 09 02:49:16 PM PDT 24
Finished May 09 02:49:24 PM PDT 24
Peak memory 204732 kb
Host smart-e5b59fb2-4ea7-4aff-af7b-edb7cd8896cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
92779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1283292779
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2237681558
Short name T24
Test name
Test status
Simulation time 8414187437 ps
CPU time 9.12 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204572 kb
Host smart-ea0826bf-64ff-4aab-b631-c9652aba9d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22376
81558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2237681558
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2183679239
Short name T1192
Test name
Test status
Simulation time 8370469400 ps
CPU time 7.97 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204568 kb
Host smart-6c503769-1b10-4195-ba3f-271c21759cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21836
79239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2183679239
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1126046010
Short name T1078
Test name
Test status
Simulation time 8447820805 ps
CPU time 10.2 seconds
Started May 09 02:49:15 PM PDT 24
Finished May 09 02:49:33 PM PDT 24
Peak memory 204576 kb
Host smart-ccffce09-cce5-457e-b2cb-fc2af701a75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11260
46010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1126046010
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2367429455
Short name T822
Test name
Test status
Simulation time 8434439271 ps
CPU time 7.69 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:29 PM PDT 24
Peak memory 204568 kb
Host smart-6050e192-da12-46e5-8c12-bbf3e187b84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23674
29455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2367429455
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1115220742
Short name T1262
Test name
Test status
Simulation time 8373799508 ps
CPU time 7.73 seconds
Started May 09 02:49:20 PM PDT 24
Finished May 09 02:49:35 PM PDT 24
Peak memory 204564 kb
Host smart-47ec66e9-402d-4508-a76f-9fcaa3dd13f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11152
20742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1115220742
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.989589469
Short name T100
Test name
Test status
Simulation time 8429056577 ps
CPU time 7.44 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204476 kb
Host smart-e6009df1-5554-4c99-8372-cdc703429559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98958
9469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.989589469
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2987659598
Short name T1414
Test name
Test status
Simulation time 8375567478 ps
CPU time 8.03 seconds
Started May 09 02:49:20 PM PDT 24
Finished May 09 02:49:36 PM PDT 24
Peak memory 204564 kb
Host smart-d1251a4a-f28f-42cb-a857-f80d2abd97c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29876
59598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2987659598
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2303968276
Short name T865
Test name
Test status
Simulation time 8409841068 ps
CPU time 7.64 seconds
Started May 09 02:49:20 PM PDT 24
Finished May 09 02:49:35 PM PDT 24
Peak memory 204580 kb
Host smart-843a3e49-ef1f-4ecd-ba70-dda2d7fb9476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
68276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2303968276
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.4124411541
Short name T1021
Test name
Test status
Simulation time 8382137348 ps
CPU time 8.07 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204560 kb
Host smart-b693d4a1-5448-4182-90cd-a995e40254a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41244
11541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.4124411541
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1155011537
Short name T716
Test name
Test status
Simulation time 8428677612 ps
CPU time 7.71 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204556 kb
Host smart-a358340a-d04a-4f66-83a9-714199b9e3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11550
11537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1155011537
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3522180600
Short name T647
Test name
Test status
Simulation time 46367527 ps
CPU time 0.68 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:35 PM PDT 24
Peak memory 204492 kb
Host smart-7ae9d60f-7983-4283-bed5-c51d008fe3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35221
80600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3522180600
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2380246714
Short name T842
Test name
Test status
Simulation time 29813446316 ps
CPU time 59.11 seconds
Started May 09 02:49:19 PM PDT 24
Finished May 09 02:50:26 PM PDT 24
Peak memory 204768 kb
Host smart-0d85ee4d-0f3f-4ff0-a3e4-a39bf1f19154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802
46714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2380246714
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3206027590
Short name T396
Test name
Test status
Simulation time 8421661732 ps
CPU time 7.36 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204480 kb
Host smart-8bebb249-1729-4b8b-b443-91f848a828c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060
27590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3206027590
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.658448336
Short name T916
Test name
Test status
Simulation time 8395122813 ps
CPU time 8.34 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204588 kb
Host smart-f8cfba92-1ca6-48a3-8691-2d3aaf579ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65844
8336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.658448336
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.4146404647
Short name T407
Test name
Test status
Simulation time 8428990710 ps
CPU time 8.85 seconds
Started May 09 02:49:14 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 204500 kb
Host smart-6c9c5188-7d94-4775-9aa6-20839b26a76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
04647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.4146404647
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3191069266
Short name T885
Test name
Test status
Simulation time 8377362776 ps
CPU time 7.37 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:40 PM PDT 24
Peak memory 204576 kb
Host smart-819c0a25-7418-4550-a6a7-d38558b37fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31910
69266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3191069266
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2540496186
Short name T420
Test name
Test status
Simulation time 8370364529 ps
CPU time 9.1 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204548 kb
Host smart-79032262-6682-4673-8f43-378c36c86725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
96186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2540496186
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.4001883681
Short name T1392
Test name
Test status
Simulation time 8441538430 ps
CPU time 7.58 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:38 PM PDT 24
Peak memory 204564 kb
Host smart-649b03fc-9f31-47c0-bd22-ec0497849b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40018
83681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4001883681
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2006846097
Short name T838
Test name
Test status
Simulation time 8417306072 ps
CPU time 8.16 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204552 kb
Host smart-c8d844e0-bfe5-499d-bb70-f6d2981d940b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
46097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2006846097
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1516845569
Short name T980
Test name
Test status
Simulation time 8385260171 ps
CPU time 9.3 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204576 kb
Host smart-d86be95e-6c5a-4c69-8f6a-5b2d08d73b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
45569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1516845569
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.2072573333
Short name T1353
Test name
Test status
Simulation time 8459336860 ps
CPU time 8.35 seconds
Started May 09 02:46:11 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 204548 kb
Host smart-d3f56b3b-848a-44fa-a28e-059fa310dbc5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2072573333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.2072573333
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2143669896
Short name T888
Test name
Test status
Simulation time 8377148147 ps
CPU time 8.39 seconds
Started May 09 02:46:20 PM PDT 24
Finished May 09 02:46:30 PM PDT 24
Peak memory 204384 kb
Host smart-fbf00e65-fa63-4bcc-9c5d-4771339f40dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2143669896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2143669896
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.1588485269
Short name T1418
Test name
Test status
Simulation time 8436358828 ps
CPU time 8.85 seconds
Started May 09 02:46:12 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 204608 kb
Host smart-f60cf093-9f4f-441e-a6b0-14f2f63ec89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884
85269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.1588485269
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.182309322
Short name T1134
Test name
Test status
Simulation time 8376492476 ps
CPU time 10.29 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 204608 kb
Host smart-ae482fce-f2f2-4b59-86c3-758573c7077a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18230
9322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.182309322
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1721863073
Short name T198
Test name
Test status
Simulation time 8971963694 ps
CPU time 14.64 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:20 PM PDT 24
Peak memory 204816 kb
Host smart-39bfa81c-4103-45b7-9513-6af3624081a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
63073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1721863073
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_enable.3132902901
Short name T483
Test name
Test status
Simulation time 8437031084 ps
CPU time 8.62 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 204584 kb
Host smart-30ca94dd-9e9c-4ebf-96a8-f57468afb254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329
02901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3132902901
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.797563262
Short name T1400
Test name
Test status
Simulation time 301471741 ps
CPU time 2.49 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:08 PM PDT 24
Peak memory 204776 kb
Host smart-9f28be21-edeb-405c-9833-c2c2ef2a5b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79756
3262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.797563262
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1538244689
Short name T134
Test name
Test status
Simulation time 8440483118 ps
CPU time 7.8 seconds
Started May 09 02:46:11 PM PDT 24
Finished May 09 02:46:21 PM PDT 24
Peak memory 204596 kb
Host smart-67af3043-d090-4811-975a-069d97caa408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15382
44689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1538244689
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.90066697
Short name T882
Test name
Test status
Simulation time 8361383144 ps
CPU time 8.59 seconds
Started May 09 02:46:15 PM PDT 24
Finished May 09 02:46:26 PM PDT 24
Peak memory 204540 kb
Host smart-cdfd07a2-8486-4ca7-9246-b8e798be4f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90066
697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.90066697
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1369179134
Short name T834
Test name
Test status
Simulation time 8449436851 ps
CPU time 7.69 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204628 kb
Host smart-f42f0f1c-a9d4-4889-8b2b-50e4fdbe05c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13691
79134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1369179134
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2952523898
Short name T384
Test name
Test status
Simulation time 8410285480 ps
CPU time 8.72 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:12 PM PDT 24
Peak memory 204600 kb
Host smart-c87cd3a1-71a7-4b83-bd4c-f115109a500a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29525
23898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2952523898
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2551653363
Short name T1062
Test name
Test status
Simulation time 8380573326 ps
CPU time 8 seconds
Started May 09 02:46:07 PM PDT 24
Finished May 09 02:46:17 PM PDT 24
Peak memory 204564 kb
Host smart-af05266e-ea58-47bb-a4cf-cf128bb4c66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25516
53363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2551653363
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3654083787
Short name T119
Test name
Test status
Simulation time 8413377061 ps
CPU time 9.04 seconds
Started May 09 02:45:59 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204564 kb
Host smart-dfe927ea-3106-4a90-b065-d0fe56547b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36540
83787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3654083787
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.4089671507
Short name T884
Test name
Test status
Simulation time 8400392348 ps
CPU time 8.36 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204580 kb
Host smart-0ee12b63-e5d7-4952-88a5-dfb6611dffcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
71507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.4089671507
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1677596116
Short name T830
Test name
Test status
Simulation time 8395495665 ps
CPU time 8.06 seconds
Started May 09 02:46:04 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204556 kb
Host smart-23b721b6-5784-4f57-8e56-6432a36d71e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16775
96116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1677596116
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4277702860
Short name T29
Test name
Test status
Simulation time 8373055827 ps
CPU time 7.89 seconds
Started May 09 02:46:04 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 204548 kb
Host smart-a9c8456b-43b9-46c4-8843-38dc021dcb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42777
02860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4277702860
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3864876255
Short name T883
Test name
Test status
Simulation time 57243951 ps
CPU time 0.68 seconds
Started May 09 02:46:20 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 204328 kb
Host smart-6f05918b-0d98-4830-9bb0-2a8f694a5970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38648
76255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3864876255
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.553156760
Short name T228
Test name
Test status
Simulation time 28087065154 ps
CPU time 59.77 seconds
Started May 09 02:46:04 PM PDT 24
Finished May 09 02:47:07 PM PDT 24
Peak memory 204736 kb
Host smart-8ca29ef4-39f3-48aa-b89f-32ebed569ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55315
6760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.553156760
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2570168761
Short name T902
Test name
Test status
Simulation time 8433401892 ps
CPU time 7.97 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204556 kb
Host smart-cbb0393d-3a0a-4622-bb4e-2fbb3b529031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25701
68761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2570168761
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2869910737
Short name T683
Test name
Test status
Simulation time 8403069763 ps
CPU time 7.86 seconds
Started May 09 02:46:08 PM PDT 24
Finished May 09 02:46:17 PM PDT 24
Peak memory 204528 kb
Host smart-1669269f-66f1-43aa-8197-339a197c423f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
10737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2869910737
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1965049771
Short name T997
Test name
Test status
Simulation time 8426405945 ps
CPU time 7.71 seconds
Started May 09 02:45:59 PM PDT 24
Finished May 09 02:46:09 PM PDT 24
Peak memory 204548 kb
Host smart-283b409a-fd2c-4719-832c-0b2ea54d52db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19650
49771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1965049771
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.783286063
Short name T78
Test name
Test status
Simulation time 860303408 ps
CPU time 1.71 seconds
Started May 09 02:46:11 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 221984 kb
Host smart-327128f0-b528-4581-a72d-dd2217c1c358
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=783286063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.783286063
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2094061124
Short name T1228
Test name
Test status
Simulation time 8380047900 ps
CPU time 9.21 seconds
Started May 09 02:46:00 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 204484 kb
Host smart-fdbd6ec8-417e-4298-8d3f-4a08a2602c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20940
61124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2094061124
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1923469523
Short name T1304
Test name
Test status
Simulation time 8366392153 ps
CPU time 8.34 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204556 kb
Host smart-130fe040-461b-40fc-aa99-adcb74c04815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234
69523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1923469523
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4099825993
Short name T183
Test name
Test status
Simulation time 8442847738 ps
CPU time 7.78 seconds
Started May 09 02:46:02 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 204504 kb
Host smart-e1527ec1-0f14-40d7-91b6-cc3ee1598ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
25993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4099825993
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.343229785
Short name T762
Test name
Test status
Simulation time 8369195304 ps
CPU time 8.01 seconds
Started May 09 02:46:01 PM PDT 24
Finished May 09 02:46:12 PM PDT 24
Peak memory 204564 kb
Host smart-4174b439-5386-461e-9219-c5d9c0e4798b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34322
9785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.343229785
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3988354093
Short name T1286
Test name
Test status
Simulation time 8397265661 ps
CPU time 7.81 seconds
Started May 09 02:46:03 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 204520 kb
Host smart-6f577605-09dd-40af-b269-bcf38f80b54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39883
54093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3988354093
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.1279655935
Short name T861
Test name
Test status
Simulation time 8465481371 ps
CPU time 8.39 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204560 kb
Host smart-f468af07-e30a-4eed-9989-62e6097122e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1279655935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.1279655935
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3014414483
Short name T833
Test name
Test status
Simulation time 8382220864 ps
CPU time 8.28 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:43 PM PDT 24
Peak memory 204600 kb
Host smart-ff73334d-ce9b-4440-9c54-5da9d8fbcdcc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3014414483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3014414483
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.1558507784
Short name T703
Test name
Test status
Simulation time 8505882033 ps
CPU time 9.2 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:46 PM PDT 24
Peak memory 204624 kb
Host smart-291a3b01-bf3d-4d86-a0fa-97b937e0e8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
07784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.1558507784
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.223798179
Short name T450
Test name
Test status
Simulation time 8379508858 ps
CPU time 8.31 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204568 kb
Host smart-516d5aa6-1550-4eb5-8eff-c3b482f2621b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22379
8179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.223798179
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2710554329
Short name T194
Test name
Test status
Simulation time 9744852716 ps
CPU time 14.47 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:49 PM PDT 24
Peak memory 204844 kb
Host smart-ce854562-4e60-4449-aa8d-3b6f879e3e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27105
54329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2710554329
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_enable.665438969
Short name T540
Test name
Test status
Simulation time 8372578051 ps
CPU time 9.28 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204568 kb
Host smart-6f9d9209-ab86-466f-bc12-4fe246ed2b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66543
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.665438969
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2945463435
Short name T408
Test name
Test status
Simulation time 55196105 ps
CPU time 1.48 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:34 PM PDT 24
Peak memory 204732 kb
Host smart-e1effc85-6168-4d8e-9541-b1ab9613f287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454
63435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2945463435
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.176271440
Short name T132
Test name
Test status
Simulation time 8401434957 ps
CPU time 7.8 seconds
Started May 09 02:49:29 PM PDT 24
Finished May 09 02:49:46 PM PDT 24
Peak memory 204608 kb
Host smart-99932b76-7dd6-4e54-a3d4-b10de1df2f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17627
1440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.176271440
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3399762934
Short name T200
Test name
Test status
Simulation time 8375525304 ps
CPU time 7.8 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:40 PM PDT 24
Peak memory 204496 kb
Host smart-e682fd2d-56a7-4386-8169-29b38acaa3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33997
62934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3399762934
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1980653205
Short name T1326
Test name
Test status
Simulation time 8385838368 ps
CPU time 8.05 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204524 kb
Host smart-603750e9-ea21-4084-a9ad-c9e4e3fb036c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19806
53205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1980653205
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2245252458
Short name T943
Test name
Test status
Simulation time 8433353165 ps
CPU time 7.91 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204512 kb
Host smart-005bf873-fbad-44fd-8fe7-739445b90e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22452
52458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2245252458
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3863269589
Short name T445
Test name
Test status
Simulation time 8384784306 ps
CPU time 9.77 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204568 kb
Host smart-3d59c681-241a-43c3-8654-057a6a8bd217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632
69589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3863269589
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3684463038
Short name T1196
Test name
Test status
Simulation time 8438008807 ps
CPU time 7.7 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:39 PM PDT 24
Peak memory 204528 kb
Host smart-5a129aab-a9b7-4133-bc7e-dcefcf6bb7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
63038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3684463038
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2065166743
Short name T441
Test name
Test status
Simulation time 8391253795 ps
CPU time 8.05 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204568 kb
Host smart-77388f1e-29ad-407a-a444-e1a3624c8925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20651
66743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2065166743
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1494142267
Short name T1367
Test name
Test status
Simulation time 8412174060 ps
CPU time 7.93 seconds
Started May 09 02:49:28 PM PDT 24
Finished May 09 02:49:46 PM PDT 24
Peak memory 204512 kb
Host smart-4c2c8c8a-1134-46a3-89f9-fca10b38e16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14941
42267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1494142267
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.737811783
Short name T1155
Test name
Test status
Simulation time 8396219963 ps
CPU time 7.54 seconds
Started May 09 02:49:28 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204564 kb
Host smart-9cd5ffff-7b29-4225-9840-2a32726c691a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73781
1783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.737811783
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3036751523
Short name T700
Test name
Test status
Simulation time 8390873297 ps
CPU time 7.61 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204508 kb
Host smart-e3e4ef38-7ec5-4182-a2b8-90efbd9a5580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
51523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3036751523
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3020040823
Short name T418
Test name
Test status
Simulation time 85260407 ps
CPU time 0.68 seconds
Started May 09 02:49:28 PM PDT 24
Finished May 09 02:49:39 PM PDT 24
Peak memory 204560 kb
Host smart-493378c5-8707-425b-a97d-4bbc85bf56be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
40823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3020040823
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2366286821
Short name T981
Test name
Test status
Simulation time 14716914821 ps
CPU time 24.97 seconds
Started May 09 02:49:28 PM PDT 24
Finished May 09 02:50:02 PM PDT 24
Peak memory 204792 kb
Host smart-c87ea6a5-cdbb-4f54-8cd2-23c54ddd371f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
86821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2366286821
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2637942386
Short name T1209
Test name
Test status
Simulation time 8401336778 ps
CPU time 7.75 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204596 kb
Host smart-d24ab417-02e0-4314-834d-16709c994180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26379
42386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2637942386
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1011239201
Short name T1237
Test name
Test status
Simulation time 8469048928 ps
CPU time 10 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:43 PM PDT 24
Peak memory 204540 kb
Host smart-fb6250f4-0ac6-4098-bc35-3977086ee463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10112
39201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1011239201
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3968520482
Short name T1152
Test name
Test status
Simulation time 8383829644 ps
CPU time 8.47 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:43 PM PDT 24
Peak memory 204552 kb
Host smart-bed443c5-b9a9-44eb-831a-6e97f7e2ca3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39685
20482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3968520482
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2413243986
Short name T807
Test name
Test status
Simulation time 8380943931 ps
CPU time 8.19 seconds
Started May 09 02:49:21 PM PDT 24
Finished May 09 02:49:37 PM PDT 24
Peak memory 204580 kb
Host smart-28be78f3-7a5f-4635-aa09-d174dfcca0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
43986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2413243986
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.818145324
Short name T996
Test name
Test status
Simulation time 8370390718 ps
CPU time 7.9 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204580 kb
Host smart-45178574-d493-47de-8197-ceb28da1e1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81814
5324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.818145324
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2920734558
Short name T1098
Test name
Test status
Simulation time 8474996595 ps
CPU time 9.75 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204576 kb
Host smart-ebb53c66-8a7f-43f2-9d6a-dfa012524e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
34558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2920734558
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1512262447
Short name T740
Test name
Test status
Simulation time 8381604684 ps
CPU time 9.73 seconds
Started May 09 02:49:28 PM PDT 24
Finished May 09 02:49:47 PM PDT 24
Peak memory 204564 kb
Host smart-dff06480-268d-44a8-8c6a-aeb034055043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15122
62447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1512262447
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.4009445383
Short name T1120
Test name
Test status
Simulation time 8377258836 ps
CPU time 8.63 seconds
Started May 09 02:49:29 PM PDT 24
Finished May 09 02:49:47 PM PDT 24
Peak memory 204616 kb
Host smart-fce4eb5f-edb9-42ab-910c-3126ac1ea8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40094
45383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.4009445383
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.996150254
Short name T594
Test name
Test status
Simulation time 8470118554 ps
CPU time 7.74 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204208 kb
Host smart-a5c4368e-ec0c-4008-8622-411c62b3cd3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=996150254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.996150254
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.4166101359
Short name T1300
Test name
Test status
Simulation time 8385072180 ps
CPU time 7.51 seconds
Started May 09 02:49:22 PM PDT 24
Finished May 09 02:49:37 PM PDT 24
Peak memory 204504 kb
Host smart-fbb9a8c6-7f4e-496b-954d-2974f8ea016b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4166101359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.4166101359
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1198531936
Short name T1181
Test name
Test status
Simulation time 8419867386 ps
CPU time 9.86 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:43 PM PDT 24
Peak memory 204604 kb
Host smart-41578c82-e0cb-4dfe-852a-9cc1fb7256d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11985
31936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1198531936
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2087581904
Short name T1197
Test name
Test status
Simulation time 8381923578 ps
CPU time 9.31 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:40 PM PDT 24
Peak memory 204616 kb
Host smart-048a5ef1-ce15-4b33-bbd5-dea950a5bd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20875
81904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2087581904
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1445458093
Short name T59
Test name
Test status
Simulation time 9265670825 ps
CPU time 15.28 seconds
Started May 09 02:49:29 PM PDT 24
Finished May 09 02:49:54 PM PDT 24
Peak memory 204832 kb
Host smart-87aaab83-9833-4428-9ae7-c78f9e4f73e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454
58093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1445458093
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_enable.3685917059
Short name T391
Test name
Test status
Simulation time 8402137966 ps
CPU time 7.92 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204584 kb
Host smart-51daf758-fc7e-4e4c-a613-e1654fc24887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
17059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3685917059
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1676624162
Short name T1011
Test name
Test status
Simulation time 175586131 ps
CPU time 1.87 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:35 PM PDT 24
Peak memory 204684 kb
Host smart-11157848-7789-46a5-8065-cdfce9e267fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766
24162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1676624162
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3838196355
Short name T136
Test name
Test status
Simulation time 8436979436 ps
CPU time 10.42 seconds
Started May 09 02:49:21 PM PDT 24
Finished May 09 02:49:39 PM PDT 24
Peak memory 204576 kb
Host smart-741ae8e8-ef50-45fd-8c4d-087ad540da2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38381
96355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3838196355
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1968865515
Short name T6
Test name
Test status
Simulation time 8372540953 ps
CPU time 8.09 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204544 kb
Host smart-e9e386ca-ad85-4874-a6a8-79eb489e15b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19688
65515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1968865515
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1256215403
Short name T1238
Test name
Test status
Simulation time 8542463160 ps
CPU time 8.33 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204544 kb
Host smart-44062646-af6f-47fd-9667-1bf45427d4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
15403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1256215403
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.455790486
Short name T1296
Test name
Test status
Simulation time 8414235862 ps
CPU time 7.93 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204536 kb
Host smart-e528bb43-ffe3-4d6f-bec9-5c8e5fe1f7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45579
0486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.455790486
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.272390830
Short name T344
Test name
Test status
Simulation time 8382119221 ps
CPU time 7.54 seconds
Started May 09 02:49:28 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204576 kb
Host smart-461abc30-cdbf-4a51-994f-e84d82491a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27239
0830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.272390830
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3609422420
Short name T1312
Test name
Test status
Simulation time 8421596350 ps
CPU time 9.18 seconds
Started May 09 02:49:29 PM PDT 24
Finished May 09 02:49:48 PM PDT 24
Peak memory 204580 kb
Host smart-31c81034-4914-48ce-8fb8-8c4266cec205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
22420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3609422420
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2093938638
Short name T37
Test name
Test status
Simulation time 8490264424 ps
CPU time 7.88 seconds
Started May 09 02:49:29 PM PDT 24
Finished May 09 02:49:46 PM PDT 24
Peak memory 204576 kb
Host smart-8ec43583-0b26-4e39-92d2-426034277f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20939
38638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2093938638
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.353842616
Short name T801
Test name
Test status
Simulation time 8380315544 ps
CPU time 8.47 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204508 kb
Host smart-f2faba1b-255a-4733-a65a-5b5528844cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35384
2616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.353842616
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1140107376
Short name T179
Test name
Test status
Simulation time 8395362132 ps
CPU time 8.24 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204508 kb
Host smart-7c8c2069-4086-4252-adc2-a7a85bad59e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11401
07376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1140107376
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.185692737
Short name T405
Test name
Test status
Simulation time 8363538959 ps
CPU time 10.05 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204564 kb
Host smart-65535c78-7b7d-4e82-9299-cf75f1cd1413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569
2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.185692737
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2021956466
Short name T975
Test name
Test status
Simulation time 56322975 ps
CPU time 0.72 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:37 PM PDT 24
Peak memory 204496 kb
Host smart-884404e1-9459-4958-be97-7cf674a3b0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20219
56466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2021956466
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3763686885
Short name T856
Test name
Test status
Simulation time 16201434473 ps
CPU time 26.9 seconds
Started May 09 02:49:29 PM PDT 24
Finished May 09 02:50:05 PM PDT 24
Peak memory 204776 kb
Host smart-018453c1-6f1d-496b-a10b-9d9cec3ec5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37636
86885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3763686885
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3637279701
Short name T331
Test name
Test status
Simulation time 8373935466 ps
CPU time 7.98 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:43 PM PDT 24
Peak memory 204548 kb
Host smart-621c9994-3934-4b21-9cea-ad53865a29d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372
79701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3637279701
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.598126043
Short name T454
Test name
Test status
Simulation time 8382344287 ps
CPU time 7.78 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204516 kb
Host smart-71c6f87d-7646-4aff-a320-75b837250470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59812
6043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.598126043
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.3553869904
Short name T928
Test name
Test status
Simulation time 8473331973 ps
CPU time 7.75 seconds
Started May 09 02:49:24 PM PDT 24
Finished May 09 02:49:41 PM PDT 24
Peak memory 204516 kb
Host smart-3df2590f-f559-498f-8754-574fc941a707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35538
69904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.3553869904
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3694947886
Short name T664
Test name
Test status
Simulation time 8375595583 ps
CPU time 7.93 seconds
Started May 09 02:49:23 PM PDT 24
Finished May 09 02:49:39 PM PDT 24
Peak memory 204588 kb
Host smart-11ee35ec-2dd6-4940-b427-10bdc252516a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36949
47886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3694947886
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.697872383
Short name T83
Test name
Test status
Simulation time 8392680169 ps
CPU time 7.58 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204184 kb
Host smart-407b0f7e-a463-43bb-9a54-258c554b24a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69787
2383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.697872383
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2499411998
Short name T1102
Test name
Test status
Simulation time 8471039459 ps
CPU time 9.23 seconds
Started May 09 02:49:26 PM PDT 24
Finished May 09 02:49:45 PM PDT 24
Peak memory 204572 kb
Host smart-eb13ab20-2e59-430f-9843-961a273c7636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24994
11998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2499411998
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1139790950
Short name T619
Test name
Test status
Simulation time 8403673635 ps
CPU time 7.86 seconds
Started May 09 02:49:27 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204512 kb
Host smart-c98ad9f2-0d9c-44c2-bf40-be4be4602923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
90950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1139790950
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4210227920
Short name T1381
Test name
Test status
Simulation time 8394017618 ps
CPU time 7.58 seconds
Started May 09 02:49:25 PM PDT 24
Finished May 09 02:49:42 PM PDT 24
Peak memory 204612 kb
Host smart-23eeb4f7-fc71-45f6-93f2-36fbb31e3f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102
27920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4210227920
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2172746597
Short name T479
Test name
Test status
Simulation time 8466970919 ps
CPU time 9.65 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204568 kb
Host smart-c19a1d8c-9909-4366-a200-69cc58d9e5a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2172746597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2172746597
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3838375281
Short name T1105
Test name
Test status
Simulation time 8403633437 ps
CPU time 9.39 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:54 PM PDT 24
Peak memory 204588 kb
Host smart-1429b67e-c247-45ac-8adf-152eb652d75b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3838375281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3838375281
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2178448815
Short name T1009
Test name
Test status
Simulation time 8446055439 ps
CPU time 9.66 seconds
Started May 09 02:49:37 PM PDT 24
Finished May 09 02:49:53 PM PDT 24
Peak memory 204568 kb
Host smart-8d8efca3-a2f2-4c67-ba65-6122f491a049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784
48815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2178448815
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2940148149
Short name T89
Test name
Test status
Simulation time 8377203427 ps
CPU time 7.69 seconds
Started May 09 02:49:36 PM PDT 24
Finished May 09 02:49:50 PM PDT 24
Peak memory 204600 kb
Host smart-ab3e958e-1d11-4a13-aa65-a90d98501fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29401
48149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2940148149
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1911006927
Short name T185
Test name
Test status
Simulation time 8693298619 ps
CPU time 12.6 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:50:00 PM PDT 24
Peak memory 204756 kb
Host smart-40d92733-2e12-4929-a9cc-73e66fc09dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
06927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1911006927
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_enable.3575441504
Short name T836
Test name
Test status
Simulation time 8374637682 ps
CPU time 7.61 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:53 PM PDT 24
Peak memory 204556 kb
Host smart-35db9f92-9135-48f0-a9c8-350b739a10a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35754
41504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3575441504
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1395710083
Short name T562
Test name
Test status
Simulation time 66616144 ps
CPU time 1.82 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:46 PM PDT 24
Peak memory 204688 kb
Host smart-87744b5c-56b2-48c2-962c-6db5411e8d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13957
10083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1395710083
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.539577376
Short name T1140
Test name
Test status
Simulation time 8391347591 ps
CPU time 8.31 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204556 kb
Host smart-52e10e1c-bdf2-42d6-8bf3-eda4e1d15dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53957
7376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.539577376
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2508486884
Short name T681
Test name
Test status
Simulation time 8364349220 ps
CPU time 9.18 seconds
Started May 09 02:49:36 PM PDT 24
Finished May 09 02:49:52 PM PDT 24
Peak memory 204564 kb
Host smart-3661bf03-0b31-4569-8403-00bc215c75de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
86884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2508486884
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1581098856
Short name T744
Test name
Test status
Simulation time 8442462281 ps
CPU time 7.76 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:53 PM PDT 24
Peak memory 204536 kb
Host smart-8a8094a2-82bd-405f-8319-eedec0bc9bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
98856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1581098856
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3488514716
Short name T753
Test name
Test status
Simulation time 8417498354 ps
CPU time 7.85 seconds
Started May 09 02:49:37 PM PDT 24
Finished May 09 02:49:51 PM PDT 24
Peak memory 204520 kb
Host smart-cb8392a9-e57c-404b-a913-fcc607f6fb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
14716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3488514716
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2585005231
Short name T1412
Test name
Test status
Simulation time 8378556562 ps
CPU time 8.21 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 203872 kb
Host smart-f4f2cd13-b79c-4698-a974-3790433332c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25850
05231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2585005231
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3727874908
Short name T121
Test name
Test status
Simulation time 8392132081 ps
CPU time 8.19 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204540 kb
Host smart-2043b096-f1e6-434d-87b7-57f0071a644e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37278
74908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3727874908
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3804633401
Short name T306
Test name
Test status
Simulation time 8377356786 ps
CPU time 7.65 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:53 PM PDT 24
Peak memory 204544 kb
Host smart-6816cf3a-164a-42b4-81dd-4372e2eb1f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38046
33401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3804633401
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1590743925
Short name T1204
Test name
Test status
Simulation time 8381931407 ps
CPU time 8.72 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204548 kb
Host smart-4245903b-5831-444b-99c9-17e5b080d845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15907
43925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1590743925
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.675193476
Short name T1253
Test name
Test status
Simulation time 8404630021 ps
CPU time 10.33 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204584 kb
Host smart-77d1101d-9e10-46cb-a04d-4acde8f0da9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67519
3476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.675193476
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.522006660
Short name T1202
Test name
Test status
Simulation time 8390565964 ps
CPU time 7.38 seconds
Started May 09 02:49:44 PM PDT 24
Finished May 09 02:49:57 PM PDT 24
Peak memory 204516 kb
Host smart-78763a40-ef51-4f3e-928a-ccc42b469648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52200
6660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.522006660
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2600035020
Short name T826
Test name
Test status
Simulation time 35130026 ps
CPU time 0.65 seconds
Started May 09 02:49:36 PM PDT 24
Finished May 09 02:49:44 PM PDT 24
Peak memory 204524 kb
Host smart-38e7279c-c397-4379-9255-221bfa4fccc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26000
35020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2600035020
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.980272598
Short name T1167
Test name
Test status
Simulation time 17202812443 ps
CPU time 34.17 seconds
Started May 09 02:49:43 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 204832 kb
Host smart-a2249d12-24ff-4655-8862-13f36d66ff6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98027
2598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.980272598
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1418147789
Short name T872
Test name
Test status
Simulation time 8380054824 ps
CPU time 8.47 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 204452 kb
Host smart-917eaa08-1e42-49a8-ae47-ae59b59886db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14181
47789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1418147789
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4036839784
Short name T878
Test name
Test status
Simulation time 8383945676 ps
CPU time 8.02 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204556 kb
Host smart-897e284f-90c9-4284-a2b1-a4a447cef7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40368
39784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4036839784
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3749951858
Short name T499
Test name
Test status
Simulation time 8414985006 ps
CPU time 7.9 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 204508 kb
Host smart-96d924d9-de80-4860-8298-7732df5f626e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499
51858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3749951858
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3978963596
Short name T1008
Test name
Test status
Simulation time 8381576728 ps
CPU time 9.04 seconds
Started May 09 02:49:37 PM PDT 24
Finished May 09 02:49:53 PM PDT 24
Peak memory 204588 kb
Host smart-38afebff-c2cc-47b5-ab47-cb423a50f5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39789
63596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3978963596
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.104015463
Short name T1022
Test name
Test status
Simulation time 8421901409 ps
CPU time 8.06 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 203864 kb
Host smart-498286e2-5f09-4778-93fc-8bbbc2ebf86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401
5463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.104015463
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1371561319
Short name T1074
Test name
Test status
Simulation time 8474262444 ps
CPU time 7.97 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204604 kb
Host smart-85bbf187-42f8-48dd-81e4-109d607f4d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13715
61319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1371561319
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1666800181
Short name T1087
Test name
Test status
Simulation time 8418019362 ps
CPU time 7.61 seconds
Started May 09 02:49:41 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 204540 kb
Host smart-c865dacb-e778-42dc-aad5-1d0b5f27914a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16668
00181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1666800181
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.722188947
Short name T422
Test name
Test status
Simulation time 8400159426 ps
CPU time 8.35 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:53 PM PDT 24
Peak memory 204568 kb
Host smart-0a977b96-3cb3-4934-8b29-ae5a40003139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72218
8947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.722188947
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3132225920
Short name T339
Test name
Test status
Simulation time 8458621725 ps
CPU time 8.1 seconds
Started May 09 02:49:46 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204556 kb
Host smart-ec5e77ec-dcf7-4083-bb0d-f487f58120ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3132225920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3132225920
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.2720634966
Short name T307
Test name
Test status
Simulation time 8382543345 ps
CPU time 8.5 seconds
Started May 09 02:49:46 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204556 kb
Host smart-231b6baa-ec61-4473-bebb-75ccc3748ec2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2720634966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.2720634966
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.4137146020
Short name T304
Test name
Test status
Simulation time 8413754760 ps
CPU time 10.01 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204548 kb
Host smart-6e0c46f5-76ae-4cf3-9c47-4dae3fda054c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371
46020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.4137146020
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2430561430
Short name T1305
Test name
Test status
Simulation time 8397782797 ps
CPU time 8.26 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204588 kb
Host smart-8026892e-628c-47fa-b961-e3eccfc2a562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305
61430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2430561430
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.898169607
Short name T1106
Test name
Test status
Simulation time 8807296367 ps
CPU time 11.66 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:50:00 PM PDT 24
Peak memory 204744 kb
Host smart-05ac435c-4667-44fe-848e-fd2f69c3c472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89816
9607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.898169607
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_enable.3204479632
Short name T814
Test name
Test status
Simulation time 8373417325 ps
CPU time 7.56 seconds
Started May 09 02:49:41 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 204588 kb
Host smart-09ccc309-2ccd-4ab2-8831-d68c4d490891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32044
79632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3204479632
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3007366385
Short name T1198
Test name
Test status
Simulation time 136612742 ps
CPU time 1.47 seconds
Started May 09 02:49:41 PM PDT 24
Finished May 09 02:49:50 PM PDT 24
Peak memory 204672 kb
Host smart-3c725ff1-a710-4c53-841e-3935a4a8201e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30073
66385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3007366385
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3130681757
Short name T731
Test name
Test status
Simulation time 8401337671 ps
CPU time 8.08 seconds
Started May 09 02:49:44 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204516 kb
Host smart-5ebb3d9a-671e-4aef-9ed4-a3aa3093ecb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31306
81757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3130681757
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.831468441
Short name T1072
Test name
Test status
Simulation time 8363701438 ps
CPU time 7.86 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 204556 kb
Host smart-bd1787bd-50d8-4e7e-a428-08a16b5500af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83146
8441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.831468441
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1018136434
Short name T695
Test name
Test status
Simulation time 8379867097 ps
CPU time 9.54 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204600 kb
Host smart-c3c1936b-9552-49fc-ac68-c56345ab8298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10181
36434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1018136434
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.360531564
Short name T1055
Test name
Test status
Simulation time 8428646142 ps
CPU time 8.25 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:54 PM PDT 24
Peak memory 204588 kb
Host smart-8aaf0c84-cfee-4424-a79a-1561981e012f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36053
1564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.360531564
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.972304590
Short name T1333
Test name
Test status
Simulation time 8391574346 ps
CPU time 9.34 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204556 kb
Host smart-582b1a70-b357-421b-b6e8-1cdc930b1f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97230
4590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.972304590
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.747933000
Short name T1122
Test name
Test status
Simulation time 8459079914 ps
CPU time 8.54 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204540 kb
Host smart-f9dcdacb-b743-4bb8-9017-06ddab6e6e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74793
3000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.747933000
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.4153294079
Short name T312
Test name
Test status
Simulation time 8422651069 ps
CPU time 8.81 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:54 PM PDT 24
Peak memory 204560 kb
Host smart-f66b7264-2457-4560-a48c-9cd2aef84238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41532
94079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.4153294079
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3551454582
Short name T913
Test name
Test status
Simulation time 8406500949 ps
CPU time 7.54 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:49:56 PM PDT 24
Peak memory 204480 kb
Host smart-1fea2ec5-97f0-4d89-ac01-e7722ec7dab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
54582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3551454582
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3113391105
Short name T627
Test name
Test status
Simulation time 8404501893 ps
CPU time 7.68 seconds
Started May 09 02:49:43 PM PDT 24
Finished May 09 02:49:57 PM PDT 24
Peak memory 204516 kb
Host smart-9010de84-b222-48ab-b4e5-f5b3940bb380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31133
91105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3113391105
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.125442937
Short name T458
Test name
Test status
Simulation time 8367938095 ps
CPU time 8.69 seconds
Started May 09 02:49:41 PM PDT 24
Finished May 09 02:49:57 PM PDT 24
Peak memory 204540 kb
Host smart-0e87f13e-3efb-466b-bec5-524132ff5aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544
2937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.125442937
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2148115000
Short name T770
Test name
Test status
Simulation time 76916401 ps
CPU time 0.72 seconds
Started May 09 02:49:46 PM PDT 24
Finished May 09 02:49:51 PM PDT 24
Peak memory 204512 kb
Host smart-652d8e3c-817e-4c29-ab32-1236eb95579d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21481
15000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2148115000
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2892699949
Short name T245
Test name
Test status
Simulation time 16432563819 ps
CPU time 31.76 seconds
Started May 09 02:49:37 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204788 kb
Host smart-7c74251e-aab1-47ad-a08f-34b4f3566ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28926
99949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2892699949
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2351159863
Short name T478
Test name
Test status
Simulation time 8376382825 ps
CPU time 7.64 seconds
Started May 09 02:49:38 PM PDT 24
Finished May 09 02:49:52 PM PDT 24
Peak memory 204520 kb
Host smart-65c99d8f-137d-47d2-a32d-aef185be969e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23511
59863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2351159863
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2399787863
Short name T446
Test name
Test status
Simulation time 8441006897 ps
CPU time 8.64 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204568 kb
Host smart-55b8b2ea-a7a2-4bd0-979c-78bfd4317fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
87863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2399787863
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1725816397
Short name T847
Test name
Test status
Simulation time 8410857000 ps
CPU time 7.75 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204552 kb
Host smart-2f9a3bae-bd0a-494c-9a39-5589eb5929e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258
16397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1725816397
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3404853632
Short name T661
Test name
Test status
Simulation time 8392403970 ps
CPU time 8.94 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204480 kb
Host smart-43c63409-38e5-49ae-a334-65e811bd5589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
53632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3404853632
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1942733392
Short name T300
Test name
Test status
Simulation time 8368392161 ps
CPU time 7.8 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:49:57 PM PDT 24
Peak memory 204568 kb
Host smart-fb2a6e43-7b10-4e9c-b73a-f27d6f5b8775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19427
33392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1942733392
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1919076715
Short name T1416
Test name
Test status
Simulation time 8440243185 ps
CPU time 10.24 seconds
Started May 09 02:49:41 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204568 kb
Host smart-6dfcb86e-3a1a-4706-9db1-07dd4704545e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
76715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1919076715
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.263128112
Short name T1317
Test name
Test status
Simulation time 8406121981 ps
CPU time 8.33 seconds
Started May 09 02:49:42 PM PDT 24
Finished May 09 02:49:57 PM PDT 24
Peak memory 204572 kb
Host smart-cd48ce1c-0728-4909-bc11-45298e381611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26312
8112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.263128112
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3524977
Short name T415
Test name
Test status
Simulation time 8404898542 ps
CPU time 8.15 seconds
Started May 09 02:49:40 PM PDT 24
Finished May 09 02:49:55 PM PDT 24
Peak memory 204560 kb
Host smart-02aace17-916a-4219-9676-f13b351978ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35249
77 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3524977
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.233502230
Short name T645
Test name
Test status
Simulation time 8469259211 ps
CPU time 7.69 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:13 PM PDT 24
Peak memory 204824 kb
Host smart-cb396920-32b7-4b84-9aa6-a2cd19ff80c8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=233502230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.233502230
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.734369293
Short name T305
Test name
Test status
Simulation time 8379212884 ps
CPU time 7.94 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204544 kb
Host smart-8c810a35-b249-4354-a6d5-88eebe56fb4d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=734369293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.734369293
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1819624672
Short name T894
Test name
Test status
Simulation time 8380644235 ps
CPU time 7.81 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204600 kb
Host smart-c833c16f-4b00-44f7-ab48-7be546c033c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18196
24672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1819624672
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.991982833
Short name T948
Test name
Test status
Simulation time 8405402333 ps
CPU time 7.96 seconds
Started May 09 02:49:39 PM PDT 24
Finished May 09 02:49:54 PM PDT 24
Peak memory 204580 kb
Host smart-427a2cf6-bce3-432e-a38d-42e3e8c582e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99198
2833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.991982833
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1492188243
Short name T202
Test name
Test status
Simulation time 9300911070 ps
CPU time 14.77 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204812 kb
Host smart-7c363733-5a55-484b-b152-0a4f80e32635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14921
88243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1492188243
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_enable.572160019
Short name T1261
Test name
Test status
Simulation time 8377043672 ps
CPU time 7.45 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:08 PM PDT 24
Peak memory 204556 kb
Host smart-ed18137b-2d00-4c63-8a82-4c24a19fff98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57216
0019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.572160019
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.88180730
Short name T976
Test name
Test status
Simulation time 155526310 ps
CPU time 1.49 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:04 PM PDT 24
Peak memory 204736 kb
Host smart-312b54cb-7111-41cb-a5f3-4aa9058facfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88180
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.88180730
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3388411014
Short name T895
Test name
Test status
Simulation time 8425368601 ps
CPU time 8.28 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204560 kb
Host smart-b7d30014-79e6-490a-8f4a-9e654d4941b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33884
11014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3388411014
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.484537962
Short name T410
Test name
Test status
Simulation time 8432913554 ps
CPU time 8.44 seconds
Started May 09 02:49:53 PM PDT 24
Finished May 09 02:50:04 PM PDT 24
Peak memory 204620 kb
Host smart-518a239f-04dd-4e29-984e-a79837d6db50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48453
7962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.484537962
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3979716636
Short name T156
Test name
Test status
Simulation time 8440346063 ps
CPU time 10.21 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204528 kb
Host smart-5ce650d3-9014-43df-b600-85d2b22a44d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
16636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3979716636
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3065112743
Short name T440
Test name
Test status
Simulation time 8418043808 ps
CPU time 8.38 seconds
Started May 09 02:49:54 PM PDT 24
Finished May 09 02:50:05 PM PDT 24
Peak memory 204600 kb
Host smart-9ff0931a-34ec-47a6-b0f7-1f8666f226b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
12743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3065112743
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3212901527
Short name T379
Test name
Test status
Simulation time 8380128904 ps
CPU time 8.35 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:08 PM PDT 24
Peak memory 204468 kb
Host smart-ee01a5bd-0491-430b-8902-d0a5400c44ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129
01527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3212901527
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.666981885
Short name T112
Test name
Test status
Simulation time 8417030446 ps
CPU time 7.59 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:13 PM PDT 24
Peak memory 204568 kb
Host smart-1024cdf8-db33-4954-b1db-b2373d67bfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66698
1885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.666981885
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2637786565
Short name T723
Test name
Test status
Simulation time 8417822803 ps
CPU time 8.92 seconds
Started May 09 02:49:54 PM PDT 24
Finished May 09 02:50:06 PM PDT 24
Peak memory 204496 kb
Host smart-a701fb4b-3e84-438f-965f-d49cd7d7d1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377
86565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2637786565
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3111741709
Short name T711
Test name
Test status
Simulation time 8410143281 ps
CPU time 9.11 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:08 PM PDT 24
Peak memory 204520 kb
Host smart-d280a3d4-7c63-4282-8f31-7fdc50a17572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
41709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3111741709
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.826237977
Short name T1314
Test name
Test status
Simulation time 8422629675 ps
CPU time 8.13 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:07 PM PDT 24
Peak memory 204544 kb
Host smart-87b257f5-ccca-499a-8aed-b26ef212fa9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82623
7977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.826237977
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3319422827
Short name T25
Test name
Test status
Simulation time 8367982417 ps
CPU time 7.75 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:14 PM PDT 24
Peak memory 204564 kb
Host smart-48cfce9c-eec0-4f0c-b68f-3720e2f747b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
22827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3319422827
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3411408390
Short name T1316
Test name
Test status
Simulation time 67954438 ps
CPU time 0.73 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:01 PM PDT 24
Peak memory 204544 kb
Host smart-6016b884-dc83-4422-bff2-bb76aca0f793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34114
08390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3411408390
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.631735789
Short name T267
Test name
Test status
Simulation time 28307249447 ps
CPU time 64.62 seconds
Started May 09 02:49:54 PM PDT 24
Finished May 09 02:51:01 PM PDT 24
Peak memory 204840 kb
Host smart-5db28f86-010c-418c-afa9-18de67d60ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63173
5789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.631735789
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2515974124
Short name T329
Test name
Test status
Simulation time 8460114518 ps
CPU time 8.95 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204588 kb
Host smart-d266cf63-c5c7-4fa7-9939-6912b7279859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159
74124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2515974124
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2638149198
Short name T414
Test name
Test status
Simulation time 8448467454 ps
CPU time 9.91 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204556 kb
Host smart-aa0904d9-660c-4eab-8309-89a836e6c023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381
49198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2638149198
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3436161098
Short name T655
Test name
Test status
Simulation time 8434547349 ps
CPU time 8.29 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204564 kb
Host smart-b186883c-9962-4cb4-95a3-c936a4d781f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34361
61098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3436161098
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3549452656
Short name T615
Test name
Test status
Simulation time 8447304416 ps
CPU time 7.5 seconds
Started May 09 02:49:46 PM PDT 24
Finished May 09 02:49:58 PM PDT 24
Peak memory 204584 kb
Host smart-02e9c376-35b5-4c2b-8fa7-2b50f2f6b1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35494
52656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3549452656
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1384271094
Short name T701
Test name
Test status
Simulation time 8365521124 ps
CPU time 7.98 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:08 PM PDT 24
Peak memory 204584 kb
Host smart-14fbca7f-01a1-4ae0-8199-f5ef88a46f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
71094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1384271094
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1288695207
Short name T769
Test name
Test status
Simulation time 8401849231 ps
CPU time 7.98 seconds
Started May 09 02:49:44 PM PDT 24
Finished May 09 02:49:57 PM PDT 24
Peak memory 204528 kb
Host smart-0e4124a2-2eae-4f50-80bd-b416f104c8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
95207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1288695207
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.269702947
Short name T385
Test name
Test status
Simulation time 8377825507 ps
CPU time 8.38 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204556 kb
Host smart-d781840b-ca74-4ffe-8c6c-556cb8d5ff14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
2947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.269702947
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.62966760
Short name T1107
Test name
Test status
Simulation time 8457456496 ps
CPU time 9.04 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204564 kb
Host smart-d790e8dc-a4af-464d-9642-dc872d112ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62966
760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.62966760
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1339288494
Short name T906
Test name
Test status
Simulation time 8466340783 ps
CPU time 7.74 seconds
Started May 09 02:49:54 PM PDT 24
Finished May 09 02:50:05 PM PDT 24
Peak memory 204556 kb
Host smart-935abe2f-3f6f-4024-98d0-41eea24ac85b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1339288494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1339288494
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.460142399
Short name T733
Test name
Test status
Simulation time 8437448769 ps
CPU time 7.95 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204504 kb
Host smart-daf95151-cb4e-48c6-803f-d0cb211ed64a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=460142399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.460142399
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.3207802859
Short name T1356
Test name
Test status
Simulation time 8461988915 ps
CPU time 7.86 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204528 kb
Host smart-875d03ce-be20-4b99-9e80-1ae2de0185d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32078
02859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3207802859
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.194072588
Short name T794
Test name
Test status
Simulation time 8378514665 ps
CPU time 8.56 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204572 kb
Host smart-2ea35880-2236-41f5-ae51-1c594ada0073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19407
2588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.194072588
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2677449659
Short name T449
Test name
Test status
Simulation time 8413924533 ps
CPU time 11.61 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:11 PM PDT 24
Peak memory 204788 kb
Host smart-a83d332d-fba8-4183-9ac3-3510af3de532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26774
49659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2677449659
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_enable.974807107
Short name T1225
Test name
Test status
Simulation time 8375632141 ps
CPU time 7.45 seconds
Started May 09 02:49:52 PM PDT 24
Finished May 09 02:50:01 PM PDT 24
Peak memory 204552 kb
Host smart-4b5c757a-73d7-4eeb-844a-fc77abb57b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97480
7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.974807107
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.4109256071
Short name T1174
Test name
Test status
Simulation time 75437216 ps
CPU time 1.99 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:02 PM PDT 24
Peak memory 204708 kb
Host smart-ef322ecd-7211-4f94-9565-4833152fe222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
56071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.4109256071
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.4277896979
Short name T671
Test name
Test status
Simulation time 8441895828 ps
CPU time 7.78 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:13 PM PDT 24
Peak memory 204548 kb
Host smart-d1977362-026c-4014-8513-1fd0a8027f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
96979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.4277896979
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2966467799
Short name T1060
Test name
Test status
Simulation time 8365983280 ps
CPU time 9.49 seconds
Started May 09 02:49:54 PM PDT 24
Finished May 09 02:50:07 PM PDT 24
Peak memory 204524 kb
Host smart-c24aba4f-a439-44c6-850b-b0b7ea23aee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29664
67799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2966467799
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2009847130
Short name T1004
Test name
Test status
Simulation time 8486959688 ps
CPU time 9.6 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204504 kb
Host smart-2e35a8a8-fe9e-44b6-ae38-7f9dfe4e90b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20098
47130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2009847130
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1057045732
Short name T535
Test name
Test status
Simulation time 8415388459 ps
CPU time 7.5 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:13 PM PDT 24
Peak memory 204836 kb
Host smart-70b5910e-72f8-4511-b73d-9913bcab85e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10570
45732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1057045732
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.213836110
Short name T1368
Test name
Test status
Simulation time 8384812513 ps
CPU time 7.83 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204560 kb
Host smart-28ae15a5-8aa7-4d19-b1bb-af3592106e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21383
6110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.213836110
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3315316774
Short name T128
Test name
Test status
Simulation time 8444946698 ps
CPU time 8.06 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204516 kb
Host smart-1dd128d6-8a5e-4921-80c1-2b6e5e4b4391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33153
16774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3315316774
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1457461542
Short name T618
Test name
Test status
Simulation time 8421912142 ps
CPU time 8.74 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204528 kb
Host smart-dafd0ec9-c552-42a6-a42a-69204bd79d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14574
61542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1457461542
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1130393967
Short name T459
Test name
Test status
Simulation time 8402663978 ps
CPU time 8.23 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204540 kb
Host smart-bf298b5f-131f-4fc3-ba32-e2ff6928da29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303
93967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1130393967
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3717213687
Short name T907
Test name
Test status
Simulation time 8380589845 ps
CPU time 9.84 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:11 PM PDT 24
Peak memory 204500 kb
Host smart-6a36fd01-bc17-4f14-8a5a-08d52276b55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37172
13687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3717213687
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1474259739
Short name T827
Test name
Test status
Simulation time 8369014613 ps
CPU time 8.3 seconds
Started May 09 02:49:53 PM PDT 24
Finished May 09 02:50:04 PM PDT 24
Peak memory 204568 kb
Host smart-8b0b7691-b82a-4ba1-a19f-bb0247dc0037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14742
59739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1474259739
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2224436072
Short name T1095
Test name
Test status
Simulation time 35104038 ps
CPU time 0.65 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:06 PM PDT 24
Peak memory 204304 kb
Host smart-4b189f89-c684-4e79-87d6-5020e0bbb0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22244
36072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2224436072
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.749432530
Short name T247
Test name
Test status
Simulation time 16230090318 ps
CPU time 27.59 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:34 PM PDT 24
Peak memory 204668 kb
Host smart-4625dec9-dad3-4181-83fa-e887012c8299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74943
2530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.749432530
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3832629338
Short name T1073
Test name
Test status
Simulation time 8408988143 ps
CPU time 7.84 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204604 kb
Host smart-3b0e6891-a2c3-4821-a9a3-20586674e82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
29338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3832629338
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1236451106
Short name T722
Test name
Test status
Simulation time 8437590729 ps
CPU time 9.53 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204600 kb
Host smart-af561990-3c88-427e-9ba3-885a670995ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12364
51106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1236451106
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1684719618
Short name T745
Test name
Test status
Simulation time 8420731595 ps
CPU time 8.58 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:08 PM PDT 24
Peak memory 204552 kb
Host smart-49613240-3404-4b4f-99e6-1e2315a61b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
19618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1684719618
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3686162417
Short name T1407
Test name
Test status
Simulation time 8380269097 ps
CPU time 8.87 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204556 kb
Host smart-81dda037-a088-4c4f-82b1-1b62539365d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
62417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3686162417
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2611529237
Short name T335
Test name
Test status
Simulation time 8377953104 ps
CPU time 8.36 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204444 kb
Host smart-e628c428-fea9-469b-9cad-f66e3a336780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26115
29237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2611529237
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.347844617
Short name T524
Test name
Test status
Simulation time 8439331665 ps
CPU time 9.01 seconds
Started May 09 02:49:53 PM PDT 24
Finished May 09 02:50:04 PM PDT 24
Peak memory 204568 kb
Host smart-b6319a43-31d9-440a-a539-2244544972a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34784
4617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.347844617
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2485545591
Short name T526
Test name
Test status
Simulation time 8410265487 ps
CPU time 8.29 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:14 PM PDT 24
Peak memory 204356 kb
Host smart-bd89f174-1153-40fa-8f38-b4119f453e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
45591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2485545591
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2484209346
Short name T346
Test name
Test status
Simulation time 8398840166 ps
CPU time 9.54 seconds
Started May 09 02:49:54 PM PDT 24
Finished May 09 02:50:08 PM PDT 24
Peak memory 204544 kb
Host smart-653072a4-f6a4-4e83-b9d2-274adb0663ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24842
09346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2484209346
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.2900666055
Short name T1019
Test name
Test status
Simulation time 8462859536 ps
CPU time 8.43 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204516 kb
Host smart-46e4acc3-9600-4b1a-941d-c2dcec18d087
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2900666055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.2900666055
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.1414699474
Short name T45
Test name
Test status
Simulation time 8379329354 ps
CPU time 7.75 seconds
Started May 09 02:50:07 PM PDT 24
Finished May 09 02:50:21 PM PDT 24
Peak memory 204596 kb
Host smart-bedaeadf-0290-4556-b9d9-ae66c9f3e04f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1414699474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.1414699474
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.462185424
Short name T1025
Test name
Test status
Simulation time 8391601255 ps
CPU time 8.43 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204604 kb
Host smart-ecac0e27-efc4-47e7-9658-4c159934ef5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46218
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.462185424
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.4290144827
Short name T816
Test name
Test status
Simulation time 8379862668 ps
CPU time 7.96 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:13 PM PDT 24
Peak memory 204580 kb
Host smart-e1b51d34-8ffb-4035-a037-6c7eda0c65d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
44827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.4290144827
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.682064540
Short name T601
Test name
Test status
Simulation time 8521721111 ps
CPU time 11.83 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 204808 kb
Host smart-935a7be9-0e92-45ff-8176-d7b5cca52289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68206
4540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.682064540
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_enable.333791753
Short name T1136
Test name
Test status
Simulation time 8375677286 ps
CPU time 8.36 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:11 PM PDT 24
Peak memory 204556 kb
Host smart-4d06bed8-e7c7-4584-8c72-30ffabb03323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
1753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.333791753
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3910057306
Short name T92
Test name
Test status
Simulation time 232662111 ps
CPU time 1.91 seconds
Started May 09 02:49:56 PM PDT 24
Finished May 09 02:50:02 PM PDT 24
Peak memory 204720 kb
Host smart-0ef9b404-fac1-42ab-bc27-b5f8052e63df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39100
57306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3910057306
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2366175386
Short name T612
Test name
Test status
Simulation time 8416251574 ps
CPU time 9.99 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 204512 kb
Host smart-2ad0ab45-9650-4c1b-90cf-e951bc398955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23661
75386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2366175386
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.940963249
Short name T1018
Test name
Test status
Simulation time 8366115153 ps
CPU time 7.94 seconds
Started May 09 02:50:06 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 204580 kb
Host smart-9d3d9daf-8690-4abc-8aa7-569649e3e85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94096
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.940963249
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1234841422
Short name T1422
Test name
Test status
Simulation time 8443170429 ps
CPU time 8.26 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204564 kb
Host smart-9d5e2946-280b-441b-ab45-c97ef292f510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12348
41422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1234841422
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.4039622297
Short name T874
Test name
Test status
Simulation time 8418868182 ps
CPU time 8.13 seconds
Started May 09 02:49:55 PM PDT 24
Finished May 09 02:50:06 PM PDT 24
Peak memory 204616 kb
Host smart-f8f97414-818b-4ee2-b53c-a1ab01cd7d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
22297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.4039622297
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3118992732
Short name T1114
Test name
Test status
Simulation time 8371999282 ps
CPU time 8.23 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204576 kb
Host smart-1bd0171c-d05c-436f-929b-f622156a97a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
92732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3118992732
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2509716803
Short name T118
Test name
Test status
Simulation time 8441305203 ps
CPU time 8.61 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204508 kb
Host smart-17070093-3e5e-46e1-b6d8-646765e0c547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25097
16803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2509716803
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3031338092
Short name T1429
Test name
Test status
Simulation time 8386316816 ps
CPU time 8.61 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204584 kb
Host smart-42f4680d-e36b-4e4c-aa1d-4b77c07076f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30313
38092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3031338092
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3133002781
Short name T659
Test name
Test status
Simulation time 8410668445 ps
CPU time 7.88 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204536 kb
Host smart-3d2cf90b-13be-41df-9228-a1afc239bd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
02781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3133002781
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2934636471
Short name T173
Test name
Test status
Simulation time 8442290325 ps
CPU time 8.64 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204520 kb
Host smart-548b4c05-0847-4ea8-a458-5772f089365c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346
36471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2934636471
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3558533143
Short name T582
Test name
Test status
Simulation time 8395959345 ps
CPU time 8.01 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:14 PM PDT 24
Peak memory 204572 kb
Host smart-9fd823b8-6142-4e2d-9f45-ef990b6ae5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35585
33143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3558533143
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1405653335
Short name T51
Test name
Test status
Simulation time 42691322 ps
CPU time 0.68 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:07 PM PDT 24
Peak memory 204500 kb
Host smart-6e280697-8dbd-4dcc-aaa8-140af945bfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14056
53335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1405653335
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.730948773
Short name T463
Test name
Test status
Simulation time 23093123185 ps
CPU time 43.95 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:52 PM PDT 24
Peak memory 204816 kb
Host smart-87c246bb-19e2-4f8d-8916-b8a54ef57fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73094
8773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.730948773
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3209318746
Short name T1285
Test name
Test status
Simulation time 8441603959 ps
CPU time 8.38 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204612 kb
Host smart-20fd955a-89a5-4b07-9937-2bd80f151bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32093
18746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3209318746
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1430594158
Short name T1217
Test name
Test status
Simulation time 8415523802 ps
CPU time 9.82 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204556 kb
Host smart-ad8f2c34-1abc-40b6-bdf7-ffd3b7ff78cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14305
94158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1430594158
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.2136745780
Short name T1083
Test name
Test status
Simulation time 8393753429 ps
CPU time 8.05 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204560 kb
Host smart-819a8216-8d33-4944-bf31-bee4a07e854f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21367
45780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.2136745780
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2512609007
Short name T528
Test name
Test status
Simulation time 8379481620 ps
CPU time 8.04 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204596 kb
Host smart-2413c58b-ff43-45dd-bcc2-40b3a84812c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
09007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2512609007
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1996584136
Short name T1413
Test name
Test status
Simulation time 8362147206 ps
CPU time 8.22 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204508 kb
Host smart-99cc2045-b5cc-47dd-a755-bbfd7f2f6d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19965
84136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1996584136
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4263499893
Short name T147
Test name
Test status
Simulation time 8456029436 ps
CPU time 7.78 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204512 kb
Host smart-22f89fe2-bdf2-41f8-bcd2-3e33371be344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42634
99893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4263499893
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.4091295097
Short name T624
Test name
Test status
Simulation time 8376503022 ps
CPU time 7.93 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204576 kb
Host smart-e885bea3-4353-4f41-a3b1-ad9c193b3db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
95097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.4091295097
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.4088974116
Short name T962
Test name
Test status
Simulation time 8405134302 ps
CPU time 7.92 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204568 kb
Host smart-ce0bea0c-4472-431a-a0bc-67464c17a6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40889
74116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.4088974116
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1278114210
Short name T1057
Test name
Test status
Simulation time 8492777830 ps
CPU time 8.6 seconds
Started May 09 02:50:04 PM PDT 24
Finished May 09 02:50:19 PM PDT 24
Peak memory 204584 kb
Host smart-84b70745-cb55-4ed5-9261-c2c6e098e4c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1278114210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1278114210
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.2053796435
Short name T663
Test name
Test status
Simulation time 8379410128 ps
CPU time 8.86 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204596 kb
Host smart-d6863500-7464-4aaf-a19d-863334a9e0c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2053796435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.2053796435
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.939279902
Short name T654
Test name
Test status
Simulation time 8409869301 ps
CPU time 7.58 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204604 kb
Host smart-463893e5-eef1-4131-b2b8-30bf1f1c1328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93927
9902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.939279902
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3846240883
Short name T748
Test name
Test status
Simulation time 8391444724 ps
CPU time 9.29 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:11 PM PDT 24
Peak memory 204580 kb
Host smart-ed0bd7ad-a60a-4bb8-8337-6f03fd931fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38462
40883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3846240883
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1805628029
Short name T1166
Test name
Test status
Simulation time 8739134509 ps
CPU time 12.72 seconds
Started May 09 02:49:58 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204764 kb
Host smart-e5ab229d-8686-4110-b6ef-694a5231fb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
28029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1805628029
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_enable.1782242094
Short name T1091
Test name
Test status
Simulation time 8380042256 ps
CPU time 8.35 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204608 kb
Host smart-4bfb68c7-e7a3-4e8e-b7c2-6a8d2b59f303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
42094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1782242094
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3888681841
Short name T873
Test name
Test status
Simulation time 93443339 ps
CPU time 2.17 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204684 kb
Host smart-7d28f9b5-1a52-4221-85be-2ea0e7c8837d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38886
81841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3888681841
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3559071756
Short name T550
Test name
Test status
Simulation time 8387899920 ps
CPU time 7.29 seconds
Started May 09 02:50:07 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 204576 kb
Host smart-e832861e-53a2-45e9-9891-4b06b677b861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35590
71756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3559071756
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4184914309
Short name T956
Test name
Test status
Simulation time 8385085266 ps
CPU time 7.77 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204556 kb
Host smart-c5ad05cc-eb6a-43c8-958f-8f39190582b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41849
14309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4184914309
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2316050593
Short name T162
Test name
Test status
Simulation time 8481704923 ps
CPU time 7.92 seconds
Started May 09 02:50:03 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204584 kb
Host smart-0c423220-eed6-4900-a4f7-9067f0273a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
50593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2316050593
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2873017663
Short name T91
Test name
Test status
Simulation time 8413974554 ps
CPU time 8.74 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:14 PM PDT 24
Peak memory 204596 kb
Host smart-1045e67d-aab8-4a29-b30b-e711d7d4d55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
17663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2873017663
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.481465902
Short name T357
Test name
Test status
Simulation time 8366970277 ps
CPU time 7.85 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204572 kb
Host smart-95abe759-1dde-47b5-a74e-1ac284104fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48146
5902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.481465902
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.525448897
Short name T34
Test name
Test status
Simulation time 8433449458 ps
CPU time 7.5 seconds
Started May 09 02:50:07 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 204580 kb
Host smart-4bc03467-9460-48c7-8e07-6581bfabf5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52544
8897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.525448897
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1417173555
Short name T353
Test name
Test status
Simulation time 8421361606 ps
CPU time 7.86 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204576 kb
Host smart-7a88aa89-91de-4e51-b39c-86bf56ea8bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14171
73555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1417173555
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.639664319
Short name T1040
Test name
Test status
Simulation time 8408688668 ps
CPU time 9.2 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204588 kb
Host smart-edcfe460-fa5c-4e62-ba09-dc7666b4fabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63966
4319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.639664319
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.942490864
Short name T166
Test name
Test status
Simulation time 8424795677 ps
CPU time 8.73 seconds
Started May 09 02:50:07 PM PDT 24
Finished May 09 02:50:21 PM PDT 24
Peak memory 204584 kb
Host smart-e1286a4e-f0cb-4b0f-b1bb-195abad5c32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94249
0864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.942490864
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2501429592
Short name T840
Test name
Test status
Simulation time 8430937935 ps
CPU time 10.03 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204576 kb
Host smart-d747de19-b5de-45a0-bbf3-0270a7a03424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25014
29592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2501429592
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2733708165
Short name T390
Test name
Test status
Simulation time 48078955 ps
CPU time 0.7 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204528 kb
Host smart-eb7ad750-71b7-469c-a295-b85a7d09cd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27337
08165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2733708165
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3239132854
Short name T632
Test name
Test status
Simulation time 27401046076 ps
CPU time 52.86 seconds
Started May 09 02:50:03 PM PDT 24
Finished May 09 02:51:03 PM PDT 24
Peak memory 204796 kb
Host smart-14733bd4-1962-478e-bad0-985a7a064d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32391
32854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3239132854
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1129345609
Short name T1396
Test name
Test status
Simulation time 8409671786 ps
CPU time 7.48 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204628 kb
Host smart-eb74e0b2-bb26-41a2-be3b-71d4ac5bea20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11293
45609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1129345609
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1290754284
Short name T665
Test name
Test status
Simulation time 8481257963 ps
CPU time 7.74 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204824 kb
Host smart-c86f5a17-f633-47c3-96dc-b03867e11d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12907
54284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1290754284
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3590684422
Short name T669
Test name
Test status
Simulation time 8414907067 ps
CPU time 7.84 seconds
Started May 09 02:50:03 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 204628 kb
Host smart-07729bff-cca3-4860-9ce8-ba550944895a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
84422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3590684422
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3381071720
Short name T876
Test name
Test status
Simulation time 8381642657 ps
CPU time 7.59 seconds
Started May 09 02:50:01 PM PDT 24
Finished May 09 02:50:16 PM PDT 24
Peak memory 204588 kb
Host smart-12354051-a19c-4c41-9980-4c4be616ed4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33810
71720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3381071720
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3502243349
Short name T746
Test name
Test status
Simulation time 8364574615 ps
CPU time 7.93 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:17 PM PDT 24
Peak memory 204600 kb
Host smart-70ee8992-f59e-48bc-bb84-079b366bdf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35022
43349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3502243349
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1728666732
Short name T897
Test name
Test status
Simulation time 8474504983 ps
CPU time 8.27 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204600 kb
Host smart-cd4ec8c1-fd31-4aa0-8cc6-5edcaae9138c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286
66732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1728666732
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2147514289
Short name T529
Test name
Test status
Simulation time 8414200815 ps
CPU time 8.21 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:10 PM PDT 24
Peak memory 204524 kb
Host smart-82d2952b-a6b9-42e9-88c2-6d49ed573def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
14289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2147514289
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1795896665
Short name T1318
Test name
Test status
Simulation time 8415305113 ps
CPU time 8.21 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204820 kb
Host smart-6fd06454-ca0b-4812-b74e-0da0d2c0b1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
96665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1795896665
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.1531822571
Short name T513
Test name
Test status
Simulation time 8459309731 ps
CPU time 9.5 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 204204 kb
Host smart-829d31b1-7ec7-4cb7-9448-a0a9e2589a13
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1531822571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.1531822571
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.111641955
Short name T859
Test name
Test status
Simulation time 8376789786 ps
CPU time 8.17 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 204556 kb
Host smart-869a3fd2-d80b-43e8-9e76-04c0b8be2471
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=111641955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.111641955
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.8029120
Short name T987
Test name
Test status
Simulation time 8453080555 ps
CPU time 7.91 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:34 PM PDT 24
Peak memory 204824 kb
Host smart-f5c02c78-00a5-4e2c-86ba-7e79c9a8e188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80291
20 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.8029120
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.795641614
Short name T1308
Test name
Test status
Simulation time 8379984078 ps
CPU time 10 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:12 PM PDT 24
Peak memory 204560 kb
Host smart-ea2bd9c4-8cff-458e-8782-081cebcfc3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79564
1614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.795641614
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1619155226
Short name T140
Test name
Test status
Simulation time 9391697635 ps
CPU time 13.78 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 204676 kb
Host smart-a94781e4-0f09-48a0-91ce-502c6b291aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16191
55226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1619155226
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_enable.3391406583
Short name T598
Test name
Test status
Simulation time 8376240346 ps
CPU time 7.92 seconds
Started May 09 02:49:58 PM PDT 24
Finished May 09 02:50:12 PM PDT 24
Peak memory 204596 kb
Host smart-fdacd6fd-ae3b-48a3-9411-d288c1752d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914
06583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3391406583
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.4039471782
Short name T373
Test name
Test status
Simulation time 107649069 ps
CPU time 2.22 seconds
Started May 09 02:50:02 PM PDT 24
Finished May 09 02:50:12 PM PDT 24
Peak memory 204712 kb
Host smart-334a29cd-4f00-494e-9c12-fc0be3257c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40394
71782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.4039471782
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3906919994
Short name T560
Test name
Test status
Simulation time 8401042575 ps
CPU time 8.7 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 204572 kb
Host smart-89f60c83-73e5-4df1-9992-65a1f11e75cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39069
19994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3906919994
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1243937145
Short name T204
Test name
Test status
Simulation time 8375665565 ps
CPU time 8.57 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:33 PM PDT 24
Peak memory 204552 kb
Host smart-66f6ed24-e4e0-4a05-a046-39ae9fbe42fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12439
37145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1243937145
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.744542395
Short name T867
Test name
Test status
Simulation time 8378982033 ps
CPU time 8.94 seconds
Started May 09 02:50:03 PM PDT 24
Finished May 09 02:50:20 PM PDT 24
Peak memory 204604 kb
Host smart-1ad68643-88c6-4394-ae6e-d612062d5697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74454
2395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.744542395
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1074323962
Short name T376
Test name
Test status
Simulation time 8442161169 ps
CPU time 8.21 seconds
Started May 09 02:49:59 PM PDT 24
Finished May 09 02:50:13 PM PDT 24
Peak memory 204596 kb
Host smart-0b385048-e3ab-4a68-adb0-3c1d43aa3ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10743
23962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1074323962
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.90458
Short name T1099
Test name
Test status
Simulation time 8406446576 ps
CPU time 7.79 seconds
Started May 09 02:49:57 PM PDT 24
Finished May 09 02:50:09 PM PDT 24
Peak memory 204540 kb
Host smart-155bc908-411f-420f-8acf-22565a155a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90458
-assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.90458
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2633465181
Short name T1315
Test name
Test status
Simulation time 8454892806 ps
CPU time 8.09 seconds
Started May 09 02:50:00 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 204572 kb
Host smart-eafd11c0-a638-4f27-a9fa-d3ee20fe91ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26334
65181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2633465181
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2508134337
Short name T812
Test name
Test status
Simulation time 8398969830 ps
CPU time 7.6 seconds
Started May 09 02:50:16 PM PDT 24
Finished May 09 02:50:33 PM PDT 24
Peak memory 204524 kb
Host smart-3c745ecf-7b11-40a1-8fed-7ce38b8e2a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25081
34337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2508134337
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1705860991
Short name T880
Test name
Test status
Simulation time 8388195228 ps
CPU time 7.36 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 204600 kb
Host smart-1bb80e5d-fd99-4221-b611-b74a70d8cc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17058
60991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1705860991
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.526633152
Short name T191
Test name
Test status
Simulation time 8391872657 ps
CPU time 7.59 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:34 PM PDT 24
Peak memory 204600 kb
Host smart-02ce5cb5-36de-422e-8ece-be6d54a0c40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52663
3152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.526633152
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2756468594
Short name T757
Test name
Test status
Simulation time 8377443805 ps
CPU time 8.08 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:30 PM PDT 24
Peak memory 204608 kb
Host smart-a3f6a284-4635-4f12-bbb2-bcf5d315e45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27564
68594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2756468594
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3186120586
Short name T500
Test name
Test status
Simulation time 91048204 ps
CPU time 0.73 seconds
Started May 09 02:50:31 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 204484 kb
Host smart-b81939bf-08e7-4e11-ae58-729ce645ab09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31861
20586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3186120586
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.4236162581
Short name T921
Test name
Test status
Simulation time 18159514300 ps
CPU time 35.52 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:54 PM PDT 24
Peak memory 204808 kb
Host smart-83c6d42a-c76e-41c3-8688-94a2a015c478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42361
62581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.4236162581
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.390465365
Short name T982
Test name
Test status
Simulation time 8419698512 ps
CPU time 9.92 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:26 PM PDT 24
Peak memory 204636 kb
Host smart-60e3203d-19e4-4961-b91e-8c3c4607bcd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
5365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.390465365
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.222813288
Short name T899
Test name
Test status
Simulation time 8451229760 ps
CPU time 8.59 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:34 PM PDT 24
Peak memory 204572 kb
Host smart-e38fcedb-3493-48b1-b033-4eccc12ef730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22281
3288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.222813288
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2014299635
Short name T338
Test name
Test status
Simulation time 8382628278 ps
CPU time 7.84 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:25 PM PDT 24
Peak memory 204584 kb
Host smart-1d2d21e2-4ac9-46a8-83b6-fe0b0a2da0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142
99635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2014299635
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3605295753
Short name T170
Test name
Test status
Simulation time 8390625044 ps
CPU time 8.57 seconds
Started May 09 02:50:19 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 204552 kb
Host smart-81ada409-165b-45a2-9a6f-310ac0a04195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36052
95753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3605295753
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.142214246
Short name T578
Test name
Test status
Simulation time 8370774368 ps
CPU time 8.01 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 204520 kb
Host smart-caf346f7-1262-4b72-8e45-f4553d1618e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14221
4246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.142214246
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3324368936
Short name T781
Test name
Test status
Simulation time 8459824762 ps
CPU time 8.54 seconds
Started May 09 02:50:07 PM PDT 24
Finished May 09 02:50:21 PM PDT 24
Peak memory 204592 kb
Host smart-f76cf37e-4845-481e-b575-ecbd9944b8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33243
68936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3324368936
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.856205744
Short name T580
Test name
Test status
Simulation time 8458969551 ps
CPU time 7.71 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 204560 kb
Host smart-d3698a37-e77d-4984-b957-81f1a7949b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85620
5744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.856205744
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1070761512
Short name T685
Test name
Test status
Simulation time 8393252878 ps
CPU time 8.78 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:26 PM PDT 24
Peak memory 204588 kb
Host smart-91c0e6f0-3330-43dc-af17-e62c094cf9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
61512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1070761512
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.1074202576
Short name T764
Test name
Test status
Simulation time 8548987718 ps
CPU time 10.28 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 204572 kb
Host smart-7c23cae8-3dfe-49eb-a967-379acfdfb8a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1074202576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.1074202576
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.2855072100
Short name T988
Test name
Test status
Simulation time 8379342099 ps
CPU time 7.92 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:35 PM PDT 24
Peak memory 204164 kb
Host smart-1a43f3bd-81d7-4834-a1d0-625268393143
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2855072100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.2855072100
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.1062061632
Short name T778
Test name
Test status
Simulation time 8466620837 ps
CPU time 7.7 seconds
Started May 09 02:50:22 PM PDT 24
Finished May 09 02:50:41 PM PDT 24
Peak memory 204560 kb
Host smart-8b2df69f-1eb9-4708-803e-71ace2709ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10620
61632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.1062061632
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2955327580
Short name T1249
Test name
Test status
Simulation time 8373370909 ps
CPU time 8.94 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 204508 kb
Host smart-830b1e6a-fa37-490c-9e1b-0c7c506b9f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553
27580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2955327580
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.1741457926
Short name T558
Test name
Test status
Simulation time 9686038315 ps
CPU time 13.99 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:33 PM PDT 24
Peak memory 204760 kb
Host smart-e646029a-5faf-494a-92c6-63f1d0820976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17414
57926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1741457926
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_enable.1663808197
Short name T893
Test name
Test status
Simulation time 8374617880 ps
CPU time 8.44 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 204584 kb
Host smart-0fe46fce-d5a0-44d5-b765-632e20be22bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
08197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1663808197
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1085207024
Short name T426
Test name
Test status
Simulation time 64513719 ps
CPU time 1.14 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 204764 kb
Host smart-4df0babc-f42d-4cfc-bd8f-b9b91fcc7d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852
07024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1085207024
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3070155715
Short name T148
Test name
Test status
Simulation time 8415675590 ps
CPU time 7.79 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:28 PM PDT 24
Peak memory 204592 kb
Host smart-45b68aeb-4749-4a67-b4e2-80dc7de68337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30701
55715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3070155715
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3917511935
Short name T1130
Test name
Test status
Simulation time 8361819893 ps
CPU time 9.15 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 204528 kb
Host smart-5900e39b-08a4-4029-84e4-b297f3f4ec59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39175
11935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3917511935
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4279831602
Short name T936
Test name
Test status
Simulation time 8395590464 ps
CPU time 7.69 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:25 PM PDT 24
Peak memory 204600 kb
Host smart-56eb77fa-38ed-41be-b57f-9abc68fb3600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42798
31602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4279831602
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.665219242
Short name T1294
Test name
Test status
Simulation time 8415124492 ps
CPU time 9.62 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 204564 kb
Host smart-0cc6b590-329b-4cb8-a79d-a3e522b76bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66521
9242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.665219242
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.465280245
Short name T1278
Test name
Test status
Simulation time 8378802929 ps
CPU time 10.12 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:30 PM PDT 24
Peak memory 204568 kb
Host smart-2f29e977-2439-496e-8f3c-95b9c1267269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46528
0245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.465280245
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3371866035
Short name T1051
Test name
Test status
Simulation time 8388691721 ps
CPU time 8.64 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:33 PM PDT 24
Peak memory 204524 kb
Host smart-d3c7c2ed-9cce-4728-843c-65b0832d08ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33718
66035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3371866035
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3234637660
Short name T401
Test name
Test status
Simulation time 8420937632 ps
CPU time 8.74 seconds
Started May 09 02:50:15 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 204556 kb
Host smart-0ebf5f1e-fa05-47c3-b229-82cdc99a0081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32346
37660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3234637660
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1967201759
Short name T946
Test name
Test status
Simulation time 8407269254 ps
CPU time 8.49 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 204576 kb
Host smart-35181236-37ab-4f6a-99ef-6682a1482aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
01759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1967201759
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2585340633
Short name T1201
Test name
Test status
Simulation time 8386625926 ps
CPU time 9.23 seconds
Started May 09 02:50:18 PM PDT 24
Finished May 09 02:50:37 PM PDT 24
Peak memory 204556 kb
Host smart-742254f0-3e05-47ce-8b73-24ad24182bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25853
40633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2585340633
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2762036033
Short name T1419
Test name
Test status
Simulation time 8373784968 ps
CPU time 9.15 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 204508 kb
Host smart-14ffecc0-336c-45e1-bba8-0d3969eabfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27620
36033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2762036033
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1269693464
Short name T630
Test name
Test status
Simulation time 31788721 ps
CPU time 0.65 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 204416 kb
Host smart-45ab4ed3-cf71-46f2-b841-bbe39cfcec7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12696
93464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1269693464
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.4087202089
Short name T488
Test name
Test status
Simulation time 29841936242 ps
CPU time 56.98 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:51:16 PM PDT 24
Peak memory 204744 kb
Host smart-d0066e1c-8a11-4a4b-a239-f2fbf98aba45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40872
02089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.4087202089
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3235445210
Short name T689
Test name
Test status
Simulation time 8454463800 ps
CPU time 8.11 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 204580 kb
Host smart-684a30f9-3f2b-4eba-9be6-c1b7a47efe32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32354
45210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3235445210
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3378638251
Short name T1269
Test name
Test status
Simulation time 8407882191 ps
CPU time 8.19 seconds
Started May 09 02:50:14 PM PDT 24
Finished May 09 02:50:29 PM PDT 24
Peak memory 204456 kb
Host smart-1df6c4c7-a0b8-4cd7-9bc8-27dd746cee97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33786
38251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3378638251
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3986538599
Short name T983
Test name
Test status
Simulation time 8427504225 ps
CPU time 9.55 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 204552 kb
Host smart-9849623a-4162-4f66-b511-04f76e637291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39865
38599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3986538599
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.306758031
Short name T1212
Test name
Test status
Simulation time 8375177455 ps
CPU time 8.52 seconds
Started May 09 02:50:13 PM PDT 24
Finished May 09 02:50:27 PM PDT 24
Peak memory 204568 kb
Host smart-e7c2622a-ced4-498e-b06c-e4566b09bd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
8031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.306758031
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3978223430
Short name T828
Test name
Test status
Simulation time 8365821727 ps
CPU time 8.02 seconds
Started May 09 02:50:12 PM PDT 24
Finished May 09 02:50:25 PM PDT 24
Peak memory 204584 kb
Host smart-d63e5fe9-4f5a-4bed-afaf-cc649d5f085a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782
23430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3978223430
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4099417213
Short name T626
Test name
Test status
Simulation time 8454214113 ps
CPU time 7.89 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:23 PM PDT 24
Peak memory 204556 kb
Host smart-5b40c69c-9a59-4dd4-8942-08fbafcbf0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
17213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4099417213
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.967023596
Short name T1232
Test name
Test status
Simulation time 8435741942 ps
CPU time 8.38 seconds
Started May 09 02:50:11 PM PDT 24
Finished May 09 02:50:24 PM PDT 24
Peak memory 204568 kb
Host smart-770e92bc-b316-4cf0-ae31-56dc76261781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96702
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.967023596
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.704945452
Short name T570
Test name
Test status
Simulation time 8413181411 ps
CPU time 9.22 seconds
Started May 09 02:50:17 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 204524 kb
Host smart-caa2774c-2d9e-4463-a124-60dac37b2ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70494
5452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.704945452
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2160068689
Short name T354
Test name
Test status
Simulation time 8469834743 ps
CPU time 9.66 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:38 PM PDT 24
Peak memory 204580 kb
Host smart-dd29b711-29b0-4388-87fc-1a0782776c0b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2160068689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2160068689
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1703829846
Short name T1251
Test name
Test status
Simulation time 8392841468 ps
CPU time 7.62 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204508 kb
Host smart-2e87a050-131c-4229-835c-7dec60831e59
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1703829846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1703829846
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.274858027
Short name T23
Test name
Test status
Simulation time 8405803805 ps
CPU time 7.71 seconds
Started May 09 02:46:24 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204600 kb
Host smart-d0b573f1-22d1-4acf-9aa0-3b083c6feb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27485
8027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.274858027
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.498421475
Short name T432
Test name
Test status
Simulation time 8377756092 ps
CPU time 7.8 seconds
Started May 09 02:46:13 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 204592 kb
Host smart-69bab585-cbf3-4d9b-b8df-89d096a89e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49842
1475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.498421475
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.308860795
Short name T506
Test name
Test status
Simulation time 8613133323 ps
CPU time 11.7 seconds
Started May 09 02:46:14 PM PDT 24
Finished May 09 02:46:28 PM PDT 24
Peak memory 204816 kb
Host smart-55c1e98b-9a70-4430-b508-15265714ba38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30886
0795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.308860795
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_enable.2951872156
Short name T651
Test name
Test status
Simulation time 8375650471 ps
CPU time 8.74 seconds
Started May 09 02:46:12 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 204540 kb
Host smart-6c5ef81d-3aca-453f-908e-8191b10a7378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29518
72156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2951872156
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1638820652
Short name T4
Test name
Test status
Simulation time 185696399 ps
CPU time 1.96 seconds
Started May 09 02:46:19 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 204684 kb
Host smart-f416a207-cbe9-4db3-b429-57a1553b03b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
20652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1638820652
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3554219508
Short name T1343
Test name
Test status
Simulation time 8493337863 ps
CPU time 8.81 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:36 PM PDT 24
Peak memory 204576 kb
Host smart-3d19f63b-5bdb-4abc-84b0-9918167fee4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
19508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3554219508
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.782659349
Short name T1281
Test name
Test status
Simulation time 8431271113 ps
CPU time 7.8 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204544 kb
Host smart-20ccbc48-e2ec-4655-94c6-339595e3240f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78265
9349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.782659349
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1187568905
Short name T930
Test name
Test status
Simulation time 8439769272 ps
CPU time 7.54 seconds
Started May 09 02:46:10 PM PDT 24
Finished May 09 02:46:20 PM PDT 24
Peak memory 204564 kb
Host smart-643375b7-2051-4c0d-9ef3-88ebb930fd75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11875
68905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1187568905
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.182430034
Short name T437
Test name
Test status
Simulation time 8418850005 ps
CPU time 7.41 seconds
Started May 09 02:46:14 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 204600 kb
Host smart-7efd8d0e-71fd-4825-8fee-5912b34b7bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18243
0034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.182430034
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1961620466
Short name T1330
Test name
Test status
Simulation time 8371319679 ps
CPU time 7.55 seconds
Started May 09 02:46:14 PM PDT 24
Finished May 09 02:46:24 PM PDT 24
Peak memory 204572 kb
Host smart-cb2d9b0a-38dd-45ea-848c-9ca51ff888a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19616
20466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1961620466
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3721069701
Short name T98
Test name
Test status
Simulation time 8426358633 ps
CPU time 10.25 seconds
Started May 09 02:46:14 PM PDT 24
Finished May 09 02:46:27 PM PDT 24
Peak memory 204572 kb
Host smart-8effcf71-36a3-4713-b476-5dc4d3925b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37210
69701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3721069701
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.980427398
Short name T356
Test name
Test status
Simulation time 8379415250 ps
CPU time 8.46 seconds
Started May 09 02:46:11 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 204576 kb
Host smart-263c01a4-f980-426b-ab75-47228b88d6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98042
7398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.980427398
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1084736491
Short name T603
Test name
Test status
Simulation time 8382205532 ps
CPU time 7.53 seconds
Started May 09 02:46:16 PM PDT 24
Finished May 09 02:46:25 PM PDT 24
Peak memory 204528 kb
Host smart-83543ce8-4be7-4ce4-96f8-1aa578a99b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
36491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1084736491
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.151141638
Short name T1375
Test name
Test status
Simulation time 8399966988 ps
CPU time 8.13 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:36 PM PDT 24
Peak memory 204516 kb
Host smart-d72e72fd-ede6-4791-afd3-0fdd22c7ef9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15114
1638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.151141638
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3887725087
Short name T1282
Test name
Test status
Simulation time 8422134585 ps
CPU time 9.78 seconds
Started May 09 02:46:12 PM PDT 24
Finished May 09 02:46:25 PM PDT 24
Peak memory 204588 kb
Host smart-3b6c9bcf-bb89-482d-a7af-0b5d9402f432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
25087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3887725087
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.4277373124
Short name T994
Test name
Test status
Simulation time 81869674 ps
CPU time 0.71 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:29 PM PDT 24
Peak memory 204460 kb
Host smart-dee59fbd-357a-4421-9580-5cde46fd0aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773
73124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.4277373124
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.317262709
Short name T628
Test name
Test status
Simulation time 28653510379 ps
CPU time 58.95 seconds
Started May 09 02:46:12 PM PDT 24
Finished May 09 02:47:13 PM PDT 24
Peak memory 204856 kb
Host smart-5b3ebd91-ad8a-48e3-8acd-345ad8da5848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31726
2709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.317262709
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2783999636
Short name T363
Test name
Test status
Simulation time 8386914494 ps
CPU time 7.96 seconds
Started May 09 02:46:15 PM PDT 24
Finished May 09 02:46:25 PM PDT 24
Peak memory 204544 kb
Host smart-d97ba9bd-1628-47b0-927f-219591902860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27839
99636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2783999636
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4257865141
Short name T648
Test name
Test status
Simulation time 8455288341 ps
CPU time 10.25 seconds
Started May 09 02:46:20 PM PDT 24
Finished May 09 02:46:31 PM PDT 24
Peak memory 204396 kb
Host smart-e0a2a55f-82fc-4a23-816d-64641b5ccaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
65141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4257865141
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2287256282
Short name T1184
Test name
Test status
Simulation time 8423288443 ps
CPU time 7.64 seconds
Started May 09 02:46:10 PM PDT 24
Finished May 09 02:46:20 PM PDT 24
Peak memory 204612 kb
Host smart-7197b656-daaa-4e0e-9230-e5cc55a31e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22872
56282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2287256282
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2387838913
Short name T1301
Test name
Test status
Simulation time 8375274563 ps
CPU time 8.69 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204576 kb
Host smart-2eb5d56c-a8cf-4631-9137-251f4282ad35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
38913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2387838913
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1604946105
Short name T1044
Test name
Test status
Simulation time 8365029710 ps
CPU time 8.25 seconds
Started May 09 02:46:14 PM PDT 24
Finished May 09 02:46:24 PM PDT 24
Peak memory 204556 kb
Host smart-29b95f7a-6a8a-45af-abf5-d703f68c7cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16049
46105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1604946105
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.991391651
Short name T1277
Test name
Test status
Simulation time 8464780492 ps
CPU time 8.77 seconds
Started May 09 02:46:20 PM PDT 24
Finished May 09 02:46:30 PM PDT 24
Peak memory 204276 kb
Host smart-8d62ae73-8ca5-40bc-92a3-6f7156f507c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99139
1651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.991391651
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2767928241
Short name T317
Test name
Test status
Simulation time 8394073732 ps
CPU time 7.49 seconds
Started May 09 02:46:14 PM PDT 24
Finished May 09 02:46:24 PM PDT 24
Peak memory 204568 kb
Host smart-9a74d5bb-a4e8-4733-989a-08f9b1ee11ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27679
28241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2767928241
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3379729887
Short name T1276
Test name
Test status
Simulation time 8378306444 ps
CPU time 8.41 seconds
Started May 09 02:46:12 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 204592 kb
Host smart-5e7e8a4b-a0fe-4f1e-b186-67eda31be6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
29887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3379729887
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.1914599930
Short name T1030
Test name
Test status
Simulation time 8523183704 ps
CPU time 8.68 seconds
Started May 09 02:46:37 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204548 kb
Host smart-e06966ee-4789-40c4-8b84-76271da4da8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1914599930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.1914599930
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.4211435606
Short name T1425
Test name
Test status
Simulation time 8380400957 ps
CPU time 8.09 seconds
Started May 09 02:46:21 PM PDT 24
Finished May 09 02:46:34 PM PDT 24
Peak memory 204508 kb
Host smart-4c0719e3-da68-4a96-ba74-83fff1956731
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4211435606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.4211435606
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.307344606
Short name T1365
Test name
Test status
Simulation time 8441983544 ps
CPU time 7.85 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204552 kb
Host smart-31b0d1dd-492d-49ab-9350-73dfa77080bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30734
4606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.307344606
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2355790907
Short name T1283
Test name
Test status
Simulation time 8396208388 ps
CPU time 8.15 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204532 kb
Host smart-8997d314-d96a-491c-9ca5-45ef59c15813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
90907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2355790907
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3736770057
Short name T1257
Test name
Test status
Simulation time 8814280475 ps
CPU time 12.11 seconds
Started May 09 02:46:24 PM PDT 24
Finished May 09 02:46:41 PM PDT 24
Peak memory 204716 kb
Host smart-2bb2e8df-d6b5-4e0f-8dfe-03899f4923e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37367
70057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3736770057
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_enable.2924583196
Short name T775
Test name
Test status
Simulation time 8381859425 ps
CPU time 7.77 seconds
Started May 09 02:46:24 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204568 kb
Host smart-81557615-3458-41ca-a650-fc8af954a520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29245
83196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2924583196
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3880273244
Short name T653
Test name
Test status
Simulation time 144505424 ps
CPU time 1.35 seconds
Started May 09 02:46:24 PM PDT 24
Finished May 09 02:46:31 PM PDT 24
Peak memory 204736 kb
Host smart-8f18a137-ebf8-4e72-8d5a-743799f4499c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
73244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3880273244
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3777937655
Short name T416
Test name
Test status
Simulation time 8449405036 ps
CPU time 8.46 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204608 kb
Host smart-ad304738-308e-45f4-9ac1-89a5a247a76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
37655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3777937655
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1366478933
Short name T595
Test name
Test status
Simulation time 8368491101 ps
CPU time 9.58 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204588 kb
Host smart-4fe77846-36ca-4415-ac6c-155f1142fc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13664
78933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1366478933
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1312295104
Short name T43
Test name
Test status
Simulation time 8400015800 ps
CPU time 8.32 seconds
Started May 09 02:46:25 PM PDT 24
Finished May 09 02:46:38 PM PDT 24
Peak memory 204572 kb
Host smart-720ebb8b-5c3c-410f-acee-637507c7ab42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13122
95104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1312295104
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3943015870
Short name T563
Test name
Test status
Simulation time 8415414482 ps
CPU time 7.61 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:36 PM PDT 24
Peak memory 204560 kb
Host smart-4d44a487-445a-485e-93aa-8633c807f353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39430
15870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3943015870
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.616722009
Short name T295
Test name
Test status
Simulation time 8395070092 ps
CPU time 7.63 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204492 kb
Host smart-07c5c831-98e6-4d75-9e95-8f0578904114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61672
2009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.616722009
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.356574721
Short name T109
Test name
Test status
Simulation time 8409848267 ps
CPU time 7.95 seconds
Started May 09 02:46:20 PM PDT 24
Finished May 09 02:46:31 PM PDT 24
Peak memory 204580 kb
Host smart-3bd1ad29-0dfc-4892-9bab-76bd34417d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657
4721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.356574721
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3188672084
Short name T604
Test name
Test status
Simulation time 8397484915 ps
CPU time 7.91 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:36 PM PDT 24
Peak memory 204568 kb
Host smart-98783251-2785-4631-9c40-26d6b848d331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
72084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3188672084
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.655604560
Short name T1218
Test name
Test status
Simulation time 8400267193 ps
CPU time 7.72 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204616 kb
Host smart-2013f34e-b8fd-44d7-b42c-9294c6430c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65560
4560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.655604560
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3145985616
Short name T60
Test name
Test status
Simulation time 8382630667 ps
CPU time 7.63 seconds
Started May 09 02:46:21 PM PDT 24
Finished May 09 02:46:33 PM PDT 24
Peak memory 204548 kb
Host smart-54621e18-9188-4e68-8a25-d869d17b43d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459
85616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3145985616
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.189715448
Short name T12
Test name
Test status
Simulation time 8370918877 ps
CPU time 9.65 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:38 PM PDT 24
Peak memory 204588 kb
Host smart-1e032cf9-decb-44a5-8043-ffdd262fb0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18971
5448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.189715448
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2884515703
Short name T583
Test name
Test status
Simulation time 38198864 ps
CPU time 0.64 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:28 PM PDT 24
Peak memory 204308 kb
Host smart-48d2996b-8209-4f49-ada9-46f7076a1343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28845
15703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2884515703
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2459621011
Short name T248
Test name
Test status
Simulation time 26807942285 ps
CPU time 50.55 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:47:18 PM PDT 24
Peak memory 204840 kb
Host smart-62a70a30-228b-411e-b447-84131559fab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24596
21011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2459621011
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4017667133
Short name T439
Test name
Test status
Simulation time 8405941954 ps
CPU time 8.87 seconds
Started May 09 02:46:24 PM PDT 24
Finished May 09 02:46:39 PM PDT 24
Peak memory 204592 kb
Host smart-d7af8f14-0e67-4ec2-8a7a-662476e94dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40176
67133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4017667133
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2715457261
Short name T146
Test name
Test status
Simulation time 8413114901 ps
CPU time 7.96 seconds
Started May 09 02:46:24 PM PDT 24
Finished May 09 02:46:38 PM PDT 24
Peak memory 204576 kb
Host smart-895ae158-7783-4450-acdc-0d0cca384a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27154
57261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2715457261
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3507554324
Short name T377
Test name
Test status
Simulation time 8402672827 ps
CPU time 8.22 seconds
Started May 09 02:46:23 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204564 kb
Host smart-922d43d2-d015-4a42-857d-a06c02ef9811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35075
54324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3507554324
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.551588884
Short name T738
Test name
Test status
Simulation time 8392949256 ps
CPU time 7.81 seconds
Started May 09 02:46:21 PM PDT 24
Finished May 09 02:46:33 PM PDT 24
Peak memory 204608 kb
Host smart-c2ae896d-8e1f-41bd-9a9e-411db349f579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55158
8884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.551588884
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1249821353
Short name T944
Test name
Test status
Simulation time 8369354571 ps
CPU time 8.85 seconds
Started May 09 02:46:25 PM PDT 24
Finished May 09 02:46:39 PM PDT 24
Peak memory 204452 kb
Host smart-90b54bfc-1cab-4c85-badf-fc59f6c3f560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12498
21353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1249821353
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2162867916
Short name T97
Test name
Test status
Simulation time 8442160185 ps
CPU time 8 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:35 PM PDT 24
Peak memory 204616 kb
Host smart-4c679105-ae7f-4201-9002-cb85882b1197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21628
67916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2162867916
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1044605076
Short name T333
Test name
Test status
Simulation time 8396813654 ps
CPU time 9.19 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:36 PM PDT 24
Peak memory 204568 kb
Host smart-24d35a88-ff15-471d-8180-cdff216d8fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10446
05076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1044605076
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.240626724
Short name T519
Test name
Test status
Simulation time 8451957298 ps
CPU time 10.26 seconds
Started May 09 02:46:22 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 204536 kb
Host smart-a57cb2ef-a955-4d64-be78-8e2ce212621f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.240626724
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.2250842019
Short name T699
Test name
Test status
Simulation time 8475049639 ps
CPU time 7.81 seconds
Started May 09 02:46:38 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204572 kb
Host smart-b5d15908-d31e-46a3-b686-d2d6c859451a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2250842019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.2250842019
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.1612682237
Short name T538
Test name
Test status
Simulation time 8373624944 ps
CPU time 8.26 seconds
Started May 09 02:46:36 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204516 kb
Host smart-4df17ed5-2c68-4bd9-9e06-127274410403
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1612682237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.1612682237
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.2325764405
Short name T802
Test name
Test status
Simulation time 8428980536 ps
CPU time 10.19 seconds
Started May 09 02:46:37 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204544 kb
Host smart-df636eb9-1d8d-460b-8a87-37f3c897f447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23257
64405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.2325764405
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3849318221
Short name T925
Test name
Test status
Simulation time 8377450228 ps
CPU time 8.86 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:49 PM PDT 24
Peak memory 204568 kb
Host smart-f04fe0fb-5685-4018-bfd2-65a90bd69de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38493
18221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3849318221
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.4270981076
Short name T688
Test name
Test status
Simulation time 9255572681 ps
CPU time 13.55 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:54 PM PDT 24
Peak memory 204788 kb
Host smart-242f31d5-e51f-45a1-a9ea-7f263628fd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42709
81076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.4270981076
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_enable.1240953054
Short name T498
Test name
Test status
Simulation time 8384053844 ps
CPU time 9.49 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:48 PM PDT 24
Peak memory 204576 kb
Host smart-e3206044-87ee-492f-931e-59516126cd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12409
53054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1240953054
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2109078366
Short name T1226
Test name
Test status
Simulation time 113953126 ps
CPU time 1.17 seconds
Started May 09 02:46:37 PM PDT 24
Finished May 09 02:46:44 PM PDT 24
Peak memory 204660 kb
Host smart-022bd9b8-0894-4e8f-8948-fd4f6450afcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
78366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2109078366
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2045117776
Short name T61
Test name
Test status
Simulation time 8444352517 ps
CPU time 7.88 seconds
Started May 09 02:47:05 PM PDT 24
Finished May 09 02:47:17 PM PDT 24
Peak memory 204556 kb
Host smart-bb469a94-eeee-483d-8b32-6c7e70b748d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
17776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2045117776
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3075071626
Short name T209
Test name
Test status
Simulation time 8368541860 ps
CPU time 7.7 seconds
Started May 09 02:46:37 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204528 kb
Host smart-fea7627f-f13d-43d1-8bae-4fd9cb1951de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30750
71626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3075071626
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3515241684
Short name T1313
Test name
Test status
Simulation time 8393091892 ps
CPU time 8.38 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:47 PM PDT 24
Peak memory 204592 kb
Host smart-388a1984-28ce-4ede-81fc-ea0a681bed4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35152
41684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3515241684
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2110879804
Short name T845
Test name
Test status
Simulation time 8414672257 ps
CPU time 8.23 seconds
Started May 09 02:46:32 PM PDT 24
Finished May 09 02:46:45 PM PDT 24
Peak memory 204536 kb
Host smart-9504d77e-f76b-4327-93a9-3b4984fb19f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
79804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2110879804
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3108277210
Short name T776
Test name
Test status
Simulation time 8366738048 ps
CPU time 7.95 seconds
Started May 09 02:46:35 PM PDT 24
Finished May 09 02:46:50 PM PDT 24
Peak memory 204544 kb
Host smart-8b5405ae-febe-4d52-a45f-9e0787c8b347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31082
77210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3108277210
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3852680632
Short name T1032
Test name
Test status
Simulation time 8446367793 ps
CPU time 7.87 seconds
Started May 09 02:46:32 PM PDT 24
Finished May 09 02:46:45 PM PDT 24
Peak memory 204524 kb
Host smart-8f474a42-8aae-4d9a-9f52-220343850395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38526
80632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3852680632
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2864090758
Short name T429
Test name
Test status
Simulation time 8436952813 ps
CPU time 8.79 seconds
Started May 09 02:46:32 PM PDT 24
Finished May 09 02:46:47 PM PDT 24
Peak memory 204572 kb
Host smart-b1f1ff87-eee0-4b6a-8a9d-dce64e249763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28640
90758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2864090758
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.4261448643
Short name T1221
Test name
Test status
Simulation time 8413524672 ps
CPU time 9.58 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:50 PM PDT 24
Peak memory 204592 kb
Host smart-f96c04c0-f712-4099-b1be-f98e72a3bdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
48643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.4261448643
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2568875633
Short name T30
Test name
Test status
Simulation time 8409399775 ps
CPU time 9.24 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:47 PM PDT 24
Peak memory 204532 kb
Host smart-886e19c6-969b-45c8-9e10-32fdc8cd6e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688
75633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2568875633
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.868509042
Short name T1096
Test name
Test status
Simulation time 8372471924 ps
CPU time 9.98 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:48 PM PDT 24
Peak memory 204572 kb
Host smart-41bc2ca7-2816-4fda-befa-93ea3c3ae6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86850
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.868509042
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2339489764
Short name T430
Test name
Test status
Simulation time 37521985 ps
CPU time 0.69 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:41 PM PDT 24
Peak memory 204468 kb
Host smart-8f2bc060-5217-4968-b580-f48b2de72904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23394
89764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2339489764
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.194056032
Short name T797
Test name
Test status
Simulation time 25416733049 ps
CPU time 47.17 seconds
Started May 09 02:46:35 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 204820 kb
Host smart-a244b3b6-c193-4749-a9c0-1c0a85305e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405
6032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.194056032
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2390303970
Short name T1321
Test name
Test status
Simulation time 8377031991 ps
CPU time 9.18 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:48 PM PDT 24
Peak memory 204572 kb
Host smart-573b54b5-60d3-4726-a92a-62052409b755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23903
03970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2390303970
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2157853679
Short name T1347
Test name
Test status
Simulation time 8444792557 ps
CPU time 8.19 seconds
Started May 09 02:46:40 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204520 kb
Host smart-df0d467d-e546-478c-996c-b8924d41fb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
53679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2157853679
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.3998781660
Short name T1133
Test name
Test status
Simulation time 8396186471 ps
CPU time 8.41 seconds
Started May 09 02:46:36 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204392 kb
Host smart-adac778d-5e68-4a2b-aeb8-b8bff9d96108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39987
81660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.3998781660
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.872144613
Short name T1239
Test name
Test status
Simulation time 8373744430 ps
CPU time 9.11 seconds
Started May 09 02:46:36 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204612 kb
Host smart-3126014d-4f9f-48f5-a62c-218dd71d3fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87214
4613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.872144613
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.912075065
Short name T1186
Test name
Test status
Simulation time 8370852828 ps
CPU time 8.77 seconds
Started May 09 02:46:35 PM PDT 24
Finished May 09 02:46:50 PM PDT 24
Peak memory 204572 kb
Host smart-b7e3f4b6-b23b-4aa3-a803-2e8da887cdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91207
5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.912075065
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2207432437
Short name T1291
Test name
Test status
Simulation time 8419176318 ps
CPU time 7.79 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:46 PM PDT 24
Peak memory 204576 kb
Host smart-fd2017d5-e2ea-4f16-8119-45b4c3ab2550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22074
32437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2207432437
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.756992954
Short name T963
Test name
Test status
Simulation time 8409911422 ps
CPU time 9.75 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:49 PM PDT 24
Peak memory 204576 kb
Host smart-462a78e4-c330-442f-ba5b-6d4bb078b975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75699
2954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.756992954
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3855192293
Short name T1014
Test name
Test status
Simulation time 8374175701 ps
CPU time 8.26 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:48 PM PDT 24
Peak memory 204588 kb
Host smart-d5c356d8-b8ab-4e44-a619-12a8b83753d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
92293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3855192293
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.963285229
Short name T431
Test name
Test status
Simulation time 8466499275 ps
CPU time 7.65 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:48 PM PDT 24
Peak memory 204560 kb
Host smart-12a270cd-6b29-4fc9-8584-850c262c1dab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=963285229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.963285229
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.2316687930
Short name T1161
Test name
Test status
Simulation time 8374478365 ps
CPU time 7.89 seconds
Started May 09 02:46:40 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204500 kb
Host smart-6da4315b-519d-4643-ab34-022f3e913252
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2316687930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.2316687930
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1937603080
Short name T328
Test name
Test status
Simulation time 8411415812 ps
CPU time 9.5 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:54 PM PDT 24
Peak memory 204500 kb
Host smart-c1c69706-04a8-495b-9950-1ce148da90fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376
03080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1937603080
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2464828730
Short name T1215
Test name
Test status
Simulation time 8376361947 ps
CPU time 8.67 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:47 PM PDT 24
Peak memory 204840 kb
Host smart-027959a1-d288-424a-8a83-40be1b887f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24648
28730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2464828730
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.182485424
Short name T497
Test name
Test status
Simulation time 9272614768 ps
CPU time 12.28 seconds
Started May 09 02:46:32 PM PDT 24
Finished May 09 02:46:50 PM PDT 24
Peak memory 204756 kb
Host smart-9ffa1fe3-dad9-42fb-aeea-8858d8505181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18248
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.182485424
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_enable.1635254148
Short name T1132
Test name
Test status
Simulation time 8384096766 ps
CPU time 7.34 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204568 kb
Host smart-a648c826-84b5-46b0-8f7e-9e6cc9de9258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
54148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1635254148
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1473220955
Short name T650
Test name
Test status
Simulation time 56889098 ps
CPU time 1.44 seconds
Started May 09 02:46:35 PM PDT 24
Finished May 09 02:46:43 PM PDT 24
Peak memory 204748 kb
Host smart-9bb2cd53-78c5-42d0-b1e5-8a35dcb794a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
20955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1473220955
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1453872252
Short name T1397
Test name
Test status
Simulation time 8422650553 ps
CPU time 7.86 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204600 kb
Host smart-5a510b92-b784-4563-87aa-5e8c28c0d611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14538
72252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1453872252
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3017922574
Short name T668
Test name
Test status
Simulation time 8369423976 ps
CPU time 8.51 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204580 kb
Host smart-d04af499-631f-4a7c-92e8-2039b1da9912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179
22574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3017922574
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.538944081
Short name T887
Test name
Test status
Simulation time 8463550383 ps
CPU time 7.94 seconds
Started May 09 02:46:33 PM PDT 24
Finished May 09 02:46:47 PM PDT 24
Peak memory 204564 kb
Host smart-ca46e9c8-d6ac-4200-b34d-070e792d35d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53894
4081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.538944081
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.363014425
Short name T447
Test name
Test status
Simulation time 8442993252 ps
CPU time 7.46 seconds
Started May 09 02:46:37 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204560 kb
Host smart-1ae9f171-a9ee-4dcb-8761-d1f4a9e075c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36301
4425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.363014425
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3360070278
Short name T427
Test name
Test status
Simulation time 8394056957 ps
CPU time 8.57 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204388 kb
Host smart-2e0e155a-fa27-4d1f-91f1-eeb3d9940d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33600
70278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3360070278
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3035505790
Short name T1387
Test name
Test status
Simulation time 8400564114 ps
CPU time 7.94 seconds
Started May 09 02:46:38 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204576 kb
Host smart-c85a6cb8-08c2-4334-9009-62003027274d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355
05790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3035505790
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3139812091
Short name T1383
Test name
Test status
Simulation time 8429797442 ps
CPU time 8.82 seconds
Started May 09 02:46:35 PM PDT 24
Finished May 09 02:46:50 PM PDT 24
Peak memory 204552 kb
Host smart-3d8e3d88-be9b-4ca8-a2e4-b18d4d6b29f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31398
12091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3139812091
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.854234781
Short name T926
Test name
Test status
Simulation time 8421626194 ps
CPU time 9.88 seconds
Started May 09 02:46:36 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204620 kb
Host smart-d63851d8-187a-4a19-a686-c4dce2c427c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85423
4781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.854234781
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.905144987
Short name T1211
Test name
Test status
Simulation time 8402041527 ps
CPU time 8.88 seconds
Started May 09 02:46:40 PM PDT 24
Finished May 09 02:46:54 PM PDT 24
Peak memory 204560 kb
Host smart-9e12fd9b-4e60-48bd-9f4b-944162a8e3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90514
4987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.905144987
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2903169667
Short name T28
Test name
Test status
Simulation time 8371184043 ps
CPU time 7.76 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204556 kb
Host smart-3c78ec3f-86ad-4ec6-9a23-f7f6a2786599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031
69667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2903169667
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1409893138
Short name T614
Test name
Test status
Simulation time 54675355 ps
CPU time 0.68 seconds
Started May 09 02:46:40 PM PDT 24
Finished May 09 02:46:46 PM PDT 24
Peak memory 204512 kb
Host smart-537e120b-74f9-4b3a-a63c-c6ce250a3f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098
93138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1409893138
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2443375691
Short name T96
Test name
Test status
Simulation time 26517756422 ps
CPU time 53.63 seconds
Started May 09 02:46:38 PM PDT 24
Finished May 09 02:47:37 PM PDT 24
Peak memory 204840 kb
Host smart-05831d7e-3705-4f13-9d2f-2c08448ca123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24433
75691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2443375691
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3852612686
Short name T658
Test name
Test status
Simulation time 8401635419 ps
CPU time 7.69 seconds
Started May 09 02:46:38 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204592 kb
Host smart-c0f742f5-e119-468b-b92e-16e2745aa1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38526
12686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3852612686
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1656289539
Short name T966
Test name
Test status
Simulation time 8430630359 ps
CPU time 8.41 seconds
Started May 09 02:46:37 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204588 kb
Host smart-37a6350f-852e-4ac4-a3a2-e6f38ee953cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16562
89539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1656289539
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2261575761
Short name T968
Test name
Test status
Simulation time 8408452820 ps
CPU time 7.94 seconds
Started May 09 02:46:38 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 204560 kb
Host smart-3e5b9a6f-9c85-4bb0-a3f0-51f082acb57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615
75761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2261575761
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4109929200
Short name T998
Test name
Test status
Simulation time 8376750408 ps
CPU time 7.48 seconds
Started May 09 02:46:40 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204576 kb
Host smart-1390da47-02c4-4f9f-8692-c59a46fe0a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41099
29200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4109929200
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2851176183
Short name T465
Test name
Test status
Simulation time 8374414908 ps
CPU time 7.96 seconds
Started May 09 02:46:34 PM PDT 24
Finished May 09 02:46:48 PM PDT 24
Peak memory 204616 kb
Host smart-7b7581fd-de7b-4691-b26f-f4062582664f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
76183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2851176183
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3863446843
Short name T172
Test name
Test status
Simulation time 8472142484 ps
CPU time 9.76 seconds
Started May 09 02:46:36 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204572 kb
Host smart-b21ad3db-ddbd-4833-b91e-37f61872d75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
46843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3863446843
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3651765046
Short name T923
Test name
Test status
Simulation time 8382204125 ps
CPU time 7.59 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 204604 kb
Host smart-001ef468-cca7-4422-bd96-603ac3810449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36517
65046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3651765046
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.262203195
Short name T399
Test name
Test status
Simulation time 8415116041 ps
CPU time 9.85 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:54 PM PDT 24
Peak memory 204612 kb
Host smart-8c10e241-ad5b-4188-8d68-f0bfdbf5c48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
3195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.262203195
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.1172687266
Short name T1370
Test name
Test status
Simulation time 8539755110 ps
CPU time 10.77 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:06 PM PDT 24
Peak memory 204512 kb
Host smart-c948dc97-7f57-4cfa-ba89-6cc1991cfd13
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1172687266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.1172687266
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.944389825
Short name T909
Test name
Test status
Simulation time 8392791405 ps
CPU time 7.56 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204472 kb
Host smart-975b42fe-deef-4310-8f27-510a7f205f4e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=944389825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.944389825
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2128942567
Short name T682
Test name
Test status
Simulation time 8388758070 ps
CPU time 8.22 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:02 PM PDT 24
Peak memory 204468 kb
Host smart-9358011f-4933-4ccb-a752-22043613303d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21289
42567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2128942567
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.900404882
Short name T901
Test name
Test status
Simulation time 8380431548 ps
CPU time 7.99 seconds
Started May 09 02:46:46 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204616 kb
Host smart-1410a1c7-ca2d-4215-b87d-310b3a0894f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90040
4882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.900404882
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3862028024
Short name T82
Test name
Test status
Simulation time 9262592515 ps
CPU time 14.32 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 204816 kb
Host smart-f24aaf69-41d6-4ae8-809f-c8e128b7cad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
28024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3862028024
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_enable.3979441511
Short name T512
Test name
Test status
Simulation time 8376994639 ps
CPU time 7.93 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204584 kb
Host smart-4b544bdb-e892-41dc-8898-1262b42c86f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39794
41511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3979441511
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1428550788
Short name T556
Test name
Test status
Simulation time 132512099 ps
CPU time 1.54 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:46:55 PM PDT 24
Peak memory 204704 kb
Host smart-dbb84ce0-4fc0-4847-a248-827c6a8aee05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14285
50788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1428550788
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.53399945
Short name T1100
Test name
Test status
Simulation time 8432493776 ps
CPU time 7.66 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204568 kb
Host smart-fd07edcc-7e54-4e76-95c3-586a8e233e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53399
945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.53399945
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.4200222977
Short name T810
Test name
Test status
Simulation time 8382457420 ps
CPU time 8 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204604 kb
Host smart-d3834497-eace-45f9-af03-24f1efbc10a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42002
22977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.4200222977
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3914507467
Short name T749
Test name
Test status
Simulation time 8456717201 ps
CPU time 7.61 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:02 PM PDT 24
Peak memory 204580 kb
Host smart-84e23ba8-a7c1-494b-9c1e-2a98a63edc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39145
07467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3914507467
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2827783297
Short name T90
Test name
Test status
Simulation time 8421030909 ps
CPU time 7.98 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 204560 kb
Host smart-478d254c-8b5b-43db-af35-0aafd5408f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
83297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2827783297
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3015125019
Short name T1423
Test name
Test status
Simulation time 8431314517 ps
CPU time 9.87 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204544 kb
Host smart-27f6e6d0-8be2-400e-ba06-ee49012026a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30151
25019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3015125019
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3995317824
Short name T123
Test name
Test status
Simulation time 8437443469 ps
CPU time 9.72 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 204564 kb
Host smart-26f6b7e5-9a26-4754-98b9-2e893a820077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39953
17824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3995317824
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3788983174
Short name T889
Test name
Test status
Simulation time 8403149352 ps
CPU time 7.71 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204544 kb
Host smart-9e667b9d-1ca9-4422-b708-75b345b71828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
83174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3788983174
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.604576960
Short name T533
Test name
Test status
Simulation time 8408622404 ps
CPU time 8.65 seconds
Started May 09 02:46:52 PM PDT 24
Finished May 09 02:47:06 PM PDT 24
Peak memory 204592 kb
Host smart-d4644d7b-2b67-412b-9b7a-5484c6105c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60457
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.604576960
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1159186108
Short name T175
Test name
Test status
Simulation time 8437754307 ps
CPU time 8.01 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:00 PM PDT 24
Peak memory 204452 kb
Host smart-f6508e2e-1856-4d0b-a15a-d0986ede422f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11591
86108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1159186108
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4060155222
Short name T974
Test name
Test status
Simulation time 8370394030 ps
CPU time 7.6 seconds
Started May 09 02:46:47 PM PDT 24
Finished May 09 02:46:58 PM PDT 24
Peak memory 204508 kb
Host smart-9be0aa91-84f1-4c8c-bbd4-e4fc5cd6989d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601
55222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4060155222
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1870897862
Short name T48
Test name
Test status
Simulation time 39565258 ps
CPU time 0.67 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:46:56 PM PDT 24
Peak memory 204536 kb
Host smart-0acaac9a-3e24-420c-91c0-aaf2521c306d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
97862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1870897862
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2393657173
Short name T1116
Test name
Test status
Simulation time 25603946061 ps
CPU time 54 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:50 PM PDT 24
Peak memory 204784 kb
Host smart-204c919b-8114-4bb3-9da3-af9b28085a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23936
57173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2393657173
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1708855069
Short name T243
Test name
Test status
Simulation time 8430965274 ps
CPU time 8.47 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:05 PM PDT 24
Peak memory 204548 kb
Host smart-a148f6c1-cf42-4052-934b-fe82478e849f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088
55069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1708855069
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3795727093
Short name T158
Test name
Test status
Simulation time 8415185714 ps
CPU time 8.32 seconds
Started May 09 02:46:48 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 204556 kb
Host smart-1a0e6393-37eb-4695-88bb-5d69809dee5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
27093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3795727093
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2790834334
Short name T1359
Test name
Test status
Simulation time 8418306626 ps
CPU time 10.29 seconds
Started May 09 02:46:47 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 204512 kb
Host smart-941bcb1d-ee5f-45ab-8f0a-899873549654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
34334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2790834334
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3105461312
Short name T178
Test name
Test status
Simulation time 8395959000 ps
CPU time 8.27 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204592 kb
Host smart-eba5858b-bc1e-4e4f-89cf-de3af1e5ef56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31054
61312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3105461312
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1562616013
Short name T741
Test name
Test status
Simulation time 8363932933 ps
CPU time 8.48 seconds
Started May 09 02:46:49 PM PDT 24
Finished May 09 02:47:01 PM PDT 24
Peak memory 204624 kb
Host smart-8a55052b-d13e-4332-af2d-0c3a202d6d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
16013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1562616013
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2389839363
Short name T1424
Test name
Test status
Simulation time 8460064244 ps
CPU time 8.62 seconds
Started May 09 02:46:39 PM PDT 24
Finished May 09 02:46:53 PM PDT 24
Peak memory 204544 kb
Host smart-c7a1f3b9-ab6f-4a4f-b7a9-5f95af561fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
39363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2389839363
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1831629738
Short name T752
Test name
Test status
Simulation time 8436175781 ps
CPU time 8.23 seconds
Started May 09 02:46:51 PM PDT 24
Finished May 09 02:47:04 PM PDT 24
Peak memory 204568 kb
Host smart-eabf456e-9b6b-4d1b-91e1-b25ab2dd5350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18316
29738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1831629738
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.959875540
Short name T600
Test name
Test status
Simulation time 8390347965 ps
CPU time 8.24 seconds
Started May 09 02:46:50 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 204576 kb
Host smart-972132f6-65bf-48c6-8690-47d23250a90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95987
5540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.959875540
Directory /workspace/9.usbdev_stall_trans/latest
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