Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115714	1		T1	3		T2	2		T3	4
all_values[1]	115714	1		T1	3		T2	2		T3	4
all_values[2]	115714	1		T1	3		T2	2		T3	4
all_values[3]	115714	1		T1	3		T2	2		T3	4
all_values[4]	115714	1		T1	3		T2	2		T3	4
all_values[5]	115714	1		T1	3		T2	2		T3	4
all_values[6]	115714	1		T1	3		T2	2		T3	4
all_values[7]	115714	1		T1	3		T2	2		T3	4
all_values[8]	115714	1		T1	3		T2	2		T3	4
all_values[9]	115714	1		T1	3		T2	2		T3	4
all_values[10]	115714	1		T1	3		T2	2		T3	4
all_values[11]	115714	1		T1	3		T2	2		T3	4
all_values[12]	115714	1		T1	3		T2	2		T3	4
all_values[13]	115714	1		T1	3		T2	2		T3	4
all_values[14]	115714	1		T1	3		T2	2		T3	4
all_values[15]	115714	1		T1	3		T2	2		T3	4
all_values[16]	115714	1		T1	3		T2	2		T3	4
all_values[17]	115714	1		T1	3		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2078979	1		T1	54		T2	36		T3	72
auto[1]	3873	1		T22	4		T49	4		T17	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2078051	1		T1	54		T2	36		T3	72
auto[1]	4801	1		T71	120		T72	65		T73	66

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114726	1		T1	3		T2	2		T3	4
all_values[0]	auto[0]	auto[1]	134	1		T71	3		T72	2		T73	1
all_values[0]	auto[1]	auto[0]	731	1		T22	4		T49	4		T17	3
all_values[0]	auto[1]	auto[1]	123	1		T71	3		T72	3		T73	4
all_values[1]	auto[0]	auto[0]	115129	1		T1	3		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	133	1		T71	2		T74	4		T77	3
all_values[1]	auto[1]	auto[0]	324	1		T39	3		T42	3		T43	3
all_values[1]	auto[1]	auto[1]	128	1		T71	6		T77	1		T75	1
all_values[2]	auto[0]	auto[0]	115422	1		T1	3		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	136	1		T71	2		T72	4		T73	3
all_values[2]	auto[1]	auto[0]	19	1		T77	1		T309	1		T310	1
all_values[2]	auto[1]	auto[1]	137	1		T71	6		T72	1		T73	1
all_values[3]	auto[0]	auto[0]	115428	1		T1	3		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	143	1		T71	3		T72	1		T73	1
all_values[3]	auto[1]	auto[0]	21	1		T71	1		T76	1		T311	1
all_values[3]	auto[1]	auto[1]	122	1		T71	2		T72	4		T73	4
all_values[4]	auto[0]	auto[0]	115415	1		T1	3		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	128	1		T71	5		T73	1		T77	5
all_values[4]	auto[1]	auto[0]	20	1		T72	4		T76	4		T74	1
all_values[4]	auto[1]	auto[1]	151	1		T71	1		T73	4		T74	3
all_values[5]	auto[0]	auto[0]	115433	1		T1	3		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	125	1		T71	6		T72	4		T75	4
all_values[5]	auto[1]	auto[0]	23	1		T73	1		T74	2		T77	1
all_values[5]	auto[1]	auto[1]	133	1		T72	1		T76	5		T74	3
all_values[6]	auto[0]	auto[0]	115427	1		T1	3		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	135	1		T71	3		T73	4		T74	3
all_values[6]	auto[1]	auto[0]	27	1		T71	1		T73	1		T76	1
all_values[6]	auto[1]	auto[1]	125	1		T71	4		T72	3		T76	4
all_values[7]	auto[0]	auto[0]	115416	1		T1	3		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	153	1		T71	7		T76	3		T74	5
all_values[7]	auto[1]	auto[0]	13	1		T72	1		T73	1		T312	1
all_values[7]	auto[1]	auto[1]	132	1		T71	1		T72	3		T73	4
all_values[8]	auto[0]	auto[0]	115424	1		T1	3		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	137	1		T71	6		T72	3		T73	2
all_values[8]	auto[1]	auto[0]	18	1		T76	1		T311	1		T307	1
all_values[8]	auto[1]	auto[1]	135	1		T71	1		T72	1		T73	3
all_values[9]	auto[0]	auto[0]	115419	1		T1	3		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	150	1		T71	1		T76	3		T74	1
all_values[9]	auto[1]	auto[0]	19	1		T72	1		T76	2		T313	2
all_values[9]	auto[1]	auto[1]	126	1		T71	4		T72	3		T73	5
all_values[10]	auto[0]	auto[0]	115420	1		T1	3		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	117	1		T71	5		T74	3		T75	5
all_values[10]	auto[1]	auto[0]	30	1		T71	1		T73	1		T76	1
all_values[10]	auto[1]	auto[1]	147	1		T71	1		T72	5		T73	4
all_values[11]	auto[0]	auto[0]	115422	1		T1	3		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	111	1		T71	5		T76	4		T74	4
all_values[11]	auto[1]	auto[0]	31	1		T71	1		T72	1		T77	4
all_values[11]	auto[1]	auto[1]	150	1		T71	2		T72	4		T73	5
all_values[12]	auto[0]	auto[0]	115419	1		T1	3		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	121	1		T71	5		T76	1		T74	4
all_values[12]	auto[1]	auto[0]	26	1		T72	2		T73	2		T75	2
all_values[12]	auto[1]	auto[1]	148	1		T71	1		T72	3		T76	4
all_values[13]	auto[0]	auto[0]	115432	1		T1	3		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	126	1		T71	5		T72	3		T73	3
all_values[13]	auto[1]	auto[0]	31	1		T72	2		T73	1		T311	2
all_values[13]	auto[1]	auto[1]	125	1		T71	3		T76	4		T75	1
all_values[14]	auto[0]	auto[0]	115423	1		T1	3		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	130	1		T71	2		T73	4		T77	2
all_values[14]	auto[1]	auto[0]	33	1		T72	1		T76	1		T74	4
all_values[14]	auto[1]	auto[1]	128	1		T71	4		T72	3		T73	1
all_values[15]	auto[0]	auto[0]	115422	1		T1	3		T2	2		T3	4
all_values[15]	auto[0]	auto[1]	127	1		T71	3		T72	1		T73	1
all_values[15]	auto[1]	auto[0]	30	1		T71	1		T72	1		T73	1
all_values[15]	auto[1]	auto[1]	135	1		T71	4		T72	3		T73	3
all_values[16]	auto[0]	auto[0]	115419	1		T1	3		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	129	1		T71	5		T72	1		T73	4
all_values[16]	auto[1]	auto[0]	24	1		T71	1		T76	1		T309	2
all_values[16]	auto[1]	auto[1]	142	1		T71	1		T72	4		T76	3
all_values[17]	auto[0]	auto[0]	115418	1		T1	3		T2	2		T3	4
all_values[17]	auto[0]	auto[1]	130	1		T71	2		T73	4		T74	5
all_values[17]	auto[1]	auto[0]	17	1		T76	1		T313	1		T314	2
all_values[17]	auto[1]	auto[1]	149	1		T71	6		T72	5		T76	4