Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	115714	1		T1	3		T2	2		T3	4
all_pins[1]	115714	1		T1	3		T2	2		T3	4
all_pins[2]	115714	1		T1	3		T2	2		T3	4
all_pins[3]	115714	1		T1	3		T2	2		T3	4
all_pins[4]	115714	1		T1	3		T2	2		T3	4
all_pins[5]	115714	1		T1	3		T2	2		T3	4
all_pins[6]	115714	1		T1	3		T2	2		T3	4
all_pins[7]	115714	1		T1	3		T2	2		T3	4
all_pins[8]	115714	1		T1	3		T2	2		T3	4
all_pins[9]	115714	1		T1	3		T2	2		T3	4
all_pins[10]	115714	1		T1	3		T2	2		T3	4
all_pins[11]	115714	1		T1	3		T2	2		T3	4
all_pins[12]	115714	1		T1	3		T2	2		T3	4
all_pins[13]	115714	1		T1	3		T2	2		T3	4
all_pins[14]	115714	1		T1	3		T2	2		T3	4
all_pins[15]	115714	1		T1	3		T2	2		T3	4
all_pins[16]	115714	1		T1	3		T2	2		T3	4
all_pins[17]	115714	1		T1	3		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2081495	1		T1	54		T2	36		T3	72
values[0x1]	1357	1		T22	1		T49	1		T39	1
transitions[0x0=>0x1]	1042	1		T22	1		T49	1		T39	1
transitions[0x1=>0x0]	1058	1		T22	1		T49	1		T39	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115565	1		T1	3		T2	2		T3	4
all_pins[0]	values[0x1]	149	1		T22	1		T49	1		T50	1
all_pins[0]	transitions[0x0=>0x1]	135	1		T22	1		T49	1		T50	1
all_pins[0]	transitions[0x1=>0x0]	136	1		T39	1		T42	1		T43	1
all_pins[1]	values[0x0]	115564	1		T1	3		T2	2		T3	4
all_pins[1]	values[0x1]	150	1		T39	1		T42	1		T43	1
all_pins[1]	transitions[0x0=>0x1]	139	1		T39	1		T42	1		T43	1
all_pins[1]	transitions[0x1=>0x0]	61	1		T71	3		T72	1		T73	1
all_pins[2]	values[0x0]	115642	1		T1	3		T2	2		T3	4
all_pins[2]	values[0x1]	72	1		T71	5		T72	1		T73	1
all_pins[2]	transitions[0x0=>0x1]	57	1		T71	3		T72	1		T76	1
all_pins[2]	transitions[0x1=>0x0]	54	1		T72	3		T73	2		T74	2
all_pins[3]	values[0x0]	115645	1		T1	3		T2	2		T3	4
all_pins[3]	values[0x1]	69	1		T71	2		T72	3		T73	3
all_pins[3]	transitions[0x0=>0x1]	40	1		T71	2		T72	3		T74	2
all_pins[3]	transitions[0x1=>0x0]	44	1		T309	1		T312	2		T315	1
all_pins[4]	values[0x0]	115641	1		T1	3		T2	2		T3	4
all_pins[4]	values[0x1]	73	1		T73	3		T309	3		T307	1
all_pins[4]	transitions[0x0=>0x1]	51	1		T73	3		T309	1		T307	1
all_pins[4]	transitions[0x1=>0x0]	43	1		T76	4		T77	1		T75	1
all_pins[5]	values[0x0]	115649	1		T1	3		T2	2		T3	4
all_pins[5]	values[0x1]	65	1		T76	4		T77	1		T75	1
all_pins[5]	transitions[0x0=>0x1]	54	1		T76	1		T77	1		T75	1
all_pins[5]	transitions[0x1=>0x0]	41	1		T71	1		T72	2		T75	3
all_pins[6]	values[0x0]	115662	1		T1	3		T2	2		T3	4
all_pins[6]	values[0x1]	52	1		T71	1		T72	2		T76	3
all_pins[6]	transitions[0x0=>0x1]	42	1		T71	1		T72	1		T76	3
all_pins[6]	transitions[0x1=>0x0]	41	1		T73	2		T76	1		T75	2
all_pins[7]	values[0x0]	115663	1		T1	3		T2	2		T3	4
all_pins[7]	values[0x1]	51	1		T72	1		T73	2		T76	1
all_pins[7]	transitions[0x0=>0x1]	34	1		T72	1		T73	2		T76	1
all_pins[7]	transitions[0x1=>0x0]	41	1		T71	1		T72	1		T77	1
all_pins[8]	values[0x0]	115656	1		T1	3		T2	2		T3	4
all_pins[8]	values[0x1]	58	1		T71	1		T72	1		T77	1
all_pins[8]	transitions[0x0=>0x1]	44	1		T72	1		T77	1		T310	1
all_pins[8]	transitions[0x1=>0x0]	51	1		T71	2		T72	2		T73	2
all_pins[9]	values[0x0]	115649	1		T1	3		T2	2		T3	4
all_pins[9]	values[0x1]	65	1		T71	3		T72	2		T73	2
all_pins[9]	transitions[0x0=>0x1]	45	1		T71	3		T73	1		T74	2
all_pins[9]	transitions[0x1=>0x0]	62	1		T71	1		T72	1		T73	2
all_pins[10]	values[0x0]	115632	1		T1	3		T2	2		T3	4
all_pins[10]	values[0x1]	82	1		T71	1		T72	3		T73	3
all_pins[10]	transitions[0x0=>0x1]	51	1		T72	1		T73	2		T74	1
all_pins[10]	transitions[0x1=>0x0]	42	1		T71	1		T72	1		T73	1
all_pins[11]	values[0x0]	115641	1		T1	3		T2	2		T3	4
all_pins[11]	values[0x1]	73	1		T71	2		T72	3		T73	2
all_pins[11]	transitions[0x0=>0x1]	51	1		T71	1		T72	1		T73	2
all_pins[11]	transitions[0x1=>0x0]	60	1		T76	3		T75	1		T307	1
all_pins[12]	values[0x0]	115632	1		T1	3		T2	2		T3	4
all_pins[12]	values[0x1]	82	1		T71	1		T72	2		T76	3
all_pins[12]	transitions[0x0=>0x1]	66	1		T71	1		T72	2		T76	3
all_pins[12]	transitions[0x1=>0x0]	44	1		T71	2		T76	1		T311	2
all_pins[13]	values[0x0]	115654	1		T1	3		T2	2		T3	4
all_pins[13]	values[0x1]	60	1		T71	2		T76	1		T311	2
all_pins[13]	transitions[0x0=>0x1]	47	1		T71	2		T76	1		T310	2
all_pins[13]	transitions[0x1=>0x0]	45	1		T71	1		T72	2		T73	1
all_pins[14]	values[0x0]	115656	1		T1	3		T2	2		T3	4
all_pins[14]	values[0x1]	58	1		T71	1		T72	2		T73	1
all_pins[14]	transitions[0x0=>0x1]	43	1		T71	1		T73	1		T75	2
all_pins[14]	transitions[0x1=>0x0]	47	1		T71	1		T76	2		T74	2
all_pins[15]	values[0x0]	115652	1		T1	3		T2	2		T3	4
all_pins[15]	values[0x1]	62	1		T71	1		T72	2		T76	2
all_pins[15]	transitions[0x0=>0x1]	46	1		T71	1		T76	2		T74	2
all_pins[15]	transitions[0x1=>0x0]	59	1		T71	1		T72	1		T74	1
all_pins[16]	values[0x0]	115639	1		T1	3		T2	2		T3	4
all_pins[16]	values[0x1]	75	1		T71	1		T72	3		T74	1
all_pins[16]	transitions[0x0=>0x1]	58	1		T71	1		T72	1		T74	1
all_pins[16]	transitions[0x1=>0x0]	44	1		T71	2		T72	1		T76	1
all_pins[17]	values[0x0]	115653	1		T1	3		T2	2		T3	4
all_pins[17]	values[0x1]	61	1		T71	2		T72	3		T76	1
all_pins[17]	transitions[0x0=>0x1]	39	1		T71	1		T72	2		T76	1
all_pins[17]	transitions[0x1=>0x0]	143	1		T22	1		T49	1		T50	1