Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.18 96.70 89.94 97.32 51.56 94.63 97.56 96.58


Total test records in report: 1530
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T317 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1271036050 May 12 12:45:24 PM PDT 24 May 12 12:45:26 PM PDT 24 41620921 ps
T1504 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.782977641 May 12 12:45:06 PM PDT 24 May 12 12:45:08 PM PDT 24 112134740 ps
T1505 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3733899365 May 12 12:45:28 PM PDT 24 May 12 12:45:31 PM PDT 24 165569980 ps
T1506 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1646438002 May 12 12:45:21 PM PDT 24 May 12 12:45:24 PM PDT 24 189968937 ps
T1507 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2103432240 May 12 12:44:48 PM PDT 24 May 12 12:44:51 PM PDT 24 98129998 ps
T1508 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4056284794 May 12 12:44:51 PM PDT 24 May 12 12:44:54 PM PDT 24 122475618 ps
T261 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1693670316 May 12 12:45:39 PM PDT 24 May 12 12:45:42 PM PDT 24 433617276 ps
T1509 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3224293081 May 12 12:45:11 PM PDT 24 May 12 12:45:13 PM PDT 24 37836061 ps
T1510 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.147826538 May 12 12:45:23 PM PDT 24 May 12 12:45:25 PM PDT 24 78449116 ps
T1511 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4267239329 May 12 12:45:27 PM PDT 24 May 12 12:45:28 PM PDT 24 30415957 ps
T1512 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.904399637 May 12 12:45:12 PM PDT 24 May 12 12:45:14 PM PDT 24 54593153 ps
T1513 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1152422946 May 12 12:44:50 PM PDT 24 May 12 12:44:53 PM PDT 24 138990072 ps
T1514 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.339690726 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 67596119 ps
T1515 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1772823244 May 12 12:45:28 PM PDT 24 May 12 12:45:30 PM PDT 24 34320566 ps
T1516 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4218131407 May 12 12:44:59 PM PDT 24 May 12 12:45:03 PM PDT 24 277290923 ps
T1517 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1483675478 May 12 12:44:58 PM PDT 24 May 12 12:45:07 PM PDT 24 1437723318 ps
T1518 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.536203 May 12 12:45:33 PM PDT 24 May 12 12:45:35 PM PDT 24 126835923 ps
T1519 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1386807312 May 12 12:45:22 PM PDT 24 May 12 12:45:24 PM PDT 24 25296410 ps
T1520 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1255448356 May 12 12:45:05 PM PDT 24 May 12 12:45:07 PM PDT 24 97961391 ps
T328 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3957770564 May 12 12:44:57 PM PDT 24 May 12 12:45:01 PM PDT 24 512314581 ps
T1521 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2364750555 May 12 12:45:22 PM PDT 24 May 12 12:45:26 PM PDT 24 238206194 ps
T1522 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3159783675 May 12 12:45:33 PM PDT 24 May 12 12:45:35 PM PDT 24 26863871 ps
T1523 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.417555515 May 12 12:45:55 PM PDT 24 May 12 12:45:59 PM PDT 24 365165758 ps
T1524 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3076523347 May 12 12:44:57 PM PDT 24 May 12 12:44:59 PM PDT 24 69729369 ps
T1525 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1553065994 May 12 12:45:14 PM PDT 24 May 12 12:45:15 PM PDT 24 43951862 ps
T1526 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2977561385 May 12 12:45:19 PM PDT 24 May 12 12:45:21 PM PDT 24 59861120 ps
T1527 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.782966336 May 12 12:45:21 PM PDT 24 May 12 12:45:24 PM PDT 24 165482116 ps
T1528 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.327147189 May 12 12:45:23 PM PDT 24 May 12 12:45:24 PM PDT 24 31980875 ps
T1529 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.669585661 May 12 12:45:26 PM PDT 24 May 12 12:45:29 PM PDT 24 113748983 ps
T1530 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4026515691 May 12 12:45:37 PM PDT 24 May 12 12:45:38 PM PDT 24 33419804 ps

Test location /workspace/coverage/default/31.min_length_in_transaction.1260216952
Short name T21
Test name
Test status
Simulation time 8378535775 ps
CPU time 7.87 seconds
Started May 12 12:56:40 PM PDT 24
Finished May 12 12:56:48 PM PDT 24
Peak memory 204316 kb
Host smart-17b6bfff-c36c-40eb-b402-778583f6a62e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1260216952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.1260216952
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2749593778
Short name T33
Test name
Test status
Simulation time 9098955592 ps
CPU time 12.15 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:59 PM PDT 24
Peak memory 204536 kb
Host smart-874a5aab-da04-432b-8a5a-024a4a8fd317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27495
93778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2749593778
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1613508604
Short name T71
Test name
Test status
Simulation time 46591816 ps
CPU time 0.7 seconds
Started May 12 12:45:32 PM PDT 24
Finished May 12 12:45:33 PM PDT 24
Peak memory 203032 kb
Host smart-40aafe41-f8d9-486a-93d0-63e16c47cdb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1613508604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1613508604
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2203749538
Short name T56
Test name
Test status
Simulation time 77537629 ps
CPU time 1.54 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204492 kb
Host smart-6cdabc4a-d9bf-413c-9d0a-443afae8c130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037
49538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2203749538
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2776400810
Short name T59
Test name
Test status
Simulation time 158490813 ps
CPU time 1.75 seconds
Started May 12 12:45:13 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 212128 kb
Host smart-a7d90fb7-d205-4179-b405-901aadf11e09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776400810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2776400810
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3061636329
Short name T28
Test name
Test status
Simulation time 8414249265 ps
CPU time 7.81 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204396 kb
Host smart-1b6f3209-8f3d-4c18-856e-9868cd612393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
36329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3061636329
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.359312983
Short name T3
Test name
Test status
Simulation time 8413719842 ps
CPU time 7.75 seconds
Started May 12 12:56:48 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204472 kb
Host smart-34819e4f-bbd6-45b1-b408-5f61b29e5758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
2983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.359312983
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3035669444
Short name T52
Test name
Test status
Simulation time 8403385102 ps
CPU time 8.75 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204472 kb
Host smart-d2c0f58f-8792-45ed-a73e-ba6dd2a9b0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356
69444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3035669444
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3672543762
Short name T314
Test name
Test status
Simulation time 32877078 ps
CPU time 0.66 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 202940 kb
Host smart-692b6c7d-9837-4c07-baa9-86d2508e4dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3672543762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3672543762
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.777973261
Short name T229
Test name
Test status
Simulation time 8394325089 ps
CPU time 7.99 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 204336 kb
Host smart-4fde5a15-1b07-48db-a625-808f8f4c00c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77797
3261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.777973261
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1017061707
Short name T36
Test name
Test status
Simulation time 38881952 ps
CPU time 0.7 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204364 kb
Host smart-e40c8eed-f632-4638-b16f-031d64c2f296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170
61707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1017061707
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3267361895
Short name T10
Test name
Test status
Simulation time 8373313557 ps
CPU time 7.72 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204504 kb
Host smart-b64d5c1c-6613-4fc9-a164-2cb126e379a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673
61895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3267361895
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3477399438
Short name T123
Test name
Test status
Simulation time 8459212848 ps
CPU time 7.66 seconds
Started May 12 12:54:52 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204400 kb
Host smart-74b3a612-ba2d-44bf-b797-c352ab066f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
99438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3477399438
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.876172396
Short name T60
Test name
Test status
Simulation time 363721731 ps
CPU time 3.88 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:08 PM PDT 24
Peak memory 203860 kb
Host smart-c3469418-f478-47e5-8eaa-af2a6ba79d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=876172396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.876172396
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3608821193
Short name T12
Test name
Test status
Simulation time 17971201129 ps
CPU time 32.38 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:56 PM PDT 24
Peak memory 204696 kb
Host smart-ac75b44c-e546-4680-b498-e664d5a7302c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
21193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3608821193
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1370105801
Short name T4
Test name
Test status
Simulation time 92910755 ps
CPU time 0.93 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203524 kb
Host smart-081b4058-4afd-41f2-95a3-6ba5f62e88bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1370105801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1370105801
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3283860664
Short name T312
Test name
Test status
Simulation time 42965506 ps
CPU time 0.7 seconds
Started May 12 12:45:20 PM PDT 24
Finished May 12 12:45:22 PM PDT 24
Peak memory 203028 kb
Host smart-95ea3aa1-0d8f-4964-9ba4-6703351499eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3283860664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3283860664
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3143095472
Short name T78
Test name
Test status
Simulation time 150106990 ps
CPU time 0.98 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:28 PM PDT 24
Peak memory 220988 kb
Host smart-44d5b21c-bbfa-40be-9161-d95e66c5803e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3143095472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3143095472
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2820275838
Short name T42
Test name
Test status
Simulation time 8437100254 ps
CPU time 7.9 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204372 kb
Host smart-1926c703-ce7e-4994-8424-fd7e19077851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28202
75838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2820275838
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2640607184
Short name T277
Test name
Test status
Simulation time 44792201 ps
CPU time 0.94 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203620 kb
Host smart-f3de387b-8b9d-413f-a9d9-d682aba51c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2640607184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2640607184
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3823211323
Short name T76
Test name
Test status
Simulation time 42188077 ps
CPU time 0.62 seconds
Started May 12 12:45:06 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 202980 kb
Host smart-aebff3e6-b661-440e-a082-60b17a6d4b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3823211323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3823211323
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4220885662
Short name T259
Test name
Test status
Simulation time 245747963 ps
CPU time 3 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:26 PM PDT 24
Peak memory 203756 kb
Host smart-d044c788-ed7e-4dc2-bfcc-c7075e81e123
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4220885662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4220885662
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2433115670
Short name T325
Test name
Test status
Simulation time 1097418376 ps
CPU time 4.72 seconds
Started May 12 12:45:13 PM PDT 24
Finished May 12 12:45:18 PM PDT 24
Peak memory 203876 kb
Host smart-2a243728-78d4-425b-b204-d0eb59faa186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2433115670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2433115670
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/10.usbdev_enable.2590561034
Short name T49
Test name
Test status
Simulation time 8375289239 ps
CPU time 9.15 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 203724 kb
Host smart-3097eb2b-6e3a-45f3-8bcc-350c39e0d185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25905
61034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2590561034
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3187727858
Short name T265
Test name
Test status
Simulation time 273144314 ps
CPU time 2.39 seconds
Started May 12 12:45:09 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 203852 kb
Host smart-e7832782-7d36-482e-811f-71940552c4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3187727858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3187727858
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.783165251
Short name T75
Test name
Test status
Simulation time 32187916 ps
CPU time 0.65 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 202780 kb
Host smart-135023a2-c7da-47d8-9b13-44c2f858936f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=783165251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.783165251
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2355076757
Short name T11
Test name
Test status
Simulation time 5110172517 ps
CPU time 136.42 seconds
Started May 12 12:54:20 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204636 kb
Host smart-4beb4a6f-4d4e-420e-a330-4fb32342c789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550
76757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2355076757
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2172080103
Short name T276
Test name
Test status
Simulation time 21076049962 ps
CPU time 39.57 seconds
Started May 12 12:56:10 PM PDT 24
Finished May 12 12:56:50 PM PDT 24
Peak memory 204524 kb
Host smart-9e74de5d-2c45-4525-b8a0-3dae1bdaf244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21720
80103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2172080103
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2743621698
Short name T65
Test name
Test status
Simulation time 61645680 ps
CPU time 0.8 seconds
Started May 12 12:45:08 PM PDT 24
Finished May 12 12:45:09 PM PDT 24
Peak memory 203556 kb
Host smart-c630a7d3-4dd3-4e7f-b17d-984876d49d78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2743621698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2743621698
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1292572513
Short name T321
Test name
Test status
Simulation time 536571967 ps
CPU time 4.39 seconds
Started May 12 12:45:35 PM PDT 24
Finished May 12 12:45:40 PM PDT 24
Peak memory 204004 kb
Host smart-2757df82-1ab1-48a7-be81-00b80db59aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1292572513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1292572513
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3560036568
Short name T202
Test name
Test status
Simulation time 9481102705 ps
CPU time 12.82 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204636 kb
Host smart-9a68be29-3389-4d3f-9ae8-240595e5a986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600
36568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3560036568
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.1861179239
Short name T19
Test name
Test status
Simulation time 8467391604 ps
CPU time 9.02 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204420 kb
Host smart-bff87555-4094-4ecc-83aa-3dcf996707c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1861179239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.1861179239
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2581222074
Short name T256
Test name
Test status
Simulation time 282916630 ps
CPU time 2.81 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 203800 kb
Host smart-fa87dc9e-c23e-49bd-a14c-99788961161c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2581222074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2581222074
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.830351642
Short name T1307
Test name
Test status
Simulation time 9424250784 ps
CPU time 15.97 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204716 kb
Host smart-891d87bc-31a7-4d39-b45b-40b7e8f72c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83035
1642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.830351642
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.54652570
Short name T199
Test name
Test status
Simulation time 8376616659 ps
CPU time 8.58 seconds
Started May 12 12:54:39 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 204464 kb
Host smart-c88c94b7-dc9f-48a6-a628-4508a17f4aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54652
570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.54652570
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4294791968
Short name T186
Test name
Test status
Simulation time 8385881897 ps
CPU time 7.62 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 204456 kb
Host smart-cbe970e8-6dfa-492b-b372-8f21fb8499df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42947
91968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4294791968
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.4027900675
Short name T182
Test name
Test status
Simulation time 8395812388 ps
CPU time 7.87 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204380 kb
Host smart-6ad43990-5d68-4e26-ba0b-fba601e4ac3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
00675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.4027900675
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1758258746
Short name T189
Test name
Test status
Simulation time 8470048442 ps
CPU time 9.89 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204532 kb
Host smart-b24233bb-c6ee-4caa-a4c6-88ce98b946a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17582
58746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1758258746
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2155052586
Short name T184
Test name
Test status
Simulation time 8409937093 ps
CPU time 8.02 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:35 PM PDT 24
Peak memory 204216 kb
Host smart-cc1dc677-cc4a-4b75-9002-965d4c180932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21550
52586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2155052586
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_smoke.773343796
Short name T943
Test name
Test status
Simulation time 8418787564 ps
CPU time 7.91 seconds
Started May 12 12:55:36 PM PDT 24
Finished May 12 12:55:45 PM PDT 24
Peak memory 204552 kb
Host smart-a1145fba-6010-4601-8421-91c28ef0ac71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77334
3796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.773343796
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.99065464
Short name T216
Test name
Test status
Simulation time 8415390995 ps
CPU time 7.48 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:46 PM PDT 24
Peak memory 204748 kb
Host smart-0e789e8c-9d5a-41fe-82f5-a2c9d07b8662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99065
464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.99065464
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1882462593
Short name T145
Test name
Test status
Simulation time 8418074443 ps
CPU time 7.6 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:35 PM PDT 24
Peak memory 204396 kb
Host smart-3d06cee7-dd46-4fdd-a657-d108f1547945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
62593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1882462593
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4194779977
Short name T905
Test name
Test status
Simulation time 8408204694 ps
CPU time 7.77 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204336 kb
Host smart-3dc0ce50-886b-4f5c-8e07-2534e677370f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41947
79977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4194779977
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3897732143
Short name T213
Test name
Test status
Simulation time 8402700945 ps
CPU time 7.61 seconds
Started May 12 12:56:14 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204408 kb
Host smart-ba48a088-b120-4d30-b94f-8bcd7a8ac06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38977
32143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3897732143
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.745763005
Short name T44
Test name
Test status
Simulation time 37267726 ps
CPU time 0.64 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204328 kb
Host smart-08ebe648-d134-4d47-b66c-ef806acb9184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74576
3005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.745763005
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2026240561
Short name T1404
Test name
Test status
Simulation time 9221661513 ps
CPU time 12.61 seconds
Started May 12 12:57:00 PM PDT 24
Finished May 12 12:57:13 PM PDT 24
Peak memory 204676 kb
Host smart-37489961-4965-457f-9f8c-cd94a03e0928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
40561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2026240561
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2262309449
Short name T335
Test name
Test status
Simulation time 8406542488 ps
CPU time 7.39 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204400 kb
Host smart-cee78f98-bd1c-47c9-80fe-af8d0aee6876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
09449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2262309449
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.464451423
Short name T339
Test name
Test status
Simulation time 8369455918 ps
CPU time 9.98 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 204448 kb
Host smart-b3cdec87-d9e2-4180-826e-2c243b9ed451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46445
1423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.464451423
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.283184623
Short name T204
Test name
Test status
Simulation time 9617053723 ps
CPU time 12.75 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 204600 kb
Host smart-1ba07132-ae97-4ab3-99a8-5641c2e25870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.283184623
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2613929141
Short name T263
Test name
Test status
Simulation time 679008324 ps
CPU time 2.98 seconds
Started May 12 12:45:26 PM PDT 24
Finished May 12 12:45:30 PM PDT 24
Peak memory 203900 kb
Host smart-d2b0da33-0584-49bd-8f1a-234a622b09bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2613929141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2613929141
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1693670316
Short name T261
Test name
Test status
Simulation time 433617276 ps
CPU time 2.74 seconds
Started May 12 12:45:39 PM PDT 24
Finished May 12 12:45:42 PM PDT 24
Peak memory 203908 kb
Host smart-fdef5074-f49c-46c9-a09c-a80d96264276
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1693670316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1693670316
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3027312701
Short name T237
Test name
Test status
Simulation time 83948374 ps
CPU time 0.9 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:02 PM PDT 24
Peak memory 203792 kb
Host smart-3a547d8b-7e2f-466f-849c-253aa7562a7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3027312701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3027312701
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1796525659
Short name T454
Test name
Test status
Simulation time 8434009517 ps
CPU time 7.56 seconds
Started May 12 12:54:28 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 204488 kb
Host smart-2113254c-f164-422c-8cfb-42f02a0cae62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965
25659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1796525659
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2949189988
Short name T911
Test name
Test status
Simulation time 8427108896 ps
CPU time 8.26 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204324 kb
Host smart-a9de42ee-b520-4c7a-b43b-a60806a56a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
89988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2949189988
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3366507656
Short name T1100
Test name
Test status
Simulation time 8364079809 ps
CPU time 9.89 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 204488 kb
Host smart-f2926d35-30bf-4852-983a-d8a0a7a864f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33665
07656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3366507656
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2055286396
Short name T140
Test name
Test status
Simulation time 8471417845 ps
CPU time 7.98 seconds
Started May 12 12:54:28 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 204384 kb
Host smart-c4f241c8-a92a-4641-ace6-cae0667c8465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20552
86396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2055286396
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1099266027
Short name T152
Test name
Test status
Simulation time 8468686400 ps
CPU time 7.76 seconds
Started May 12 12:55:08 PM PDT 24
Finished May 12 12:55:16 PM PDT 24
Peak memory 204408 kb
Host smart-c13055d4-a53d-478b-830c-5c94f2342796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10992
66027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1099266027
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1948568930
Short name T1391
Test name
Test status
Simulation time 8473421569 ps
CPU time 9.26 seconds
Started May 12 12:55:10 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204420 kb
Host smart-747a03bb-b8e0-4e18-8436-7e2ecfaa41ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19485
68930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1948568930
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3624708037
Short name T903
Test name
Test status
Simulation time 8425034351 ps
CPU time 7.7 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:19 PM PDT 24
Peak memory 204340 kb
Host smart-7835da38-f567-4da0-958f-7dcfef305840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36247
08037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3624708037
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2516445277
Short name T122
Test name
Test status
Simulation time 8461197320 ps
CPU time 8.2 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204428 kb
Host smart-10927a5c-2d50-4852-98e7-b8104c0ad1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25164
45277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2516445277
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4087360069
Short name T1331
Test name
Test status
Simulation time 25876891779 ps
CPU time 53.25 seconds
Started May 12 12:55:15 PM PDT 24
Finished May 12 12:56:08 PM PDT 24
Peak memory 204628 kb
Host smart-6e85246e-fbad-44c9-88ae-d3900e82e79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873
60069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4087360069
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3374160777
Short name T227
Test name
Test status
Simulation time 8380133536 ps
CPU time 8.28 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204420 kb
Host smart-005c8a4e-f5b6-4d1a-9182-6ecff3a1cb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33741
60777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3374160777
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2390300532
Short name T129
Test name
Test status
Simulation time 8435365837 ps
CPU time 7.91 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 204340 kb
Host smart-51403eef-1d3e-45a6-9c6f-d75f912186e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23903
00532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2390300532
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3356144680
Short name T1060
Test name
Test status
Simulation time 8429074035 ps
CPU time 8.15 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 204456 kb
Host smart-896fbd55-00d7-4f2d-bf80-dd404923c8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33561
44680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3356144680
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2517113358
Short name T1008
Test name
Test status
Simulation time 8431452283 ps
CPU time 9.79 seconds
Started May 12 12:55:35 PM PDT 24
Finished May 12 12:55:46 PM PDT 24
Peak memory 204400 kb
Host smart-b509d37c-e60c-4f1e-a081-14e06648e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171
13358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2517113358
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3452853698
Short name T1173
Test name
Test status
Simulation time 8411096244 ps
CPU time 7.64 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204428 kb
Host smart-c02a85a8-e39c-4e69-8429-ac97fb044a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34528
53698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3452853698
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1892535111
Short name T915
Test name
Test status
Simulation time 8409527668 ps
CPU time 10.22 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204416 kb
Host smart-b8dca22b-9581-4b0b-b7c3-82ca80a47819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925
35111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1892535111
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2382777882
Short name T5
Test name
Test status
Simulation time 8392030662 ps
CPU time 7.33 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204420 kb
Host smart-198e773e-02d6-4040-a1c8-4955111be261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23827
77882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2382777882
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2025206939
Short name T503
Test name
Test status
Simulation time 8405065029 ps
CPU time 7.51 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204420 kb
Host smart-329a846f-6dad-415f-b417-9f8420bdf467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252
06939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2025206939
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2438722200
Short name T1093
Test name
Test status
Simulation time 8399370021 ps
CPU time 8.55 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204460 kb
Host smart-e3e2f000-fd84-45fa-9811-60fb77642474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387
22200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2438722200
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2560489661
Short name T112
Test name
Test status
Simulation time 8412390326 ps
CPU time 9.38 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 204376 kb
Host smart-684074c8-4f93-450c-b6e5-c9cc497027c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25604
89661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2560489661
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1715530849
Short name T1354
Test name
Test status
Simulation time 8446394181 ps
CPU time 8.96 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204384 kb
Host smart-8da0dca6-9643-4485-8e09-3e8c0b751c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17155
30849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1715530849
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1839546714
Short name T110
Test name
Test status
Simulation time 8432347810 ps
CPU time 7.7 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204480 kb
Host smart-d9bb2237-364c-4e7d-8565-33d2e2838a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18395
46714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1839546714
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2160879246
Short name T1494
Test name
Test status
Simulation time 294233222 ps
CPU time 3.61 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:16 PM PDT 24
Peak memory 203832 kb
Host smart-124285ca-a10d-4c1b-9c5e-8a58151330eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2160879246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2160879246
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1483675478
Short name T1517
Test name
Test status
Simulation time 1437723318 ps
CPU time 8.11 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 203688 kb
Host smart-9230f99c-ba2a-4f93-b8be-73e3cba356cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1483675478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1483675478
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.339690726
Short name T1514
Test name
Test status
Simulation time 67596119 ps
CPU time 0.95 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 201912 kb
Host smart-a4a79611-a7e0-4e58-8d72-354d004727f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=339690726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.339690726
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3990100431
Short name T1493
Test name
Test status
Simulation time 53235538 ps
CPU time 1.29 seconds
Started May 12 12:45:05 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 212028 kb
Host smart-263c608e-e141-4e30-b807-66f0813850a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990100431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3990100431
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3249993616
Short name T285
Test name
Test status
Simulation time 70496568 ps
CPU time 0.97 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 203724 kb
Host smart-821d7607-3abf-428d-b3f9-b5a74f9ba6a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3249993616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3249993616
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3883946238
Short name T1501
Test name
Test status
Simulation time 34142964 ps
CPU time 0.63 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 202980 kb
Host smart-64ddcf24-9a18-481a-b054-5c85d1ec89a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3883946238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3883946238
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4081532380
Short name T280
Test name
Test status
Simulation time 198409744 ps
CPU time 2.4 seconds
Started May 12 12:45:20 PM PDT 24
Finished May 12 12:45:28 PM PDT 24
Peak memory 211988 kb
Host smart-604a0b63-9b2c-4e7c-a807-604a4940d09d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4081532380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4081532380
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3005612661
Short name T1449
Test name
Test status
Simulation time 162506485 ps
CPU time 3.77 seconds
Started May 12 12:45:08 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 203688 kb
Host smart-764b9019-27ab-468c-9ae5-7159bf00ed31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3005612661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3005612661
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.863115118
Short name T293
Test name
Test status
Simulation time 85305064 ps
CPU time 1.13 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203664 kb
Host smart-d4427312-7292-44f6-ad5c-f8e402f53d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=863115118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.863115118
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1763804620
Short name T239
Test name
Test status
Simulation time 211808568 ps
CPU time 2.4 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203792 kb
Host smart-99ce0ac6-9caf-4c9e-a836-2d1278b67e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763804620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1763804620
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3957770564
Short name T328
Test name
Test status
Simulation time 512314581 ps
CPU time 2.96 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 203828 kb
Host smart-eef05e4f-0730-4a19-8406-69ee338061f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3957770564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3957770564
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1945511661
Short name T1439
Test name
Test status
Simulation time 70431172 ps
CPU time 1.92 seconds
Started May 12 12:45:09 PM PDT 24
Finished May 12 12:45:11 PM PDT 24
Peak memory 203772 kb
Host smart-3f42af42-e4ad-49bf-b269-7080444e7ade
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1945511661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1945511661
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.765850131
Short name T231
Test name
Test status
Simulation time 628153988 ps
CPU time 4.3 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203788 kb
Host smart-79035c0e-5e87-4b86-89fe-6300ec4774d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=765850131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.765850131
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2534050394
Short name T264
Test name
Test status
Simulation time 111728214 ps
CPU time 2.46 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 212032 kb
Host smart-f583c990-2623-420f-bf74-8286bd930b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534050394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2534050394
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.950937141
Short name T291
Test name
Test status
Simulation time 57699801 ps
CPU time 0.97 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203844 kb
Host smart-127635f8-3561-43aa-9d4d-9139b7d9e45b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=950937141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.950937141
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2283854951
Short name T286
Test name
Test status
Simulation time 228637298 ps
CPU time 2.49 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 211956 kb
Host smart-46aaf1a0-2364-4e61-82f8-a868d27ae8b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2283854951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2283854951
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1685456272
Short name T1473
Test name
Test status
Simulation time 316575910 ps
CPU time 2.47 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203716 kb
Host smart-eca2849a-3734-44e2-adcb-907988ddd29a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1685456272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1685456272
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.356348578
Short name T68
Test name
Test status
Simulation time 44446225 ps
CPU time 1.02 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203820 kb
Host smart-2a3c51ea-cfff-42c3-a795-3c964442bc9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=356348578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.356348578
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.782977641
Short name T1504
Test name
Test status
Simulation time 112134740 ps
CPU time 1.41 seconds
Started May 12 12:45:06 PM PDT 24
Finished May 12 12:45:08 PM PDT 24
Peak memory 203796 kb
Host smart-d279b6a2-e2d7-4870-a3e2-b77f19bfa749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=782977641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.782977641
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1860438032
Short name T233
Test name
Test status
Simulation time 209967887 ps
CPU time 2.37 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203804 kb
Host smart-875aa099-241e-472f-bd0f-b113673627e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1860438032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1860438032
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.515949497
Short name T1475
Test name
Test status
Simulation time 123080973 ps
CPU time 1.23 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 213212 kb
Host smart-ac4b3226-fd87-460e-9ad3-6ee136b61693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515949497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.515949497
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.40638553
Short name T294
Test name
Test status
Simulation time 66573268 ps
CPU time 0.98 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 203828 kb
Host smart-50374a80-b703-4065-92f4-04d6ad5555f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=40638553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.40638553
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3166097135
Short name T1499
Test name
Test status
Simulation time 83608808 ps
CPU time 1.46 seconds
Started May 12 12:45:15 PM PDT 24
Finished May 12 12:45:17 PM PDT 24
Peak memory 203748 kb
Host smart-6f65b208-951c-4e72-b556-c6eac206ceb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3166097135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3166097135
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1646438002
Short name T1506
Test name
Test status
Simulation time 189968937 ps
CPU time 2.32 seconds
Started May 12 12:45:21 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 203760 kb
Host smart-84b3ca5b-7948-40e3-96b0-1bf46f645af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1646438002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1646438002
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1427722973
Short name T1468
Test name
Test status
Simulation time 113522136 ps
CPU time 1.19 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:02 PM PDT 24
Peak memory 213184 kb
Host smart-78e5d0be-d68f-4a45-b463-4290db894b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427722973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1427722973
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3224293081
Short name T1509
Test name
Test status
Simulation time 37836061 ps
CPU time 0.91 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:13 PM PDT 24
Peak memory 203824 kb
Host smart-dde2d6f4-3e2d-4527-bac7-4f087a04f95c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3224293081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3224293081
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1248297508
Short name T1500
Test name
Test status
Simulation time 31763820 ps
CPU time 0.66 seconds
Started May 12 12:45:16 PM PDT 24
Finished May 12 12:45:17 PM PDT 24
Peak memory 202920 kb
Host smart-6144b4a4-a23b-4864-95e7-af6d07795019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1248297508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1248297508
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2119016353
Short name T1474
Test name
Test status
Simulation time 148067011 ps
CPU time 1.57 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:26 PM PDT 24
Peak memory 203820 kb
Host smart-cf286071-0d45-4846-80cc-9a65e86678d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2119016353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2119016353
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4224934609
Short name T323
Test name
Test status
Simulation time 384403867 ps
CPU time 4.07 seconds
Started May 12 12:45:31 PM PDT 24
Finished May 12 12:45:36 PM PDT 24
Peak memory 203876 kb
Host smart-fb76ed97-97cf-4ee2-84af-cbfee5c2c573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4224934609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4224934609
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1669035058
Short name T1451
Test name
Test status
Simulation time 46376483 ps
CPU time 1.28 seconds
Started May 12 12:45:20 PM PDT 24
Finished May 12 12:45:22 PM PDT 24
Peak memory 212064 kb
Host smart-ea1a2c0e-ef94-4d9d-b81a-2f49df8ad9bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669035058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1669035058
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3207023020
Short name T1460
Test name
Test status
Simulation time 36834052 ps
CPU time 0.82 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:30 PM PDT 24
Peak memory 203668 kb
Host smart-96bdfc92-cf63-4a2c-822b-9a7ccf36f058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3207023020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3207023020
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3202908931
Short name T232
Test name
Test status
Simulation time 264370912 ps
CPU time 1.69 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203784 kb
Host smart-188f2658-be0e-4838-9213-359447d9d5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3202908931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3202908931
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3475311649
Short name T1467
Test name
Test status
Simulation time 274519316 ps
CPU time 2.75 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 203832 kb
Host smart-db494618-d525-467a-9438-f6fae64bf748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3475311649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3475311649
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.370056761
Short name T1466
Test name
Test status
Simulation time 71487836 ps
CPU time 1.46 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:29 PM PDT 24
Peak memory 212000 kb
Host smart-adaeaa08-5a05-4ec9-8495-41ed373b4448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370056761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.370056761
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3776856284
Short name T1496
Test name
Test status
Simulation time 28217939 ps
CPU time 0.76 seconds
Started May 12 12:45:16 PM PDT 24
Finished May 12 12:45:18 PM PDT 24
Peak memory 203532 kb
Host smart-9bd6482e-d3ba-42b0-aecb-972ef9a4c27a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3776856284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3776856284
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2611142440
Short name T1457
Test name
Test status
Simulation time 30540432 ps
CPU time 0.67 seconds
Started May 12 12:45:22 PM PDT 24
Finished May 12 12:45:23 PM PDT 24
Peak memory 202964 kb
Host smart-669be232-e4db-4934-92c0-c7686a8c0d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2611142440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2611142440
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3247438028
Short name T1487
Test name
Test status
Simulation time 133658916 ps
CPU time 1.65 seconds
Started May 12 12:45:14 PM PDT 24
Finished May 12 12:45:16 PM PDT 24
Peak memory 203840 kb
Host smart-63802fd3-3a59-4f2e-a2ab-d651113e5623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3247438028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3247438028
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1189988726
Short name T1482
Test name
Test status
Simulation time 294781974 ps
CPU time 2.88 seconds
Started May 12 12:45:08 PM PDT 24
Finished May 12 12:45:17 PM PDT 24
Peak memory 203844 kb
Host smart-5172a722-6aaa-4870-8cff-4e1c79b68305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1189988726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1189988726
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3507528781
Short name T1463
Test name
Test status
Simulation time 1250356592 ps
CPU time 5.31 seconds
Started May 12 12:45:28 PM PDT 24
Finished May 12 12:45:34 PM PDT 24
Peak memory 203856 kb
Host smart-df7bd2f2-d2d8-470f-be8b-b7f2b62cb7a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3507528781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3507528781
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2802348317
Short name T1446
Test name
Test status
Simulation time 110682706 ps
CPU time 1.39 seconds
Started May 12 12:45:19 PM PDT 24
Finished May 12 12:45:21 PM PDT 24
Peak memory 212064 kb
Host smart-214818f8-7fff-4dc1-a4ed-b24d8ce2d8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802348317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2802348317
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.536203
Short name T1518
Test name
Test status
Simulation time 126835923 ps
CPU time 0.92 seconds
Started May 12 12:45:33 PM PDT 24
Finished May 12 12:45:35 PM PDT 24
Peak memory 203552 kb
Host smart-f68d3849-8240-47c7-a295-1107b50f2fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=536203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.536203
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.327147189
Short name T1528
Test name
Test status
Simulation time 31980875 ps
CPU time 0.65 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 203008 kb
Host smart-2d89853e-ee72-4eb5-a653-a6d90dc6d20d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=327147189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.327147189
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3262674183
Short name T1464
Test name
Test status
Simulation time 125042458 ps
CPU time 1.29 seconds
Started May 12 12:45:12 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 202960 kb
Host smart-64efa0ce-67fb-45ee-902f-aa628c1b109f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3262674183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3262674183
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3101629660
Short name T1455
Test name
Test status
Simulation time 88696226 ps
CPU time 2.72 seconds
Started May 12 12:45:28 PM PDT 24
Finished May 12 12:45:31 PM PDT 24
Peak memory 212112 kb
Host smart-1a761e07-0ff5-4b74-bbfe-ff15a680d819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3101629660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3101629660
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4107291756
Short name T322
Test name
Test status
Simulation time 643169531 ps
CPU time 5.01 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 202192 kb
Host smart-ab0bba22-68b3-471c-b33f-62b47febfe95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4107291756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.4107291756
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.711311170
Short name T1452
Test name
Test status
Simulation time 51534601 ps
CPU time 1.49 seconds
Started May 12 12:45:22 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 212076 kb
Host smart-32178e74-96f5-4549-a89d-adaaa10a408d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711311170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.711311170
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.49144370
Short name T284
Test name
Test status
Simulation time 56645057 ps
CPU time 0.83 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 203580 kb
Host smart-1d1517f9-5022-4f37-a22b-68d61570e095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=49144370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.49144370
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3151910062
Short name T1450
Test name
Test status
Simulation time 34607892 ps
CPU time 0.64 seconds
Started May 12 12:45:34 PM PDT 24
Finished May 12 12:45:36 PM PDT 24
Peak memory 202980 kb
Host smart-2357e933-d3f0-4a45-b735-99eec569204b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151910062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3151910062
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3538986509
Short name T1478
Test name
Test status
Simulation time 60372557 ps
CPU time 1.16 seconds
Started May 12 12:45:14 PM PDT 24
Finished May 12 12:45:16 PM PDT 24
Peak memory 203848 kb
Host smart-f5eabd0d-ec60-4ac5-9859-c108197beef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3538986509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3538986509
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1837031665
Short name T1461
Test name
Test status
Simulation time 249248471 ps
CPU time 2.69 seconds
Started May 12 12:45:10 PM PDT 24
Finished May 12 12:45:13 PM PDT 24
Peak memory 203788 kb
Host smart-6055617d-a4f1-434d-b3b7-319485b5bcf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1837031665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1837031665
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.669585661
Short name T1529
Test name
Test status
Simulation time 113748983 ps
CPU time 1.55 seconds
Started May 12 12:45:26 PM PDT 24
Finished May 12 12:45:29 PM PDT 24
Peak memory 211856 kb
Host smart-8d2c8be8-2418-48f7-986e-8a801173c123
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669585661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.669585661
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3076523347
Short name T1524
Test name
Test status
Simulation time 69729369 ps
CPU time 0.96 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:44:59 PM PDT 24
Peak memory 203772 kb
Host smart-64fdf322-026a-49b1-9a12-ac0c1a3b591c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3076523347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3076523347
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2691190296
Short name T1480
Test name
Test status
Simulation time 43159631 ps
CPU time 0.68 seconds
Started May 12 12:45:32 PM PDT 24
Finished May 12 12:45:33 PM PDT 24
Peak memory 202976 kb
Host smart-c5fff2df-4e37-4869-9491-eb7e28f6c232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2691190296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2691190296
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2602295568
Short name T1443
Test name
Test status
Simulation time 88640372 ps
CPU time 1.11 seconds
Started May 12 12:45:16 PM PDT 24
Finished May 12 12:45:18 PM PDT 24
Peak memory 203828 kb
Host smart-c8bb8849-fe77-44ff-9a48-2fe178da4893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2602295568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2602295568
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2364750555
Short name T1521
Test name
Test status
Simulation time 238206194 ps
CPU time 3.22 seconds
Started May 12 12:45:22 PM PDT 24
Finished May 12 12:45:26 PM PDT 24
Peak memory 203756 kb
Host smart-8c058d34-1d70-4da4-8bdd-e33938433164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2364750555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2364750555
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2811539262
Short name T234
Test name
Test status
Simulation time 255923815 ps
CPU time 2.22 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203832 kb
Host smart-48d8ca7f-9a0f-4138-aeed-88f94e4880fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2811539262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2811539262
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1788842792
Short name T258
Test name
Test status
Simulation time 81910557 ps
CPU time 1.31 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:30 PM PDT 24
Peak memory 213252 kb
Host smart-22d21cff-5660-422c-870b-8ae7a2c0849a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788842792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1788842792
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2522144018
Short name T1454
Test name
Test status
Simulation time 47517174 ps
CPU time 0.82 seconds
Started May 12 12:45:29 PM PDT 24
Finished May 12 12:45:36 PM PDT 24
Peak memory 203548 kb
Host smart-5ffd2e29-9b5c-4136-a110-e6222d732f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2522144018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2522144018
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2977561385
Short name T1526
Test name
Test status
Simulation time 59861120 ps
CPU time 0.68 seconds
Started May 12 12:45:19 PM PDT 24
Finished May 12 12:45:21 PM PDT 24
Peak memory 202984 kb
Host smart-c11a2297-cfd5-4a13-b6c7-bc5472555c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2977561385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2977561385
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3067745619
Short name T1440
Test name
Test status
Simulation time 298273964 ps
CPU time 1.62 seconds
Started May 12 12:45:34 PM PDT 24
Finished May 12 12:45:36 PM PDT 24
Peak memory 203992 kb
Host smart-c3a7c35b-26c6-41a8-8a91-7b2f9b0bfc2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3067745619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3067745619
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1277145907
Short name T1497
Test name
Test status
Simulation time 139412234 ps
CPU time 2.15 seconds
Started May 12 12:45:08 PM PDT 24
Finished May 12 12:45:11 PM PDT 24
Peak memory 203764 kb
Host smart-9a38462f-34ad-4151-89b2-2dfe8254074f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1277145907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1277145907
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.330782898
Short name T1472
Test name
Test status
Simulation time 81576277 ps
CPU time 1.22 seconds
Started May 12 12:44:49 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 213140 kb
Host smart-ee9211b9-476a-44b4-abaa-af2e6706ef89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330782898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.330782898
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1864954231
Short name T69
Test name
Test status
Simulation time 33314360 ps
CPU time 0.77 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203564 kb
Host smart-7c5ab3be-ab0f-4447-9ee6-670206dd78a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1864954231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1864954231
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1703698729
Short name T318
Test name
Test status
Simulation time 37035640 ps
CPU time 0.65 seconds
Started May 12 12:45:18 PM PDT 24
Finished May 12 12:45:20 PM PDT 24
Peak memory 203004 kb
Host smart-aa5f2e15-a6f9-418c-b772-5ea62f0fd0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1703698729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1703698729
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1255448356
Short name T1520
Test name
Test status
Simulation time 97961391 ps
CPU time 1.1 seconds
Started May 12 12:45:05 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 203700 kb
Host smart-bc1b829f-fd02-4280-90a4-4ddbcb3357e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1255448356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1255448356
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3063566550
Short name T1491
Test name
Test status
Simulation time 313054536 ps
CPU time 3.29 seconds
Started May 12 12:45:05 PM PDT 24
Finished May 12 12:45:13 PM PDT 24
Peak memory 203828 kb
Host smart-9af96173-4d89-4081-b067-3038e1a2f0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3063566550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3063566550
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3733899365
Short name T1505
Test name
Test status
Simulation time 165569980 ps
CPU time 1.79 seconds
Started May 12 12:45:28 PM PDT 24
Finished May 12 12:45:31 PM PDT 24
Peak memory 212080 kb
Host smart-5f18e4cb-9df0-46d9-9e77-4e22f0430643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733899365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3733899365
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3416037340
Short name T1492
Test name
Test status
Simulation time 41090037 ps
CPU time 0.8 seconds
Started May 12 12:45:18 PM PDT 24
Finished May 12 12:45:20 PM PDT 24
Peak memory 203492 kb
Host smart-4b16e951-0fd2-49b9-b022-9cf3c8f7d727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3416037340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3416037340
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.759569170
Short name T66
Test name
Test status
Simulation time 89568262 ps
CPU time 1.13 seconds
Started May 12 12:45:12 PM PDT 24
Finished May 12 12:45:14 PM PDT 24
Peak memory 203748 kb
Host smart-fc7cd2ba-a3a6-4c6a-a7d9-e5a0f12da2ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=759569170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.759569170
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3727240952
Short name T1458
Test name
Test status
Simulation time 75195765 ps
CPU time 2.1 seconds
Started May 12 12:45:33 PM PDT 24
Finished May 12 12:45:36 PM PDT 24
Peak memory 203928 kb
Host smart-31f8cd62-bf8b-48bb-84aa-c1a581d74266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3727240952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3727240952
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2940877585
Short name T329
Test name
Test status
Simulation time 1254059095 ps
CPU time 5.61 seconds
Started May 12 12:45:15 PM PDT 24
Finished May 12 12:45:22 PM PDT 24
Peak memory 203804 kb
Host smart-e7875ef6-fd75-4da8-baf1-2a2fda9db72d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2940877585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2940877585
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2197966865
Short name T303
Test name
Test status
Simulation time 382768988 ps
CPU time 3.74 seconds
Started May 12 12:44:51 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203788 kb
Host smart-83f2dd78-8012-4ba5-88db-005b9d550f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2197966865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2197966865
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1169852516
Short name T1438
Test name
Test status
Simulation time 533651447 ps
CPU time 7.06 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203720 kb
Host smart-d3078851-b624-4f62-99db-18b2b14842ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1169852516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1169852516
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3380680703
Short name T70
Test name
Test status
Simulation time 48277967 ps
CPU time 0.72 seconds
Started May 12 12:45:08 PM PDT 24
Finished May 12 12:45:09 PM PDT 24
Peak memory 203456 kb
Host smart-a27f7e46-ea8e-4ca3-9041-bd98785b6c55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3380680703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3380680703
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.904399637
Short name T1512
Test name
Test status
Simulation time 54593153 ps
CPU time 1.44 seconds
Started May 12 12:45:12 PM PDT 24
Finished May 12 12:45:14 PM PDT 24
Peak memory 212012 kb
Host smart-7a922a72-8c29-49b1-b2a3-2ae6e0e8a16b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904399637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.904399637
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.807742929
Short name T1495
Test name
Test status
Simulation time 30569977 ps
CPU time 0.66 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 202852 kb
Host smart-ffa57fe2-6981-4dec-a195-d5cd406976e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=807742929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.807742929
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3762554160
Short name T289
Test name
Test status
Simulation time 43325765 ps
CPU time 1.22 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 203800 kb
Host smart-9e33c5a2-0f3c-4ebe-b90b-6b87ab3b3d09
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3762554160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3762554160
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3823898791
Short name T1485
Test name
Test status
Simulation time 303110044 ps
CPU time 2.52 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203736 kb
Host smart-cfb94ead-4e12-4ae6-87b3-0ad3acc74c70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3823898791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3823898791
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3143831665
Short name T1486
Test name
Test status
Simulation time 68385748 ps
CPU time 1.39 seconds
Started May 12 12:45:26 PM PDT 24
Finished May 12 12:45:28 PM PDT 24
Peak memory 203908 kb
Host smart-f8f95c54-a5e5-4d4f-a7ed-5b1018c96f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3143831665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3143831665
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1004598207
Short name T255
Test name
Test status
Simulation time 76568509 ps
CPU time 2.04 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203848 kb
Host smart-c9f22f74-272f-4fc5-8643-3832fc97265f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1004598207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1004598207
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.25303715
Short name T327
Test name
Test status
Simulation time 385521507 ps
CPU time 2.61 seconds
Started May 12 12:45:02 PM PDT 24
Finished May 12 12:45:06 PM PDT 24
Peak memory 203832 kb
Host smart-58d02a36-e179-48c6-b3bf-2829774d3945
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=25303715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.25303715
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2920193247
Short name T1479
Test name
Test status
Simulation time 34815403 ps
CPU time 0.66 seconds
Started May 12 12:45:38 PM PDT 24
Finished May 12 12:45:40 PM PDT 24
Peak memory 202960 kb
Host smart-25c8e1d9-d730-42b6-80b1-931702bf0482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2920193247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2920193247
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1271036050
Short name T317
Test name
Test status
Simulation time 41620921 ps
CPU time 0.69 seconds
Started May 12 12:45:24 PM PDT 24
Finished May 12 12:45:26 PM PDT 24
Peak memory 202988 kb
Host smart-b6f68ed9-cd95-4f03-b80e-d0e2ea578bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1271036050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1271036050
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4175149267
Short name T72
Test name
Test status
Simulation time 46055352 ps
CPU time 0.67 seconds
Started May 12 12:45:22 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 202792 kb
Host smart-6d53ed7a-c74a-4849-a919-415ee71d308a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4175149267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4175149267
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4047103266
Short name T1481
Test name
Test status
Simulation time 30723202 ps
CPU time 0.62 seconds
Started May 12 12:45:18 PM PDT 24
Finished May 12 12:45:20 PM PDT 24
Peak memory 202956 kb
Host smart-b4c19d81-4e6a-4558-94f0-d5ff15905773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4047103266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4047103266
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1519424075
Short name T313
Test name
Test status
Simulation time 38439306 ps
CPU time 0.64 seconds
Started May 12 12:45:16 PM PDT 24
Finished May 12 12:45:17 PM PDT 24
Peak memory 202920 kb
Host smart-f549f530-c6f7-4218-82cd-3dcb481d5ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1519424075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1519424075
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4267239329
Short name T1511
Test name
Test status
Simulation time 30415957 ps
CPU time 0.65 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:28 PM PDT 24
Peak memory 203028 kb
Host smart-e319d9c6-b03a-43f8-8130-5cedc593a38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4267239329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4267239329
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4094707644
Short name T1477
Test name
Test status
Simulation time 85886338 ps
CPU time 0.71 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:16 PM PDT 24
Peak memory 203464 kb
Host smart-011693ac-6ad3-4bba-9854-a4aeefd63418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4094707644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4094707644
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3873949321
Short name T1444
Test name
Test status
Simulation time 25248553 ps
CPU time 0.63 seconds
Started May 12 12:45:28 PM PDT 24
Finished May 12 12:45:30 PM PDT 24
Peak memory 202980 kb
Host smart-bf2b0141-c12b-4dbf-b3a2-4c7f052473d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3873949321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3873949321
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1386807312
Short name T1519
Test name
Test status
Simulation time 25296410 ps
CPU time 0.63 seconds
Started May 12 12:45:22 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 202884 kb
Host smart-0eaa964c-0bb7-42be-b3d0-45132bf2d7a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1386807312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1386807312
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2919133976
Short name T1483
Test name
Test status
Simulation time 29710700 ps
CPU time 0.63 seconds
Started May 12 12:45:21 PM PDT 24
Finished May 12 12:45:23 PM PDT 24
Peak memory 203084 kb
Host smart-31fb3be3-7e2a-4597-b3a6-89370617946e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2919133976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2919133976
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2701793231
Short name T1442
Test name
Test status
Simulation time 154190690 ps
CPU time 2.03 seconds
Started May 12 12:45:07 PM PDT 24
Finished May 12 12:45:10 PM PDT 24
Peak memory 203852 kb
Host smart-77bbfe1b-1708-44c7-87c1-16c3966b6102
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2701793231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2701793231
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3980094248
Short name T1448
Test name
Test status
Simulation time 459135262 ps
CPU time 6.95 seconds
Started May 12 12:44:49 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203820 kb
Host smart-77d945d6-fed2-43c6-8f2f-a2a8814f3a52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3980094248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3980094248
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2103432240
Short name T1507
Test name
Test status
Simulation time 98129998 ps
CPU time 2.16 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 220168 kb
Host smart-bbdba3f5-60cc-41ab-a172-595a603b5315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103432240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2103432240
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1676272455
Short name T319
Test name
Test status
Simulation time 33368715 ps
CPU time 0.66 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203060 kb
Host smart-f267bf43-46b2-420d-af02-69bbec0a026d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1676272455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1676272455
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2993198587
Short name T283
Test name
Test status
Simulation time 158965022 ps
CPU time 2.13 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 211920 kb
Host smart-783593be-2ae9-4f9b-ac7b-5fc11ee26ae7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2993198587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2993198587
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.417555515
Short name T1523
Test name
Test status
Simulation time 365165758 ps
CPU time 2.59 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:59 PM PDT 24
Peak memory 203768 kb
Host smart-fd9984f2-7fb9-4e02-acba-10d664926d7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=417555515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.417555515
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2977951602
Short name T304
Test name
Test status
Simulation time 114887363 ps
CPU time 1.09 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:10 PM PDT 24
Peak memory 203900 kb
Host smart-864061ff-dfc6-4d3f-a3b6-37fa2245a98d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2977951602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2977951602
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2911434073
Short name T260
Test name
Test status
Simulation time 270763328 ps
CPU time 2.99 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:31 PM PDT 24
Peak memory 203776 kb
Host smart-27ed1ed7-6245-4454-984c-61b79b1ae791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2911434073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2911434073
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.758067859
Short name T1498
Test name
Test status
Simulation time 278803266 ps
CPU time 2.82 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203868 kb
Host smart-7e9c5747-c5a9-4f66-8121-c6732352e115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=758067859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.758067859
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1264873050
Short name T77
Test name
Test status
Simulation time 35522381 ps
CPU time 0.67 seconds
Started May 12 12:45:17 PM PDT 24
Finished May 12 12:45:19 PM PDT 24
Peak memory 202988 kb
Host smart-ff43c812-450c-4433-abff-cc213d891194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1264873050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1264873050
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3159783675
Short name T1522
Test name
Test status
Simulation time 26863871 ps
CPU time 0.66 seconds
Started May 12 12:45:33 PM PDT 24
Finished May 12 12:45:35 PM PDT 24
Peak memory 203064 kb
Host smart-dcf695d9-7fb9-4956-808c-aaefb7e3df91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3159783675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3159783675
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2032837641
Short name T309
Test name
Test status
Simulation time 39473145 ps
CPU time 0.68 seconds
Started May 12 12:45:06 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 202956 kb
Host smart-767b362b-48a9-4a1c-bb2d-385dc8abf580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2032837641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2032837641
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3810848237
Short name T1476
Test name
Test status
Simulation time 28161853 ps
CPU time 0.66 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:28 PM PDT 24
Peak memory 202972 kb
Host smart-b8f328a9-41fa-4e69-9c79-1980ee4d5c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3810848237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3810848237
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.128413150
Short name T315
Test name
Test status
Simulation time 29380875 ps
CPU time 0.65 seconds
Started May 12 12:45:19 PM PDT 24
Finished May 12 12:45:21 PM PDT 24
Peak memory 203016 kb
Host smart-23e440e3-e81b-4419-9a55-5ee78025618e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=128413150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.128413150
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.888594566
Short name T311
Test name
Test status
Simulation time 27311484 ps
CPU time 0.63 seconds
Started May 12 12:45:34 PM PDT 24
Finished May 12 12:45:35 PM PDT 24
Peak memory 203076 kb
Host smart-06edbc29-f3d6-4393-9366-77a501fbb15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=888594566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.888594566
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4026515691
Short name T1530
Test name
Test status
Simulation time 33419804 ps
CPU time 0.66 seconds
Started May 12 12:45:37 PM PDT 24
Finished May 12 12:45:38 PM PDT 24
Peak memory 203092 kb
Host smart-c76df1e6-73d1-486f-a00d-3ada67e83951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4026515691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4026515691
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3789601130
Short name T1447
Test name
Test status
Simulation time 44811522 ps
CPU time 0.67 seconds
Started May 12 12:45:18 PM PDT 24
Finished May 12 12:45:20 PM PDT 24
Peak memory 202896 kb
Host smart-0f9fb9a8-51d2-4af7-b867-6ee4b4fbfa1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3789601130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3789601130
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.387808972
Short name T1456
Test name
Test status
Simulation time 32503671 ps
CPU time 0.66 seconds
Started May 12 12:45:38 PM PDT 24
Finished May 12 12:45:40 PM PDT 24
Peak memory 203004 kb
Host smart-fc7eb878-15c2-4277-a871-abf260f1c4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=387808972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.387808972
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1705617480
Short name T316
Test name
Test status
Simulation time 102212071 ps
CPU time 0.73 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203352 kb
Host smart-ac1871ff-2409-4348-b760-4a9e04351d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1705617480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1705617480
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.814494779
Short name T281
Test name
Test status
Simulation time 223609016 ps
CPU time 2.09 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:02 PM PDT 24
Peak memory 203680 kb
Host smart-20cabe46-2870-4bc4-8298-f21e8aa522a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=814494779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.814494779
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3739090068
Short name T308
Test name
Test status
Simulation time 792935128 ps
CPU time 4.72 seconds
Started May 12 12:45:17 PM PDT 24
Finished May 12 12:45:23 PM PDT 24
Peak memory 203724 kb
Host smart-5d385793-fd39-4667-9a61-61ff83be3791
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3739090068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3739090068
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.713436658
Short name T279
Test name
Test status
Simulation time 36402683 ps
CPU time 0.74 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 203492 kb
Host smart-96d48935-3912-4673-ad83-ef101f7f6f86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=713436658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.713436658
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4056284794
Short name T1508
Test name
Test status
Simulation time 122475618 ps
CPU time 2.2 seconds
Started May 12 12:44:51 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 211984 kb
Host smart-eac2d9f4-1d48-45dc-9e8a-bb4efb275ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056284794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.4056284794
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1579039748
Short name T290
Test name
Test status
Simulation time 71872363 ps
CPU time 0.93 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:44:59 PM PDT 24
Peak memory 203720 kb
Host smart-3d770127-ded8-4fb2-acee-69328bd53229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1579039748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1579039748
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2197971443
Short name T307
Test name
Test status
Simulation time 82216157 ps
CPU time 0.74 seconds
Started May 12 12:45:14 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 203024 kb
Host smart-540103f2-ee53-4cee-90db-5cd7b9da83c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2197971443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2197971443
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3767817975
Short name T282
Test name
Test status
Simulation time 103880481 ps
CPU time 1.42 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 203832 kb
Host smart-a7c74c15-9aad-41fb-b6c7-7a3121f0462e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3767817975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3767817975
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.782966336
Short name T1527
Test name
Test status
Simulation time 165482116 ps
CPU time 2.35 seconds
Started May 12 12:45:21 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 203724 kb
Host smart-2560d8d2-804c-4378-a14f-8dcd2773e41a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=782966336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.782966336
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4056642156
Short name T1484
Test name
Test status
Simulation time 82696495 ps
CPU time 1.05 seconds
Started May 12 12:45:26 PM PDT 24
Finished May 12 12:45:28 PM PDT 24
Peak memory 203872 kb
Host smart-ea1b491d-3637-4c3b-98e2-a14eb4bd8bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4056642156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.4056642156
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.744635378
Short name T235
Test name
Test status
Simulation time 142217520 ps
CPU time 1.72 seconds
Started May 12 12:45:18 PM PDT 24
Finished May 12 12:45:21 PM PDT 24
Peak memory 203812 kb
Host smart-bd46d876-fd51-44c1-a678-a66daca57a46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=744635378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.744635378
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.55775757
Short name T1470
Test name
Test status
Simulation time 206106983 ps
CPU time 2.46 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 203004 kb
Host smart-c100b4df-58b2-428c-9987-fb7c69103765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=55775757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.55775757
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2868667644
Short name T74
Test name
Test status
Simulation time 47752846 ps
CPU time 0.61 seconds
Started May 12 12:45:13 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 202944 kb
Host smart-01713ff1-bc63-477b-b17a-380bbf2d6929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2868667644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2868667644
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1819781255
Short name T1465
Test name
Test status
Simulation time 24620154 ps
CPU time 0.66 seconds
Started May 12 12:45:26 PM PDT 24
Finished May 12 12:45:28 PM PDT 24
Peak memory 202952 kb
Host smart-9f1bb42f-1064-4ca5-858d-80e9724b40b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1819781255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1819781255
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.381430032
Short name T1471
Test name
Test status
Simulation time 33334977 ps
CPU time 0.65 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:24 PM PDT 24
Peak memory 203048 kb
Host smart-31a44411-d2af-4ee9-8cf2-0a531935afa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=381430032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.381430032
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.145728267
Short name T1469
Test name
Test status
Simulation time 29649943 ps
CPU time 0.67 seconds
Started May 12 12:45:32 PM PDT 24
Finished May 12 12:45:33 PM PDT 24
Peak memory 202996 kb
Host smart-b87c03c7-b3ad-49ff-9120-968fb24bc30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=145728267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.145728267
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2726461966
Short name T1488
Test name
Test status
Simulation time 32919900 ps
CPU time 0.63 seconds
Started May 12 12:45:34 PM PDT 24
Finished May 12 12:45:35 PM PDT 24
Peak memory 203024 kb
Host smart-7dda7bd4-afb0-4218-9906-0bd601c02853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726461966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2726461966
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1085043736
Short name T310
Test name
Test status
Simulation time 34595193 ps
CPU time 0.63 seconds
Started May 12 12:45:15 PM PDT 24
Finished May 12 12:45:22 PM PDT 24
Peak memory 203016 kb
Host smart-114de2a7-b7a1-422f-b414-820f9f49a6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1085043736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1085043736
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1532293606
Short name T1502
Test name
Test status
Simulation time 49513595 ps
CPU time 0.67 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 203036 kb
Host smart-1f4158bf-0a04-404b-90f4-fdc99b1482ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532293606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1532293606
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1553065994
Short name T1525
Test name
Test status
Simulation time 43951862 ps
CPU time 0.69 seconds
Started May 12 12:45:14 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 203048 kb
Host smart-03e3c12c-e774-456f-bcca-ed98546a83c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1553065994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1553065994
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2640593433
Short name T1459
Test name
Test status
Simulation time 41742231 ps
CPU time 0.62 seconds
Started May 12 12:45:07 PM PDT 24
Finished May 12 12:45:08 PM PDT 24
Peak memory 202980 kb
Host smart-0601c432-8682-4eaa-b307-400dddf979b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2640593433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2640593433
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1772823244
Short name T1515
Test name
Test status
Simulation time 34320566 ps
CPU time 0.65 seconds
Started May 12 12:45:28 PM PDT 24
Finished May 12 12:45:30 PM PDT 24
Peak memory 202980 kb
Host smart-cf83b9cb-b0f4-4ab9-88b7-45824c1cfcc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1772823244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1772823244
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1122204328
Short name T306
Test name
Test status
Simulation time 278524516 ps
CPU time 2.02 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 211980 kb
Host smart-950eec45-0b98-4dc2-86f2-9bcd332ecd40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122204328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1122204328
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1800593723
Short name T287
Test name
Test status
Simulation time 71847673 ps
CPU time 0.98 seconds
Started May 12 12:45:22 PM PDT 24
Finished May 12 12:45:23 PM PDT 24
Peak memory 203844 kb
Host smart-390053b2-c38d-4045-a3b4-117cc91a9df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1800593723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1800593723
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3219188291
Short name T1503
Test name
Test status
Simulation time 58049020 ps
CPU time 0.69 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 202840 kb
Host smart-9fa42f32-df39-4af1-a1c6-579d2e17d899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219188291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3219188291
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.147826538
Short name T1510
Test name
Test status
Simulation time 78449116 ps
CPU time 1.13 seconds
Started May 12 12:45:23 PM PDT 24
Finished May 12 12:45:25 PM PDT 24
Peak memory 203928 kb
Host smart-3bebdcdc-9638-460b-aa2f-8f740e806dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=147826538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.147826538
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3755834016
Short name T262
Test name
Test status
Simulation time 113756182 ps
CPU time 1.43 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203908 kb
Host smart-d37ae120-b378-4bee-8d72-cb0753fe6229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3755834016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3755834016
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.855928778
Short name T324
Test name
Test status
Simulation time 597615067 ps
CPU time 4.24 seconds
Started May 12 12:45:18 PM PDT 24
Finished May 12 12:45:23 PM PDT 24
Peak memory 203908 kb
Host smart-39c5028e-468a-483b-90e4-8accb674b1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=855928778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.855928778
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4177966396
Short name T305
Test name
Test status
Simulation time 51321920 ps
CPU time 0.79 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 203468 kb
Host smart-ca607061-b5f5-4811-a8d4-97f5dc7dc6de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4177966396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4177966396
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2365708869
Short name T1453
Test name
Test status
Simulation time 41586094 ps
CPU time 0.64 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:06 PM PDT 24
Peak memory 203072 kb
Host smart-5f6416ed-f7c7-432d-9ca0-d64351f15d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2365708869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2365708869
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2933530588
Short name T1489
Test name
Test status
Simulation time 66911724 ps
CPU time 1.02 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203744 kb
Host smart-c10957f7-68c0-405d-a4a3-a04702fd1667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933530588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2933530588
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3366111272
Short name T61
Test name
Test status
Simulation time 54950164 ps
CPU time 1.3 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 203836 kb
Host smart-23d2b6c6-ae91-4794-a2f8-7c9215eac1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3366111272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3366111272
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.833431552
Short name T238
Test name
Test status
Simulation time 1625240806 ps
CPU time 5.51 seconds
Started May 12 12:45:24 PM PDT 24
Finished May 12 12:45:30 PM PDT 24
Peak memory 203848 kb
Host smart-62dbaabb-1756-4e1d-bc6b-73bf3d627e73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=833431552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.833431552
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3969110784
Short name T1441
Test name
Test status
Simulation time 57300955 ps
CPU time 1.27 seconds
Started May 12 12:45:53 PM PDT 24
Finished May 12 12:45:56 PM PDT 24
Peak memory 212020 kb
Host smart-651996cc-280d-4936-9215-bc4057a756a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969110784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3969110784
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1740339619
Short name T292
Test name
Test status
Simulation time 50812252 ps
CPU time 0.83 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:29 PM PDT 24
Peak memory 203492 kb
Host smart-1a897944-130d-440c-97f4-cecd4f4d7631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1740339619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1740339619
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.153563579
Short name T236
Test name
Test status
Simulation time 257936075 ps
CPU time 1.43 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 203896 kb
Host smart-2de756bc-bb9e-4c27-9b5f-af264cf86ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=153563579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.153563579
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4218131407
Short name T1516
Test name
Test status
Simulation time 277290923 ps
CPU time 2.83 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203776 kb
Host smart-9a674990-7a74-499e-af57-93bd2ff52364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4218131407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4218131407
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2278715766
Short name T326
Test name
Test status
Simulation time 378310201 ps
CPU time 2.6 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:45:06 PM PDT 24
Peak memory 203868 kb
Host smart-ec5cc732-1a90-4bc3-8778-0144c8da8707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2278715766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2278715766
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1152422946
Short name T1513
Test name
Test status
Simulation time 138990072 ps
CPU time 1.35 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 212052 kb
Host smart-a4f3f3e0-db3b-4975-93d6-6b06258e0938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152422946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1152422946
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.463675256
Short name T288
Test name
Test status
Simulation time 62760052 ps
CPU time 0.96 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:57 PM PDT 24
Peak memory 203776 kb
Host smart-ff3c64c9-1b9e-4d39-9c05-2aee20b837b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=463675256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.463675256
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.646501435
Short name T1490
Test name
Test status
Simulation time 30884057 ps
CPU time 0.62 seconds
Started May 12 12:45:20 PM PDT 24
Finished May 12 12:45:22 PM PDT 24
Peak memory 202920 kb
Host smart-c748b089-cb55-40d1-bf59-0eed767a8e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=646501435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.646501435
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2615490000
Short name T67
Test name
Test status
Simulation time 71824711 ps
CPU time 1.06 seconds
Started May 12 12:45:38 PM PDT 24
Finished May 12 12:45:40 PM PDT 24
Peak memory 203848 kb
Host smart-d510c3eb-efb1-4198-869e-324aff3d9f88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2615490000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2615490000
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1206920578
Short name T1445
Test name
Test status
Simulation time 143985462 ps
CPU time 1.77 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 212048 kb
Host smart-79bc2a4b-b157-4692-bf9a-e88b10c58c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206920578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1206920578
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3561956670
Short name T278
Test name
Test status
Simulation time 35947835 ps
CPU time 0.95 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 203672 kb
Host smart-3f9870dd-4c94-4a4d-8e0f-73545b488cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3561956670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3561956670
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.774264172
Short name T73
Test name
Test status
Simulation time 32005782 ps
CPU time 0.63 seconds
Started May 12 12:45:10 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 202960 kb
Host smart-88d11a24-b449-4611-8b4d-e18692a1fb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=774264172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.774264172
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2935103733
Short name T1462
Test name
Test status
Simulation time 102877677 ps
CPU time 1.09 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203808 kb
Host smart-e0cb4e77-56c7-46db-8404-a97055cdbc8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2935103733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2935103733
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4158897508
Short name T257
Test name
Test status
Simulation time 96027259 ps
CPU time 1.3 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203848 kb
Host smart-6237c293-4592-4bb8-871b-88fe83523259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4158897508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4158897508
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2207422289
Short name T320
Test name
Test status
Simulation time 560767225 ps
CPU time 4.23 seconds
Started May 12 12:45:53 PM PDT 24
Finished May 12 12:45:59 PM PDT 24
Peak memory 203920 kb
Host smart-51093ee8-0731-4ee4-a4b3-c384c19f8bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2207422289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2207422289
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3360286174
Short name T633
Test name
Test status
Simulation time 8475712938 ps
CPU time 10.16 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:37 PM PDT 24
Peak memory 204380 kb
Host smart-802b569a-5a04-4c07-b80e-04f1c1758ed2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3360286174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3360286174
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2209457624
Short name T1293
Test name
Test status
Simulation time 8389119800 ps
CPU time 7.61 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:34 PM PDT 24
Peak memory 204344 kb
Host smart-cbbf2300-9ca4-4aa5-ac1f-970d7f356b6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2209457624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2209457624
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3430698226
Short name T1341
Test name
Test status
Simulation time 8387869958 ps
CPU time 8.7 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204436 kb
Host smart-c872b3c3-0a5d-4961-9b31-4b10a0bcbcfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34306
98226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3430698226
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1531678307
Short name T658
Test name
Test status
Simulation time 8404119180 ps
CPU time 8.73 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:34 PM PDT 24
Peak memory 204456 kb
Host smart-b1705409-a6fb-42e6-8c51-4b69fdb05bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
78307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1531678307
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1822544663
Short name T197
Test name
Test status
Simulation time 9457201567 ps
CPU time 13.23 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 204720 kb
Host smart-8c05098a-94a5-416b-badc-79dcf85a5c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225
44663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1822544663
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_enable.1887454754
Short name T493
Test name
Test status
Simulation time 8384347240 ps
CPU time 7.95 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204456 kb
Host smart-3424147d-9972-4b2a-83d7-f0f820965721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874
54754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1887454754
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2300274367
Short name T812
Test name
Test status
Simulation time 119715664 ps
CPU time 1.27 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 204584 kb
Host smart-6385966f-5745-4854-95ad-29d4c394d23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23002
74367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2300274367
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3171504524
Short name T796
Test name
Test status
Simulation time 8401555683 ps
CPU time 7.88 seconds
Started May 12 12:54:23 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 204488 kb
Host smart-efd1a83b-8622-43c3-8cd9-7a0614cfb9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31715
04524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3171504524
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2495861773
Short name T820
Test name
Test status
Simulation time 8406650040 ps
CPU time 7.55 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 204460 kb
Host smart-25bd3aab-4df0-486f-8a14-63bd37c8ba4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
61773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2495861773
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1329983128
Short name T475
Test name
Test status
Simulation time 8488214774 ps
CPU time 8.11 seconds
Started May 12 12:54:24 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 204392 kb
Host smart-20ba4264-5187-4114-8482-0bbae02f342b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
83128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1329983128
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.25662974
Short name T1059
Test name
Test status
Simulation time 8409134895 ps
CPU time 8.77 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:34 PM PDT 24
Peak memory 204384 kb
Host smart-37f37f08-7fa0-400c-b747-a97487203fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25662
974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.25662974
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3501241660
Short name T385
Test name
Test status
Simulation time 8384210435 ps
CPU time 7.88 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 204500 kb
Host smart-aff02cf8-581f-4373-aadc-357b0ed9dff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35012
41660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3501241660
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3996879410
Short name T789
Test name
Test status
Simulation time 8387779002 ps
CPU time 9.92 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:37 PM PDT 24
Peak memory 204444 kb
Host smart-3679c708-3098-410f-8df7-9643ae59cab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39968
79410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3996879410
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1961313679
Short name T921
Test name
Test status
Simulation time 8365692221 ps
CPU time 7.36 seconds
Started May 12 12:54:45 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204372 kb
Host smart-c6096a06-9350-4a44-aa40-3b293e396c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
13679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1961313679
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1784784255
Short name T884
Test name
Test status
Simulation time 134127675 ps
CPU time 0.77 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:28 PM PDT 24
Peak memory 204364 kb
Host smart-232c4a16-5d2e-4330-9253-e226acf735f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847
84255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1784784255
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.905323853
Short name T1243
Test name
Test status
Simulation time 27551549249 ps
CPU time 54.74 seconds
Started May 12 12:54:42 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204636 kb
Host smart-41f8ef5b-1a4d-443c-901c-a3d246520da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90532
3853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.905323853
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3687251522
Short name T463
Test name
Test status
Simulation time 8419144647 ps
CPU time 7.99 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204452 kb
Host smart-676d80f8-0195-47a0-ba7c-27f84a65ec22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
51522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3687251522
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.4232934473
Short name T141
Test name
Test status
Simulation time 8463401326 ps
CPU time 9.3 seconds
Started May 12 12:54:31 PM PDT 24
Finished May 12 12:54:41 PM PDT 24
Peak memory 204488 kb
Host smart-01f56925-d1de-4906-b932-11e9d1531dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42329
34473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.4232934473
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.4098021758
Short name T515
Test name
Test status
Simulation time 8404749314 ps
CPU time 8.5 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 204432 kb
Host smart-01bf402b-0e4f-4bd2-86bb-47f3fbe4e9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
21758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.4098021758
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.4029887173
Short name T919
Test name
Test status
Simulation time 8384652779 ps
CPU time 10.22 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 204500 kb
Host smart-2cc48d6c-54ea-4e5c-9cee-9bcdf49647cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298
87173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.4029887173
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.532499958
Short name T439
Test name
Test status
Simulation time 8370651256 ps
CPU time 8.64 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204456 kb
Host smart-8349559d-97e6-4ab9-bd10-e82cb1280fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53249
9958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.532499958
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1232879871
Short name T1412
Test name
Test status
Simulation time 8466742905 ps
CPU time 9.28 seconds
Started May 12 12:54:21 PM PDT 24
Finished May 12 12:54:31 PM PDT 24
Peak memory 204420 kb
Host smart-58363955-39c6-4435-97b3-836c5949e3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12328
79871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1232879871
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2871934438
Short name T444
Test name
Test status
Simulation time 8437249516 ps
CPU time 8.41 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204436 kb
Host smart-c31146e6-bf0b-4561-a005-b4922286f44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28719
34438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2871934438
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.787766473
Short name T934
Test name
Test status
Simulation time 8395852083 ps
CPU time 7.85 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 204496 kb
Host smart-8219626d-97aa-4301-a94f-6c535d53a6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78776
6473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.787766473
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1295488387
Short name T1201
Test name
Test status
Simulation time 8460180107 ps
CPU time 8.17 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:38 PM PDT 24
Peak memory 204400 kb
Host smart-a71692a7-83a0-43c2-a0f1-fb6a44664f97
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1295488387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1295488387
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3519056194
Short name T1054
Test name
Test status
Simulation time 8389249681 ps
CPU time 9.89 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204356 kb
Host smart-ba931dd5-8a8c-4ee2-b645-6aba4b4a109f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3519056194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3519056194
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1391187256
Short name T963
Test name
Test status
Simulation time 8442324657 ps
CPU time 7.81 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 204364 kb
Host smart-b86205b4-e6a9-4b46-9728-78cb77e9d793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
87256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1391187256
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.4010909488
Short name T692
Test name
Test status
Simulation time 8373391870 ps
CPU time 8.66 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204472 kb
Host smart-0a34acc4-a6fb-430c-b29c-b7d39d5decc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
09488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4010909488
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2270317751
Short name T1428
Test name
Test status
Simulation time 9220071077 ps
CPU time 12.82 seconds
Started May 12 12:54:33 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204704 kb
Host smart-73a8fab2-6309-416c-ac2c-2a0b47782615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
17751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2270317751
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_enable.2945082364
Short name T1233
Test name
Test status
Simulation time 8375385497 ps
CPU time 7.86 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:38 PM PDT 24
Peak memory 204352 kb
Host smart-103b6bd9-d903-4a55-9f4d-e39e51858216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29450
82364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2945082364
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2714202463
Short name T621
Test name
Test status
Simulation time 276519176 ps
CPU time 2.22 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:40 PM PDT 24
Peak memory 204552 kb
Host smart-ebb3df61-3c82-4ad4-b8b4-6e540bfb974e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27142
02463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2714202463
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1285449930
Short name T1370
Test name
Test status
Simulation time 8454947110 ps
CPU time 8.66 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204456 kb
Host smart-cd8f9aba-23fb-4a79-bfb5-7bdaf66bd6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12854
49930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1285449930
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.890167815
Short name T875
Test name
Test status
Simulation time 8457229313 ps
CPU time 7.85 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204444 kb
Host smart-e9005d55-6000-4f62-8af4-f59c42886cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89016
7815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.890167815
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2341903000
Short name T668
Test name
Test status
Simulation time 8372073350 ps
CPU time 8.67 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204516 kb
Host smart-1d626114-4730-45ae-b525-0eb4b8152e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23419
03000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2341903000
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1809197087
Short name T778
Test name
Test status
Simulation time 8411788469 ps
CPU time 8.72 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204476 kb
Host smart-1396dd0e-a523-44a7-8376-f7cc61bd9518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18091
97087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1809197087
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3644042817
Short name T510
Test name
Test status
Simulation time 8380790035 ps
CPU time 8.53 seconds
Started May 12 12:54:32 PM PDT 24
Finished May 12 12:54:41 PM PDT 24
Peak memory 204372 kb
Host smart-4ca64503-0a5a-43c2-8231-a015ac688b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
42817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3644042817
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1550897331
Short name T804
Test name
Test status
Simulation time 8386041770 ps
CPU time 7.71 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204524 kb
Host smart-e7afa4b5-37b5-459f-949b-f1f1a4c6cb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15508
97331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1550897331
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2146165915
Short name T1120
Test name
Test status
Simulation time 8367780289 ps
CPU time 8.27 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 204420 kb
Host smart-48f0e19a-69be-4d28-8bc5-c616a4acb221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21461
65915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2146165915
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.103794115
Short name T1166
Test name
Test status
Simulation time 35201148 ps
CPU time 0.63 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204468 kb
Host smart-0ea47b6b-faec-4330-8f76-3ce95398ffdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10379
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.103794115
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3799581498
Short name T1040
Test name
Test status
Simulation time 17281848274 ps
CPU time 31.76 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204944 kb
Host smart-5ffb32e4-b8bd-479d-9e55-e1548c9a9bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37995
81498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3799581498
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2511030485
Short name T613
Test name
Test status
Simulation time 8405432622 ps
CPU time 9.07 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 204464 kb
Host smart-a3c37a72-9cf4-478a-a768-09b7e42d81f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25110
30485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2511030485
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3975417392
Short name T1050
Test name
Test status
Simulation time 8381184300 ps
CPU time 9.9 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204428 kb
Host smart-76d5b934-c313-42d8-a75d-e07ba5b55a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
17392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3975417392
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3830887676
Short name T781
Test name
Test status
Simulation time 8416767083 ps
CPU time 7.52 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204432 kb
Host smart-e612f187-6356-4ebb-8de6-7d076a867474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
87676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3830887676
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4140680265
Short name T79
Test name
Test status
Simulation time 795178884 ps
CPU time 1.49 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 220752 kb
Host smart-aafa7d24-a85c-4a3f-b126-bdf6356554b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4140680265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4140680265
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3137553894
Short name T373
Test name
Test status
Simulation time 8435408398 ps
CPU time 8.4 seconds
Started May 12 12:54:33 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 204324 kb
Host smart-50dedb61-ee1e-42ca-bfc3-cec378ace2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31375
53894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3137553894
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1361431630
Short name T384
Test name
Test status
Simulation time 8365763115 ps
CPU time 8.72 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204756 kb
Host smart-c54281f1-e092-4f86-9c36-a3f61990dfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
31630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1361431630
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3235230204
Short name T1385
Test name
Test status
Simulation time 8467094223 ps
CPU time 7.85 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204368 kb
Host smart-d919297d-e0f7-4bd6-b9a1-705fed896086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32352
30204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3235230204
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.362233231
Short name T1302
Test name
Test status
Simulation time 8405211060 ps
CPU time 9.64 seconds
Started May 12 12:54:24 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 204496 kb
Host smart-f09e9018-8364-46a1-baba-031241a20616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36223
3231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.362233231
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.2526023002
Short name T1267
Test name
Test status
Simulation time 8465194647 ps
CPU time 9.42 seconds
Started May 12 12:55:09 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204408 kb
Host smart-fcc2aac1-d62a-47c3-97f7-472a9d341fca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2526023002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.2526023002
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2859536542
Short name T1433
Test name
Test status
Simulation time 8449778362 ps
CPU time 9.55 seconds
Started May 12 12:55:10 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204336 kb
Host smart-b54cfcdb-5273-4008-8b2b-dccf265cc371
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2859536542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2859536542
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.4032476037
Short name T342
Test name
Test status
Simulation time 8397571223 ps
CPU time 8.46 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204428 kb
Host smart-38df54a5-fa2c-460d-93cf-823e5014b6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40324
76037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.4032476037
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2299532063
Short name T990
Test name
Test status
Simulation time 8379377660 ps
CPU time 8.18 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204512 kb
Host smart-af0259b7-cdc1-4ef4-bc9d-4476e8a91269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22995
32063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2299532063
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3480760278
Short name T695
Test name
Test status
Simulation time 8455457201 ps
CPU time 11.93 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:15 PM PDT 24
Peak memory 204804 kb
Host smart-c15c9682-c798-450a-8e2e-559be593708a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34807
60278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3480760278
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3898252455
Short name T55
Test name
Test status
Simulation time 332716752 ps
CPU time 2.32 seconds
Started May 12 12:55:10 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204520 kb
Host smart-15473950-fd23-4994-8387-cd8d4c40c485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38982
52455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3898252455
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1441179423
Short name T1192
Test name
Test status
Simulation time 8421174224 ps
CPU time 8.33 seconds
Started May 12 12:55:15 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204340 kb
Host smart-c7534f57-f22b-4c10-b0c0-38259a3725d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
79423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1441179423
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3527646496
Short name T1126
Test name
Test status
Simulation time 8372015586 ps
CPU time 9.67 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 203816 kb
Host smart-a2e8e3bb-963f-4dc3-8785-7580060fa63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
46496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3527646496
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3927540260
Short name T747
Test name
Test status
Simulation time 8416594218 ps
CPU time 8.19 seconds
Started May 12 12:55:09 PM PDT 24
Finished May 12 12:55:18 PM PDT 24
Peak memory 204476 kb
Host smart-fa035e71-3ef8-454a-9569-9423f07fb3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
40260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3927540260
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.818867105
Short name T473
Test name
Test status
Simulation time 8369028833 ps
CPU time 8.56 seconds
Started May 12 12:55:10 PM PDT 24
Finished May 12 12:55:19 PM PDT 24
Peak memory 204332 kb
Host smart-c843ce89-a69f-49d8-9839-0098afac2c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81886
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.818867105
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3219529596
Short name T1352
Test name
Test status
Simulation time 8399011493 ps
CPU time 8.91 seconds
Started May 12 12:55:12 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204324 kb
Host smart-4dd3e20c-1249-4663-890b-78fcddc5671c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
29596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3219529596
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1380857068
Short name T1189
Test name
Test status
Simulation time 8418043918 ps
CPU time 8.26 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204412 kb
Host smart-30bf6dbc-d8c0-4fff-a057-ce9f170b31d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13808
57068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1380857068
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1051291598
Short name T171
Test name
Test status
Simulation time 8396375911 ps
CPU time 7.5 seconds
Started May 12 12:55:15 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204456 kb
Host smart-c3b5d644-da86-4cd9-ab4c-a73b57d25384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10512
91598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1051291598
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3550844941
Short name T413
Test name
Test status
Simulation time 8396492499 ps
CPU time 8.04 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204432 kb
Host smart-9aa36d40-98ca-4220-b1f9-d78b7e508cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508
44941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3550844941
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1125274558
Short name T1225
Test name
Test status
Simulation time 56397207 ps
CPU time 0.7 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204272 kb
Host smart-157e4944-a681-401f-98c5-50e1b5e352d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11252
74558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1125274558
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3503301398
Short name T660
Test name
Test status
Simulation time 16310508887 ps
CPU time 30.04 seconds
Started May 12 12:55:09 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204644 kb
Host smart-cc890980-a12a-41c9-a3f2-9159e146ec78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
01398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3503301398
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.948828493
Short name T714
Test name
Test status
Simulation time 8385217661 ps
CPU time 7.45 seconds
Started May 12 12:55:09 PM PDT 24
Finished May 12 12:55:18 PM PDT 24
Peak memory 204348 kb
Host smart-dc227d83-9ad2-4965-ab85-9236a368520f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94882
8493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.948828493
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3191498475
Short name T465
Test name
Test status
Simulation time 8398559674 ps
CPU time 8.44 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204560 kb
Host smart-4807a816-cac3-47d4-b93a-ad53d7dd74ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31914
98475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3191498475
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1463275417
Short name T862
Test name
Test status
Simulation time 8388267443 ps
CPU time 8.57 seconds
Started May 12 12:55:15 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204380 kb
Host smart-ec20428b-fc06-4def-a488-68b07c034476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14632
75417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1463275417
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2395139841
Short name T1376
Test name
Test status
Simulation time 8375831502 ps
CPU time 7.94 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204180 kb
Host smart-4d5dde3d-e120-40a7-8f07-4e3502cc52de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23951
39841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2395139841
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1165895512
Short name T185
Test name
Test status
Simulation time 8444062796 ps
CPU time 7.64 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204396 kb
Host smart-80eca2b1-0953-49bc-b414-32f1e1cf0064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11658
95512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1165895512
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3396266610
Short name T852
Test name
Test status
Simulation time 8413541472 ps
CPU time 8.75 seconds
Started May 12 12:55:08 PM PDT 24
Finished May 12 12:55:17 PM PDT 24
Peak memory 204408 kb
Host smart-66ab9fdc-c958-4f6a-a943-751ca675568d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33962
66610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3396266610
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.969041495
Short name T1239
Test name
Test status
Simulation time 8428673201 ps
CPU time 8.32 seconds
Started May 12 12:55:09 PM PDT 24
Finished May 12 12:55:17 PM PDT 24
Peak memory 204696 kb
Host smart-c79ad22b-5184-4bd8-a218-32bfd27a93e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96904
1495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.969041495
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.250670827
Short name T433
Test name
Test status
Simulation time 8460665684 ps
CPU time 7.59 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204464 kb
Host smart-24378a6d-cd9b-461e-8759-cc5d419c1af3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=250670827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.250670827
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.531415470
Short name T1066
Test name
Test status
Simulation time 8382772015 ps
CPU time 9.8 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204460 kb
Host smart-7daeac52-a3a4-4791-bead-06c430249f78
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=531415470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.531415470
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1929825454
Short name T1106
Test name
Test status
Simulation time 8376603005 ps
CPU time 7.7 seconds
Started May 12 12:55:19 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204756 kb
Host smart-55ad9f6a-f081-4de5-ac87-3eabf2c9de97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19298
25454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1929825454
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3907052330
Short name T501
Test name
Test status
Simulation time 8377731473 ps
CPU time 9.46 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204532 kb
Host smart-a186a915-0f76-4472-9830-b0b12eafb8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39070
52330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3907052330
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3865776866
Short name T35
Test name
Test status
Simulation time 8799829421 ps
CPU time 13.8 seconds
Started May 12 12:55:12 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 204632 kb
Host smart-870c42eb-c5ef-4c0c-8cd8-8e024e96f619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
76866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3865776866
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_enable.2224338558
Short name T492
Test name
Test status
Simulation time 8375647370 ps
CPU time 8.45 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204388 kb
Host smart-26e9df12-df8b-422f-9fdd-1db1a5763afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243
38558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2224338558
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2914012082
Short name T680
Test name
Test status
Simulation time 284236680 ps
CPU time 2.21 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:17 PM PDT 24
Peak memory 204576 kb
Host smart-c7aeb3e3-1eee-4f4a-a879-90493b7587b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29140
12082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2914012082
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1515356863
Short name T636
Test name
Test status
Simulation time 8383479697 ps
CPU time 7.8 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204340 kb
Host smart-08bcfbb7-6734-4f67-9a2d-af08428ff377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15153
56863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1515356863
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1341157465
Short name T559
Test name
Test status
Simulation time 8372059300 ps
CPU time 8.33 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204428 kb
Host smart-d3602200-8fd0-46f9-9acf-e589bf5b9c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
57465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1341157465
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.641328568
Short name T352
Test name
Test status
Simulation time 8483185569 ps
CPU time 7.93 seconds
Started May 12 12:55:12 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 204480 kb
Host smart-91591a87-3985-4b64-8580-ed4f4b197b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64132
8568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.641328568
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2873005386
Short name T773
Test name
Test status
Simulation time 8412891377 ps
CPU time 9 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204396 kb
Host smart-de80b087-d667-4074-a519-62d676617266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
05386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2873005386
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1452802101
Short name T922
Test name
Test status
Simulation time 8374463608 ps
CPU time 8.03 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204428 kb
Host smart-a4c6fe62-e190-4cc5-a085-f827334c54f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
02101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1452802101
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.717786811
Short name T483
Test name
Test status
Simulation time 8396466226 ps
CPU time 7.56 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204488 kb
Host smart-fca43b94-d97c-4910-9280-7532d53e4048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71778
6811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.717786811
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.150569778
Short name T1003
Test name
Test status
Simulation time 8403948603 ps
CPU time 8.43 seconds
Started May 12 12:55:16 PM PDT 24
Finished May 12 12:55:25 PM PDT 24
Peak memory 204336 kb
Host smart-dfb86125-fd76-4bb7-8de6-993b4872e873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15056
9778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.150569778
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2082129879
Short name T1419
Test name
Test status
Simulation time 8394266688 ps
CPU time 10.22 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:29 PM PDT 24
Peak memory 204420 kb
Host smart-53a2624f-0352-49fb-aff3-aff1e8be8c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20821
29879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2082129879
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1366983160
Short name T482
Test name
Test status
Simulation time 8368581219 ps
CPU time 7.89 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204464 kb
Host smart-0e4113b0-60dc-497d-83e9-2a2b880891e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
83160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1366983160
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.157759419
Short name T557
Test name
Test status
Simulation time 59922301 ps
CPU time 0.67 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204348 kb
Host smart-87eba4d9-017f-4a2c-8de8-984d6471d654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15775
9419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.157759419
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1998221489
Short name T880
Test name
Test status
Simulation time 8418392758 ps
CPU time 7.89 seconds
Started May 12 12:55:12 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 204380 kb
Host smart-ba01d234-26ef-45a4-bb3b-7353f8d9ae50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19982
21489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1998221489
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2744611278
Short name T711
Test name
Test status
Simulation time 8418514262 ps
CPU time 7.92 seconds
Started May 12 12:55:15 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204324 kb
Host smart-79f1295c-9777-4c4f-8a7b-c6bb9b42f695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27446
11278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2744611278
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2766427167
Short name T860
Test name
Test status
Simulation time 8423584135 ps
CPU time 8.01 seconds
Started May 12 12:55:15 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204520 kb
Host smart-502bccc7-828a-4277-b40b-32ed3f7cd564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27664
27167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2766427167
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2566171088
Short name T927
Test name
Test status
Simulation time 8415055140 ps
CPU time 9.03 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204372 kb
Host smart-86f3ee55-f44e-489f-8912-40d4d60d75cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25661
71088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2566171088
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.830751555
Short name T728
Test name
Test status
Simulation time 8373357999 ps
CPU time 8.56 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204484 kb
Host smart-81bbe6d2-8d5c-4ee4-af4e-dc4d9fa9d7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83075
1555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.830751555
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3851109757
Short name T838
Test name
Test status
Simulation time 8425328329 ps
CPU time 7.95 seconds
Started May 12 12:55:11 PM PDT 24
Finished May 12 12:55:20 PM PDT 24
Peak memory 204228 kb
Host smart-ff2b86cb-9125-4482-ac14-5a0cf181c80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38511
09757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3851109757
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3801983455
Short name T1204
Test name
Test status
Simulation time 8386693290 ps
CPU time 7.83 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204440 kb
Host smart-a5228af4-d3e0-4155-a128-a6badf75ec0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38019
83455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3801983455
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2747971037
Short name T1212
Test name
Test status
Simulation time 8431421648 ps
CPU time 8.67 seconds
Started May 12 12:55:13 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 204372 kb
Host smart-aa7a101b-efb9-4eac-967f-016f500066f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27479
71037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2747971037
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.1242423890
Short name T504
Test name
Test status
Simulation time 8481218006 ps
CPU time 7.97 seconds
Started May 12 12:55:20 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 204364 kb
Host smart-426629b1-c504-41b2-a492-092be51258d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1242423890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1242423890
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.3857454283
Short name T966
Test name
Test status
Simulation time 8387354417 ps
CPU time 10.11 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 204480 kb
Host smart-58a04fe4-acfd-425f-b86b-cab144bf8d41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3857454283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.3857454283
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.3375681343
Short name T560
Test name
Test status
Simulation time 8386315921 ps
CPU time 7.86 seconds
Started May 12 12:55:16 PM PDT 24
Finished May 12 12:55:25 PM PDT 24
Peak memory 204368 kb
Host smart-e7284aaa-8b79-4567-9f9d-0bf1ac305208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33756
81343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.3375681343
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3265605924
Short name T639
Test name
Test status
Simulation time 8374925010 ps
CPU time 8.71 seconds
Started May 12 12:55:14 PM PDT 24
Finished May 12 12:55:23 PM PDT 24
Peak memory 204488 kb
Host smart-1fbd0190-2d81-41e8-bc85-dc7d0c7f765b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32656
05924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3265605924
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1858690349
Short name T1372
Test name
Test status
Simulation time 8883550970 ps
CPU time 15.91 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:34 PM PDT 24
Peak memory 204684 kb
Host smart-15fd0d11-3969-4ac4-ac0a-e5b0b77d2a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18586
90349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1858690349
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_enable.1594576311
Short name T244
Test name
Test status
Simulation time 8414299058 ps
CPU time 8.2 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204396 kb
Host smart-047dd2c6-6bc2-47ea-9fb1-c31a1da2bc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15945
76311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1594576311
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1431716152
Short name T1242
Test name
Test status
Simulation time 125000002 ps
CPU time 1.73 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 204600 kb
Host smart-fc35d270-5b85-433f-985f-9456bfbb3c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14317
16152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1431716152
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.174799190
Short name T790
Test name
Test status
Simulation time 8457071446 ps
CPU time 9.63 seconds
Started May 12 12:55:21 PM PDT 24
Finished May 12 12:55:32 PM PDT 24
Peak memory 204428 kb
Host smart-d3a5f1f9-6de7-40c2-90e5-abbed9358465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
9190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.174799190
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.448521623
Short name T1328
Test name
Test status
Simulation time 8395704950 ps
CPU time 9.88 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 204408 kb
Host smart-38e62267-dd80-4fee-a8b8-c248756512b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44852
1623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.448521623
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1057445636
Short name T1088
Test name
Test status
Simulation time 8408145975 ps
CPU time 7.75 seconds
Started May 12 12:55:16 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204480 kb
Host smart-5209c591-1663-4a08-bed0-400267b328a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574
45636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1057445636
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3718961008
Short name T867
Test name
Test status
Simulation time 8382702374 ps
CPU time 8.86 seconds
Started May 12 12:55:20 PM PDT 24
Finished May 12 12:55:29 PM PDT 24
Peak memory 204480 kb
Host smart-0ec9231d-6f1a-4ad6-aba7-2e1ecea6a51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189
61008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3718961008
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3286525935
Short name T380
Test name
Test status
Simulation time 8387195187 ps
CPU time 7.65 seconds
Started May 12 12:55:23 PM PDT 24
Finished May 12 12:55:31 PM PDT 24
Peak memory 204456 kb
Host smart-d0bd19e7-0e4b-4907-9770-bb57a5e50e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
25935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3286525935
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2853003914
Short name T1426
Test name
Test status
Simulation time 8410778177 ps
CPU time 8.26 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204416 kb
Host smart-52de3c5d-14de-4803-84b7-8efea63eeffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28530
03914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2853003914
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.966654787
Short name T1081
Test name
Test status
Simulation time 8372855396 ps
CPU time 8.03 seconds
Started May 12 12:55:21 PM PDT 24
Finished May 12 12:55:30 PM PDT 24
Peak memory 204352 kb
Host smart-7c63ad78-70a2-4de6-955f-b7ae33e9028f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96665
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.966654787
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3220715392
Short name T573
Test name
Test status
Simulation time 44575809 ps
CPU time 0.68 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:19 PM PDT 24
Peak memory 204252 kb
Host smart-4110656a-dabf-4241-b7de-e4782cde9914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32207
15392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3220715392
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2692244505
Short name T14
Test name
Test status
Simulation time 15712271257 ps
CPU time 27.22 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:45 PM PDT 24
Peak memory 204684 kb
Host smart-72c9f83d-1996-4cd1-bc0d-85294437e7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26922
44505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2692244505
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2482443856
Short name T582
Test name
Test status
Simulation time 8408698393 ps
CPU time 8.46 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 204496 kb
Host smart-2b924537-c7e9-41ff-b1fa-2f25d7a33213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
43856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2482443856
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2116006426
Short name T585
Test name
Test status
Simulation time 8394343676 ps
CPU time 7.97 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204132 kb
Host smart-971614bf-354c-4f6d-9835-dd0555433828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
06426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2116006426
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.106021742
Short name T1422
Test name
Test status
Simulation time 8377757931 ps
CPU time 8.59 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204416 kb
Host smart-eb9ef1f7-44d5-454d-bdf4-f8ce113529f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10602
1742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.106021742
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.433889598
Short name T1358
Test name
Test status
Simulation time 8389842028 ps
CPU time 7.96 seconds
Started May 12 12:55:21 PM PDT 24
Finished May 12 12:55:30 PM PDT 24
Peak memory 204460 kb
Host smart-80ce6347-97bc-4afa-9043-0fb33d0895da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43388
9598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.433889598
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3793920168
Short name T666
Test name
Test status
Simulation time 8372660028 ps
CPU time 9.52 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 204532 kb
Host smart-cfaae12f-c8f2-4515-9877-44cd8a9731d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
20168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3793920168
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3174155556
Short name T525
Test name
Test status
Simulation time 8399098498 ps
CPU time 7.76 seconds
Started May 12 12:55:16 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204364 kb
Host smart-4aed05ed-b461-460c-9b16-44340910279d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31741
55556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3174155556
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4260286310
Short name T1069
Test name
Test status
Simulation time 8379065446 ps
CPU time 10.42 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204508 kb
Host smart-4424ee1d-394d-4c5f-937f-7f25eef8199a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42602
86310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4260286310
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3599479621
Short name T784
Test name
Test status
Simulation time 8428109225 ps
CPU time 7.56 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 204412 kb
Host smart-02cd5093-5672-40fb-9179-f6ef69d2406d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35994
79621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3599479621
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.65480794
Short name T979
Test name
Test status
Simulation time 8498030152 ps
CPU time 8.09 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204508 kb
Host smart-586a2279-7d21-4174-9ae0-3a35859d9b54
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=65480794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.65480794
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.3335503400
Short name T760
Test name
Test status
Simulation time 8376087277 ps
CPU time 7.97 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204452 kb
Host smart-aaf45546-ebf9-4576-8b40-6d969fc1794c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3335503400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.3335503400
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.533317165
Short name T523
Test name
Test status
Simulation time 8460156457 ps
CPU time 8.16 seconds
Started May 12 12:55:35 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204448 kb
Host smart-4f191ee6-5dd7-4e6b-9a31-f8626add483a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53331
7165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.533317165
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3255259655
Short name T92
Test name
Test status
Simulation time 8383285232 ps
CPU time 7.87 seconds
Started May 12 12:55:23 PM PDT 24
Finished May 12 12:55:32 PM PDT 24
Peak memory 204396 kb
Host smart-a5d7c21e-c80d-412b-93e5-672318c47de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32552
59655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3255259655
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2044336491
Short name T1321
Test name
Test status
Simulation time 9461564916 ps
CPU time 14.18 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:32 PM PDT 24
Peak memory 204640 kb
Host smart-dd57a739-6444-4430-adf4-0e2a6fd42709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
36491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2044336491
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_enable.583561983
Short name T1377
Test name
Test status
Simulation time 8378833483 ps
CPU time 7.73 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204440 kb
Host smart-330976b2-8fef-4a2e-b41e-5ce804784b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58356
1983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.583561983
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2858786221
Short name T54
Test name
Test status
Simulation time 74141527 ps
CPU time 1.17 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:31 PM PDT 24
Peak memory 204180 kb
Host smart-c3735a37-5d2e-4d79-aa2d-fb2e7de4e9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28587
86221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2858786221
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.904937752
Short name T1403
Test name
Test status
Simulation time 8460530448 ps
CPU time 10.19 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204496 kb
Host smart-1fec5ebb-b6e4-4102-9dde-71d2c060f601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90493
7752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.904937752
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1728048469
Short name T936
Test name
Test status
Simulation time 8383367836 ps
CPU time 7.82 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 204428 kb
Host smart-2621c8d3-d8e2-42d9-a4a4-6fc04280d004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17280
48469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1728048469
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2817903680
Short name T158
Test name
Test status
Simulation time 8433146125 ps
CPU time 9.05 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 204400 kb
Host smart-2e958687-0e9b-43b8-ad65-8f91285e7927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28179
03680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2817903680
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.44337171
Short name T809
Test name
Test status
Simulation time 8414214015 ps
CPU time 8.07 seconds
Started May 12 12:55:21 PM PDT 24
Finished May 12 12:55:29 PM PDT 24
Peak memory 204360 kb
Host smart-38cb54c6-f703-4f76-82c3-ab2b1b42ca77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44337
171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.44337171
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2846455716
Short name T1061
Test name
Test status
Simulation time 8373788728 ps
CPU time 7.56 seconds
Started May 12 12:55:21 PM PDT 24
Finished May 12 12:55:29 PM PDT 24
Peak memory 204352 kb
Host smart-aa675a05-e388-4fb4-bbe7-66560048eb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28464
55716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2846455716
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.4137274352
Short name T808
Test name
Test status
Simulation time 8398909000 ps
CPU time 7.67 seconds
Started May 12 12:55:20 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 204676 kb
Host smart-080783c3-e028-4325-8ec9-ef0c3f44542a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
74352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.4137274352
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3076686478
Short name T1136
Test name
Test status
Simulation time 8415800268 ps
CPU time 9.27 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 204440 kb
Host smart-37e34e3e-0152-428c-8096-79515500acb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30766
86478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3076686478
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3568108387
Short name T269
Test name
Test status
Simulation time 8374516355 ps
CPU time 8.52 seconds
Started May 12 12:55:22 PM PDT 24
Finished May 12 12:55:31 PM PDT 24
Peak memory 204516 kb
Host smart-6ea003ef-11f0-4c86-8cfb-d9d206e1b9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681
08387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3568108387
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1244489814
Short name T37
Test name
Test status
Simulation time 99924746 ps
CPU time 0.73 seconds
Started May 12 12:55:23 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 204460 kb
Host smart-d065ee44-e4af-46d5-8e99-754e6c21e429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12444
89814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1244489814
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3494615509
Short name T302
Test name
Test status
Simulation time 22731093216 ps
CPU time 44.1 seconds
Started May 12 12:55:17 PM PDT 24
Finished May 12 12:56:02 PM PDT 24
Peak memory 204720 kb
Host smart-f17c6c5e-0f4a-4498-8d8c-5dc6fcd94eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
15509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3494615509
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.900270848
Short name T1424
Test name
Test status
Simulation time 8419739312 ps
CPU time 7.66 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204396 kb
Host smart-1cd91ed2-d1d8-4b7d-a428-a5fae2effadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90027
0848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.900270848
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2118045793
Short name T1297
Test name
Test status
Simulation time 8420656009 ps
CPU time 10.23 seconds
Started May 12 12:55:23 PM PDT 24
Finished May 12 12:55:34 PM PDT 24
Peak memory 204456 kb
Host smart-e328577c-50ac-46ea-8b6c-72fe3817f79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
45793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2118045793
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.122668196
Short name T1125
Test name
Test status
Simulation time 8395343834 ps
CPU time 7.47 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204484 kb
Host smart-56a885d7-8575-4c82-b6ff-1ecce14352e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12266
8196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.122668196
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4273000982
Short name T428
Test name
Test status
Simulation time 8387831553 ps
CPU time 7.86 seconds
Started May 12 12:55:18 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 204456 kb
Host smart-cedcccf6-d6ff-4d8a-b070-753351c3c57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
00982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4273000982
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.108327202
Short name T298
Test name
Test status
Simulation time 8377816123 ps
CPU time 9.21 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204388 kb
Host smart-e31c5127-96c2-435c-ba2f-947dd04166ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10832
7202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.108327202
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1963699336
Short name T561
Test name
Test status
Simulation time 8405407721 ps
CPU time 7.9 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204384 kb
Host smart-f34986a6-e205-415d-9741-9f65c7643789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19636
99336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1963699336
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3402567950
Short name T506
Test name
Test status
Simulation time 8455800425 ps
CPU time 8.11 seconds
Started May 12 12:55:22 PM PDT 24
Finished May 12 12:55:31 PM PDT 24
Peak memory 204380 kb
Host smart-27c6c33f-a056-4d7e-8e17-e199df699987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
67950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3402567950
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.1496865532
Short name T732
Test name
Test status
Simulation time 8510854365 ps
CPU time 9.77 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204420 kb
Host smart-8a518119-cd51-41dd-88a2-63abb0337c8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1496865532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.1496865532
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.4127296768
Short name T1207
Test name
Test status
Simulation time 8378393740 ps
CPU time 8.09 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204544 kb
Host smart-e2cae062-a63e-4de9-9eea-85ac077b63e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4127296768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.4127296768
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.1552450598
Short name T467
Test name
Test status
Simulation time 8446966391 ps
CPU time 7.67 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204496 kb
Host smart-fdc6e494-bfc0-4ae3-b841-e333ac407084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
50598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.1552450598
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1847458087
Short name T765
Test name
Test status
Simulation time 8373187440 ps
CPU time 8.12 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204004 kb
Host smart-5dd3dad3-383d-4da7-89af-2e0ad350739b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18474
58087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1847458087
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2278143944
Short name T210
Test name
Test status
Simulation time 8467697789 ps
CPU time 11.92 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204660 kb
Host smart-4317dffb-f969-4da9-8d26-5bd53beee604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
43944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2278143944
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_enable.1721364502
Short name T893
Test name
Test status
Simulation time 8371621735 ps
CPU time 9.65 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204344 kb
Host smart-84a6ec6b-90c6-44bb-a3d1-0793b9095064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17213
64502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1721364502
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.573871020
Short name T417
Test name
Test status
Simulation time 288296365 ps
CPU time 2.24 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:30 PM PDT 24
Peak memory 204456 kb
Host smart-ca6c6a5d-4866-429b-98cb-2aca544af1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57387
1020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.573871020
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1867736502
Short name T1107
Test name
Test status
Simulation time 8420686370 ps
CPU time 10.25 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204100 kb
Host smart-8bd21f0d-bbc8-4679-9b04-3608285162fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18677
36502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1867736502
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.809429403
Short name T1167
Test name
Test status
Simulation time 8370443577 ps
CPU time 9.83 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204212 kb
Host smart-400dd8e0-c73d-47c3-b5ff-f9786ed0fc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80942
9403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.809429403
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2223115177
Short name T1053
Test name
Test status
Simulation time 8457271830 ps
CPU time 8.14 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204460 kb
Host smart-e69ac8b3-a613-409b-8ab2-0acb55280d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22231
15177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2223115177
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1231259305
Short name T388
Test name
Test status
Simulation time 8417102002 ps
CPU time 8.32 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204504 kb
Host smart-aa6b013b-2324-46b7-bc37-da5d25cac501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
59305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1231259305
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3636932157
Short name T354
Test name
Test status
Simulation time 8364855148 ps
CPU time 8.22 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204332 kb
Host smart-5f65b8ed-2526-40e3-93e9-17b26f5b07de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36369
32157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3636932157
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2751837578
Short name T1406
Test name
Test status
Simulation time 8411962597 ps
CPU time 7.77 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204372 kb
Host smart-6ba8061b-adc2-4095-bde4-a17049200abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27518
37578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2751837578
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3242224679
Short name T671
Test name
Test status
Simulation time 8431398390 ps
CPU time 7.74 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204368 kb
Host smart-6db4a6b9-8662-4fbc-8532-fea2935f2f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
24679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3242224679
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1591005929
Short name T1374
Test name
Test status
Simulation time 8373599969 ps
CPU time 8.57 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204428 kb
Host smart-3f1e8bcb-c010-40cb-ab87-66a3c6b3769d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15910
05929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1591005929
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3268238636
Short name T487
Test name
Test status
Simulation time 42361608 ps
CPU time 0.64 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:55:30 PM PDT 24
Peak memory 204356 kb
Host smart-72bc8935-9659-42e0-8d08-aa173657f2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32682
38636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3268238636
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2370147257
Short name T674
Test name
Test status
Simulation time 27703042680 ps
CPU time 55.97 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:56:25 PM PDT 24
Peak memory 204740 kb
Host smart-0cf8a225-0c85-4320-b120-498d7fccfa5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23701
47257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2370147257
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3038090338
Short name T1103
Test name
Test status
Simulation time 8418073581 ps
CPU time 7.81 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204416 kb
Host smart-3582e63e-249a-490d-89ed-3aad82b6d220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30380
90338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3038090338
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2554917734
Short name T673
Test name
Test status
Simulation time 8441228859 ps
CPU time 7.71 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204316 kb
Host smart-86058319-0420-4fb5-9d04-55d076b7a35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
17734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2554917734
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2551096180
Short name T1199
Test name
Test status
Simulation time 8390592801 ps
CPU time 8.4 seconds
Started May 12 12:55:22 PM PDT 24
Finished May 12 12:55:31 PM PDT 24
Peak memory 204424 kb
Host smart-4de95023-5324-4c2f-b494-0b8d0fc4633d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
96180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2551096180
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3372192726
Short name T724
Test name
Test status
Simulation time 8373124828 ps
CPU time 8.17 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204456 kb
Host smart-be6f8ddc-c6f4-4fa0-a33f-41720732d04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
92726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3372192726
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1697604813
Short name T461
Test name
Test status
Simulation time 8385581663 ps
CPU time 8.35 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204320 kb
Host smart-32b195b6-728e-49af-b74f-b950ec8ffb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
04813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1697604813
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.683131437
Short name T866
Test name
Test status
Simulation time 8420459550 ps
CPU time 7.82 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204424 kb
Host smart-66c16e12-d0fa-4fc7-9e60-8944ed74de55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68313
1437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.683131437
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3700739551
Short name T527
Test name
Test status
Simulation time 8392969295 ps
CPU time 8.18 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 204532 kb
Host smart-e62b3d78-21ed-4aa6-ba69-93f52d49ec46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37007
39551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3700739551
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1677201530
Short name T828
Test name
Test status
Simulation time 8470454913 ps
CPU time 8.23 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204368 kb
Host smart-b46add51-db75-4dca-98d5-04807aae9fae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1677201530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1677201530
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.3184670967
Short name T1200
Test name
Test status
Simulation time 8385322216 ps
CPU time 8.36 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204392 kb
Host smart-23bcdcf6-5a5b-4632-99a6-0637de6dd93b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3184670967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.3184670967
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.87230058
Short name T953
Test name
Test status
Simulation time 8384785456 ps
CPU time 8.51 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204404 kb
Host smart-564a5b32-2ee3-4c93-b3a2-35d94f334eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87230
058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.87230058
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.753870329
Short name T679
Test name
Test status
Simulation time 8375744652 ps
CPU time 7.97 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:34 PM PDT 24
Peak memory 204340 kb
Host smart-5a7efb07-0cc2-4a18-adbf-edbdc0db5c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75387
0329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.753870329
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3713644767
Short name T1421
Test name
Test status
Simulation time 9076055211 ps
CPU time 13.02 seconds
Started May 12 12:55:23 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204744 kb
Host smart-95e45409-c388-427d-964e-30d41835d5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37136
44767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3713644767
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_enable.1095724879
Short name T511
Test name
Test status
Simulation time 8380217667 ps
CPU time 8.1 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:34 PM PDT 24
Peak memory 204524 kb
Host smart-5d40f798-3b7f-4ed1-8115-38bad47469e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
24879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1095724879
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3282723332
Short name T251
Test name
Test status
Simulation time 162505778 ps
CPU time 1.84 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204540 kb
Host smart-f52792e9-b76a-4b3d-9773-01b6a9b8d32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32827
23332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3282723332
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2241282231
Short name T1030
Test name
Test status
Simulation time 8391856586 ps
CPU time 7.99 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204376 kb
Host smart-e8ca9cbd-b025-4431-90bc-b86cabf3d124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
82231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2241282231
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.181636655
Short name T701
Test name
Test status
Simulation time 8377506628 ps
CPU time 7.51 seconds
Started May 12 12:55:26 PM PDT 24
Finished May 12 12:55:35 PM PDT 24
Peak memory 204416 kb
Host smart-f62c5d54-2837-4dd5-b567-66e77aa87350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18163
6655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.181636655
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4272096788
Short name T556
Test name
Test status
Simulation time 8436429857 ps
CPU time 7.79 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 204428 kb
Host smart-329444ce-3d7f-4e1f-9306-db19de6eb9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42720
96788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4272096788
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.834031797
Short name T360
Test name
Test status
Simulation time 8412095958 ps
CPU time 9.72 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204440 kb
Host smart-ee240a5a-c2e3-4854-8bde-f711fd3a76f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83403
1797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.834031797
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.4152754193
Short name T490
Test name
Test status
Simulation time 8368422735 ps
CPU time 9.75 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204432 kb
Host smart-0bc33661-8f5e-41dd-a856-d7e198d2484f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41527
54193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.4152754193
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.747194625
Short name T361
Test name
Test status
Simulation time 8388020562 ps
CPU time 7.72 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204332 kb
Host smart-54d70bb1-bebb-47c4-84a8-c2bbf9543f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74719
4625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.747194625
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.897660647
Short name T544
Test name
Test status
Simulation time 8418895753 ps
CPU time 8.25 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204392 kb
Host smart-c2d84ea9-249b-4863-9996-5a9a3f442592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89766
0647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.897660647
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.771708876
Short name T1329
Test name
Test status
Simulation time 8369154235 ps
CPU time 8.26 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204420 kb
Host smart-24d63205-e0d3-44dd-914e-03e6b4aa6cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77170
8876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.771708876
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1018754319
Short name T1178
Test name
Test status
Simulation time 71025234 ps
CPU time 0.65 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:33 PM PDT 24
Peak memory 204356 kb
Host smart-06410bc7-3f49-476a-a704-7227543724ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
54319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1018754319
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1385662266
Short name T1340
Test name
Test status
Simulation time 27015338282 ps
CPU time 55.7 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204524 kb
Host smart-06f91515-9dc7-47d3-a9bc-67df9bcf1790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
62266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1385662266
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.260915216
Short name T600
Test name
Test status
Simulation time 8396409578 ps
CPU time 8.45 seconds
Started May 12 12:55:36 PM PDT 24
Finished May 12 12:55:45 PM PDT 24
Peak memory 204496 kb
Host smart-18fc3cde-d971-43e4-bdd3-993f681f33f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26091
5216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.260915216
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1973272089
Short name T696
Test name
Test status
Simulation time 8434630457 ps
CPU time 8.01 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204288 kb
Host smart-e5ff796a-c103-4ffb-b454-bfb3cf27bbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19732
72089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1973272089
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.349405825
Short name T488
Test name
Test status
Simulation time 8401820934 ps
CPU time 7.7 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 204548 kb
Host smart-e4472933-9af4-406e-ad9e-1d569a0068eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940
5825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.349405825
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2411572614
Short name T1213
Test name
Test status
Simulation time 8388092583 ps
CPU time 9.91 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:49 PM PDT 24
Peak memory 204456 kb
Host smart-d77a2f84-4ce9-44b7-b3d2-690f9ab3aff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
72614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2411572614
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3085748451
Short name T1158
Test name
Test status
Simulation time 8397432081 ps
CPU time 7.42 seconds
Started May 12 12:55:28 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204324 kb
Host smart-32911491-f7cf-4622-a293-c04634fb20fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
48451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3085748451
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1242470186
Short name T933
Test name
Test status
Simulation time 8401060461 ps
CPU time 7.72 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204412 kb
Host smart-09ad7422-26f9-4d55-aa2e-c6d83685ec14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
70186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1242470186
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.1812136563
Short name T725
Test name
Test status
Simulation time 8465129629 ps
CPU time 8.43 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204412 kb
Host smart-3e668cbf-f317-40f2-b4f9-9e11d1f9c96d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1812136563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.1812136563
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.3164533503
Short name T627
Test name
Test status
Simulation time 8392339283 ps
CPU time 7.85 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204448 kb
Host smart-9e3ba48a-759e-4952-93c8-be4a1dabf964
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3164533503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.3164533503
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.3072452280
Short name T587
Test name
Test status
Simulation time 8414597928 ps
CPU time 9.02 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204444 kb
Host smart-d85eff29-e331-4595-b7e9-318159fba5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
52280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.3072452280
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3790117251
Short name T502
Test name
Test status
Simulation time 8408186997 ps
CPU time 8.03 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204532 kb
Host smart-a93d7e12-1765-47f2-b356-a06724bbe228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37901
17251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3790117251
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.1255754347
Short name T50
Test name
Test status
Simulation time 8375207677 ps
CPU time 7.65 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 204468 kb
Host smart-f7474bc6-a7a1-4091-968e-1af2d71bde15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12557
54347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1255754347
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3242995858
Short name T403
Test name
Test status
Simulation time 211948041 ps
CPU time 2.05 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 204536 kb
Host smart-0fadfdc9-a17a-405d-9cbf-ec383c9fe2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
95858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3242995858
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2989529841
Short name T749
Test name
Test status
Simulation time 8414076552 ps
CPU time 7.99 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 204352 kb
Host smart-9affd6a8-1b36-4e5d-b64f-49462a0d9fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29895
29841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2989529841
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.979286580
Short name T1065
Test name
Test status
Simulation time 8429907944 ps
CPU time 8.34 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204452 kb
Host smart-bc1f08db-7500-4d0f-b1b0-976e1eebdba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97928
6580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.979286580
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2828625105
Short name T689
Test name
Test status
Simulation time 8417094699 ps
CPU time 9.59 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204384 kb
Host smart-4440aea5-a7f7-4920-b5df-185577bec7dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
25105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2828625105
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.4262750246
Short name T596
Test name
Test status
Simulation time 8383597140 ps
CPU time 7.97 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204476 kb
Host smart-593d5d3a-716f-4074-8f9c-143b2a91ecc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42627
50246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.4262750246
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1644872553
Short name T119
Test name
Test status
Simulation time 8477519755 ps
CPU time 8.61 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204416 kb
Host smart-48f85f72-7f54-46dc-9fd3-ae3ae1611305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16448
72553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1644872553
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1134309345
Short name T1151
Test name
Test status
Simulation time 8484177216 ps
CPU time 8.83 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204384 kb
Host smart-77094a72-4e12-47b2-bb06-dd4ffcdab5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11343
09345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1134309345
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1392032522
Short name T1070
Test name
Test status
Simulation time 8404713892 ps
CPU time 8.24 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:46 PM PDT 24
Peak memory 204504 kb
Host smart-69371c73-e13e-4cb6-9f3d-e1de95405b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13920
32522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1392032522
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2134914566
Short name T631
Test name
Test status
Simulation time 8372937521 ps
CPU time 8.04 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 204460 kb
Host smart-0d157c5a-3322-4963-8c76-671e507f4fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
14566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2134914566
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3665909283
Short name T973
Test name
Test status
Simulation time 52001201 ps
CPU time 0.73 seconds
Started May 12 12:55:37 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204472 kb
Host smart-6765867a-cc39-4fd2-84b1-327c9e0a8f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659
09283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3665909283
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3289500305
Short name T100
Test name
Test status
Simulation time 21805410191 ps
CPU time 41.92 seconds
Started May 12 12:55:29 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204652 kb
Host smart-e91dbc8d-34af-4d48-8061-17c7f4afd7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32895
00305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3289500305
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3105339881
Short name T708
Test name
Test status
Simulation time 8397766909 ps
CPU time 7.72 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204452 kb
Host smart-1c1631ce-d137-4f8f-9e74-a9f332d2ac5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31053
39881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3105339881
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1627056612
Short name T153
Test name
Test status
Simulation time 8385079144 ps
CPU time 8.79 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:40 PM PDT 24
Peak memory 204444 kb
Host smart-1fa44fed-f18d-4773-ad17-64ff98c27bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270
56612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1627056612
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3796720911
Short name T989
Test name
Test status
Simulation time 8381527609 ps
CPU time 9.33 seconds
Started May 12 12:55:27 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 204436 kb
Host smart-4960bdae-3cd8-4f2f-b225-cf7fee0d29a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967
20911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3796720911
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3408052452
Short name T726
Test name
Test status
Simulation time 8407616238 ps
CPU time 9.15 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204416 kb
Host smart-f7bd156b-5558-45b5-b336-6aef47462c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34080
52452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3408052452
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.270885658
Short name T391
Test name
Test status
Simulation time 8371248754 ps
CPU time 8.81 seconds
Started May 12 12:55:35 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 204420 kb
Host smart-118fb837-ba89-4fc0-a4b8-db8715d96a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
5658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.270885658
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3748111792
Short name T975
Test name
Test status
Simulation time 8439155890 ps
CPU time 7.84 seconds
Started May 12 12:55:34 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204456 kb
Host smart-55d903fa-c053-44e9-96cc-ffc49248581e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37481
11792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3748111792
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.484430576
Short name T733
Test name
Test status
Simulation time 8472761578 ps
CPU time 9.25 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204336 kb
Host smart-ba2fed37-6130-4d2d-ab2e-4fffc13ef8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48443
0576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.484430576
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2569863149
Short name T486
Test name
Test status
Simulation time 8407744196 ps
CPU time 9.62 seconds
Started May 12 12:55:30 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204416 kb
Host smart-27c70896-ba64-449b-9149-fad426932939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25698
63149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2569863149
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.4083954327
Short name T143
Test name
Test status
Simulation time 8484489200 ps
CPU time 8.28 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204436 kb
Host smart-61073d1a-ddfe-400c-8fe6-5467637f2c57
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4083954327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.4083954327
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2995344112
Short name T370
Test name
Test status
Simulation time 8379031079 ps
CPU time 8 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204452 kb
Host smart-e003679c-1bf7-4b38-8797-95c46b46157e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2995344112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2995344112
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.1177286158
Short name T481
Test name
Test status
Simulation time 8448258437 ps
CPU time 9.37 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204428 kb
Host smart-9a2e927e-d78c-4eb4-855a-7017855ae6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11772
86158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.1177286158
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3643860603
Short name T336
Test name
Test status
Simulation time 8373219859 ps
CPU time 9.22 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204396 kb
Host smart-7e45d625-fe24-4b12-94ae-633f599a9c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36438
60603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3643860603
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.346397655
Short name T217
Test name
Test status
Simulation time 9147636419 ps
CPU time 13.23 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:55 PM PDT 24
Peak memory 204620 kb
Host smart-22bc86a5-eba1-4471-b438-7a85ca95e445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34639
7655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.346397655
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_enable.1836776477
Short name T931
Test name
Test status
Simulation time 8447066663 ps
CPU time 7.7 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204476 kb
Host smart-b74f1a7f-3b45-48a8-8ec5-caa1b6363824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18367
76477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1836776477
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.475697511
Short name T722
Test name
Test status
Simulation time 8468619326 ps
CPU time 8.5 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204460 kb
Host smart-18e59838-a36e-455b-8bd6-43db48001980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47569
7511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.475697511
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.584211367
Short name T1075
Test name
Test status
Simulation time 8414070171 ps
CPU time 7.98 seconds
Started May 12 12:55:49 PM PDT 24
Finished May 12 12:55:58 PM PDT 24
Peak memory 204428 kb
Host smart-63b40c7e-f1c6-4e2c-8456-cda93f6118f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58421
1367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.584211367
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3966859276
Short name T780
Test name
Test status
Simulation time 8370475781 ps
CPU time 8.78 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 204484 kb
Host smart-42ce91a2-aa09-466b-b257-5cc71f49cfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39668
59276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3966859276
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3882173125
Short name T109
Test name
Test status
Simulation time 8458389771 ps
CPU time 9.08 seconds
Started May 12 12:55:53 PM PDT 24
Finished May 12 12:56:03 PM PDT 24
Peak memory 204416 kb
Host smart-3d36310c-0ba8-42ee-b306-f676a1a0206d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38821
73125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3882173125
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2564418156
Short name T764
Test name
Test status
Simulation time 8423664467 ps
CPU time 10.45 seconds
Started May 12 12:55:53 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204416 kb
Host smart-fd412d7a-e454-4a7e-b5df-d990666887dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
18156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2564418156
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.686213133
Short name T842
Test name
Test status
Simulation time 8410666218 ps
CPU time 10.1 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204436 kb
Host smart-afc1196d-5cac-4331-bd8d-dd03247f3468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68621
3133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.686213133
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2151956300
Short name T1244
Test name
Test status
Simulation time 8419689717 ps
CPU time 7.44 seconds
Started May 12 12:55:52 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204412 kb
Host smart-6e62ba93-f2f7-4fcc-b071-9e39b1165d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21519
56300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2151956300
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2621939060
Short name T1014
Test name
Test status
Simulation time 102322418 ps
CPU time 0.71 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:35 PM PDT 24
Peak memory 204432 kb
Host smart-0f8670ac-4345-4ec1-ac56-8fade4bc327b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26219
39060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2621939060
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.968073025
Short name T273
Test name
Test status
Simulation time 15877923545 ps
CPU time 32.15 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:56:05 PM PDT 24
Peak memory 204940 kb
Host smart-6d8ba0b9-accf-4688-a045-4ae9ab6f3154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96807
3025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.968073025
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1292319835
Short name T1168
Test name
Test status
Simulation time 8375892646 ps
CPU time 7.82 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204756 kb
Host smart-d3198f66-e906-4908-b4fd-5e79c59fd0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
19835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1292319835
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.527986270
Short name T937
Test name
Test status
Simulation time 8425791308 ps
CPU time 7.55 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204380 kb
Host smart-91805acc-895e-4260-9460-cf0f3c2fde0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52798
6270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.527986270
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.3685910599
Short name T584
Test name
Test status
Simulation time 8401882532 ps
CPU time 8.22 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204464 kb
Host smart-b278a534-94d0-4128-8324-83d7bc400b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
10599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.3685910599
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.4286984630
Short name T169
Test name
Test status
Simulation time 8390820249 ps
CPU time 7.42 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 204372 kb
Host smart-d51ca28e-298e-4fb7-a1f9-7fed9f17aa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42869
84630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.4286984630
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3225080681
Short name T552
Test name
Test status
Simulation time 8371861885 ps
CPU time 7.53 seconds
Started May 12 12:55:35 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204452 kb
Host smart-cb1ed00e-e741-453e-94eb-ee94000378a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
80681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3225080681
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.803581977
Short name T1005
Test name
Test status
Simulation time 8449967971 ps
CPU time 8.95 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204472 kb
Host smart-6eaaabf1-c6dc-441a-9cfd-e025a649864d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80358
1977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.803581977
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4135713374
Short name T1022
Test name
Test status
Simulation time 8418199864 ps
CPU time 9.3 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 204748 kb
Host smart-93761ed0-a9da-4641-b883-e8b531fbd3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
13374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.4135713374
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.199692909
Short name T371
Test name
Test status
Simulation time 8389806011 ps
CPU time 7.59 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204412 kb
Host smart-1b0ac602-91a3-404f-937c-a7a4500a9cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19969
2909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.199692909
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.748605097
Short name T485
Test name
Test status
Simulation time 8463128012 ps
CPU time 7.9 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204380 kb
Host smart-53d00d07-c626-4c26-a355-f80feb056627
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=748605097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.748605097
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.4055273565
Short name T805
Test name
Test status
Simulation time 8404506018 ps
CPU time 7.49 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 204420 kb
Host smart-4a34f429-6fcb-412f-8ebc-ce6cc5e7b7af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4055273565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.4055273565
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.3481648727
Short name T1229
Test name
Test status
Simulation time 8460135381 ps
CPU time 9.39 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 204428 kb
Host smart-40d85426-bdf6-47f2-82af-59d63f54c9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34816
48727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.3481648727
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.133281350
Short name T376
Test name
Test status
Simulation time 8393076568 ps
CPU time 8.09 seconds
Started May 12 12:55:37 PM PDT 24
Finished May 12 12:55:45 PM PDT 24
Peak memory 204488 kb
Host smart-fbb6ef88-41b2-49e5-aa1f-a9cb4e1ffe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13328
1350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.133281350
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2953467297
Short name T898
Test name
Test status
Simulation time 8542357628 ps
CPU time 12.23 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204664 kb
Host smart-29a1db0d-1736-4657-9518-ef37232e2dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
67297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2953467297
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_enable.429880470
Short name T270
Test name
Test status
Simulation time 8402475896 ps
CPU time 7.88 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204396 kb
Host smart-2ca2dd48-5613-4563-98e5-63569d9f656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42988
0470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.429880470
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2578024641
Short name T735
Test name
Test status
Simulation time 187770679 ps
CPU time 1.91 seconds
Started May 12 12:55:31 PM PDT 24
Finished May 12 12:55:34 PM PDT 24
Peak memory 204568 kb
Host smart-a8d8e159-4bd8-411c-b53f-3c4bf0784c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25780
24641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2578024641
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3015984173
Short name T1410
Test name
Test status
Simulation time 8407215263 ps
CPU time 7.62 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:49 PM PDT 24
Peak memory 204340 kb
Host smart-18db5766-c7cc-44c3-a27a-9fdacff30262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
84173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3015984173
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2662457477
Short name T1319
Test name
Test status
Simulation time 8366500091 ps
CPU time 8.1 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:49 PM PDT 24
Peak memory 204460 kb
Host smart-1f5aa8f7-20f2-434a-8dce-537e3d843b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
57477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2662457477
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2272625469
Short name T946
Test name
Test status
Simulation time 8389695264 ps
CPU time 7.5 seconds
Started May 12 12:55:32 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 204436 kb
Host smart-774ad60b-3790-4b87-aea3-caa6581cbc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22726
25469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2272625469
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.170660962
Short name T1209
Test name
Test status
Simulation time 8423989900 ps
CPU time 10.26 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 204552 kb
Host smart-07b03314-ae14-420f-8945-a44626816139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
0962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.170660962
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3988876542
Short name T513
Test name
Test status
Simulation time 8372321514 ps
CPU time 7.67 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204524 kb
Host smart-9d688acf-0eea-4965-9247-d4dc890c900b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39888
76542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3988876542
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2949888542
Short name T2
Test name
Test status
Simulation time 8404232028 ps
CPU time 7.59 seconds
Started May 12 12:55:52 PM PDT 24
Finished May 12 12:56:01 PM PDT 24
Peak memory 204412 kb
Host smart-41a76659-5a6e-4331-8703-ad5730d2d2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
88542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2949888542
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1177161363
Short name T451
Test name
Test status
Simulation time 8390834948 ps
CPU time 10.1 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 204380 kb
Host smart-a472b33b-5a4d-4ee4-9363-fcf7d4535a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11771
61363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1177161363
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1729981478
Short name T1211
Test name
Test status
Simulation time 8421858464 ps
CPU time 9.01 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204428 kb
Host smart-3379e553-b8c8-4cce-8137-339017f58379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17299
81478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1729981478
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1178127641
Short name T188
Test name
Test status
Simulation time 8398277283 ps
CPU time 7.76 seconds
Started May 12 12:55:48 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 204460 kb
Host smart-1467b17c-25d4-498d-8d46-27ac02e06589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
27641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1178127641
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1219448873
Short name T1024
Test name
Test status
Simulation time 8376295580 ps
CPU time 7.81 seconds
Started May 12 12:55:52 PM PDT 24
Finished May 12 12:56:01 PM PDT 24
Peak memory 204420 kb
Host smart-686ce3d2-55a4-4acb-8a70-7e2aa3984b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12194
48873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1219448873
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3675211559
Short name T46
Test name
Test status
Simulation time 54452104 ps
CPU time 0.72 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 204692 kb
Host smart-639b7273-a1d4-41f1-af1e-3922407eae5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
11559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3675211559
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.47898925
Short name T97
Test name
Test status
Simulation time 30115547175 ps
CPU time 58.49 seconds
Started May 12 12:55:34 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204724 kb
Host smart-363af64a-9aea-46b3-a774-f39d42bb539f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47898
925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.47898925
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2559520672
Short name T632
Test name
Test status
Simulation time 8424536755 ps
CPU time 8.02 seconds
Started May 12 12:55:38 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204536 kb
Host smart-e1377dae-f0a3-4902-a19c-74479c00a2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25595
20672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2559520672
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4207627399
Short name T1255
Test name
Test status
Simulation time 8450618853 ps
CPU time 8.59 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204372 kb
Host smart-9df547b8-ea9f-4b4a-977a-53c877753b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
27399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4207627399
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2243740918
Short name T349
Test name
Test status
Simulation time 8436979680 ps
CPU time 7.7 seconds
Started May 12 12:55:36 PM PDT 24
Finished May 12 12:55:45 PM PDT 24
Peak memory 204788 kb
Host smart-542643a9-3f0a-4670-9b1b-e3e6a0c5541f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
40918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2243740918
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3876175831
Short name T445
Test name
Test status
Simulation time 8418820135 ps
CPU time 8.58 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:49 PM PDT 24
Peak memory 204380 kb
Host smart-31b0cc80-a8fb-44c5-abbd-bc6e2aecb381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38761
75831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3876175831
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3731733879
Short name T531
Test name
Test status
Simulation time 8385625254 ps
CPU time 7.53 seconds
Started May 12 12:55:52 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204408 kb
Host smart-8398e658-f3b9-4ef2-a413-4af7557aafdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
33879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3731733879
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3796025400
Short name T754
Test name
Test status
Simulation time 8415602764 ps
CPU time 7.62 seconds
Started May 12 12:55:52 PM PDT 24
Finished May 12 12:56:01 PM PDT 24
Peak memory 204428 kb
Host smart-8b4d3b1b-29ea-436c-957e-6ef1835c9e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37960
25400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3796025400
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1375141487
Short name T1411
Test name
Test status
Simulation time 8405200295 ps
CPU time 7.96 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 204480 kb
Host smart-4e24ff00-6a58-4f13-98a7-56056e38099b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13751
41487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1375141487
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1523521912
Short name T1071
Test name
Test status
Simulation time 8368406696 ps
CPU time 8.29 seconds
Started May 12 12:55:33 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204416 kb
Host smart-0496865a-81fa-47cc-b06e-b6d4eb499a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15235
21912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1523521912
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.143682307
Short name T378
Test name
Test status
Simulation time 8470354823 ps
CPU time 8.11 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204468 kb
Host smart-b45ea482-594e-4290-a060-d6622a44f42d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=143682307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.143682307
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1326626543
Short name T1009
Test name
Test status
Simulation time 8385485417 ps
CPU time 7.75 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204412 kb
Host smart-3f252283-c909-4554-b31f-85f685a2489e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1326626543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1326626543
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.2684878878
Short name T887
Test name
Test status
Simulation time 8464208863 ps
CPU time 7.82 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204404 kb
Host smart-c3a6a0a9-0fb9-401b-b8c9-8b660c2e5742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26848
78878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.2684878878
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3955622746
Short name T1162
Test name
Test status
Simulation time 8380571486 ps
CPU time 8.07 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204412 kb
Host smart-6ad18dec-1810-429b-9ee6-883a87cc7bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39556
22746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3955622746
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.287175780
Short name T215
Test name
Test status
Simulation time 9098258331 ps
CPU time 14.92 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 204608 kb
Host smart-3a35daf2-fe21-42c6-a3ba-389dd53a5865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28717
5780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.287175780
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_enable.3123334633
Short name T1000
Test name
Test status
Simulation time 8377422048 ps
CPU time 8.76 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204408 kb
Host smart-5bfa1924-d07d-42a8-950d-9ab2dac01312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31233
34633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3123334633
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1072066311
Short name T514
Test name
Test status
Simulation time 55661795 ps
CPU time 1.04 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:46 PM PDT 24
Peak memory 204572 kb
Host smart-874e0712-b8f1-402e-9cb8-ad2fd4166b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10720
66311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1072066311
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1579142787
Short name T874
Test name
Test status
Simulation time 8407458999 ps
CPU time 8.37 seconds
Started May 12 12:55:47 PM PDT 24
Finished May 12 12:55:57 PM PDT 24
Peak memory 204376 kb
Host smart-6b39d92c-5782-4690-8e9d-b3c60de379ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15791
42787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1579142787
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2626753518
Short name T222
Test name
Test status
Simulation time 8378259253 ps
CPU time 7.59 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 204476 kb
Host smart-fa7a2b90-6d16-47d5-a95c-e93ee17458f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
53518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2626753518
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.265108775
Short name T146
Test name
Test status
Simulation time 8465223499 ps
CPU time 7.89 seconds
Started May 12 12:55:49 PM PDT 24
Finished May 12 12:55:57 PM PDT 24
Peak memory 204424 kb
Host smart-011ff4af-ca79-4821-ab32-0b400ffbd532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
8775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.265108775
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.359806621
Short name T367
Test name
Test status
Simulation time 8412269454 ps
CPU time 7.88 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204500 kb
Host smart-68b054ee-f9d7-4642-881b-9b25730fa91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35980
6621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.359806621
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3182891084
Short name T994
Test name
Test status
Simulation time 8405758501 ps
CPU time 9.78 seconds
Started May 12 12:55:36 PM PDT 24
Finished May 12 12:55:46 PM PDT 24
Peak memory 204388 kb
Host smart-9d07743b-56df-488e-9245-749c5d9945b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31828
91084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3182891084
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1196359814
Short name T889
Test name
Test status
Simulation time 8398859830 ps
CPU time 7.73 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204408 kb
Host smart-911db155-18f6-48fb-960b-138fd5c77e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11963
59814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1196359814
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1797691339
Short name T545
Test name
Test status
Simulation time 8412333128 ps
CPU time 7.82 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 203988 kb
Host smart-ff1dae47-4e8a-4cc3-bbf4-dcb825ef2f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17976
91339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1797691339
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.182343363
Short name T1080
Test name
Test status
Simulation time 8433829870 ps
CPU time 8.89 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 204424 kb
Host smart-7b9a012c-0fb4-43e7-b797-93e07de36de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18234
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.182343363
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2372910908
Short name T1076
Test name
Test status
Simulation time 8367462964 ps
CPU time 7.64 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:55:59 PM PDT 24
Peak memory 204412 kb
Host smart-f7bb5513-faea-41d1-a239-bda31dd5bf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
10908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2372910908
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1326918840
Short name T447
Test name
Test status
Simulation time 45638628 ps
CPU time 0.66 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:42 PM PDT 24
Peak memory 204420 kb
Host smart-9f8defda-e7d1-43db-b0c1-49a6bd5b0f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13269
18840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1326918840
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2077416961
Short name T13
Test name
Test status
Simulation time 18071213493 ps
CPU time 35.25 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:56:18 PM PDT 24
Peak memory 204576 kb
Host smart-554fa547-123e-431b-b73f-42c503adadeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
16961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2077416961
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.677906310
Short name T670
Test name
Test status
Simulation time 8471498900 ps
CPU time 7.61 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204416 kb
Host smart-0e83952e-2e79-46d5-a0a7-3875ed532fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67790
6310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.677906310
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2976348551
Short name T568
Test name
Test status
Simulation time 8429921472 ps
CPU time 7.6 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204520 kb
Host smart-c83881bc-8a90-4c4f-81f2-120380a427f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
48551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2976348551
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.139294422
Short name T923
Test name
Test status
Simulation time 8383051749 ps
CPU time 8.8 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204452 kb
Host smart-015cea5f-7e82-4049-ac4e-f773bbb47bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13929
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.139294422
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1650474339
Short name T420
Test name
Test status
Simulation time 8375526941 ps
CPU time 7.56 seconds
Started May 12 12:55:40 PM PDT 24
Finished May 12 12:55:49 PM PDT 24
Peak memory 204396 kb
Host smart-65a50ca7-0262-40d7-ab62-9e01affcdb70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
74339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1650474339
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4145060670
Short name T401
Test name
Test status
Simulation time 8372154199 ps
CPU time 9.75 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:56:01 PM PDT 24
Peak memory 204396 kb
Host smart-912e354a-8cc4-438b-8dc0-98277ed29e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41450
60670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4145060670
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4140258197
Short name T1205
Test name
Test status
Simulation time 8484912250 ps
CPU time 7.65 seconds
Started May 12 12:55:58 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204388 kb
Host smart-9fd0daa1-0633-48ad-b997-16f8577e5858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
58197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4140258197
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2723407471
Short name T441
Test name
Test status
Simulation time 8387435670 ps
CPU time 7.58 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204436 kb
Host smart-abbf93cc-cca9-4716-b439-728e0abd32c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
07471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2723407471
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3703332219
Short name T1122
Test name
Test status
Simulation time 8387385142 ps
CPU time 10.35 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204440 kb
Host smart-8b4850e2-b574-45a5-bb5b-0e3c646f3236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
32219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3703332219
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.409413696
Short name T1305
Test name
Test status
Simulation time 8467242115 ps
CPU time 9.74 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204540 kb
Host smart-340f6e30-f9be-450a-a551-60ac32f6dfa2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=409413696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.409413696
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3306673367
Short name T1015
Test name
Test status
Simulation time 8378831133 ps
CPU time 7.43 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204336 kb
Host smart-0e29ac97-0d84-4787-bf79-452f31e4d086
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3306673367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3306673367
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.380078637
Short name T610
Test name
Test status
Simulation time 8442536355 ps
CPU time 8.29 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204504 kb
Host smart-599861b2-262e-438f-ab2f-8a8fbe50580a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007
8637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.380078637
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2126483788
Short name T948
Test name
Test status
Simulation time 8374785612 ps
CPU time 8.06 seconds
Started May 12 12:54:33 PM PDT 24
Finished May 12 12:54:41 PM PDT 24
Peak memory 204680 kb
Host smart-d1e67bf1-44f2-4cd1-98f9-80ab97ef1e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21264
83788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2126483788
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.3892699504
Short name T355
Test name
Test status
Simulation time 8386842744 ps
CPU time 7.74 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204396 kb
Host smart-5da95b6c-9594-4a06-bb3a-b7e9475ef413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38926
99504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3892699504
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3593631733
Short name T797
Test name
Test status
Simulation time 79048584 ps
CPU time 1.12 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:38 PM PDT 24
Peak memory 204512 kb
Host smart-38c73ab1-4ed8-4199-9c6f-b765640e8dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936
31733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3593631733
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2412860365
Short name T166
Test name
Test status
Simulation time 8455293219 ps
CPU time 8.07 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204464 kb
Host smart-c0bf0d33-bb98-4bd4-8213-c7af6b5c4848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
60365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2412860365
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1161723949
Short name T207
Test name
Test status
Simulation time 8375394926 ps
CPU time 7.78 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204412 kb
Host smart-4039005b-a18b-4850-a57a-ca90d5aab10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11617
23949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1161723949
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2717932958
Short name T858
Test name
Test status
Simulation time 8383075992 ps
CPU time 10.23 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 204332 kb
Host smart-4d69f47c-04bd-4221-8411-b9c7077b9ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
32958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2717932958
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2430660006
Short name T1327
Test name
Test status
Simulation time 8414173418 ps
CPU time 7.79 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204488 kb
Host smart-7d2bda2d-9fcc-4783-8064-4e740514e129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24306
60006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2430660006
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.336873225
Short name T902
Test name
Test status
Simulation time 8370084112 ps
CPU time 9.48 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204320 kb
Host smart-8f39eb2b-ef0a-4b88-84ab-fac02db3e7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687
3225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.336873225
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3257566717
Short name T130
Test name
Test status
Simulation time 8453384766 ps
CPU time 8.08 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204460 kb
Host smart-41ddf615-dd9a-405a-9d23-b7f7c17890d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32575
66717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3257566717
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1245534232
Short name T1317
Test name
Test status
Simulation time 8420171311 ps
CPU time 8.45 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204432 kb
Host smart-3a477f71-e934-4e63-b507-682f436bb095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12455
34232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1245534232
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.879348587
Short name T590
Test name
Test status
Simulation time 8408587935 ps
CPU time 7.67 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 204376 kb
Host smart-3a3a1357-bfe5-4835-98b4-b7d068230ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87934
8587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.879348587
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3260730586
Short name T176
Test name
Test status
Simulation time 8391900483 ps
CPU time 7.92 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204456 kb
Host smart-9aee19d8-c141-4e52-93ab-c1d16447f7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32607
30586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3260730586
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1671855747
Short name T676
Test name
Test status
Simulation time 8366432724 ps
CPU time 7.67 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204456 kb
Host smart-e73930f3-63c7-4f67-9958-a345fd6e93da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718
55747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1671855747
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4078792741
Short name T471
Test name
Test status
Simulation time 58245023 ps
CPU time 0.66 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204328 kb
Host smart-73af4a54-4357-4539-95bf-db2d9143a955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40787
92741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4078792741
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.942648142
Short name T98
Test name
Test status
Simulation time 25689876381 ps
CPU time 56.98 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:55:39 PM PDT 24
Peak memory 204588 kb
Host smart-50aa2793-b45f-47ae-9b9f-e51547a46049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94264
8142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.942648142
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3497100892
Short name T243
Test name
Test status
Simulation time 8403204022 ps
CPU time 7.61 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 204464 kb
Host smart-8fe5b670-b65b-42ab-8a2d-687867bde750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34971
00892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3497100892
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.184189063
Short name T1427
Test name
Test status
Simulation time 8433376867 ps
CPU time 8.54 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204456 kb
Host smart-c9335d4a-2fc8-4e0f-9c7e-4ce237e38525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
9063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.184189063
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.2906179019
Short name T767
Test name
Test status
Simulation time 8393436625 ps
CPU time 8.71 seconds
Started May 12 12:54:32 PM PDT 24
Finished May 12 12:54:42 PM PDT 24
Peak memory 204424 kb
Host smart-287436b3-5bd0-4d60-8e03-815773956d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29061
79019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.2906179019
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3695784654
Short name T62
Test name
Test status
Simulation time 230772529 ps
CPU time 1.15 seconds
Started May 12 12:54:31 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 221976 kb
Host smart-61e8cabc-4333-4068-b226-73d822c1827c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3695784654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3695784654
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1747391069
Short name T570
Test name
Test status
Simulation time 8397295501 ps
CPU time 8.73 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204344 kb
Host smart-695750ac-e20c-4aa6-bd64-b3eb485504e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17473
91069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1747391069
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3013462025
Short name T604
Test name
Test status
Simulation time 8367137463 ps
CPU time 7.74 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204456 kb
Host smart-e2c2ee49-985c-4078-888b-8333f4aec228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
62025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3013462025
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2232015077
Short name T1318
Test name
Test status
Simulation time 8433973815 ps
CPU time 9.04 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204432 kb
Host smart-1efbb504-c4ec-41aa-b952-ff790c85566e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22320
15077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2232015077
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.346903804
Short name T363
Test name
Test status
Simulation time 8422192701 ps
CPU time 7.71 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:42 PM PDT 24
Peak memory 204424 kb
Host smart-f80f1a16-898c-4122-abb1-a3334db58be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
3804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.346903804
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1279882632
Short name T1180
Test name
Test status
Simulation time 8376908697 ps
CPU time 7.81 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204376 kb
Host smart-04ced32f-ba27-46fc-835c-34ff1da8c943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
82632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1279882632
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.3114372272
Short name T1261
Test name
Test status
Simulation time 8375369877 ps
CPU time 8.36 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204376 kb
Host smart-e9c4262f-9d2c-4a9b-b34b-32af8742bc9c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3114372272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.3114372272
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.3096919142
Short name T83
Test name
Test status
Simulation time 8455234730 ps
CPU time 7.62 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204444 kb
Host smart-76b7fe7f-047b-4cb1-be5f-7b08543b804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
19142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.3096919142
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.161709310
Short name T1222
Test name
Test status
Simulation time 8395286912 ps
CPU time 8.03 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204472 kb
Host smart-288ae03b-dc3b-40c3-89c9-be0321e41ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16170
9310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.161709310
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2118234562
Short name T1247
Test name
Test status
Simulation time 9039667203 ps
CPU time 12.65 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204736 kb
Host smart-42b77628-04ed-492d-ad60-f5966b72455c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182
34562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2118234562
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_enable.2146667381
Short name T1393
Test name
Test status
Simulation time 8377666949 ps
CPU time 7.7 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204476 kb
Host smart-b05a9ebe-5cb1-4da4-8ef6-22282ab37bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21466
67381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2146667381
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2638307701
Short name T1118
Test name
Test status
Simulation time 138319344 ps
CPU time 1.54 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204640 kb
Host smart-54c7a2e6-c041-4c58-ae18-6032cbb5166e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
07701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2638307701
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.274589057
Short name T1196
Test name
Test status
Simulation time 8459989568 ps
CPU time 8.14 seconds
Started May 12 12:56:01 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 204452 kb
Host smart-ab5b99cf-0dd4-461f-ba77-52014e842ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458
9057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.274589057
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3050896035
Short name T7
Test name
Test status
Simulation time 8364504042 ps
CPU time 9.45 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204384 kb
Host smart-7bfd9d4b-12f7-43fc-8433-452c7554ba7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30508
96035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3050896035
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2862999187
Short name T149
Test name
Test status
Simulation time 8408353306 ps
CPU time 7.82 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204460 kb
Host smart-a09b6302-0ea8-4679-97ff-a7cb18aa4c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28629
99187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2862999187
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.4227134636
Short name T519
Test name
Test status
Simulation time 8414787978 ps
CPU time 7.54 seconds
Started May 12 12:55:48 PM PDT 24
Finished May 12 12:55:57 PM PDT 24
Peak memory 204460 kb
Host smart-239e3553-e656-4a28-9c58-62650d0cf13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
34636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.4227134636
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2023894451
Short name T1094
Test name
Test status
Simulation time 8370424891 ps
CPU time 7.42 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:55:59 PM PDT 24
Peak memory 204432 kb
Host smart-104314b6-5c3f-4f08-be1e-1b2993cf506f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
94451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2023894451
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1819230316
Short name T1183
Test name
Test status
Simulation time 8393129867 ps
CPU time 8.4 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204324 kb
Host smart-8e3f7115-7c13-4bf5-a0d2-d4588a034abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
30316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1819230316
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.602602479
Short name T16
Test name
Test status
Simulation time 8389480369 ps
CPU time 7.99 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204328 kb
Host smart-eb8a9c01-95d5-4cc6-bcc9-4779d4515c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60260
2479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.602602479
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2864533962
Short name T203
Test name
Test status
Simulation time 8404048297 ps
CPU time 9.13 seconds
Started May 12 12:55:54 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204416 kb
Host smart-045079fa-2ebd-4ab5-a870-715de699b050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28645
33962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2864533962
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2126348909
Short name T368
Test name
Test status
Simulation time 8375606882 ps
CPU time 8.01 seconds
Started May 12 12:56:00 PM PDT 24
Finished May 12 12:56:08 PM PDT 24
Peak memory 204348 kb
Host smart-d14f2e01-cca3-4748-b5ab-afea33dc41e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21263
48909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2126348909
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.847066649
Short name T1392
Test name
Test status
Simulation time 46625908 ps
CPU time 0.66 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:55:51 PM PDT 24
Peak memory 204296 kb
Host smart-f099df53-d9f7-4f09-b13f-52aa8a45bb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84706
6649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.847066649
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3066173661
Short name T96
Test name
Test status
Simulation time 20209587245 ps
CPU time 40.64 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:56:24 PM PDT 24
Peak memory 204684 kb
Host smart-b8c0e19a-4a37-44ab-8ae0-4c2d8647af21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30661
73661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3066173661
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1930358459
Short name T788
Test name
Test status
Simulation time 8428465603 ps
CPU time 8.62 seconds
Started May 12 12:55:42 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204452 kb
Host smart-af45511d-1a56-4424-b1a0-09fef731ffbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19303
58459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1930358459
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3299030312
Short name T1360
Test name
Test status
Simulation time 8481324087 ps
CPU time 8.07 seconds
Started May 12 12:55:55 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204452 kb
Host smart-91997853-f9fe-41e2-84dd-598992fdda02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32990
30312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3299030312
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3054919401
Short name T1078
Test name
Test status
Simulation time 8411462212 ps
CPU time 8.07 seconds
Started May 12 12:55:41 PM PDT 24
Finished May 12 12:55:50 PM PDT 24
Peak memory 204528 kb
Host smart-00cded39-f449-4433-af19-66a882fe1824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
19401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3054919401
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1617366794
Short name T1382
Test name
Test status
Simulation time 8376950585 ps
CPU time 7.82 seconds
Started May 12 12:55:45 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 204424 kb
Host smart-507aa7af-c97c-4f22-8da9-a65daa40b565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173
66794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1617366794
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1995050657
Short name T895
Test name
Test status
Simulation time 8372256442 ps
CPU time 8.53 seconds
Started May 12 12:55:49 PM PDT 24
Finished May 12 12:55:59 PM PDT 24
Peak memory 204428 kb
Host smart-d4bf68ad-b90f-41e5-826c-5b680567d6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19950
50657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1995050657
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3543908055
Short name T657
Test name
Test status
Simulation time 8505155863 ps
CPU time 7.74 seconds
Started May 12 12:55:39 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 204500 kb
Host smart-1bdf4205-0340-4e58-90ed-8813fd69230c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
08055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3543908055
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3468268327
Short name T424
Test name
Test status
Simulation time 8382509913 ps
CPU time 9.45 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204348 kb
Host smart-1350cadb-51c7-4b5a-86d7-e847b580fcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
68327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3468268327
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3176857650
Short name T1010
Test name
Test status
Simulation time 8469402212 ps
CPU time 7.79 seconds
Started May 12 12:55:54 PM PDT 24
Finished May 12 12:56:08 PM PDT 24
Peak memory 204412 kb
Host smart-f485ed62-a294-49f7-b0d8-e2e4e1636c2f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3176857650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3176857650
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2343520244
Short name T268
Test name
Test status
Simulation time 8429324726 ps
CPU time 9.2 seconds
Started May 12 12:55:46 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 204448 kb
Host smart-ec068a3c-84b0-4599-9d1c-9447b0f96d5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2343520244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2343520244
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3381715668
Short name T1332
Test name
Test status
Simulation time 8445895102 ps
CPU time 7.96 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:16 PM PDT 24
Peak memory 204384 kb
Host smart-31b4258e-0857-4f87-98c3-b35c1e19ea26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817
15668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3381715668
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.540306235
Short name T421
Test name
Test status
Simulation time 8393276858 ps
CPU time 8.02 seconds
Started May 12 12:55:47 PM PDT 24
Finished May 12 12:55:57 PM PDT 24
Peak memory 204468 kb
Host smart-8f6f59d7-620c-48df-a1cd-6c2d95def601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54030
6235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.540306235
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.2132034522
Short name T684
Test name
Test status
Simulation time 8371715072 ps
CPU time 7.77 seconds
Started May 12 12:55:56 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204396 kb
Host smart-a7b1f410-33d1-4c10-b16e-0ac5ddbb86e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21320
34522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2132034522
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3367819928
Short name T521
Test name
Test status
Simulation time 85451976 ps
CPU time 1.14 seconds
Started May 12 12:55:58 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204548 kb
Host smart-9bf47946-7878-49c5-9419-90072a83c274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33678
19928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3367819928
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.127770213
Short name T164
Test name
Test status
Simulation time 8375995687 ps
CPU time 7.72 seconds
Started May 12 12:55:51 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204508 kb
Host smart-035c91aa-352f-49fa-858d-a5ef94ae3bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12777
0213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.127770213
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3884445071
Short name T1429
Test name
Test status
Simulation time 8415914712 ps
CPU time 8.03 seconds
Started May 12 12:56:12 PM PDT 24
Finished May 12 12:56:20 PM PDT 24
Peak memory 204384 kb
Host smart-558ae297-7a75-4b4a-9312-e394c835d6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38844
45071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3884445071
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.414466703
Short name T1298
Test name
Test status
Simulation time 8467013199 ps
CPU time 7.65 seconds
Started May 12 12:55:44 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 204372 kb
Host smart-40c0e56e-0948-48d8-9489-7d59e5a5682f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41446
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.414466703
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3219213279
Short name T357
Test name
Test status
Simulation time 8439085592 ps
CPU time 8.66 seconds
Started May 12 12:55:43 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 204476 kb
Host smart-24507919-e336-4554-b094-f4a66a797f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
13279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3219213279
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3994511199
Short name T854
Test name
Test status
Simulation time 8371943670 ps
CPU time 8.43 seconds
Started May 12 12:56:09 PM PDT 24
Finished May 12 12:56:18 PM PDT 24
Peak memory 204432 kb
Host smart-b96ea4bb-ec60-4d89-be1c-b15a0e13e24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39945
11199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3994511199
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1039238868
Short name T1417
Test name
Test status
Simulation time 8448403958 ps
CPU time 8.03 seconds
Started May 12 12:56:04 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204428 kb
Host smart-64d399f2-09be-47ba-afe7-220e46cb28b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10392
38868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1039238868
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.675212661
Short name T1119
Test name
Test status
Simulation time 8415675014 ps
CPU time 8.17 seconds
Started May 12 12:55:56 PM PDT 24
Finished May 12 12:56:05 PM PDT 24
Peak memory 204360 kb
Host smart-7f443370-14b3-4a78-bdad-75b8fc76e75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67521
2661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.675212661
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3946578077
Short name T218
Test name
Test status
Simulation time 8435432493 ps
CPU time 7.82 seconds
Started May 12 12:56:07 PM PDT 24
Finished May 12 12:56:16 PM PDT 24
Peak memory 204448 kb
Host smart-56c9c731-fd88-48df-9ed8-cd9a17c75b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
78077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3946578077
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.793801252
Short name T432
Test name
Test status
Simulation time 8370722379 ps
CPU time 7.85 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204460 kb
Host smart-08cd2d99-66e5-4a5b-8ddd-9fc75b337b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79380
1252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.793801252
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1884876024
Short name T579
Test name
Test status
Simulation time 143310776 ps
CPU time 0.74 seconds
Started May 12 12:56:10 PM PDT 24
Finished May 12 12:56:11 PM PDT 24
Peak memory 204328 kb
Host smart-2a630092-b505-4294-8595-12363d24a59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848
76024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1884876024
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1778221723
Short name T1195
Test name
Test status
Simulation time 23300307235 ps
CPU time 44.88 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:51 PM PDT 24
Peak memory 204944 kb
Host smart-c4ab3a0b-868f-4158-b1e6-62132a343114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17782
21723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1778221723
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2669679187
Short name T1197
Test name
Test status
Simulation time 8414606548 ps
CPU time 7.65 seconds
Started May 12 12:55:55 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204416 kb
Host smart-5460e00b-d850-4f65-a9f5-76f3bb891b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
79187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2669679187
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1277155788
Short name T1252
Test name
Test status
Simulation time 8428122547 ps
CPU time 8.95 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 204748 kb
Host smart-35816bbb-7f38-4042-ace1-7f0f21f810a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12771
55788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1277155788
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2495008914
Short name T440
Test name
Test status
Simulation time 8406666597 ps
CPU time 8.66 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204348 kb
Host smart-4e92b43f-a11b-40a3-9eff-003588207248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24950
08914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2495008914
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1356778247
Short name T172
Test name
Test status
Simulation time 8372260591 ps
CPU time 8.08 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204740 kb
Host smart-29b926c6-0e1e-408d-9a6c-704300d589b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13567
78247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1356778247
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.205578799
Short name T1097
Test name
Test status
Simulation time 8365391748 ps
CPU time 7.93 seconds
Started May 12 12:55:53 PM PDT 24
Finished May 12 12:56:02 PM PDT 24
Peak memory 204452 kb
Host smart-fdfec5dc-26b4-419f-9958-1cd25bb80575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
8799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.205578799
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.4247196394
Short name T1164
Test name
Test status
Simulation time 8447207954 ps
CPU time 7.49 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:55:59 PM PDT 24
Peak memory 204440 kb
Host smart-a7571188-84f5-40ba-b595-909b76ae4bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
96394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.4247196394
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.4128144879
Short name T456
Test name
Test status
Simulation time 8390732277 ps
CPU time 9.23 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204404 kb
Host smart-1733c1c7-cb7a-4e6e-ae4d-55767948491e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
44879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.4128144879
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3418439661
Short name T484
Test name
Test status
Simulation time 8397131210 ps
CPU time 9.18 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:22 PM PDT 24
Peak memory 204736 kb
Host smart-efa99156-b460-491e-9f62-9f28850cbb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
39661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3418439661
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.577197604
Short name T998
Test name
Test status
Simulation time 8502935595 ps
CPU time 9.18 seconds
Started May 12 12:56:02 PM PDT 24
Finished May 12 12:56:11 PM PDT 24
Peak memory 204328 kb
Host smart-9b5c413e-2c0d-4e48-b1bf-9f98d752f23b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=577197604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.577197604
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3159822499
Short name T1364
Test name
Test status
Simulation time 8375860820 ps
CPU time 7.83 seconds
Started May 12 12:56:00 PM PDT 24
Finished May 12 12:56:09 PM PDT 24
Peak memory 204416 kb
Host smart-30c55585-8e45-452d-b296-db95a9b44071
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3159822499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3159822499
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.3502451452
Short name T771
Test name
Test status
Simulation time 8438966806 ps
CPU time 7.79 seconds
Started May 12 12:56:04 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204404 kb
Host smart-faf7fba1-c0f5-489b-b16c-7e45e5a8c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35024
51452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.3502451452
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1434762193
Short name T1413
Test name
Test status
Simulation time 8372661623 ps
CPU time 8.25 seconds
Started May 12 12:55:51 PM PDT 24
Finished May 12 12:56:01 PM PDT 24
Peak memory 204428 kb
Host smart-c1934645-6fbb-4688-ba4e-e7750b2197e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14347
62193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1434762193
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.721999963
Short name T201
Test name
Test status
Simulation time 9472299554 ps
CPU time 12.61 seconds
Started May 12 12:55:54 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204660 kb
Host smart-ce0848c0-9672-4585-871e-6bf614213fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72199
9963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.721999963
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_enable.64641427
Short name T1368
Test name
Test status
Simulation time 8381427535 ps
CPU time 7.96 seconds
Started May 12 12:55:53 PM PDT 24
Finished May 12 12:56:02 PM PDT 24
Peak memory 204340 kb
Host smart-7b770d42-005b-4a0b-b47a-b6b8b57e8d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64641
427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.64641427
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1023814706
Short name T712
Test name
Test status
Simulation time 176344885 ps
CPU time 1.56 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:55:59 PM PDT 24
Peak memory 204616 kb
Host smart-edf241b2-8335-4db5-b21d-5e32b213ea70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238
14706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1023814706
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1317451656
Short name T163
Test name
Test status
Simulation time 8470559331 ps
CPU time 9.66 seconds
Started May 12 12:56:04 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204740 kb
Host smart-a9ea1dec-3741-4244-bebf-2b355660f28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174
51656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1317451656
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1363234338
Short name T1108
Test name
Test status
Simulation time 8430636367 ps
CPU time 9.67 seconds
Started May 12 12:56:12 PM PDT 24
Finished May 12 12:56:22 PM PDT 24
Peak memory 204380 kb
Host smart-637c0082-7132-431e-b75b-3c610c0bcbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632
34338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1363234338
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1946476885
Short name T871
Test name
Test status
Simulation time 8466093305 ps
CPU time 9.4 seconds
Started May 12 12:55:54 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204460 kb
Host smart-7d121489-5887-4b8c-b33e-ee6f3a5bf360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19464
76885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1946476885
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3638922398
Short name T868
Test name
Test status
Simulation time 8426884562 ps
CPU time 8.1 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 204424 kb
Host smart-ab9507df-3201-4960-bf20-c4c5ebe96197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389
22398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3638922398
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.496042558
Short name T1408
Test name
Test status
Simulation time 8437188531 ps
CPU time 8.74 seconds
Started May 12 12:55:53 PM PDT 24
Finished May 12 12:56:03 PM PDT 24
Peak memory 204340 kb
Host smart-7c36cc38-25b1-4bbb-899e-3b1c873d8733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49604
2558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.496042558
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4273462340
Short name T1104
Test name
Test status
Simulation time 8442760152 ps
CPU time 9.51 seconds
Started May 12 12:55:51 PM PDT 24
Finished May 12 12:56:02 PM PDT 24
Peak memory 204420 kb
Host smart-5f26ce81-f73a-4cd0-ae4f-fef1861f3a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42734
62340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4273462340
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2396472070
Short name T533
Test name
Test status
Simulation time 8407996364 ps
CPU time 7.99 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204384 kb
Host smart-b9b129cc-bd17-48fa-ae89-b86690db8cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23964
72070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2396472070
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1015932421
Short name T1181
Test name
Test status
Simulation time 8419657231 ps
CPU time 9.32 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204404 kb
Host smart-c98f4c89-2ccb-4d2f-93ca-3536fa395e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10159
32421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1015932421
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1535825454
Short name T1401
Test name
Test status
Simulation time 8401376837 ps
CPU time 8.07 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204508 kb
Host smart-a956bdc9-0d93-43a0-b005-165b4cfded62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15358
25454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1535825454
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.327678702
Short name T993
Test name
Test status
Simulation time 8374580038 ps
CPU time 7.88 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:16 PM PDT 24
Peak memory 204420 kb
Host smart-9b1a587d-2229-4457-9314-cd4f0ef8ee59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32767
8702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.327678702
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.764402123
Short name T1157
Test name
Test status
Simulation time 35664030 ps
CPU time 0.67 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204364 kb
Host smart-bcf4abbd-4750-4a48-a12b-4c6d38adab36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76440
2123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.764402123
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1764018482
Short name T1301
Test name
Test status
Simulation time 19482942581 ps
CPU time 33.76 seconds
Started May 12 12:55:53 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 204608 kb
Host smart-7f648119-d565-4d4f-be88-985b88ed82e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17640
18482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1764018482
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2484538784
Short name T1324
Test name
Test status
Simulation time 8457470470 ps
CPU time 8.71 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204396 kb
Host smart-d5ce87f3-bc76-417d-b9d3-a246e86ae57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
38784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2484538784
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.689001917
Short name T137
Test name
Test status
Simulation time 8393315877 ps
CPU time 7.93 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204380 kb
Host smart-7ef04ec8-a92f-4f92-9e64-d6ea4de1c6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68900
1917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.689001917
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3808347193
Short name T700
Test name
Test status
Simulation time 8380233545 ps
CPU time 8.53 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:08 PM PDT 24
Peak memory 204392 kb
Host smart-62d9c694-e41f-4094-a479-5a2ffddacfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38083
47193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3808347193
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3290693369
Short name T51
Test name
Test status
Simulation time 8433016066 ps
CPU time 8.06 seconds
Started May 12 12:55:50 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204548 kb
Host smart-66feae0a-7ea0-4415-996a-f3c56a999ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906
93369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3290693369
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1543412333
Short name T896
Test name
Test status
Simulation time 8369563187 ps
CPU time 7.76 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204376 kb
Host smart-efb23722-8626-4855-ab14-870fb09fdb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15434
12333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1543412333
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.956019521
Short name T800
Test name
Test status
Simulation time 8441286963 ps
CPU time 7.66 seconds
Started May 12 12:55:57 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204756 kb
Host smart-4124115d-e49b-4578-b7c2-6232a53ae90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95601
9521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.956019521
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2610795665
Short name T1290
Test name
Test status
Simulation time 8383201966 ps
CPU time 8.22 seconds
Started May 12 12:56:01 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 204348 kb
Host smart-09f53a1b-cae3-4a56-8e85-35c9edfcd42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26107
95665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2610795665
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2325846166
Short name T81
Test name
Test status
Simulation time 8386210321 ps
CPU time 7.67 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:11 PM PDT 24
Peak memory 204416 kb
Host smart-49051ff1-09a1-4ed2-9f49-62a332bcdcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23258
46166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2325846166
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1121133334
Short name T978
Test name
Test status
Simulation time 8471645117 ps
CPU time 8.7 seconds
Started May 12 12:56:18 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204424 kb
Host smart-9e5f0bfc-bdf4-404c-9b8c-4d8615eaa735
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1121133334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1121133334
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3163688765
Short name T897
Test name
Test status
Simulation time 8383171298 ps
CPU time 7.68 seconds
Started May 12 12:56:15 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204324 kb
Host smart-0b42c8c8-9898-4b44-9ce5-07b0e397b911
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3163688765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3163688765
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.2492919832
Short name T144
Test name
Test status
Simulation time 8455452364 ps
CPU time 7.98 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204668 kb
Host smart-b1f4d1e0-aed4-4452-988b-03c3c42a78ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24929
19832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.2492919832
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2168895422
Short name T1325
Test name
Test status
Simulation time 8380454674 ps
CPU time 7.96 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204396 kb
Host smart-c559ad7b-aa84-46b8-a65c-7af76a963423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21688
95422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2168895422
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2530875372
Short name T224
Test name
Test status
Simulation time 9068193488 ps
CPU time 12.39 seconds
Started May 12 12:56:12 PM PDT 24
Finished May 12 12:56:25 PM PDT 24
Peak memory 204676 kb
Host smart-0680e1d6-5dc7-46e2-a7dd-a71e6fe53bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25308
75372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2530875372
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_enable.2626510847
Short name T1316
Test name
Test status
Simulation time 8377471469 ps
CPU time 8.67 seconds
Started May 12 12:56:01 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 204688 kb
Host smart-8f37658b-9638-49c7-99b3-f4bf0aa711d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26265
10847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2626510847
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2838379576
Short name T297
Test name
Test status
Simulation time 199772555 ps
CPU time 2.07 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:09 PM PDT 24
Peak memory 204552 kb
Host smart-2bfd0c54-9705-4263-b77c-c0f73f38ee07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
79576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2838379576
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.4234334856
Short name T762
Test name
Test status
Simulation time 8448529882 ps
CPU time 7.74 seconds
Started May 12 12:56:11 PM PDT 24
Finished May 12 12:56:19 PM PDT 24
Peak memory 204460 kb
Host smart-30680bb5-d8a0-4fb0-8778-f6dc75019e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42343
34856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.4234334856
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2146378385
Short name T839
Test name
Test status
Simulation time 8388359759 ps
CPU time 7.71 seconds
Started May 12 12:56:17 PM PDT 24
Finished May 12 12:56:25 PM PDT 24
Peak memory 204344 kb
Host smart-5b4d3b40-8904-4311-b13e-0bc029dd608e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21463
78385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2146378385
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2589377484
Short name T1313
Test name
Test status
Simulation time 8436404557 ps
CPU time 7.95 seconds
Started May 12 12:55:56 PM PDT 24
Finished May 12 12:56:05 PM PDT 24
Peak memory 204376 kb
Host smart-632778ab-44f2-412b-811b-62eb1011614d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25893
77484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2589377484
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1990017840
Short name T949
Test name
Test status
Simulation time 8495520165 ps
CPU time 8.38 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204400 kb
Host smart-fdfb6620-23e0-41e8-817c-a4b0a4778793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19900
17840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1990017840
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1123265183
Short name T746
Test name
Test status
Simulation time 8412831650 ps
CPU time 8.28 seconds
Started May 12 12:56:10 PM PDT 24
Finished May 12 12:56:19 PM PDT 24
Peak memory 204464 kb
Host smart-4aabeeeb-a606-48dc-b12a-ce542e05084f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11232
65183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1123265183
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2355418442
Short name T126
Test name
Test status
Simulation time 8474582063 ps
CPU time 8.18 seconds
Started May 12 12:56:16 PM PDT 24
Finished May 12 12:56:25 PM PDT 24
Peak memory 204376 kb
Host smart-ef2b067c-d5b1-41d5-a8bf-8e85c8f97163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
18442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2355418442
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3032934855
Short name T578
Test name
Test status
Simulation time 8412675933 ps
CPU time 7.88 seconds
Started May 12 12:56:07 PM PDT 24
Finished May 12 12:56:16 PM PDT 24
Peak memory 204416 kb
Host smart-cf5d42ab-3348-4e55-ae28-d3c8d492e0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
34855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3032934855
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3378175731
Short name T962
Test name
Test status
Simulation time 8404875965 ps
CPU time 8.15 seconds
Started May 12 12:56:14 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204404 kb
Host smart-69240ebc-4acc-4756-aecb-d984872edfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33781
75731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3378175731
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1216142293
Short name T1388
Test name
Test status
Simulation time 8371932946 ps
CPU time 7.98 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204432 kb
Host smart-3115b02f-58d2-40f7-9112-eb4a797443cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12161
42293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1216142293
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.233222393
Short name T647
Test name
Test status
Simulation time 65121751 ps
CPU time 0.67 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:09 PM PDT 24
Peak memory 204472 kb
Host smart-96bfdd46-9a21-4974-85c2-6b23752016fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23322
2393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.233222393
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1695403130
Short name T615
Test name
Test status
Simulation time 22411226381 ps
CPU time 44.56 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:58 PM PDT 24
Peak memory 204724 kb
Host smart-89ffb423-7733-46ed-a2b8-f245d41a69df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16954
03130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1695403130
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2200579244
Short name T22
Test name
Test status
Simulation time 8396920832 ps
CPU time 7.98 seconds
Started May 12 12:56:02 PM PDT 24
Finished May 12 12:56:11 PM PDT 24
Peak memory 204416 kb
Host smart-cf364b2f-99fb-43b9-a7a8-cbb8b7132e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22005
79244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2200579244
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3678454187
Short name T477
Test name
Test status
Simulation time 8377500061 ps
CPU time 7.49 seconds
Started May 12 12:56:12 PM PDT 24
Finished May 12 12:56:20 PM PDT 24
Peak memory 204432 kb
Host smart-a71036f1-98e2-4710-a685-49303d37694e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36784
54187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3678454187
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3937459020
Short name T1055
Test name
Test status
Simulation time 8374206114 ps
CPU time 8.1 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 204452 kb
Host smart-b8e5b59a-4f1f-472e-a8fb-df9cf139cbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
59020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3937459020
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1587853491
Short name T777
Test name
Test status
Simulation time 8376922348 ps
CPU time 7.37 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204424 kb
Host smart-0e339443-6962-4521-96d0-980a58662fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15878
53491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1587853491
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3999214682
Short name T351
Test name
Test status
Simulation time 8403343047 ps
CPU time 7.61 seconds
Started May 12 12:56:11 PM PDT 24
Finished May 12 12:56:19 PM PDT 24
Peak memory 204492 kb
Host smart-97c4380b-949e-4f7e-8c53-7b00263ac756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992
14682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3999214682
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.716895851
Short name T1145
Test name
Test status
Simulation time 8420495072 ps
CPU time 9.19 seconds
Started May 12 12:55:58 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204364 kb
Host smart-6ddc97d3-7618-43e9-947e-58a0fef8665f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71689
5851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.716895851
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2225933470
Short name T1359
Test name
Test status
Simulation time 8407341548 ps
CPU time 7.96 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:17 PM PDT 24
Peak memory 204424 kb
Host smart-a45b9159-1d2f-4609-9901-84531ac98cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
33470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2225933470
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3027895458
Short name T654
Test name
Test status
Simulation time 8423907660 ps
CPU time 7.79 seconds
Started May 12 12:56:04 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204428 kb
Host smart-2c3ae0e8-92cb-4177-a6c2-ca3819a342d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30278
95458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3027895458
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.2210108633
Short name T165
Test name
Test status
Simulation time 8457309333 ps
CPU time 8.32 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204412 kb
Host smart-85d5c74c-d456-4204-adf5-8d978fa8bdbe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2210108633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.2210108633
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3255927439
Short name T478
Test name
Test status
Simulation time 8381553214 ps
CPU time 8.1 seconds
Started May 12 12:56:02 PM PDT 24
Finished May 12 12:56:11 PM PDT 24
Peak memory 204452 kb
Host smart-b8482060-3ec7-4f7b-b785-f3f370f88292
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3255927439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3255927439
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.1874570
Short name T418
Test name
Test status
Simulation time 8427556828 ps
CPU time 7.64 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204344 kb
Host smart-2590bd41-fcec-46c6-9260-7fb6b24ec742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18745
70 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.1874570
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2206477769
Short name T1052
Test name
Test status
Simulation time 8384455413 ps
CPU time 7.91 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204472 kb
Host smart-111a5ef2-b479-482c-b9eb-3a658751c79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
77769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2206477769
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3474037897
Short name T381
Test name
Test status
Simulation time 8608871496 ps
CPU time 11.35 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:20 PM PDT 24
Peak memory 204716 kb
Host smart-b6f1ceda-007f-42d9-ae4a-6a2e5b202ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34740
37897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3474037897
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_enable.3953493547
Short name T572
Test name
Test status
Simulation time 8374694759 ps
CPU time 7.99 seconds
Started May 12 12:56:11 PM PDT 24
Finished May 12 12:56:20 PM PDT 24
Peak memory 204500 kb
Host smart-1a8eba35-b596-4352-b71c-8cccace32361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
93547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3953493547
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3143674148
Short name T980
Test name
Test status
Simulation time 151102943 ps
CPU time 1.67 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204576 kb
Host smart-3b4940a9-f275-4d9e-992e-74d4939df1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
74148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3143674148
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.682413881
Short name T500
Test name
Test status
Simulation time 8452730610 ps
CPU time 7.78 seconds
Started May 12 12:56:18 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204548 kb
Host smart-32e2b2e8-75fa-4794-9e5f-93100ab13fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68241
3881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.682413881
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.4166594567
Short name T1295
Test name
Test status
Simulation time 8371183694 ps
CPU time 7.64 seconds
Started May 12 12:56:09 PM PDT 24
Finished May 12 12:56:17 PM PDT 24
Peak memory 204488 kb
Host smart-6e67077b-5dbb-4e6a-937e-7d72143b42b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
94567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.4166594567
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3860022359
Short name T142
Test name
Test status
Simulation time 8454797870 ps
CPU time 8.34 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 204460 kb
Host smart-92ac6848-56f8-430d-9a31-a43345ad7b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38600
22359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3860022359
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2788968089
Short name T1077
Test name
Test status
Simulation time 8412154713 ps
CPU time 9.53 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:16 PM PDT 24
Peak memory 204436 kb
Host smart-1a2e78c0-7394-4461-bb7e-50584a754963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889
68089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2788968089
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3325606120
Short name T996
Test name
Test status
Simulation time 8414166919 ps
CPU time 8.7 seconds
Started May 12 12:56:01 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 204372 kb
Host smart-2c601af6-70e2-433b-a833-66a128902981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33256
06120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3325606120
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1412354735
Short name T103
Test name
Test status
Simulation time 8433792365 ps
CPU time 8.17 seconds
Started May 12 12:56:11 PM PDT 24
Finished May 12 12:56:20 PM PDT 24
Peak memory 204460 kb
Host smart-1789922f-19af-4907-80be-74022ee6eb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14123
54735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1412354735
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.766546457
Short name T409
Test name
Test status
Simulation time 8397486590 ps
CPU time 7.61 seconds
Started May 12 12:55:59 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 204420 kb
Host smart-c83fa653-ce2f-46a9-90a1-33e241195045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76654
6457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.766546457
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1747169569
Short name T366
Test name
Test status
Simulation time 8447668118 ps
CPU time 7.9 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204404 kb
Host smart-d3f9e1b1-5548-48c3-9c40-dc798471a388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17471
69569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1747169569
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.4217895795
Short name T1049
Test name
Test status
Simulation time 8429521924 ps
CPU time 8.66 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 204328 kb
Host smart-70c49f90-0bdd-4d6d-a29c-f96e2a464f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42178
95795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.4217895795
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2189603391
Short name T1096
Test name
Test status
Simulation time 8370497985 ps
CPU time 7.57 seconds
Started May 12 12:56:01 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 204432 kb
Host smart-dc6447e0-fc0a-413a-89ac-652097cdc78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21896
03391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2189603391
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1538262555
Short name T925
Test name
Test status
Simulation time 40544784 ps
CPU time 0.69 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204364 kb
Host smart-3c1eca9b-d7f3-4ccf-b1d7-abc15dfb1442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15382
62555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1538262555
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1230465261
Short name T249
Test name
Test status
Simulation time 20659360411 ps
CPU time 36.22 seconds
Started May 12 12:56:07 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204552 kb
Host smart-2a70ac0b-479f-4587-a2d5-f8e6acca566c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12304
65261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1230465261
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1770328884
Short name T885
Test name
Test status
Simulation time 8386777886 ps
CPU time 10.22 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204428 kb
Host smart-02113b6f-7239-4ae0-a489-7a6be255d12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17703
28884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1770328884
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1681135268
Short name T840
Test name
Test status
Simulation time 8385353955 ps
CPU time 8.52 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:17 PM PDT 24
Peak memory 204432 kb
Host smart-10132693-3973-4256-ab63-28bdc254c7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16811
35268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1681135268
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.4248778589
Short name T661
Test name
Test status
Simulation time 8390854696 ps
CPU time 7.51 seconds
Started May 12 12:56:10 PM PDT 24
Finished May 12 12:56:18 PM PDT 24
Peak memory 204436 kb
Host smart-4c33624c-ba0d-4e05-9067-5f67c84e6a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
78589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.4248778589
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3411335568
Short name T1154
Test name
Test status
Simulation time 8375164021 ps
CPU time 8.89 seconds
Started May 12 12:56:07 PM PDT 24
Finished May 12 12:56:17 PM PDT 24
Peak memory 204448 kb
Host smart-b74ecd5d-5bdf-49eb-83d8-b911c2bd868f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34113
35568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3411335568
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2223346604
Short name T586
Test name
Test status
Simulation time 8366877143 ps
CPU time 9.38 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:41 PM PDT 24
Peak memory 204468 kb
Host smart-412616b4-12d0-4fa7-9d20-4a421532e4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22233
46604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2223346604
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3146176320
Short name T177
Test name
Test status
Simulation time 8466638534 ps
CPU time 8.77 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204472 kb
Host smart-91cc12b4-b2ff-45ef-98c5-4bef85d24790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31461
76320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3146176320
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1064169021
Short name T242
Test name
Test status
Simulation time 8389254734 ps
CPU time 7.87 seconds
Started May 12 12:56:02 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 204424 kb
Host smart-da3ab730-d74d-4cb5-8b13-301c702d7ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
69021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1064169021
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1389874348
Short name T650
Test name
Test status
Simulation time 8424341136 ps
CPU time 8.21 seconds
Started May 12 12:56:03 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204328 kb
Host smart-9e9ae2f8-c65e-45c4-a816-c615de1e81da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13898
74348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1389874348
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.606070310
Short name T135
Test name
Test status
Simulation time 8514020762 ps
CPU time 8.61 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:22 PM PDT 24
Peak memory 204464 kb
Host smart-31354396-19cc-44e0-a9d5-bcca512e687f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=606070310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.606070310
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.1573076494
Short name T637
Test name
Test status
Simulation time 8417914444 ps
CPU time 7.89 seconds
Started May 12 12:56:06 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 204532 kb
Host smart-f49d4738-83cc-4de9-9b73-198bd096006f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1573076494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.1573076494
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.2471124177
Short name T1416
Test name
Test status
Simulation time 8382788787 ps
CPU time 7.85 seconds
Started May 12 12:56:14 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204324 kb
Host smart-036036d8-4681-4158-b390-1022f12503d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711
24177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.2471124177
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.4046434095
Short name T951
Test name
Test status
Simulation time 8403240538 ps
CPU time 8.2 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204352 kb
Host smart-d59db26e-991f-461a-9664-7808defd23fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40464
34095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4046434095
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1161152007
Short name T1353
Test name
Test status
Simulation time 9416927040 ps
CPU time 12.73 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204756 kb
Host smart-f389b75e-fc0b-4c30-abd2-466e313a180e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
52007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1161152007
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_enable.604983698
Short name T469
Test name
Test status
Simulation time 8384605986 ps
CPU time 8.14 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:17 PM PDT 24
Peak memory 204388 kb
Host smart-231c33c1-6601-4b0c-a128-11bc2a03f639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60498
3698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.604983698
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2298228601
Short name T766
Test name
Test status
Simulation time 115844207 ps
CPU time 1.88 seconds
Started May 12 12:56:02 PM PDT 24
Finished May 12 12:56:04 PM PDT 24
Peak memory 204600 kb
Host smart-9f65c4bc-f05f-4bf1-996e-07a0783b378b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22982
28601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2298228601
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1437667108
Short name T1124
Test name
Test status
Simulation time 8413625488 ps
CPU time 8.52 seconds
Started May 12 12:56:15 PM PDT 24
Finished May 12 12:56:24 PM PDT 24
Peak memory 204336 kb
Host smart-d7de90dd-d7f5-46dd-8b4e-12e0592cfec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14376
67108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1437667108
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3741100517
Short name T823
Test name
Test status
Simulation time 8404163404 ps
CPU time 7.99 seconds
Started May 12 12:56:15 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204460 kb
Host smart-0c241e6b-62b1-4433-adad-5fb07ac06bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37411
00517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3741100517
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3172675316
Short name T739
Test name
Test status
Simulation time 8441318411 ps
CPU time 8.03 seconds
Started May 12 12:56:16 PM PDT 24
Finished May 12 12:56:24 PM PDT 24
Peak memory 204460 kb
Host smart-1018e3fc-c9db-4df2-828b-65c1cc27ee36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31726
75316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3172675316
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1563570107
Short name T651
Test name
Test status
Simulation time 8368357521 ps
CPU time 8 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204500 kb
Host smart-88b1ba67-289f-45cd-8a17-98859714bd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15635
70107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1563570107
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3182789831
Short name T121
Test name
Test status
Simulation time 8475621924 ps
CPU time 8.29 seconds
Started May 12 12:56:12 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 204340 kb
Host smart-c8a3b5b5-378d-4e95-b587-c9bb70f56025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31827
89831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3182789831
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1763628281
Short name T430
Test name
Test status
Simulation time 8457251124 ps
CPU time 8.24 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204400 kb
Host smart-173cfcdd-6002-427c-8908-fde4adbba8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17636
28281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1763628281
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1376678776
Short name T247
Test name
Test status
Simulation time 8405138226 ps
CPU time 7.78 seconds
Started May 12 12:56:08 PM PDT 24
Finished May 12 12:56:17 PM PDT 24
Peak memory 204480 kb
Host smart-9d4056d1-0e40-4c6e-9fd3-104d6ee8f433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766
78776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1376678776
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.111851527
Short name T174
Test name
Test status
Simulation time 8407446708 ps
CPU time 7.97 seconds
Started May 12 12:56:13 PM PDT 24
Finished May 12 12:56:22 PM PDT 24
Peak memory 204344 kb
Host smart-3d0082a1-81f3-4cdd-b655-38b8bf3b6dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
1527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.111851527
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2682573127
Short name T964
Test name
Test status
Simulation time 8368198233 ps
CPU time 9.59 seconds
Started May 12 12:56:11 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 204460 kb
Host smart-ccdbd86d-bbfa-4194-817f-2866d0b4d993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
73127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2682573127
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2692532960
Short name T629
Test name
Test status
Simulation time 78589265 ps
CPU time 0.73 seconds
Started May 12 12:56:04 PM PDT 24
Finished May 12 12:56:06 PM PDT 24
Peak memory 204420 kb
Host smart-6ee2bb8f-68cd-4b73-9c74-57104d4d608e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26925
32960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2692532960
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.263533479
Short name T1091
Test name
Test status
Simulation time 8409545321 ps
CPU time 10.13 seconds
Started May 12 12:56:02 PM PDT 24
Finished May 12 12:56:13 PM PDT 24
Peak memory 204348 kb
Host smart-a6b08190-0ee7-4fbb-9458-d9e0a0166045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.263533479
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2357576087
Short name T167
Test name
Test status
Simulation time 8431373879 ps
CPU time 7.71 seconds
Started May 12 12:56:10 PM PDT 24
Finished May 12 12:56:18 PM PDT 24
Peak memory 204460 kb
Host smart-45e3e5be-4029-496b-b3e5-4447a11075ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23575
76087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2357576087
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1659119879
Short name T1294
Test name
Test status
Simulation time 8410105293 ps
CPU time 8.14 seconds
Started May 12 12:56:05 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 204332 kb
Host smart-c637ceac-025f-4845-9bad-6cb9c33d36f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
19879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1659119879
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1743546529
Short name T917
Test name
Test status
Simulation time 8387236697 ps
CPU time 9.08 seconds
Started May 12 12:56:09 PM PDT 24
Finished May 12 12:56:18 PM PDT 24
Peak memory 204484 kb
Host smart-bbc957c0-4157-4a4c-bf0b-8c15134627d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17435
46529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1743546529
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3263724997
Short name T577
Test name
Test status
Simulation time 8365029360 ps
CPU time 8.05 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204416 kb
Host smart-3af8b4c3-4249-4c3b-a718-2b59465e6335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32637
24997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3263724997
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1349973737
Short name T785
Test name
Test status
Simulation time 8459519372 ps
CPU time 7.85 seconds
Started May 12 12:56:04 PM PDT 24
Finished May 12 12:56:12 PM PDT 24
Peak memory 204428 kb
Host smart-4ef6ddc8-e7d7-4ce4-a9f8-393e885b214f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
73737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1349973737
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2048392265
Short name T575
Test name
Test status
Simulation time 8424119583 ps
CPU time 8.36 seconds
Started May 12 12:56:07 PM PDT 24
Finished May 12 12:56:16 PM PDT 24
Peak memory 204372 kb
Host smart-16a875ba-2bf9-4bd7-b7f1-78e874a11774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483
92265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2048392265
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3225108781
Short name T645
Test name
Test status
Simulation time 8398709915 ps
CPU time 8.38 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204496 kb
Host smart-f886d5c9-429f-4d21-ad05-23c71055b6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32251
08781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3225108781
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.4105578314
Short name T918
Test name
Test status
Simulation time 8461764748 ps
CPU time 7.81 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204452 kb
Host smart-34b92fe4-d00f-49c0-98a7-5fb56c888a40
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4105578314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.4105578314
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.3258493723
Short name T1366
Test name
Test status
Simulation time 8382282864 ps
CPU time 7.78 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204412 kb
Host smart-e7258777-5d73-479f-8a19-b1b2fd65632c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3258493723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.3258493723
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.3051471819
Short name T397
Test name
Test status
Simulation time 8421468357 ps
CPU time 8.76 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204312 kb
Host smart-5056494f-b5a9-4d43-a3c2-3392cf5902ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30514
71819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.3051471819
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3806145085
Short name T435
Test name
Test status
Simulation time 8379900823 ps
CPU time 7.81 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204388 kb
Host smart-34854f6e-c6c6-4da6-a4e5-631d7be5f447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38061
45085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3806145085
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.4125343061
Short name T1058
Test name
Test status
Simulation time 9166925352 ps
CPU time 12.78 seconds
Started May 12 12:56:15 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 204796 kb
Host smart-3fdc367f-122b-4d1e-8803-c2aae5bd9132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41253
43061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.4125343061
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_enable.3255376923
Short name T426
Test name
Test status
Simulation time 8379981764 ps
CPU time 7.5 seconds
Started May 12 12:56:14 PM PDT 24
Finished May 12 12:56:22 PM PDT 24
Peak memory 204396 kb
Host smart-73a6b2d2-f520-4561-80b7-b043d73d8c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
76923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3255376923
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.538505693
Short name T423
Test name
Test status
Simulation time 241754446 ps
CPU time 1.86 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204792 kb
Host smart-8637c094-47f6-46df-a428-b0da48061c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53850
5693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.538505693
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.753112036
Short name T857
Test name
Test status
Simulation time 8387068186 ps
CPU time 10.12 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204376 kb
Host smart-0e5d963d-7e44-4a50-907d-edd15c933ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75311
2036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.753112036
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1794496579
Short name T1152
Test name
Test status
Simulation time 8416181319 ps
CPU time 7.69 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204428 kb
Host smart-b6ab4d13-22c4-434a-8b4e-83c606d341f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17944
96579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1794496579
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2849844788
Short name T664
Test name
Test status
Simulation time 8425141692 ps
CPU time 8.6 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204376 kb
Host smart-75a70972-0db9-4f97-8a8d-c2c60cd303a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28498
44788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2849844788
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.12502748
Short name T1287
Test name
Test status
Simulation time 8446978281 ps
CPU time 9.64 seconds
Started May 12 12:56:14 PM PDT 24
Finished May 12 12:56:24 PM PDT 24
Peak memory 204436 kb
Host smart-916aaaed-87de-4039-9b6f-0fad9fbfcb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.12502748
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1601611058
Short name T532
Test name
Test status
Simulation time 8369228210 ps
CPU time 10.2 seconds
Started May 12 12:56:17 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 204388 kb
Host smart-cb7ca575-bd8f-4304-b562-67d1560ec3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16016
11058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1601611058
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.66599568
Short name T108
Test name
Test status
Simulation time 8437674564 ps
CPU time 7.76 seconds
Started May 12 12:56:18 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204372 kb
Host smart-9ec4f4f0-3c11-4faa-b2bd-54cb4857eb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66599
568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.66599568
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.683538091
Short name T944
Test name
Test status
Simulation time 8394337791 ps
CPU time 8.1 seconds
Started May 12 12:56:17 PM PDT 24
Finished May 12 12:56:26 PM PDT 24
Peak memory 204384 kb
Host smart-be47ddb5-8ff7-42c9-8f9c-94614533f5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68353
8091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.683538091
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.413871530
Short name T470
Test name
Test status
Simulation time 8394378471 ps
CPU time 8.21 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204412 kb
Host smart-5112547f-b046-40de-91d4-c2a02519e4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
1530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.413871530
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1999478794
Short name T168
Test name
Test status
Simulation time 8397791953 ps
CPU time 7.9 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:29 PM PDT 24
Peak memory 204496 kb
Host smart-b35af38a-6460-437d-a64e-0dab642c9779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19994
78794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1999478794
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1395499433
Short name T496
Test name
Test status
Simulation time 8410109668 ps
CPU time 8.55 seconds
Started May 12 12:56:15 PM PDT 24
Finished May 12 12:56:24 PM PDT 24
Peak memory 204400 kb
Host smart-9b6aa31d-be4f-4fb9-bc88-a66bf81c18c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
99433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1395499433
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.399881686
Short name T1266
Test name
Test status
Simulation time 88989136 ps
CPU time 0.7 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:26 PM PDT 24
Peak memory 204336 kb
Host smart-0b4f7ffa-512a-49be-bd62-09cc3c3ea07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39988
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.399881686
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1258354240
Short name T959
Test name
Test status
Simulation time 31853192377 ps
CPU time 66.66 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204724 kb
Host smart-58d5c763-f273-4fc4-9de0-98b282055ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12583
54240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1258354240
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3199085521
Short name T271
Test name
Test status
Simulation time 8385932694 ps
CPU time 7.92 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204516 kb
Host smart-30a1f0c9-db1d-49dc-85a7-49fff6c81feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31990
85521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3199085521
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.880318864
Short name T1068
Test name
Test status
Simulation time 8429817294 ps
CPU time 9.88 seconds
Started May 12 12:56:15 PM PDT 24
Finished May 12 12:56:25 PM PDT 24
Peak memory 204756 kb
Host smart-a6272626-d946-4254-8acb-849abe496f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88031
8864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.880318864
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3407142666
Short name T1063
Test name
Test status
Simulation time 8395411421 ps
CPU time 8.21 seconds
Started May 12 12:56:11 PM PDT 24
Finished May 12 12:56:19 PM PDT 24
Peak memory 204428 kb
Host smart-bd09b97f-f4e0-4f8c-9580-a61ad9e64951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071
42666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3407142666
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1382250764
Short name T267
Test name
Test status
Simulation time 8450753268 ps
CPU time 10.06 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204408 kb
Host smart-a300942c-542d-4f85-8ab5-2a90b0336b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13822
50764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1382250764
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2726350558
Short name T30
Test name
Test status
Simulation time 8373727284 ps
CPU time 8.72 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 204452 kb
Host smart-b369796a-03c1-4277-93fc-d62ef117c82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
50558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2726350558
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.416924803
Short name T945
Test name
Test status
Simulation time 8473284917 ps
CPU time 8.2 seconds
Started May 12 12:56:16 PM PDT 24
Finished May 12 12:56:24 PM PDT 24
Peak memory 204436 kb
Host smart-d8b40451-8a1a-49b6-95e9-a5f37ff55f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41692
4803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.416924803
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1403555583
Short name T1437
Test name
Test status
Simulation time 8400959869 ps
CPU time 8.24 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204364 kb
Host smart-40f6f389-aaa3-4f59-b66c-c07eda1565f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14035
55583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1403555583
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1497739461
Short name T1039
Test name
Test status
Simulation time 8377953224 ps
CPU time 7.45 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204448 kb
Host smart-f4f30658-548f-4acb-95af-4209cb6ad27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14977
39461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1497739461
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.153868527
Short name T751
Test name
Test status
Simulation time 8474537729 ps
CPU time 8.58 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204464 kb
Host smart-b3d19548-8b74-4449-b90d-aeb3fc030222
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=153868527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.153868527
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.201234310
Short name T1262
Test name
Test status
Simulation time 8375676361 ps
CPU time 8.82 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204464 kb
Host smart-ad111f8f-f7ea-4846-9168-d2088d7c6acb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=201234310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.201234310
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.3317167001
Short name T935
Test name
Test status
Simulation time 8448539646 ps
CPU time 8.78 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204448 kb
Host smart-63cd08d8-2af8-45f0-9ccf-ee007bd41cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
67001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.3317167001
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.920121699
Short name T914
Test name
Test status
Simulation time 8378062381 ps
CPU time 8.96 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204476 kb
Host smart-e1ccec7a-6869-4dee-9e65-e6dd55c09dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92012
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.920121699
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3984994961
Short name T193
Test name
Test status
Simulation time 9105564902 ps
CPU time 12.78 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204636 kb
Host smart-f89339bf-06c3-471d-98ab-e0d0af0d31e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39849
94961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3984994961
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_enable.3511569155
Short name T1035
Test name
Test status
Simulation time 8374047117 ps
CPU time 8.23 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204500 kb
Host smart-d0d89564-a7f7-41f7-a31f-4dbd78669ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
69155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3511569155
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1052370647
Short name T592
Test name
Test status
Simulation time 156887217 ps
CPU time 1.44 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204876 kb
Host smart-bcd30b81-2b32-4c2b-8424-1828ee2fa546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
70647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1052370647
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.4288441207
Short name T161
Test name
Test status
Simulation time 8431611311 ps
CPU time 8.5 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204428 kb
Host smart-99284c00-14a1-4210-9ffa-fdd052b5eaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
41207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.4288441207
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2236724094
Short name T1026
Test name
Test status
Simulation time 8363446822 ps
CPU time 7.37 seconds
Started May 12 12:56:18 PM PDT 24
Finished May 12 12:56:26 PM PDT 24
Peak memory 204412 kb
Host smart-a7f5d03e-b76d-437c-90da-439908c54464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22367
24094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2236724094
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3158285490
Short name T1363
Test name
Test status
Simulation time 8396823494 ps
CPU time 8.35 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204324 kb
Host smart-95083ad8-abf9-4f0a-b665-e9cf3e301a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
85490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3158285490
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2584314950
Short name T612
Test name
Test status
Simulation time 8416410434 ps
CPU time 10.04 seconds
Started May 12 12:56:17 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204396 kb
Host smart-56b4b093-0d08-4a20-853d-96aa79211680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25843
14950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2584314950
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3308326593
Short name T681
Test name
Test status
Simulation time 8384655392 ps
CPU time 7.59 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204460 kb
Host smart-4957d789-a3d7-468a-a514-617d89638b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
26593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3308326593
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.979283601
Short name T114
Test name
Test status
Simulation time 8418995503 ps
CPU time 9.91 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204460 kb
Host smart-d9521bc6-7f46-4218-8e66-82b15d10be66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97928
3601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.979283601
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1118953888
Short name T757
Test name
Test status
Simulation time 8410304972 ps
CPU time 9.11 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204476 kb
Host smart-30042e0c-2105-4b50-bb3b-00736d9762f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
53888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1118953888
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1679323678
Short name T1127
Test name
Test status
Simulation time 8426000062 ps
CPU time 7.58 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204472 kb
Host smart-118d8242-9fc8-426c-8a4f-75b99d2ad4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
23678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1679323678
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2963972684
Short name T1265
Test name
Test status
Simulation time 8384029107 ps
CPU time 9.96 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204456 kb
Host smart-0ada3d0a-8ec7-433f-a71e-f6b624254f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29639
72684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2963972684
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2443466807
Short name T829
Test name
Test status
Simulation time 8372016458 ps
CPU time 8.01 seconds
Started May 12 12:56:18 PM PDT 24
Finished May 12 12:56:26 PM PDT 24
Peak memory 204348 kb
Host smart-81679508-1893-403d-8d4a-f15ce02709e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24434
66807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2443466807
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.4101141731
Short name T1016
Test name
Test status
Simulation time 36036241 ps
CPU time 0.69 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:26 PM PDT 24
Peak memory 204288 kb
Host smart-3ee4c30a-86e1-4f52-8f97-6e2af3372e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41011
41731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.4101141731
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2478458860
Short name T250
Test name
Test status
Simulation time 16214857628 ps
CPU time 27.96 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:49 PM PDT 24
Peak memory 204684 kb
Host smart-2ce43bac-8cd2-491b-97c0-20904e1a38ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
58860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2478458860
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3317292233
Short name T332
Test name
Test status
Simulation time 8464820897 ps
CPU time 8.02 seconds
Started May 12 12:56:33 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204472 kb
Host smart-b93f870b-a308-48b0-943d-1a18c51add2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33172
92233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3317292233
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3227867178
Short name T1175
Test name
Test status
Simulation time 8449730859 ps
CPU time 7.82 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204416 kb
Host smart-c79f6521-034e-465b-a8f9-a851c507af49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32278
67178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3227867178
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1357285728
Short name T1259
Test name
Test status
Simulation time 8415626829 ps
CPU time 7.62 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204392 kb
Host smart-5f301228-9a7c-4d53-8747-bda44a7f311a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
85728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1357285728
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.479323930
Short name T861
Test name
Test status
Simulation time 8372638058 ps
CPU time 7.85 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 204436 kb
Host smart-6bd5571f-2e85-4e13-ab1c-e22345286e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47932
3930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.479323930
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.217715212
Short name T295
Test name
Test status
Simulation time 8372946429 ps
CPU time 10.1 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204468 kb
Host smart-ca50a9b9-d2d6-48d8-aa60-45eff38e54da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771
5212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.217715212
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2295282930
Short name T1308
Test name
Test status
Simulation time 8476467902 ps
CPU time 7.65 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204688 kb
Host smart-1cfaa479-72bc-4ddd-afb3-110cde8f8fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22952
82930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2295282930
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2934188522
Short name T1289
Test name
Test status
Simulation time 8414858545 ps
CPU time 7.71 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204336 kb
Host smart-e7e7e383-5043-4684-a3db-38a977306b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29341
88522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2934188522
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1308581975
Short name T1130
Test name
Test status
Simulation time 8376493327 ps
CPU time 8.21 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204416 kb
Host smart-ca8b3cbe-a0c1-4496-a399-5f28cabc0a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13085
81975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1308581975
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2194511665
Short name T1398
Test name
Test status
Simulation time 8463351367 ps
CPU time 9.82 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204420 kb
Host smart-da888cd1-06ea-4060-911c-6b00c964ec3c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2194511665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2194511665
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3666084254
Short name T1002
Test name
Test status
Simulation time 8379394311 ps
CPU time 7.44 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:29 PM PDT 24
Peak memory 204436 kb
Host smart-540a7735-e1f6-437f-90fc-63c116584bb3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3666084254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3666084254
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.43640665
Short name T786
Test name
Test status
Simulation time 8387720243 ps
CPU time 10.29 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204536 kb
Host smart-ec3c20e4-16f4-42a2-95d6-913f9979b6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43640
665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.43640665
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3778606059
Short name T851
Test name
Test status
Simulation time 8373340044 ps
CPU time 7.74 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204356 kb
Host smart-9663759e-e772-4f70-ab01-ca1b30918e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37786
06059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3778606059
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.820654539
Short name T192
Test name
Test status
Simulation time 8961717149 ps
CPU time 12.42 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204732 kb
Host smart-c5e99149-0588-4345-8fca-2d1c7296fc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82065
4539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.820654539
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_enable.287222605
Short name T1260
Test name
Test status
Simulation time 8372457319 ps
CPU time 9.39 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204472 kb
Host smart-5f6e22e6-8dae-493f-bcd6-0608bb092f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28722
2605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.287222605
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2123381329
Short name T1309
Test name
Test status
Simulation time 230616568 ps
CPU time 1.94 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 204540 kb
Host smart-e4b1890e-ce04-42b4-9e7e-b9f2b466e1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21233
81329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2123381329
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3940947307
Short name T961
Test name
Test status
Simulation time 8396874267 ps
CPU time 7.99 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204412 kb
Host smart-9b7386d3-ea3d-4e5b-b651-c16756bf3a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
47307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3940947307
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3324360908
Short name T891
Test name
Test status
Simulation time 8379205955 ps
CPU time 7.87 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204520 kb
Host smart-e120e39a-c0af-4e20-a44d-678e0697c6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33243
60908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3324360908
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3402562179
Short name T541
Test name
Test status
Simulation time 8445316494 ps
CPU time 8.82 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204460 kb
Host smart-36adc14a-a88a-4d87-a1d1-ff8beb0b02c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
62179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3402562179
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1336181035
Short name T346
Test name
Test status
Simulation time 8415554061 ps
CPU time 7.65 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204476 kb
Host smart-0cc1bd04-dad1-460b-af5f-f57c8584a949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
81035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1336181035
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2923039264
Short name T960
Test name
Test status
Simulation time 8377365467 ps
CPU time 8.14 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204388 kb
Host smart-d345328c-fa08-4f7f-ac13-2bc78bf6cc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
39264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2923039264
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.146090998
Short name T133
Test name
Test status
Simulation time 8447861233 ps
CPU time 8.53 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204444 kb
Host smart-c42bbb68-177a-430d-9c59-c8308d883db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14609
0998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.146090998
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.265412984
Short name T32
Test name
Test status
Simulation time 8397220804 ps
CPU time 7.58 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204460 kb
Host smart-90cf6876-90aa-46da-ba5c-2d28d379462c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26541
2984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.265412984
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.4037475352
Short name T1217
Test name
Test status
Simulation time 8393387822 ps
CPU time 8.07 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204428 kb
Host smart-1644d3ce-6aa7-4545-80c9-7b86f149be9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40374
75352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.4037475352
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.896926111
Short name T1409
Test name
Test status
Simulation time 8406419924 ps
CPU time 7.86 seconds
Started May 12 12:56:33 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204516 kb
Host smart-4bad334b-ddb2-4a7c-9edf-26edd18e91f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89692
6111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.896926111
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3278291160
Short name T849
Test name
Test status
Simulation time 8369701546 ps
CPU time 8.33 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204336 kb
Host smart-f315583d-b1ac-4500-8aaf-e84b7bcd5383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782
91160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3278291160
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3551241551
Short name T991
Test name
Test status
Simulation time 37516659 ps
CPU time 0.64 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 204248 kb
Host smart-b8829d75-fccb-471f-9204-9a892b635549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35512
41551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3551241551
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1280063423
Short name T275
Test name
Test status
Simulation time 22585908946 ps
CPU time 41.75 seconds
Started May 12 12:56:25 PM PDT 24
Finished May 12 12:57:08 PM PDT 24
Peak memory 204676 kb
Host smart-5b93d1db-bfea-45f7-b9fe-ccb9221e4fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
63423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1280063423
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1155242085
Short name T1187
Test name
Test status
Simulation time 8404517483 ps
CPU time 7.88 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204416 kb
Host smart-f59d4601-35f1-4ab8-a688-313cd811863f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
42085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1155242085
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2877221186
Short name T422
Test name
Test status
Simulation time 8440374708 ps
CPU time 7.93 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 204436 kb
Host smart-6cadc826-154a-4a0a-a80b-0220a8ade4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28772
21186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2877221186
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.570797494
Short name T1272
Test name
Test status
Simulation time 8434904627 ps
CPU time 8.49 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204528 kb
Host smart-75787ef8-7ff0-40a5-8def-05dfbc73e042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57079
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.570797494
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1163998588
Short name T822
Test name
Test status
Simulation time 8387326841 ps
CPU time 9.93 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204380 kb
Host smart-b2b456d4-d0d3-4d0b-8be3-697bf8ab67ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11639
98588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1163998588
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3666982717
Short name T396
Test name
Test status
Simulation time 8391614071 ps
CPU time 10.06 seconds
Started May 12 12:56:39 PM PDT 24
Finished May 12 12:56:49 PM PDT 24
Peak memory 204452 kb
Host smart-bcb03f64-da85-47cc-9e0b-3c9bf156837e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36669
82717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3666982717
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2260156661
Short name T1109
Test name
Test status
Simulation time 8436716256 ps
CPU time 9.98 seconds
Started May 12 12:56:18 PM PDT 24
Finished May 12 12:56:29 PM PDT 24
Peak memory 204440 kb
Host smart-1f196597-5f21-401e-9df7-681a9a84b63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22601
56661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2260156661
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3567645257
Short name T983
Test name
Test status
Simulation time 8372255800 ps
CPU time 9.26 seconds
Started May 12 12:56:25 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204516 kb
Host smart-0e2839bc-763a-491a-8894-feb66552a04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676
45257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3567645257
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2294141683
Short name T344
Test name
Test status
Simulation time 8390343627 ps
CPU time 7.56 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204380 kb
Host smart-6469c91f-186e-4455-8b6f-6063f570978f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22941
41683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2294141683
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.322856287
Short name T614
Test name
Test status
Simulation time 8496000014 ps
CPU time 9.17 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204448 kb
Host smart-42d19e01-e62e-4103-836e-00c34a300c04
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=322856287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.322856287
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2386450610
Short name T594
Test name
Test status
Simulation time 8376150758 ps
CPU time 9.93 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204344 kb
Host smart-f63d55b7-6cd0-41a7-97c7-1e94de9c303e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2386450610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2386450610
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2575664436
Short name T362
Test name
Test status
Simulation time 8453446415 ps
CPU time 10.18 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204444 kb
Host smart-86e9c008-cd8d-44c3-924d-0a9b0b872813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25756
64436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2575664436
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3169042134
Short name T814
Test name
Test status
Simulation time 8381540557 ps
CPU time 7.93 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204396 kb
Host smart-2eea2929-d412-4f1f-beda-2d8b01c3f338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
42134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3169042134
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.3614716753
Short name T395
Test name
Test status
Simulation time 8379988639 ps
CPU time 9.56 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204364 kb
Host smart-6f8c1279-0063-485d-938f-8446eacd1f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36147
16753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3614716753
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.492462733
Short name T458
Test name
Test status
Simulation time 206177044 ps
CPU time 2.17 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204660 kb
Host smart-f6913d50-8d4d-4927-b84b-0a15f489a736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49246
2733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.492462733
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3544805867
Short name T1044
Test name
Test status
Simulation time 8414899533 ps
CPU time 8.17 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204444 kb
Host smart-47e36fbc-073c-4908-84c2-ef4bdc6272c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35448
05867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3544805867
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2778629545
Short name T225
Test name
Test status
Simulation time 8367480566 ps
CPU time 9.42 seconds
Started May 12 12:56:25 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204444 kb
Host smart-3595f460-7e2a-4654-b3b7-1bb5c1d3bbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
29545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2778629545
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.71803081
Short name T909
Test name
Test status
Simulation time 8453423280 ps
CPU time 8.11 seconds
Started May 12 12:56:33 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204380 kb
Host smart-f7b4a103-0d76-4686-b961-58f3adea5912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71803
081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.71803081
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3711350294
Short name T803
Test name
Test status
Simulation time 8428677537 ps
CPU time 7.96 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204424 kb
Host smart-da52e2f5-7f5c-4c2b-aa44-6e34847b9930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37113
50294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3711350294
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3706667959
Short name T1138
Test name
Test status
Simulation time 8377092404 ps
CPU time 7.77 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204444 kb
Host smart-24ec413c-816c-470c-9b41-148c35f43fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37066
67959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3706667959
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3609040323
Short name T105
Test name
Test status
Simulation time 8462413648 ps
CPU time 8.08 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204368 kb
Host smart-17495f93-6f7a-4dd2-a8d0-0baebed1bbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090
40323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3609040323
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3554668755
Short name T84
Test name
Test status
Simulation time 8395596772 ps
CPU time 8.9 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204324 kb
Host smart-2a9327ac-48af-4e07-bd43-2955858f22fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35546
68755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3554668755
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.166023352
Short name T1270
Test name
Test status
Simulation time 8400821205 ps
CPU time 8.66 seconds
Started May 12 12:56:25 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204400 kb
Host smart-4ec2721d-31bd-4eff-8ce3-c9df30e272ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.166023352
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.488334116
Short name T1143
Test name
Test status
Simulation time 8408368293 ps
CPU time 8.13 seconds
Started May 12 12:56:37 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204440 kb
Host smart-7aafafe3-3108-4d60-ba18-1adbf5daf699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48833
4116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.488334116
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1430280005
Short name T1322
Test name
Test status
Simulation time 8370312945 ps
CPU time 7.56 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204332 kb
Host smart-d128df2a-c9e6-4bd7-b6c6-200dcbc36f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14302
80005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1430280005
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2135039230
Short name T744
Test name
Test status
Simulation time 41377385 ps
CPU time 0.65 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204348 kb
Host smart-492c836a-51f3-4096-866e-1aaeea319bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
39230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2135039230
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2275524288
Short name T607
Test name
Test status
Simulation time 14741624018 ps
CPU time 25.03 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:57:02 PM PDT 24
Peak memory 204752 kb
Host smart-c0783b79-435a-4ea7-bdab-1c4a239c88da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22755
24288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2275524288
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1996899117
Short name T498
Test name
Test status
Simulation time 8398792607 ps
CPU time 8.08 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:29 PM PDT 24
Peak memory 204372 kb
Host smart-015fbfa9-4d0e-4cdd-8e1b-ad2a5347a221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19968
99117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1996899117
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3947008917
Short name T653
Test name
Test status
Simulation time 8437997739 ps
CPU time 8.73 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204384 kb
Host smart-eba33bb4-182d-408e-b3de-402e2da81fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
08917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3947008917
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2331817111
Short name T930
Test name
Test status
Simulation time 8398139691 ps
CPU time 7.47 seconds
Started May 12 12:56:19 PM PDT 24
Finished May 12 12:56:27 PM PDT 24
Peak memory 204428 kb
Host smart-dc5761fd-1b9e-415c-8828-d01471559127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23318
17111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2331817111
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4227440699
Short name T950
Test name
Test status
Simulation time 8381327959 ps
CPU time 8.87 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204372 kb
Host smart-00e5722c-5ec5-4453-805c-d81e76a44297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
40699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4227440699
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1813908167
Short name T810
Test name
Test status
Simulation time 8371661026 ps
CPU time 8.13 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204368 kb
Host smart-5edcc54c-c65c-4655-baa1-c864697b1d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
08167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1813908167
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.802652599
Short name T156
Test name
Test status
Simulation time 8478398743 ps
CPU time 7.96 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204788 kb
Host smart-bbf9c4f2-73d0-4f51-892b-3adc28840b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80265
2599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.802652599
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1203923165
Short name T1312
Test name
Test status
Simulation time 8410694322 ps
CPU time 8.34 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204456 kb
Host smart-4d89103b-3aab-4544-8455-243486d0f180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12039
23165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1203923165
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1911287230
Short name T890
Test name
Test status
Simulation time 8413618056 ps
CPU time 7.74 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204348 kb
Host smart-9e0c135b-dcc1-4a29-8fef-63996d8f9186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19112
87230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1911287230
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1184397504
Short name T442
Test name
Test status
Simulation time 8465442692 ps
CPU time 7.46 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204400 kb
Host smart-1bce25d3-b4a0-405c-a5e3-c86fe8931ef4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1184397504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1184397504
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2084902301
Short name T1074
Test name
Test status
Simulation time 8390685357 ps
CPU time 7.93 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204436 kb
Host smart-4312f376-5063-418a-a5c9-2ac7a6cd5977
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2084902301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2084902301
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.2540774839
Short name T910
Test name
Test status
Simulation time 8425587340 ps
CPU time 7.86 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204372 kb
Host smart-e3a3b5d5-c6d2-4a2e-9b71-3ad196079094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25407
74839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.2540774839
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4061236061
Short name T938
Test name
Test status
Simulation time 8373482120 ps
CPU time 8.15 seconds
Started May 12 12:54:33 PM PDT 24
Finished May 12 12:54:42 PM PDT 24
Peak memory 204344 kb
Host smart-56e70827-1587-49db-a625-14c81ce063a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40612
36061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4061236061
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.807652027
Short name T194
Test name
Test status
Simulation time 9194390720 ps
CPU time 13.68 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204720 kb
Host smart-40e77b5a-04f5-4c1f-9f76-c2b4e0f4ff48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80765
2027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.807652027
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_enable.573220775
Short name T894
Test name
Test status
Simulation time 8378827372 ps
CPU time 7.78 seconds
Started May 12 12:54:42 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204388 kb
Host smart-565bfa34-8e37-4502-af25-f7e52391ad5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57322
0775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.573220775
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.171309662
Short name T1263
Test name
Test status
Simulation time 172176853 ps
CPU time 1.47 seconds
Started May 12 12:54:42 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204676 kb
Host smart-e63f1519-4758-42ed-a012-4cbcd0751df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17130
9662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.171309662
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1542869088
Short name T1037
Test name
Test status
Simulation time 8451660212 ps
CPU time 8.22 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204444 kb
Host smart-fb13e393-9dac-43cb-a2b6-3c0a14674c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
69088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1542869088
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.4168972383
Short name T518
Test name
Test status
Simulation time 8368838086 ps
CPU time 8.52 seconds
Started May 12 12:54:51 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 204476 kb
Host smart-0d15806b-2769-439c-8cd5-225e8c4c88bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41689
72383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4168972383
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3366121696
Short name T1274
Test name
Test status
Simulation time 8442509509 ps
CPU time 9.24 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204420 kb
Host smart-37668484-7957-4315-8bc5-ae052e8a6854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
21696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3366121696
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1405827679
Short name T713
Test name
Test status
Simulation time 8425694215 ps
CPU time 10.24 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204760 kb
Host smart-f3f5bdb5-0577-4f28-aae8-a21d2a515d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058
27679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1405827679
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2479623358
Short name T509
Test name
Test status
Simulation time 8366773700 ps
CPU time 9.05 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204440 kb
Host smart-58f9bc63-033a-4ef9-8fe6-44cb0af31c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24796
23358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2479623358
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.105031667
Short name T125
Test name
Test status
Simulation time 8415971717 ps
CPU time 7.78 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204432 kb
Host smart-3560e396-c99b-44dc-a0b9-1509595d9233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10503
1667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.105031667
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3345466474
Short name T608
Test name
Test status
Simulation time 8402160874 ps
CPU time 9.85 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204416 kb
Host smart-a4349968-afe2-4279-9936-8c8be4e83e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
66474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3345466474
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.405416078
Short name T415
Test name
Test status
Simulation time 8406841196 ps
CPU time 8.1 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204420 kb
Host smart-b7451aed-8e45-435f-a148-45d8c24c011f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
6078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.405416078
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2848698495
Short name T846
Test name
Test status
Simulation time 8406871706 ps
CPU time 8.72 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204416 kb
Host smart-c81f787f-f461-40d5-b26b-9ba6afbbefde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
98495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2848698495
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1419430808
Short name T965
Test name
Test status
Simulation time 8379673652 ps
CPU time 7.71 seconds
Started May 12 12:54:39 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204328 kb
Host smart-80421797-0406-46e8-8aaf-84f4968ed3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
30808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1419430808
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2828685693
Short name T791
Test name
Test status
Simulation time 162071257 ps
CPU time 0.77 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:54:40 PM PDT 24
Peak memory 204460 kb
Host smart-3056b38d-65d5-4a6c-9d11-703c87e331e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
85693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2828685693
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1941477799
Short name T886
Test name
Test status
Simulation time 25895757926 ps
CPU time 57.75 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:55:46 PM PDT 24
Peak memory 204776 kb
Host smart-e5ead553-3eac-48bd-a256-36fd09f2b47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
77799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1941477799
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.4276285349
Short name T974
Test name
Test status
Simulation time 8414146226 ps
CPU time 8.33 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204384 kb
Host smart-5695aa5d-b91a-4291-b29e-056db7e1f037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42762
85349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.4276285349
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2079277973
Short name T649
Test name
Test status
Simulation time 8391729061 ps
CPU time 8.51 seconds
Started May 12 12:54:33 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 204488 kb
Host smart-548a39fa-3e29-411e-bd22-b9eaa0a1a7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20792
77973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2079277973
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3692517984
Short name T554
Test name
Test status
Simulation time 8410861820 ps
CPU time 8.1 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:56 PM PDT 24
Peak memory 204432 kb
Host smart-ffc5ac94-f2fc-446a-93d6-8795c666bc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36925
17984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3692517984
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3051768629
Short name T63
Test name
Test status
Simulation time 302605295 ps
CPU time 1.23 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 221652 kb
Host smart-2c4dcc25-af64-45b4-a832-2c216163c944
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3051768629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3051768629
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2055307739
Short name T864
Test name
Test status
Simulation time 8376118322 ps
CPU time 8.32 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204428 kb
Host smart-89c25910-96e9-4c64-ab7a-76a545d22440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20553
07739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2055307739
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3978587271
Short name T1156
Test name
Test status
Simulation time 8366501313 ps
CPU time 7.82 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 204440 kb
Host smart-a9c0a89b-9741-47ac-b53f-53068263f322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
87271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3978587271
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.4153769852
Short name T619
Test name
Test status
Simulation time 8425777228 ps
CPU time 7.66 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:42 PM PDT 24
Peak memory 204364 kb
Host smart-9c010d64-5989-4d9b-8798-53ace946c928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
69852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.4153769852
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.722759488
Short name T942
Test name
Test status
Simulation time 8450299244 ps
CPU time 8.16 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204452 kb
Host smart-65d501c5-f674-4795-9b47-febdc397a751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72275
9488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.722759488
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.515085223
Short name T449
Test name
Test status
Simulation time 8392317053 ps
CPU time 8.17 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204420 kb
Host smart-3861f791-c25a-402c-a787-1d257e9cac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51508
5223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.515085223
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.3646891763
Short name T159
Test name
Test status
Simulation time 8466136630 ps
CPU time 8.61 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204436 kb
Host smart-e48cd9c8-d79f-48bb-9a9e-76df954754b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3646891763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.3646891763
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3851262445
Short name T1381
Test name
Test status
Simulation time 8376701015 ps
CPU time 8.84 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204436 kb
Host smart-740178ad-7c2f-435f-9494-a800058d3055
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3851262445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3851262445
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.4085537592
Short name T1277
Test name
Test status
Simulation time 8400084892 ps
CPU time 7.64 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204368 kb
Host smart-680959e7-9c3f-42cd-b244-0e275760a510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40855
37592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.4085537592
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.68681710
Short name T341
Test name
Test status
Simulation time 8382194343 ps
CPU time 7.93 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204428 kb
Host smart-ce95836b-7343-4123-940e-4d67c8e49811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68681
710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.68681710
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.542723106
Short name T1349
Test name
Test status
Simulation time 9217678838 ps
CPU time 13.13 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204744 kb
Host smart-bbec1963-8d7c-4e9a-af74-f53f5c10e9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54272
3106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.542723106
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_enable.549436907
Short name T939
Test name
Test status
Simulation time 8393397733 ps
CPU time 7.66 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204500 kb
Host smart-007621a1-07f6-459c-b408-5b13f40a3b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54943
6907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.549436907
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.338697369
Short name T952
Test name
Test status
Simulation time 65570951 ps
CPU time 1.02 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:25 PM PDT 24
Peak memory 204604 kb
Host smart-3b8cfa64-7826-45d1-8d51-286694faf2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33869
7369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.338697369
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2368672404
Short name T815
Test name
Test status
Simulation time 8389235722 ps
CPU time 8.46 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204484 kb
Host smart-cf219720-6d97-4b0a-bac9-cd133db10efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23686
72404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2368672404
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2000316903
Short name T1132
Test name
Test status
Simulation time 8396527887 ps
CPU time 9.91 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204428 kb
Host smart-5e769f0d-9bfd-488d-a079-38209cf18ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20003
16903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2000316903
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3883218127
Short name T906
Test name
Test status
Simulation time 8410037710 ps
CPU time 8.72 seconds
Started May 12 12:56:33 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204420 kb
Host smart-59cd1a88-eb03-4e5b-bd41-b2767606e5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38832
18127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3883218127
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1183637270
Short name T404
Test name
Test status
Simulation time 8418302981 ps
CPU time 9.66 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204444 kb
Host smart-ab71033c-81d4-478e-8958-25d12688bfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11836
37270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1183637270
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3209351215
Short name T1375
Test name
Test status
Simulation time 8369640618 ps
CPU time 8.26 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:41 PM PDT 24
Peak memory 204424 kb
Host smart-33360111-04be-44c1-a152-9209e0e65381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32093
51215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3209351215
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3333716311
Short name T1386
Test name
Test status
Simulation time 8417350631 ps
CPU time 8.08 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204460 kb
Host smart-d2ca2cee-e87c-4089-b929-a4f68ccdb042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
16311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3333716311
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1395154208
Short name T598
Test name
Test status
Simulation time 8417643529 ps
CPU time 8.57 seconds
Started May 12 12:56:21 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204420 kb
Host smart-6f503799-5fc6-464b-9000-d20f89f47e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13951
54208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1395154208
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.128610433
Short name T802
Test name
Test status
Simulation time 8406499258 ps
CPU time 8.29 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204380 kb
Host smart-37a1d35b-3c38-4e3a-b1fe-c66c3882bce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12861
0433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.128610433
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.605113390
Short name T999
Test name
Test status
Simulation time 8398714225 ps
CPU time 7.92 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204340 kb
Host smart-6c37edf2-78ae-4550-b500-6bb5a8b72b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60511
3390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.605113390
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3521702014
Short name T437
Test name
Test status
Simulation time 51156724 ps
CPU time 0.65 seconds
Started May 12 12:56:40 PM PDT 24
Finished May 12 12:56:41 PM PDT 24
Peak memory 204224 kb
Host smart-4700a600-3c80-454d-9202-32a5cf77eeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217
02014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3521702014
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2345986386
Short name T1232
Test name
Test status
Simulation time 8418701327 ps
CPU time 7.84 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204376 kb
Host smart-10c20cf2-600d-4475-ab5e-e88a8f3ed6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23459
86386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2345986386
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.877105276
Short name T813
Test name
Test status
Simulation time 8454339572 ps
CPU time 7.66 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204484 kb
Host smart-61e6d0bd-2bd5-47b5-8536-25991efeb5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87710
5276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.877105276
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1072997446
Short name T981
Test name
Test status
Simulation time 8446161843 ps
CPU time 8.25 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204336 kb
Host smart-97c7b4e3-b1c6-4347-ab74-d7333d34c946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729
97446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1072997446
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1014818604
Short name T183
Test name
Test status
Simulation time 8428579217 ps
CPU time 9.75 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204372 kb
Host smart-89869e12-0391-455f-a91f-6f1766b68350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10148
18604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1014818604
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3874656312
Short name T1193
Test name
Test status
Simulation time 8370582759 ps
CPU time 8.15 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204448 kb
Host smart-e5b6faf1-13d5-4966-9af3-b38a2be83bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746
56312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3874656312
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3484279783
Short name T597
Test name
Test status
Simulation time 8454488340 ps
CPU time 8.49 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204440 kb
Host smart-65049a45-79d7-4ba3-883d-b203b7c9231b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34842
79783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3484279783
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.411351875
Short name T883
Test name
Test status
Simulation time 8373181752 ps
CPU time 9.28 seconds
Started May 12 12:56:20 PM PDT 24
Finished May 12 12:56:30 PM PDT 24
Peak memory 204328 kb
Host smart-de241eb2-3c79-4905-8b5d-8935595d666a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41135
1875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.411351875
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3120342937
Short name T741
Test name
Test status
Simulation time 8418088991 ps
CPU time 7.97 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 204416 kb
Host smart-e9279cb3-2e6f-453f-8548-d495ef27239f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31203
42937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3120342937
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.4222267523
Short name T427
Test name
Test status
Simulation time 8463881826 ps
CPU time 9.61 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204420 kb
Host smart-e2fff1ae-54f0-45db-af22-7bfc83d662af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4222267523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.4222267523
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2951155468
Short name T1279
Test name
Test status
Simulation time 8487648221 ps
CPU time 7.71 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204448 kb
Host smart-c544398d-1938-4eee-8338-1a741f25d872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
55468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2951155468
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4285137532
Short name T460
Test name
Test status
Simulation time 8384603780 ps
CPU time 7.92 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204456 kb
Host smart-a8555ba0-1a38-4dce-908f-dcd87b7cc50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
37532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4285137532
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2063581756
Short name T377
Test name
Test status
Simulation time 8404191025 ps
CPU time 11.75 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204708 kb
Host smart-4c2fc82d-27fa-460c-8762-add1b9347489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
81756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2063581756
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_enable.1219833548
Short name T1172
Test name
Test status
Simulation time 8378097893 ps
CPU time 7.4 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204440 kb
Host smart-c00309d8-d5f1-4d95-8ced-c830c1c6824f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12198
33548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1219833548
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1417495526
Short name T759
Test name
Test status
Simulation time 157416237 ps
CPU time 1.82 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:31 PM PDT 24
Peak memory 204612 kb
Host smart-eefe7ad3-b501-47ca-8fd2-acd0eca9d738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14174
95526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1417495526
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2100251849
Short name T609
Test name
Test status
Simulation time 8506939447 ps
CPU time 8.72 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204352 kb
Host smart-391edb6e-5f28-4172-b42f-0f5bb65cc8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21002
51849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2100251849
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1509160357
Short name T228
Test name
Test status
Simulation time 8380255454 ps
CPU time 7.65 seconds
Started May 12 12:56:37 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204512 kb
Host smart-89f9d9ef-9248-486b-96c9-1e2f00822a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15091
60357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1509160357
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1341122690
Short name T663
Test name
Test status
Simulation time 8394772836 ps
CPU time 7.98 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204760 kb
Host smart-62e31bc6-3d4b-423e-9b10-8722890db40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
22690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1341122690
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3089037425
Short name T1019
Test name
Test status
Simulation time 8416076583 ps
CPU time 9.09 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204444 kb
Host smart-9f36575b-d880-46c5-a6dd-140c1323f385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30890
37425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3089037425
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3317487001
Short name T1025
Test name
Test status
Simulation time 8372206360 ps
CPU time 7.74 seconds
Started May 12 12:56:37 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204424 kb
Host smart-9313a281-916d-4277-ab16-e6e25d627e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
87001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3317487001
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.275759690
Short name T1155
Test name
Test status
Simulation time 8483060055 ps
CPU time 7.88 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:36 PM PDT 24
Peak memory 204488 kb
Host smart-d7dee705-adb2-412e-b9cb-8a0e3c7543d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
9690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.275759690
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.266018424
Short name T536
Test name
Test status
Simulation time 8405278912 ps
CPU time 7.93 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204476 kb
Host smart-126e3b1f-5c3b-43e8-a9f7-be71792dec34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26601
8424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.266018424
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2329631340
Short name T834
Test name
Test status
Simulation time 8389616930 ps
CPU time 8.42 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204480 kb
Host smart-c7bf9c68-c2dc-4a24-b1de-a36b3715f5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23296
31340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2329631340
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3171503997
Short name T191
Test name
Test status
Simulation time 8415928299 ps
CPU time 8.81 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204748 kb
Host smart-bf9c466b-9274-4731-9cc7-6aa721c55345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31715
03997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3171503997
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1090677060
Short name T9
Test name
Test status
Simulation time 8364632175 ps
CPU time 8.89 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204556 kb
Host smart-12b61113-d052-410f-8e0d-2b4c85fe1b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
77060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1090677060
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2859771211
Short name T47
Test name
Test status
Simulation time 49862449 ps
CPU time 0.69 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204296 kb
Host smart-dff6b0f1-d24c-4b73-9618-dd997762e24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28597
71211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2859771211
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1541776733
Short name T641
Test name
Test status
Simulation time 30008518353 ps
CPU time 55.81 seconds
Started May 12 12:56:23 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204620 kb
Host smart-f53cedc9-b766-4730-b9f0-daf8e6bf6a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15417
76733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1541776733
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1784359848
Short name T904
Test name
Test status
Simulation time 8396066677 ps
CPU time 9.56 seconds
Started May 12 12:56:24 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204448 kb
Host smart-945852cc-ab9f-473d-9032-f5edc1db651a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
59848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1784359848
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2548810852
Short name T900
Test name
Test status
Simulation time 8385478753 ps
CPU time 7.66 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204372 kb
Host smart-1176ed02-841f-42ad-ad40-fb2ace909dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25488
10852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2548810852
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.23910487
Short name T1335
Test name
Test status
Simulation time 8384964826 ps
CPU time 7.76 seconds
Started May 12 12:56:25 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 204548 kb
Host smart-b6251305-74ad-48b6-96cd-53547a8df993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23910
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.23910487
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.253645566
Short name T457
Test name
Test status
Simulation time 8372008257 ps
CPU time 7.75 seconds
Started May 12 12:56:37 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204444 kb
Host smart-5c3f0395-064f-4b8e-b1ca-6ced1761d32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25364
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.253645566
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4256737383
Short name T616
Test name
Test status
Simulation time 8370276013 ps
CPU time 7.42 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204332 kb
Host smart-2bb5827e-fd31-4933-9718-762f6c436738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
37383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4256737383
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.4104470978
Short name T1188
Test name
Test status
Simulation time 8464252760 ps
CPU time 10.01 seconds
Started May 12 12:56:22 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204340 kb
Host smart-f924ac82-18bb-42c8-80b1-1166495551b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
70978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.4104470978
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2156780236
Short name T721
Test name
Test status
Simulation time 8379080120 ps
CPU time 7.87 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204764 kb
Host smart-33db226b-1e1b-4e4d-8d29-68fce88b59ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567
80236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2156780236
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.337835606
Short name T1430
Test name
Test status
Simulation time 8393913635 ps
CPU time 8 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204404 kb
Host smart-d1362965-5ab4-471a-839d-46002e06daae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.337835606
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1018218084
Short name T1373
Test name
Test status
Simulation time 8468549517 ps
CPU time 9.39 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204512 kb
Host smart-202402c0-12a6-48e2-99a4-a7dc66dd03ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1018218084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1018218084
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1920974858
Short name T831
Test name
Test status
Simulation time 8382353984 ps
CPU time 7.6 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204316 kb
Host smart-339b40e3-e19f-45c9-84c2-a50443527f15
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1920974858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1920974858
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.844323212
Short name T729
Test name
Test status
Simulation time 8456605648 ps
CPU time 7.83 seconds
Started May 12 12:56:33 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204408 kb
Host smart-fcd8627b-bb93-4467-96e5-93b0a2b3a17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84432
3212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.844323212
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3471316236
Short name T717
Test name
Test status
Simulation time 8393371355 ps
CPU time 8.15 seconds
Started May 12 12:56:45 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204516 kb
Host smart-46275508-505b-46f2-9041-6252e76e42fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
16236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3471316236
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2040882726
Short name T34
Test name
Test status
Simulation time 8469527809 ps
CPU time 12.28 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:53 PM PDT 24
Peak memory 204584 kb
Host smart-2428d4a1-f4b8-4c12-aa1a-b379d8a6ee2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20408
82726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2040882726
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_enable.1920238770
Short name T1405
Test name
Test status
Simulation time 8381637651 ps
CPU time 7.98 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204412 kb
Host smart-3908d3ef-cf98-4c84-b9cd-2fbdaeec3f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19202
38770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1920238770
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3299520043
Short name T522
Test name
Test status
Simulation time 73276122 ps
CPU time 1.86 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 204584 kb
Host smart-7b75bda5-2ed9-4545-ab94-ac9ad3c83804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32995
20043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3299520043
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.96934168
Short name T1028
Test name
Test status
Simulation time 8401290402 ps
CPU time 7.57 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204384 kb
Host smart-d01bfc0f-28c0-4e3d-aebe-dea26504f1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96934
168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.96934168
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3703900495
Short name T495
Test name
Test status
Simulation time 8377037383 ps
CPU time 8.44 seconds
Started May 12 12:56:44 PM PDT 24
Finished May 12 12:56:53 PM PDT 24
Peak memory 204512 kb
Host smart-28452db1-778d-40fc-8432-9101f06f3886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039
00495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3703900495
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2231149626
Short name T581
Test name
Test status
Simulation time 8499198358 ps
CPU time 8.32 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204456 kb
Host smart-a6687355-28f2-4f89-beca-4a81b7772bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
49626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2231149626
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3376162328
Short name T555
Test name
Test status
Simulation time 8418884798 ps
CPU time 7.91 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204340 kb
Host smart-da9d4d30-3e3c-48f6-82c0-38c06675c11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33761
62328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3376162328
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2071611779
Short name T472
Test name
Test status
Simulation time 8373501305 ps
CPU time 7.66 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204340 kb
Host smart-b9a4c309-87ee-4d13-b672-cf8c628b8377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20716
11779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2071611779
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1534629159
Short name T124
Test name
Test status
Simulation time 8420877728 ps
CPU time 8.12 seconds
Started May 12 12:56:26 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 204384 kb
Host smart-4c85560b-0b6d-45bc-a7b3-fee5e9709428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15346
29159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1534629159
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.399637297
Short name T1224
Test name
Test status
Simulation time 8401107688 ps
CPU time 8.88 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204428 kb
Host smart-650ff45a-3108-4019-ac10-0fe0a872a2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
7297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.399637297
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3398494235
Short name T1436
Test name
Test status
Simulation time 8393328012 ps
CPU time 9.66 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204496 kb
Host smart-1b5aca54-a5f7-4122-9a88-2021e4178494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33984
94235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3398494235
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3686855912
Short name T968
Test name
Test status
Simulation time 8374002544 ps
CPU time 9.39 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204472 kb
Host smart-d90374b3-aa02-4d7d-bda4-9b6118e22a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36868
55912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3686855912
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3444256399
Short name T8
Test name
Test status
Simulation time 8362020421 ps
CPU time 7.52 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204524 kb
Host smart-8dc54b84-008f-42f4-bdd2-ba1fd548851b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34442
56399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3444256399
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3855760742
Short name T1153
Test name
Test status
Simulation time 45600955 ps
CPU time 0.69 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:53 PM PDT 24
Peak memory 204320 kb
Host smart-632243b9-65d7-43f0-9b3f-7c677b23644b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38557
60742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3855760742
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3854456476
Short name T248
Test name
Test status
Simulation time 26387407460 ps
CPU time 51.38 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204684 kb
Host smart-845df5f3-fdc6-4fde-9486-b5ba5ef7508a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
56476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3854456476
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2873364096
Short name T1139
Test name
Test status
Simulation time 8409152537 ps
CPU time 7.95 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:57:02 PM PDT 24
Peak memory 204396 kb
Host smart-44be0ed8-fe8a-44d6-aea2-e276e01612f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28733
64096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2873364096
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3868515640
Short name T1296
Test name
Test status
Simulation time 8416945892 ps
CPU time 10.5 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:56:49 PM PDT 24
Peak memory 204372 kb
Host smart-e9508c23-62c1-4852-97fe-65590d586bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
15640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3868515640
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3220869853
Short name T1292
Test name
Test status
Simulation time 8396975835 ps
CPU time 8.18 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204348 kb
Host smart-8371e56a-ddf9-4227-b8f8-7031fe8b62c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
69853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3220869853
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3847891907
Short name T638
Test name
Test status
Simulation time 8378482096 ps
CPU time 7.96 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204380 kb
Host smart-8e76a7b4-1e8b-45a0-b2c3-7fd1ee9bb2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38478
91907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3847891907
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.811255764
Short name T88
Test name
Test status
Simulation time 8364128749 ps
CPU time 8.31 seconds
Started May 12 12:56:33 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204412 kb
Host smart-a4b75701-5fcd-468b-8477-4ef1f1a742c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81125
5764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.811255764
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.204214622
Short name T1367
Test name
Test status
Simulation time 8463132890 ps
CPU time 8.19 seconds
Started May 12 12:56:31 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204432 kb
Host smart-06bbe64b-a6b9-40db-bdcf-7bac79459134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
4622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.204214622
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3317966554
Short name T1042
Test name
Test status
Simulation time 8479131123 ps
CPU time 9.93 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204472 kb
Host smart-4e764a0a-b4dc-421f-b2e9-479e5e5de494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33179
66554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3317966554
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1131647066
Short name T859
Test name
Test status
Simulation time 8400598217 ps
CPU time 8.84 seconds
Started May 12 12:56:37 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204508 kb
Host smart-a87e0d36-1303-4fe9-a3bb-e4b7c6198283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11316
47066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1131647066
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3103225837
Short name T1176
Test name
Test status
Simulation time 8469647133 ps
CPU time 7.65 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204360 kb
Host smart-b46db796-1ef9-44f5-8909-c3b51dbc7ada
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3103225837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3103225837
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.3656676788
Short name T507
Test name
Test status
Simulation time 8381393926 ps
CPU time 7.81 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204492 kb
Host smart-fa42ae96-bdde-4777-9877-f0c388194fe2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3656676788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.3656676788
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.3913028710
Short name T825
Test name
Test status
Simulation time 8423596276 ps
CPU time 9.32 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204484 kb
Host smart-5bb680c4-7135-4e29-946c-efcdba5ee145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
28710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.3913028710
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.863673490
Short name T410
Test name
Test status
Simulation time 8397250455 ps
CPU time 7.6 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204472 kb
Host smart-15d3a632-39a7-4401-b729-2271afc9393d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86367
3490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.863673490
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.964055719
Short name T1275
Test name
Test status
Simulation time 8779427762 ps
CPU time 12.34 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204712 kb
Host smart-15fd6f9f-be9e-4e42-ab46-6b8b0472d604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96405
5719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.964055719
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_enable.1272630146
Short name T562
Test name
Test status
Simulation time 8386985444 ps
CPU time 10.37 seconds
Started May 12 12:56:32 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204364 kb
Host smart-c4943a54-2e71-4618-83be-fd7d95a4abc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
30146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1272630146
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1848621247
Short name T1064
Test name
Test status
Simulation time 158502806 ps
CPU time 1.47 seconds
Started May 12 12:56:27 PM PDT 24
Finished May 12 12:56:29 PM PDT 24
Peak memory 204600 kb
Host smart-f3e46ffd-ef26-4084-8011-f1f7af7846e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18486
21247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1848621247
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3917349321
Short name T1121
Test name
Test status
Simulation time 8440566793 ps
CPU time 8.89 seconds
Started May 12 12:56:29 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204456 kb
Host smart-4a5da4b6-7225-4fba-8a43-e46cdbfb8e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
49321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3917349321
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3258868062
Short name T226
Test name
Test status
Simulation time 8406452791 ps
CPU time 9.7 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204420 kb
Host smart-684c46b3-58fc-430d-b0b4-7d3b2d51d8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32588
68062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3258868062
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.976898034
Short name T157
Test name
Test status
Simulation time 8410315959 ps
CPU time 8.16 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204432 kb
Host smart-84929938-c621-476f-81c5-c20a72ddf8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97689
8034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.976898034
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1254892832
Short name T364
Test name
Test status
Simulation time 8418418273 ps
CPU time 8.65 seconds
Started May 12 12:56:48 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204468 kb
Host smart-1546157c-dc34-4197-bb2b-4d4ea77b2b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
92832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1254892832
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.125476786
Short name T1185
Test name
Test status
Simulation time 8383050083 ps
CPU time 7.58 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:43 PM PDT 24
Peak memory 204460 kb
Host smart-4563d2aa-da3f-4b84-a0d4-c910da08e44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12547
6786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.125476786
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.255396875
Short name T117
Test name
Test status
Simulation time 8440495954 ps
CPU time 7.78 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204400 kb
Host smart-b90419b8-07c2-45d2-b120-39c8aee5f37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25539
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.255396875
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.622460015
Short name T245
Test name
Test status
Simulation time 8406647839 ps
CPU time 7.7 seconds
Started May 12 12:56:34 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204420 kb
Host smart-de0345c1-344a-4012-8b61-bda29c4d6d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62246
0015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.622460015
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.772568272
Short name T806
Test name
Test status
Simulation time 8387527195 ps
CPU time 8.8 seconds
Started May 12 12:56:28 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204404 kb
Host smart-b11f04b7-a71f-4036-a5a7-24b0570a38f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77256
8272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.772568272
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2708262013
Short name T57
Test name
Test status
Simulation time 8418139333 ps
CPU time 7.62 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:39 PM PDT 24
Peak memory 204472 kb
Host smart-3dc86eef-a980-43c3-8c4e-7097f2a60120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27082
62013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2708262013
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1059617599
Short name T782
Test name
Test status
Simulation time 8446085545 ps
CPU time 8.02 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:38 PM PDT 24
Peak memory 204388 kb
Host smart-6dedd01f-3f5b-47ad-8e5d-24c1c03876f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
17599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1059617599
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.4126349539
Short name T1271
Test name
Test status
Simulation time 38399419 ps
CPU time 0.66 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:02 PM PDT 24
Peak memory 204340 kb
Host smart-55fed1e9-57ee-4077-89de-723803d441b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
49539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.4126349539
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3118759610
Short name T1046
Test name
Test status
Simulation time 19008601214 ps
CPU time 39.5 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 204720 kb
Host smart-79a8e432-cf91-44e4-b002-da086c0a7bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
59610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3118759610
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3575635162
Short name T730
Test name
Test status
Simulation time 8401871255 ps
CPU time 9.89 seconds
Started May 12 12:56:40 PM PDT 24
Finished May 12 12:56:51 PM PDT 24
Peak memory 204396 kb
Host smart-87fc258e-2135-458b-b3a1-a3e9d26fac9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756
35162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3575635162
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3655736533
Short name T870
Test name
Test status
Simulation time 8402597266 ps
CPU time 7.6 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204428 kb
Host smart-3e6606db-580a-4cb1-9be2-cb399360e219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36557
36533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3655736533
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3850704188
Short name T672
Test name
Test status
Simulation time 8402883201 ps
CPU time 9.09 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204332 kb
Host smart-23864075-f5b7-4a09-9140-2e92bc9d9171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38507
04188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3850704188
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.4148952640
Short name T95
Test name
Test status
Simulation time 8454776720 ps
CPU time 8.05 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204456 kb
Host smart-a9e2fc61-d572-424e-bc41-d4751f95252f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41489
52640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.4148952640
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2797276769
Short name T450
Test name
Test status
Simulation time 8375934486 ps
CPU time 8.21 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204452 kb
Host smart-be3bcbfa-300f-4065-a3f5-74d2b223ed98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27972
76769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2797276769
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.104934348
Short name T836
Test name
Test status
Simulation time 8479334702 ps
CPU time 8 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 203872 kb
Host smart-cf41e29b-4f61-46e9-aed0-6f9f8c7f8640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10493
4348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.104934348
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1937969886
Short name T1031
Test name
Test status
Simulation time 8382629896 ps
CPU time 7.82 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:02 PM PDT 24
Peak memory 204376 kb
Host smart-ce651d7a-700a-418a-a889-01e4d031dc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
69886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1937969886
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1903314651
Short name T1268
Test name
Test status
Simulation time 8376977109 ps
CPU time 8.23 seconds
Started May 12 12:56:38 PM PDT 24
Finished May 12 12:56:47 PM PDT 24
Peak memory 204516 kb
Host smart-0e3ec402-209d-4766-aa4d-12dd6048a9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
14651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1903314651
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2892048176
Short name T640
Test name
Test status
Simulation time 8479272964 ps
CPU time 8.18 seconds
Started May 12 12:56:55 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204368 kb
Host smart-a003a79f-816f-4bfe-b725-ee7a7f9d5e04
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2892048176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2892048176
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3218627090
Short name T1018
Test name
Test status
Simulation time 8385441296 ps
CPU time 7.89 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204492 kb
Host smart-fce8d69d-964e-44b0-a933-f87e345a9ffc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3218627090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3218627090
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.71842807
Short name T1105
Test name
Test status
Simulation time 8415108450 ps
CPU time 7.78 seconds
Started May 12 12:56:42 PM PDT 24
Finished May 12 12:56:50 PM PDT 24
Peak memory 204536 kb
Host smart-c005ad10-2310-4fbd-860a-f080cf562ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71842
807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.71842807
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2745785361
Short name T446
Test name
Test status
Simulation time 8393584701 ps
CPU time 8.77 seconds
Started May 12 12:56:30 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 204420 kb
Host smart-8a785026-6032-4809-867e-d97c5b272ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
85361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2745785361
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2154929202
Short name T1089
Test name
Test status
Simulation time 9470138173 ps
CPU time 13.41 seconds
Started May 12 12:56:37 PM PDT 24
Finished May 12 12:56:52 PM PDT 24
Peak memory 204628 kb
Host smart-6d23877d-2992-478c-a42c-2b4e0637ee53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
29202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2154929202
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_enable.4291535523
Short name T881
Test name
Test status
Simulation time 8395776538 ps
CPU time 7.92 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:50 PM PDT 24
Peak memory 203824 kb
Host smart-f9c97c79-2201-4233-b329-a1d9490c29fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42915
35523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.4291535523
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.921518010
Short name T877
Test name
Test status
Simulation time 49826755 ps
CPU time 1.33 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204624 kb
Host smart-51ac8af1-a636-498e-aa4e-b57f782820c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92151
8010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.921518010
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.4033037125
Short name T40
Test name
Test status
Simulation time 8385801773 ps
CPU time 7.73 seconds
Started May 12 12:56:49 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204456 kb
Host smart-16a60d3d-9eb1-4751-9947-d3ef36d70dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330
37125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.4033037125
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.70919918
Short name T912
Test name
Test status
Simulation time 8393485606 ps
CPU time 9.66 seconds
Started May 12 12:56:45 PM PDT 24
Finished May 12 12:56:55 PM PDT 24
Peak memory 204500 kb
Host smart-c43bd810-851f-4f7a-88ec-4de94664e52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70919
918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.70919918
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3607327785
Short name T740
Test name
Test status
Simulation time 8403770089 ps
CPU time 8.84 seconds
Started May 12 12:56:49 PM PDT 24
Finished May 12 12:56:58 PM PDT 24
Peak memory 204436 kb
Host smart-1859afee-a948-44b4-8b1e-d1a4b6e0c668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
27785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3607327785
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3441357433
Short name T547
Test name
Test status
Simulation time 8422130383 ps
CPU time 8.04 seconds
Started May 12 12:56:55 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204472 kb
Host smart-f16e0d5d-269f-4912-a99b-dbcba19f9ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34413
57433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3441357433
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2837256332
Short name T1234
Test name
Test status
Simulation time 8371152594 ps
CPU time 7.65 seconds
Started May 12 12:56:40 PM PDT 24
Finished May 12 12:56:48 PM PDT 24
Peak memory 204520 kb
Host smart-dd79bd8b-e352-4693-9f34-a5e24de2bf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
56332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2837256332
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2701805312
Short name T1365
Test name
Test status
Simulation time 8435797281 ps
CPU time 7.67 seconds
Started May 12 12:56:46 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204456 kb
Host smart-ba98bcfb-dce4-4557-909b-42b27f0321b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27018
05312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2701805312
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3243459933
Short name T850
Test name
Test status
Simulation time 8410292216 ps
CPU time 8.02 seconds
Started May 12 12:56:47 PM PDT 24
Finished May 12 12:56:55 PM PDT 24
Peak memory 204420 kb
Host smart-18bfc328-2cda-4c97-af82-910e79418936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32434
59933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3243459933
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.472081513
Short name T1283
Test name
Test status
Simulation time 8405841383 ps
CPU time 7.69 seconds
Started May 12 12:56:41 PM PDT 24
Finished May 12 12:56:49 PM PDT 24
Peak memory 204360 kb
Host smart-19226753-b72c-4fd6-ad68-6322657241a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47208
1513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.472081513
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2893326019
Short name T1414
Test name
Test status
Simulation time 8401895771 ps
CPU time 8.29 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204348 kb
Host smart-3de3c734-581b-43ff-9444-144f81260a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28933
26019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2893326019
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2311622430
Short name T620
Test name
Test status
Simulation time 8378989623 ps
CPU time 8.82 seconds
Started May 12 12:56:45 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204384 kb
Host smart-847d9179-20b1-4465-9a4c-4e0d1be7a705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23116
22430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2311622430
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3176034843
Short name T642
Test name
Test status
Simulation time 43412811 ps
CPU time 0.63 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 204348 kb
Host smart-a25462f5-3729-420e-97b3-391649760e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
34843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3176034843
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.20325733
Short name T252
Test name
Test status
Simulation time 14486620796 ps
CPU time 25.16 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204756 kb
Host smart-c71c48fa-187e-4166-8b87-ba71d37b4b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.20325733
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2439522537
Short name T652
Test name
Test status
Simulation time 8384946963 ps
CPU time 8.29 seconds
Started May 12 12:56:40 PM PDT 24
Finished May 12 12:56:49 PM PDT 24
Peak memory 204456 kb
Host smart-afca78b7-3448-4995-9bec-cf362a32309c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395
22537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2439522537
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2369874927
Short name T1206
Test name
Test status
Simulation time 8385639877 ps
CPU time 8.07 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204368 kb
Host smart-6c0dc9f6-0294-49b9-bbe5-bcf58a638fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23698
74927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2369874927
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3654212823
Short name T899
Test name
Test status
Simulation time 8382331686 ps
CPU time 7.53 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:45 PM PDT 24
Peak memory 204452 kb
Host smart-8c090529-bff5-483a-b3d8-a41364af0b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
12823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3654212823
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1389715807
Short name T1057
Test name
Test status
Simulation time 8388440926 ps
CPU time 7.8 seconds
Started May 12 12:57:00 PM PDT 24
Finished May 12 12:57:08 PM PDT 24
Peak memory 204472 kb
Host smart-9030ba6c-12c7-4187-891a-a541a6884413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13897
15807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1389715807
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2257701346
Short name T1431
Test name
Test status
Simulation time 8369264252 ps
CPU time 9.91 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204408 kb
Host smart-1a3c2e5a-32cf-4c57-a199-a4521137abbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22577
01346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2257701346
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3874487863
Short name T972
Test name
Test status
Simulation time 8471040683 ps
CPU time 7.64 seconds
Started May 12 12:56:48 PM PDT 24
Finished May 12 12:56:56 PM PDT 24
Peak memory 204364 kb
Host smart-62a5b270-eb81-4e71-9889-3670fdd2837a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38744
87863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3874487863
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1831512402
Short name T1226
Test name
Test status
Simulation time 8408221281 ps
CPU time 8 seconds
Started May 12 12:56:49 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204456 kb
Host smart-bb6248c9-3b53-4bb1-b429-0a3f4cb9ef0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18315
12402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1831512402
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1407196363
Short name T480
Test name
Test status
Simulation time 8389139971 ps
CPU time 7.82 seconds
Started May 12 12:56:46 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204452 kb
Host smart-721568dc-f049-49d7-ab44-aee4373091e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14071
96363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1407196363
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.4027176304
Short name T466
Test name
Test status
Simulation time 8471043685 ps
CPU time 10.34 seconds
Started May 12 12:56:58 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204456 kb
Host smart-fb41522a-dac6-4d2e-bf95-20e8f758332f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4027176304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.4027176304
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.706360117
Short name T1231
Test name
Test status
Simulation time 8379386423 ps
CPU time 9.4 seconds
Started May 12 12:56:50 PM PDT 24
Finished May 12 12:57:00 PM PDT 24
Peak memory 204416 kb
Host smart-f48408f1-cd42-45b2-a43a-6e7bf5bb8369
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=706360117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.706360117
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.2345391464
Short name T1246
Test name
Test status
Simulation time 8425078572 ps
CPU time 8.47 seconds
Started May 12 12:56:57 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204444 kb
Host smart-d5f16a43-099f-4e30-a7a4-89c3cf201016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23453
91464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.2345391464
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2703433372
Short name T1361
Test name
Test status
Simulation time 8409046887 ps
CPU time 7.57 seconds
Started May 12 12:56:35 PM PDT 24
Finished May 12 12:56:44 PM PDT 24
Peak memory 204396 kb
Host smart-776866de-45f1-43d9-8626-fed4acff2230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
33372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2703433372
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.4030611775
Short name T817
Test name
Test status
Simulation time 8898543485 ps
CPU time 13.41 seconds
Started May 12 12:56:42 PM PDT 24
Finished May 12 12:56:55 PM PDT 24
Peak memory 204720 kb
Host smart-8449c0f3-3e09-4558-9079-577286b39c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40306
11775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.4030611775
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_enable.2994555620
Short name T1090
Test name
Test status
Simulation time 8379808111 ps
CPU time 8.55 seconds
Started May 12 12:56:36 PM PDT 24
Finished May 12 12:56:46 PM PDT 24
Peak memory 204380 kb
Host smart-b0e3a83e-9efe-43b6-b1a5-7c5f257dc8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
55620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2994555620
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2237798423
Short name T669
Test name
Test status
Simulation time 69149175 ps
CPU time 1.9 seconds
Started May 12 12:56:39 PM PDT 24
Finished May 12 12:56:42 PM PDT 24
Peak memory 204616 kb
Host smart-3165e9a7-78a9-46d3-8d92-14fd346c7ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22377
98423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2237798423
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3957072689
Short name T139
Test name
Test status
Simulation time 8491825365 ps
CPU time 8.19 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204436 kb
Host smart-6c26902c-e7e9-4ba2-87a2-8121e8163aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39570
72689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3957072689
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.799957181
Short name T1254
Test name
Test status
Simulation time 8365793455 ps
CPU time 8.14 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:57:02 PM PDT 24
Peak memory 204660 kb
Host smart-f4e7d841-9a2b-4b8f-9cae-fad183d898cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79995
7181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.799957181
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3884100917
Short name T375
Test name
Test status
Simulation time 8395555452 ps
CPU time 7.94 seconds
Started May 12 12:56:48 PM PDT 24
Finished May 12 12:56:56 PM PDT 24
Peak memory 204512 kb
Host smart-b36d50d1-5608-4857-9824-67b7c1fa6ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
00917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3884100917
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3338201259
Short name T330
Test name
Test status
Simulation time 8432163386 ps
CPU time 7.74 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:10 PM PDT 24
Peak memory 204444 kb
Host smart-dc2c044f-8bbb-4d41-ad9a-f3f218008d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33382
01259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3338201259
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1866295689
Short name T1203
Test name
Test status
Simulation time 8369257786 ps
CPU time 10.2 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204328 kb
Host smart-764b11b3-d21f-4dc2-90e4-7c7a5a388c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
95689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1866295689
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2596320401
Short name T131
Test name
Test status
Simulation time 8421761092 ps
CPU time 7.8 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204376 kb
Host smart-4e055b0b-8379-4073-bae3-bdcf4a311239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25963
20401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2596320401
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3915595548
Short name T665
Test name
Test status
Simulation time 8391231154 ps
CPU time 8.56 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204436 kb
Host smart-1c16b755-0815-4201-80a3-b46b2977c3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39155
95548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3915595548
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2278351445
Short name T340
Test name
Test status
Simulation time 8379860285 ps
CPU time 7.76 seconds
Started May 12 12:56:45 PM PDT 24
Finished May 12 12:56:53 PM PDT 24
Peak memory 204436 kb
Host smart-5b8de236-4b07-4153-9488-92619249787a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
51445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2278351445
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1772678441
Short name T179
Test name
Test status
Simulation time 8407554918 ps
CPU time 7.56 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204404 kb
Host smart-278f5189-166e-4f9e-9847-17fca2c8bfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
78441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1772678441
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1716070704
Short name T1269
Test name
Test status
Simulation time 8381992777 ps
CPU time 8.1 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204416 kb
Host smart-21355947-f301-4a98-bcd5-d6b4a9c0c850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17160
70704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1716070704
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.621155404
Short name T1351
Test name
Test status
Simulation time 16977442415 ps
CPU time 34.4 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204604 kb
Host smart-d2cce0d8-44c6-4c14-80e4-a5b9271d4325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62115
5404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.621155404
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.634629374
Short name T499
Test name
Test status
Simulation time 8372600030 ps
CPU time 7.72 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204412 kb
Host smart-533ba2dd-9ba1-432f-9af7-8c25c7cd84d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63462
9374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.634629374
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3368358012
Short name T497
Test name
Test status
Simulation time 8402225122 ps
CPU time 7.67 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204376 kb
Host smart-44e6cd45-fe8d-41ec-a1f4-72a412ad885d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
58012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3368358012
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1371681278
Short name T1389
Test name
Test status
Simulation time 8412582353 ps
CPU time 8.5 seconds
Started May 12 12:56:48 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204428 kb
Host smart-935dcb1e-4382-455a-8f5f-344fbe93d5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13716
81278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1371681278
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3878659265
Short name T599
Test name
Test status
Simulation time 8380350463 ps
CPU time 7.51 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204404 kb
Host smart-8c3f4401-5d36-4eed-aeac-1acde83a53c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786
59265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3878659265
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2153305127
Short name T731
Test name
Test status
Simulation time 8384439275 ps
CPU time 7.9 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204760 kb
Host smart-2da9e120-adcf-4d30-af48-a1771c237f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
05127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2153305127
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2783362821
Short name T187
Test name
Test status
Simulation time 8467478842 ps
CPU time 7.99 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204468 kb
Host smart-14acc728-6b5d-4b5f-8c64-461b83448d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27833
62821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2783362821
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.240676718
Short name T563
Test name
Test status
Simulation time 8375527100 ps
CPU time 7.91 seconds
Started May 12 12:56:46 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204380 kb
Host smart-40a060cb-9b13-457a-9bd2-70d5aa3ee184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24067
6718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.240676718
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1323624600
Short name T1033
Test name
Test status
Simulation time 8400006278 ps
CPU time 7.84 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:57:00 PM PDT 24
Peak memory 204408 kb
Host smart-fa53344a-67c5-4642-bdcb-37ab01288a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236
24600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1323624600
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.1425662201
Short name T333
Test name
Test status
Simulation time 8467289179 ps
CPU time 8.11 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 204392 kb
Host smart-c3a6f7d7-ff45-4d8f-ba30-1d6e0dd309e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1425662201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.1425662201
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.3749508598
Short name T1291
Test name
Test status
Simulation time 8391141694 ps
CPU time 7.98 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:01 PM PDT 24
Peak memory 204412 kb
Host smart-0a7764e1-ecff-4bd6-b693-9916c7d484ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3749508598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.3749508598
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.129482689
Short name T154
Test name
Test status
Simulation time 8443275903 ps
CPU time 8.32 seconds
Started May 12 12:57:05 PM PDT 24
Finished May 12 12:57:14 PM PDT 24
Peak memory 204312 kb
Host smart-d5c7ac53-03d7-4754-b9ba-eac6b17ad466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12948
2689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.129482689
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3029933030
Short name T1111
Test name
Test status
Simulation time 8383135896 ps
CPU time 9.26 seconds
Started May 12 12:56:47 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204440 kb
Host smart-7bde2070-8643-4634-be3f-f4fcdd238c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
33030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3029933030
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2056200871
Short name T206
Test name
Test status
Simulation time 9636431064 ps
CPU time 15.17 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 204692 kb
Host smart-78daffc4-ac0e-4564-a073-b20a54c74449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20562
00871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2056200871
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_enable.1812389176
Short name T779
Test name
Test status
Simulation time 8368696681 ps
CPU time 8.69 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:01 PM PDT 24
Peak memory 204428 kb
Host smart-bea2d818-717c-412c-afbd-619b2d9231d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18123
89176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1812389176
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2806949175
Short name T718
Test name
Test status
Simulation time 80107648 ps
CPU time 1.05 seconds
Started May 12 12:56:51 PM PDT 24
Finished May 12 12:56:53 PM PDT 24
Peak memory 204544 kb
Host smart-f055186d-7fb8-4371-85aa-95c8515b3838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
49175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2806949175
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2365840906
Short name T1163
Test name
Test status
Simulation time 8447823128 ps
CPU time 8.02 seconds
Started May 12 12:56:57 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204420 kb
Host smart-6d810378-77fb-4d8a-a0c9-0ec9f87d8523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23658
40906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2365840906
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.379552354
Short name T1113
Test name
Test status
Simulation time 8379486228 ps
CPU time 7.85 seconds
Started May 12 12:57:03 PM PDT 24
Finished May 12 12:57:11 PM PDT 24
Peak memory 204660 kb
Host smart-405c67d8-cb3e-48bb-9d53-6864df7e80a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37955
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.379552354
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2599586110
Short name T677
Test name
Test status
Simulation time 8396592951 ps
CPU time 7.84 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204664 kb
Host smart-b1034630-5b13-4058-b8c4-4ddd2c3a6aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
86110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2599586110
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.96259775
Short name T1227
Test name
Test status
Simulation time 8434356771 ps
CPU time 7.79 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 204352 kb
Host smart-c902ca19-6dd6-4ef7-bda9-2945311820c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96259
775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.96259775
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2163941318
Short name T755
Test name
Test status
Simulation time 8375155889 ps
CPU time 7.92 seconds
Started May 12 12:56:49 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 204480 kb
Host smart-ff576b99-5702-41bc-a0d3-a734419a75d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21639
41318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2163941318
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.531380678
Short name T1034
Test name
Test status
Simulation time 8468295968 ps
CPU time 10.04 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204420 kb
Host smart-e30de812-b8bc-450f-8d5a-3aa9cd55b81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53138
0678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.531380678
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3761740426
Short name T997
Test name
Test status
Simulation time 8422990798 ps
CPU time 8.88 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:03 PM PDT 24
Peak memory 204460 kb
Host smart-bde07ccd-7d15-4e23-87c3-6a4d585d75c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37617
40426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3761740426
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2653879210
Short name T93
Test name
Test status
Simulation time 8376137177 ps
CPU time 7.78 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204668 kb
Host smart-aa0155d6-cc54-4822-9926-895f537d3981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26538
79210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2653879210
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.429741535
Short name T1402
Test name
Test status
Simulation time 8372450491 ps
CPU time 9.5 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204436 kb
Host smart-8abc04e0-4e39-4deb-86c9-ac92e79705e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42974
1535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.429741535
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3283415962
Short name T843
Test name
Test status
Simulation time 8372114194 ps
CPU time 7.87 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204424 kb
Host smart-f2808e72-08a4-4497-a98d-39a3c05caead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
15962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3283415962
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1403995664
Short name T1314
Test name
Test status
Simulation time 36117359 ps
CPU time 0.63 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 204380 kb
Host smart-2ddf52fb-d1d0-449f-9fca-cef350cc9296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14039
95664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1403995664
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1287499246
Short name T685
Test name
Test status
Simulation time 30861842130 ps
CPU time 59.41 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 204816 kb
Host smart-4df4e569-6095-4f96-b38d-0ab3d9e6c02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12874
99246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1287499246
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1658228480
Short name T400
Test name
Test status
Simulation time 8378704046 ps
CPU time 8.32 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:01 PM PDT 24
Peak memory 204372 kb
Host smart-53c2dc90-e7fa-4378-b8d2-71833047e905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16582
28480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1658228480
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1443088093
Short name T459
Test name
Test status
Simulation time 8427022842 ps
CPU time 8.31 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:00 PM PDT 24
Peak memory 204376 kb
Host smart-3743f81c-fbfc-4224-a1f9-b019a5b2a473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14430
88093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1443088093
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1221072729
Short name T99
Test name
Test status
Simulation time 8414600495 ps
CPU time 7.85 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204392 kb
Host smart-aac575f5-5e28-4c24-9b16-849bbb238406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210
72729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1221072729
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.725435591
Short name T87
Test name
Test status
Simulation time 8389206820 ps
CPU time 8.54 seconds
Started May 12 12:56:55 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204760 kb
Host smart-6004b255-71e8-45f4-9cf9-ddae58527faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72543
5591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.725435591
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3126377901
Short name T29
Test name
Test status
Simulation time 8375963286 ps
CPU time 7.84 seconds
Started May 12 12:56:47 PM PDT 24
Finished May 12 12:56:56 PM PDT 24
Peak memory 204448 kb
Host smart-7b666151-7602-4334-b83b-64b0699eb22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31263
77901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3126377901
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.521036608
Short name T1258
Test name
Test status
Simulation time 8434870410 ps
CPU time 7.59 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:00 PM PDT 24
Peak memory 204396 kb
Host smart-66314202-d4d5-4e40-9857-21cf735dbd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52103
6608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.521036608
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1688517783
Short name T343
Test name
Test status
Simulation time 8440593411 ps
CPU time 9.54 seconds
Started May 12 12:56:57 PM PDT 24
Finished May 12 12:57:07 PM PDT 24
Peak memory 204492 kb
Host smart-19c87e58-7bd6-418a-87b2-ad1d383cc017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16885
17783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1688517783
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2720330317
Short name T1141
Test name
Test status
Simulation time 8406472389 ps
CPU time 8.24 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:57:00 PM PDT 24
Peak memory 204344 kb
Host smart-af0dab91-ecee-412c-b4fc-2c6a22cf453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27203
30317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2720330317
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.1374024481
Short name T516
Test name
Test status
Simulation time 8473783256 ps
CPU time 7.75 seconds
Started May 12 12:57:03 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 204376 kb
Host smart-c2a8bb4f-d2b2-4e1b-966d-41ff75e2fd5d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1374024481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.1374024481
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2622166971
Short name T398
Test name
Test status
Simulation time 8376456071 ps
CPU time 8.06 seconds
Started May 12 12:57:00 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204376 kb
Host smart-332c8d51-67f6-4c74-b84f-cc4002505ae9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2622166971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2622166971
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.609094367
Short name T134
Test name
Test status
Simulation time 8471011841 ps
CPU time 9.75 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:11 PM PDT 24
Peak memory 204360 kb
Host smart-2497c821-affc-409c-80dc-9cac3733cb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60909
4367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.609094367
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2186257956
Short name T1306
Test name
Test status
Simulation time 8416621649 ps
CPU time 10.16 seconds
Started May 12 12:56:57 PM PDT 24
Finished May 12 12:57:13 PM PDT 24
Peak memory 204464 kb
Host smart-ca330440-c682-430e-b191-239aeef76c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21862
57956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2186257956
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.1892649501
Short name T753
Test name
Test status
Simulation time 8427111239 ps
CPU time 7.46 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 204524 kb
Host smart-fadb637d-1019-47fa-bf0d-6fd62fee4bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
49501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1892649501
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.734672179
Short name T254
Test name
Test status
Simulation time 83582031 ps
CPU time 1.91 seconds
Started May 12 12:56:52 PM PDT 24
Finished May 12 12:56:55 PM PDT 24
Peak memory 204884 kb
Host smart-728c0c3e-2139-4a29-a148-18aca5b1b81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73467
2179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.734672179
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3107472055
Short name T832
Test name
Test status
Simulation time 8433952116 ps
CPU time 7.44 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 204452 kb
Host smart-0d4c0785-c48a-4e3e-8d85-107b8f976246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31074
72055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3107472055
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4212902354
Short name T752
Test name
Test status
Simulation time 8378815913 ps
CPU time 9.5 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:14 PM PDT 24
Peak memory 204744 kb
Host smart-87460fb7-d6ef-4e78-b894-b16200c63c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42129
02354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4212902354
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.4258573701
Short name T1067
Test name
Test status
Simulation time 8459316078 ps
CPU time 10.28 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204460 kb
Host smart-3d8cd709-6d9e-46c6-a910-9481a902facc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42585
73701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.4258573701
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1851204009
Short name T402
Test name
Test status
Simulation time 8429511314 ps
CPU time 8.82 seconds
Started May 12 12:56:48 PM PDT 24
Finished May 12 12:56:58 PM PDT 24
Peak memory 204740 kb
Host smart-aa4a6358-7e16-4384-b09f-b3f267f38b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18512
04009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1851204009
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2598585381
Short name T128
Test name
Test status
Simulation time 8454361646 ps
CPU time 7.96 seconds
Started May 12 12:56:50 PM PDT 24
Finished May 12 12:56:58 PM PDT 24
Peak memory 204340 kb
Host smart-f7938fdb-cf9f-4b8e-9fc9-fc1a9b522d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25985
85381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2598585381
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3374873240
Short name T419
Test name
Test status
Simulation time 8377602578 ps
CPU time 7.42 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204480 kb
Host smart-17ab6136-ff87-4bfa-bc01-78c789e2e463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
73240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3374873240
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.899637705
Short name T338
Test name
Test status
Simulation time 8390199399 ps
CPU time 7.89 seconds
Started May 12 12:56:57 PM PDT 24
Finished May 12 12:57:05 PM PDT 24
Peak memory 204404 kb
Host smart-265f8563-7a50-4d6f-9c62-eda39e7eddba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89963
7705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.899637705
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2951550401
Short name T1174
Test name
Test status
Simulation time 8391172486 ps
CPU time 8.47 seconds
Started May 12 12:57:00 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204456 kb
Host smart-d1e75fa6-1fbe-4b96-9330-ea600cb4c990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515
50401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2951550401
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3866900214
Short name T1285
Test name
Test status
Simulation time 8378371968 ps
CPU time 9.49 seconds
Started May 12 12:56:55 PM PDT 24
Finished May 12 12:57:05 PM PDT 24
Peak memory 204324 kb
Host smart-5a5b44b9-ff30-4754-afb6-2bb62f6d1285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
00214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3866900214
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2633893838
Short name T535
Test name
Test status
Simulation time 110210614 ps
CPU time 0.73 seconds
Started May 12 12:57:05 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204304 kb
Host smart-9163747c-403d-465c-8210-3d0b3410f90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
93838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2633893838
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2529794096
Short name T926
Test name
Test status
Simulation time 19551380673 ps
CPU time 37.89 seconds
Started May 12 12:57:05 PM PDT 24
Finished May 12 12:57:44 PM PDT 24
Peak memory 204724 kb
Host smart-d7309874-1763-45c9-822a-5a8b80edd5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
94096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2529794096
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3454993504
Short name T85
Test name
Test status
Simulation time 8378061055 ps
CPU time 10.37 seconds
Started May 12 12:56:54 PM PDT 24
Finished May 12 12:57:05 PM PDT 24
Peak memory 204424 kb
Host smart-0f943dca-0389-42be-87ad-07e45ae94fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34549
93504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3454993504
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.433028417
Short name T1218
Test name
Test status
Simulation time 8424073013 ps
CPU time 9.96 seconds
Started May 12 12:56:53 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204744 kb
Host smart-c5687809-181b-4587-8eed-747858b21f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43302
8417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.433028417
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1352485408
Short name T601
Test name
Test status
Simulation time 8382221141 ps
CPU time 7.63 seconds
Started May 12 12:57:07 PM PDT 24
Finished May 12 12:57:16 PM PDT 24
Peak memory 204452 kb
Host smart-8b01b34e-53be-4258-8f99-45f8f8c2aea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13524
85408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1352485408
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3004585913
Short name T170
Test name
Test status
Simulation time 8380259979 ps
CPU time 9.83 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 204672 kb
Host smart-c22dfc85-2d30-490c-81dc-964d017a788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30045
85913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3004585913
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2934460571
Short name T1038
Test name
Test status
Simulation time 8380171508 ps
CPU time 9.36 seconds
Started May 12 12:56:57 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204452 kb
Host smart-21144708-ec38-41b5-8a99-b61c0c1a6075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
60571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2934460571
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3316045472
Short name T941
Test name
Test status
Simulation time 8459498769 ps
CPU time 8.21 seconds
Started May 12 12:56:56 PM PDT 24
Finished May 12 12:57:05 PM PDT 24
Peak memory 204356 kb
Host smart-f54f68e1-d9f8-41dc-8bff-f0fc25c37eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33160
45472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3316045472
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1838329750
Short name T1072
Test name
Test status
Simulation time 8430085353 ps
CPU time 8.91 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:14 PM PDT 24
Peak memory 204484 kb
Host smart-c23ce3d2-4486-4b24-bbf8-8486bd4df971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18383
29750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1838329750
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2290804120
Short name T1186
Test name
Test status
Simulation time 8384744063 ps
CPU time 7.49 seconds
Started May 12 12:57:05 PM PDT 24
Finished May 12 12:57:13 PM PDT 24
Peak memory 204424 kb
Host smart-41ea69bc-2245-425e-875d-c2a85da53d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22908
04120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2290804120
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.1896111855
Short name T20
Test name
Test status
Simulation time 8464582698 ps
CPU time 7.51 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204544 kb
Host smart-f258ace9-cbcc-4821-8fd8-0b3b8bb98a79
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1896111855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.1896111855
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.91582212
Short name T436
Test name
Test status
Simulation time 8380743772 ps
CPU time 7.69 seconds
Started May 12 12:57:21 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204400 kb
Host smart-7647bc78-0cf6-42ba-9ed3-759088886c9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=91582212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.91582212
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.62935908
Short name T452
Test name
Test status
Simulation time 8432952505 ps
CPU time 7.73 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204360 kb
Host smart-67601719-70d7-40cd-ab28-32ff9bd4a9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62935
908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.62935908
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3912181674
Short name T551
Test name
Test status
Simulation time 8375747735 ps
CPU time 7.86 seconds
Started May 12 12:56:50 PM PDT 24
Finished May 12 12:56:59 PM PDT 24
Peak memory 204444 kb
Host smart-2d6a6cb2-7124-4fbc-83cc-0d87dc2f2b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39121
81674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3912181674
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.579656977
Short name T223
Test name
Test status
Simulation time 9076823273 ps
CPU time 12.26 seconds
Started May 12 12:57:03 PM PDT 24
Finished May 12 12:57:16 PM PDT 24
Peak memory 204676 kb
Host smart-ffefdd84-7a11-462f-8074-339d6981fef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57965
6977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.579656977
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_enable.1215287716
Short name T1223
Test name
Test status
Simulation time 8376591210 ps
CPU time 7.34 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204396 kb
Host smart-12d5ce65-a513-4f84-92fd-c1afd630ee38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
87716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1215287716
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2694785826
Short name T878
Test name
Test status
Simulation time 83721343 ps
CPU time 1.76 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204544 kb
Host smart-98449f7a-c9a0-4686-93d1-f4d1180ea6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26947
85826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2694785826
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2937134284
Short name T566
Test name
Test status
Simulation time 8393124312 ps
CPU time 8.42 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:17 PM PDT 24
Peak memory 204376 kb
Host smart-4597ac8b-1786-4fbe-943c-f02e0c5df82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
34284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2937134284
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1258650119
Short name T230
Test name
Test status
Simulation time 8368980744 ps
CPU time 7.76 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204384 kb
Host smart-f5de195f-c4fc-4f9c-886f-062bd799bd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12586
50119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1258650119
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1740361367
Short name T1384
Test name
Test status
Simulation time 8475573354 ps
CPU time 7.57 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204460 kb
Host smart-ef26b3f4-f948-4bc9-ac7e-54372bc10887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17403
61367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1740361367
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1955914184
Short name T90
Test name
Test status
Simulation time 8418708490 ps
CPU time 8 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204468 kb
Host smart-efa1d568-20fa-4447-b0cd-37da913df61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19559
14184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1955914184
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.103994632
Short name T792
Test name
Test status
Simulation time 8385043798 ps
CPU time 8.85 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204428 kb
Host smart-d470d325-b94f-4ab0-a2b0-a0796eeb85cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
4632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.103994632
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2427839553
Short name T104
Test name
Test status
Simulation time 8497647507 ps
CPU time 7.83 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204460 kb
Host smart-1de776d6-65f8-41c6-99ca-0efc97db6be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
39553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2427839553
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.171566416
Short name T411
Test name
Test status
Simulation time 8371698049 ps
CPU time 7.86 seconds
Started May 12 12:57:02 PM PDT 24
Finished May 12 12:57:10 PM PDT 24
Peak memory 204500 kb
Host smart-f97c613d-d771-4b34-b299-eb09bd26190d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17156
6416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.171566416
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.123234993
Short name T347
Test name
Test status
Simulation time 8410155169 ps
CPU time 8.22 seconds
Started May 12 12:57:07 PM PDT 24
Finished May 12 12:57:16 PM PDT 24
Peak memory 204316 kb
Host smart-754c5b09-467f-460c-9370-2305a5c6ea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
4993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.123234993
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2011320614
Short name T1399
Test name
Test status
Simulation time 8410681108 ps
CPU time 9.05 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:14 PM PDT 24
Peak memory 204416 kb
Host smart-7ee20263-a406-4603-995d-77177e3a2647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20113
20614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2011320614
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3899637742
Short name T1326
Test name
Test status
Simulation time 8397824280 ps
CPU time 8.92 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204424 kb
Host smart-2108b12f-311a-469d-a466-960ddc1d6023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
37742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3899637742
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1064064764
Short name T648
Test name
Test status
Simulation time 20976613442 ps
CPU time 41.48 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:59 PM PDT 24
Peak memory 204616 kb
Host smart-9719409b-63d1-41f5-84c6-6efbfe89268d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10640
64764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1064064764
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.36567740
Short name T387
Test name
Test status
Simulation time 8392543850 ps
CPU time 7.97 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204436 kb
Host smart-9f57719e-4b71-4bc9-9617-eb5c927e1ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36567
740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.36567740
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3347920492
Short name T1420
Test name
Test status
Simulation time 8412212947 ps
CPU time 7.85 seconds
Started May 12 12:56:58 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 204416 kb
Host smart-3558b568-a5c7-47e9-8259-34878be9a498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33479
20492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3347920492
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.1359813247
Short name T624
Test name
Test status
Simulation time 8384017332 ps
CPU time 8.24 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:16 PM PDT 24
Peak memory 204468 kb
Host smart-b24c86ef-3a80-4486-b422-318c13a9defa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13598
13247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.1359813247
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2938887412
Short name T628
Test name
Test status
Simulation time 8373604826 ps
CPU time 7.76 seconds
Started May 12 12:57:07 PM PDT 24
Finished May 12 12:57:15 PM PDT 24
Peak memory 204456 kb
Host smart-097bc37e-65d5-48e9-a04a-5f65e1b2f35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
87412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2938887412
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1381184631
Short name T365
Test name
Test status
Simulation time 8398165942 ps
CPU time 8.28 seconds
Started May 12 12:57:09 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204444 kb
Host smart-d7f5fcb2-30c4-4b7a-851a-43e4d169e339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13811
84631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1381184631
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1023944005
Short name T1169
Test name
Test status
Simulation time 8441655856 ps
CPU time 8.09 seconds
Started May 12 12:56:55 PM PDT 24
Finished May 12 12:57:04 PM PDT 24
Peak memory 204336 kb
Host smart-7f890d10-f218-4d0e-9739-89ad20b1d773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
44005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1023944005
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1730017435
Short name T646
Test name
Test status
Simulation time 8397187986 ps
CPU time 7.54 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204496 kb
Host smart-fbb812e4-82d2-42cf-9d4b-435b7fc4586f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17300
17435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1730017435
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.2281761576
Short name T425
Test name
Test status
Simulation time 8469437785 ps
CPU time 8.49 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204412 kb
Host smart-f37c9f3b-3c34-45bb-8b17-7594accf9ec8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2281761576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.2281761576
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.334241464
Short name T1131
Test name
Test status
Simulation time 8382279999 ps
CPU time 7.61 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204376 kb
Host smart-cea94def-f8a1-454e-b837-a78a79acec03
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=334241464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.334241464
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2460102410
Short name T1236
Test name
Test status
Simulation time 8402875412 ps
CPU time 10.13 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204392 kb
Host smart-fc04ba55-f74c-4ed5-b4ac-f22fb36a3ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
02410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2460102410
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.114749329
Short name T407
Test name
Test status
Simulation time 8381761052 ps
CPU time 8.03 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 204500 kb
Host smart-a0a784b7-59da-469f-9d45-55bb1500a70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
9329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.114749329
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.439502111
Short name T1237
Test name
Test status
Simulation time 8525844626 ps
CPU time 11.16 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204640 kb
Host smart-a3019d8b-1236-4ba8-917c-8cec40500c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43950
2111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.439502111
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_enable.911731068
Short name T1387
Test name
Test status
Simulation time 8399093931 ps
CPU time 7.77 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 204420 kb
Host smart-08023715-4df4-4460-9ebe-1a658786733f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91173
1068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.911731068
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1761043054
Short name T1241
Test name
Test status
Simulation time 273688946 ps
CPU time 2.28 seconds
Started May 12 12:57:06 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 204676 kb
Host smart-71315724-00b6-4d99-bc1a-903230911c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
43054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1761043054
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1912911049
Short name T1095
Test name
Test status
Simulation time 8425781148 ps
CPU time 8.49 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204420 kb
Host smart-ccbbbe86-d263-4473-8a9e-195c66124c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19129
11049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1912911049
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2866030082
Short name T565
Test name
Test status
Simulation time 8388015918 ps
CPU time 9.7 seconds
Started May 12 12:57:03 PM PDT 24
Finished May 12 12:57:13 PM PDT 24
Peak memory 204352 kb
Host smart-f6ae4c86-129e-4f78-afb6-d232ef78f38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28660
30082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2866030082
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3240694527
Short name T853
Test name
Test status
Simulation time 8484770801 ps
CPU time 8.29 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:13 PM PDT 24
Peak memory 204352 kb
Host smart-66d1d88f-44e4-438e-b229-a294ce5ed688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
94527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3240694527
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4162434307
Short name T1348
Test name
Test status
Simulation time 8424431073 ps
CPU time 8.05 seconds
Started May 12 12:57:09 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204340 kb
Host smart-9842aa08-9d38-4ba2-b9f0-654d9108311c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
34307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4162434307
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.807224524
Short name T976
Test name
Test status
Simulation time 8381995319 ps
CPU time 7.97 seconds
Started May 12 12:57:10 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204488 kb
Host smart-fca9c4fe-44dc-4eab-aa2a-53489d2d0fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80722
4524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.807224524
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.4251689706
Short name T1086
Test name
Test status
Simulation time 8501048865 ps
CPU time 7.5 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204340 kb
Host smart-49e7bf34-80e0-4d39-b68a-8c7388fb36e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
89706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.4251689706
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2010143391
Short name T1051
Test name
Test status
Simulation time 8386990130 ps
CPU time 8.03 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204408 kb
Host smart-75f386c0-5423-4b65-bb6c-9ae1c21b5eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
43391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2010143391
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.843185165
Short name T1079
Test name
Test status
Simulation time 8405964671 ps
CPU time 7.87 seconds
Started May 12 12:57:05 PM PDT 24
Finished May 12 12:57:14 PM PDT 24
Peak memory 204444 kb
Host smart-b57e23f9-dd46-43c7-94ab-20d1d2ef8597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84318
5165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.843185165
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.757992039
Short name T549
Test name
Test status
Simulation time 8404339380 ps
CPU time 7.81 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 203996 kb
Host smart-8bd40c37-af09-4155-83a0-afc57bbe6e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75799
2039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.757992039
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2820293718
Short name T540
Test name
Test status
Simulation time 8377623117 ps
CPU time 8.47 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204432 kb
Host smart-d3a52fb4-7ad1-412f-be3f-e84cb59fed83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28202
93718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2820293718
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1396521243
Short name T845
Test name
Test status
Simulation time 36613186 ps
CPU time 0.71 seconds
Started May 12 12:57:01 PM PDT 24
Finished May 12 12:57:02 PM PDT 24
Peak memory 204380 kb
Host smart-8daf192c-5df0-481e-acbd-190bfc8501cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13965
21243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1396521243
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1932258090
Short name T693
Test name
Test status
Simulation time 13904581349 ps
CPU time 23.28 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204724 kb
Host smart-54ea9dd0-c295-4689-9d17-80eac62ea351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
58090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1932258090
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3712978854
Short name T1047
Test name
Test status
Simulation time 8410851056 ps
CPU time 8.06 seconds
Started May 12 12:57:04 PM PDT 24
Finished May 12 12:57:13 PM PDT 24
Peak memory 204348 kb
Host smart-48c4aaeb-9c45-4177-94df-e714068d9db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37129
78854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3712978854
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2839562107
Short name T947
Test name
Test status
Simulation time 8454445418 ps
CPU time 8.7 seconds
Started May 12 12:57:03 PM PDT 24
Finished May 12 12:57:12 PM PDT 24
Peak memory 204420 kb
Host smart-cdde532d-9e7a-48bd-89de-127ced7f4c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28395
62107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2839562107
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2515146761
Short name T787
Test name
Test status
Simulation time 8392699147 ps
CPU time 9.54 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204756 kb
Host smart-ae3232f1-7c85-4d03-9200-059d1b451617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
46761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2515146761
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3117712864
Short name T856
Test name
Test status
Simulation time 8382072249 ps
CPU time 7.51 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204416 kb
Host smart-93d8a225-c389-4c7e-a4ef-9f8a76513b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177
12864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3117712864
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1006079085
Short name T1198
Test name
Test status
Simulation time 8371032780 ps
CPU time 8.39 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204368 kb
Host smart-4e8a41a8-56b4-4830-a0bd-167f4fe0e91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10060
79085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1006079085
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3880810823
Short name T1208
Test name
Test status
Simulation time 8483597642 ps
CPU time 8.38 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204500 kb
Host smart-63046b11-0c96-4e92-8609-79f6ec0c2dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38808
10823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3880810823
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2066185584
Short name T873
Test name
Test status
Simulation time 8381187013 ps
CPU time 7.56 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204396 kb
Host smart-be1a92d1-3441-4225-9de7-bdf6936abb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
85584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2066185584
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1354145333
Short name T1250
Test name
Test status
Simulation time 8410661500 ps
CPU time 7.81 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204452 kb
Host smart-af3b332d-59cf-4137-bc3c-76fc07a6f8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13541
45333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1354145333
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.2795782716
Short name T431
Test name
Test status
Simulation time 8536910774 ps
CPU time 7.95 seconds
Started May 12 12:54:44 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204488 kb
Host smart-550a6325-275f-40f7-b685-d7ea2e285319
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2795782716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.2795782716
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.3130695793
Short name T876
Test name
Test status
Simulation time 8379144555 ps
CPU time 7.55 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204760 kb
Host smart-dfb6e3bd-ca02-4036-b9cf-a979a45dc58c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3130695793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.3130695793
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2635773760
Short name T1210
Test name
Test status
Simulation time 8412169107 ps
CPU time 7.93 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 204448 kb
Host smart-b363a092-a070-416c-ab76-b6e52ff471dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
73760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2635773760
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2900714403
Short name T971
Test name
Test status
Simulation time 8374126731 ps
CPU time 8.81 seconds
Started May 12 12:54:44 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204432 kb
Host smart-7afd510d-82e5-4cce-946a-6758ff227916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29007
14403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2900714403
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.336659904
Short name T1418
Test name
Test status
Simulation time 9667090542 ps
CPU time 14.18 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 204924 kb
Host smart-4f5e8de9-c766-482e-99fa-03708e4bf002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33665
9904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.336659904
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_enable.3836044530
Short name T691
Test name
Test status
Simulation time 8402513490 ps
CPU time 8.86 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204564 kb
Host smart-ed183c53-9543-47ad-aa72-0fdb0fe1dfa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38360
44530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3836044530
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4173099852
Short name T1251
Test name
Test status
Simulation time 60697225 ps
CPU time 1.64 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204536 kb
Host smart-08f9d536-bf79-4e41-a78e-3020e4c9102d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41730
99852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4173099852
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1538243849
Short name T1257
Test name
Test status
Simulation time 8412749013 ps
CPU time 8.54 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 204344 kb
Host smart-b275cf03-4715-4e15-bdb4-d514fcb9db63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15382
43849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1538243849
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3821913119
Short name T967
Test name
Test status
Simulation time 8371691656 ps
CPU time 8.95 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 204328 kb
Host smart-69c8c5b7-270f-4a8b-8a4d-d94afc651caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38219
13119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3821913119
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.143828765
Short name T811
Test name
Test status
Simulation time 8380675238 ps
CPU time 8.32 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204320 kb
Host smart-a3caf97f-c860-4088-814b-faa756fe9fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382
8765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.143828765
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2836910572
Short name T1115
Test name
Test status
Simulation time 8436353481 ps
CPU time 8.09 seconds
Started May 12 12:54:35 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 204432 kb
Host smart-18d6c52f-9fad-4306-b198-2d91f8c08303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
10572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2836910572
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3754258774
Short name T736
Test name
Test status
Simulation time 8384863467 ps
CPU time 7.74 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 204340 kb
Host smart-3d9305fd-a2b5-4d7e-86ed-d3e5b5aca636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37542
58774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3754258774
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3029345286
Short name T111
Test name
Test status
Simulation time 8452784163 ps
CPU time 8.13 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204444 kb
Host smart-437c4825-83e6-4a7d-9df8-2b38852fab96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30293
45286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3029345286
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2104504399
Short name T841
Test name
Test status
Simulation time 8416348597 ps
CPU time 7.83 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:46 PM PDT 24
Peak memory 204500 kb
Host smart-2ed3d333-b9f0-4d57-b6cf-2227941dd08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
04399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2104504399
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1883443084
Short name T605
Test name
Test status
Simulation time 8400275569 ps
CPU time 8.19 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204524 kb
Host smart-add88ebd-cb97-4979-b561-ffaf3cb0cf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
43084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1883443084
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1999976793
Short name T1102
Test name
Test status
Simulation time 8405143634 ps
CPU time 8.26 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204424 kb
Host smart-076fd034-0d05-482a-a988-656e711f2179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19999
76793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1999976793
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2258770203
Short name T1202
Test name
Test status
Simulation time 8361789696 ps
CPU time 10.36 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204328 kb
Host smart-322195a3-e5ee-4a8f-9b62-6c46d5804a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22587
70203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2258770203
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.244961187
Short name T38
Test name
Test status
Simulation time 49030263 ps
CPU time 0.69 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 204616 kb
Host smart-41e52330-8354-4d93-becc-6a2e46df702c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24496
1187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.244961187
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1907846209
Short name T1323
Test name
Test status
Simulation time 19387029632 ps
CPU time 35.66 seconds
Started May 12 12:54:39 PM PDT 24
Finished May 12 12:55:16 PM PDT 24
Peak memory 204676 kb
Host smart-9fdc83cc-110b-4c04-853a-66753aaedee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078
46209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1907846209
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3454968490
Short name T331
Test name
Test status
Simulation time 8404927982 ps
CPU time 8.03 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204464 kb
Host smart-60fc4307-37be-40e2-a717-cbf5bcaddfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34549
68490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3454968490
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1925084238
Short name T1288
Test name
Test status
Simulation time 8445769397 ps
CPU time 9.51 seconds
Started May 12 12:54:40 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204428 kb
Host smart-8f6d4131-9a5e-4207-b55e-a5614bbf47c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
84238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1925084238
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3555792325
Short name T1423
Test name
Test status
Simulation time 8394573837 ps
CPU time 8.62 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204464 kb
Host smart-39a5a710-b77d-4c1b-8266-994c635c08ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
92325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3555792325
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3566456020
Short name T64
Test name
Test status
Simulation time 293204722 ps
CPU time 1.18 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 221752 kb
Host smart-020f8161-7036-4494-8257-b1a28af5d4d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3566456020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3566456020
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.496140246
Short name T1432
Test name
Test status
Simulation time 8379746597 ps
CPU time 7.74 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 204372 kb
Host smart-44da8279-3db2-4568-996b-227069765e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49614
0246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.496140246
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.967563438
Short name T1320
Test name
Test status
Simulation time 8368845338 ps
CPU time 8.69 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204516 kb
Host smart-4ecc89bb-5a54-4098-bf72-d7e8a748d72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96756
3438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.967563438
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.350020727
Short name T687
Test name
Test status
Simulation time 8463045144 ps
CPU time 9.31 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 204440 kb
Host smart-fbcda69f-845b-4f45-8377-1147eae17fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35002
0727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.350020727
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4186452146
Short name T1390
Test name
Test status
Simulation time 8382789142 ps
CPU time 7.8 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204416 kb
Host smart-2e6d5ad6-01bf-43da-8acd-df8e7346548c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41864
52146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4186452146
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1218200532
Short name T756
Test name
Test status
Simulation time 8386212959 ps
CPU time 8.04 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204416 kb
Host smart-a6239f3c-e520-4478-af01-5aa196cec77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12182
00532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1218200532
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.514142817
Short name T1434
Test name
Test status
Simulation time 8534923062 ps
CPU time 8.43 seconds
Started May 12 12:57:19 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204760 kb
Host smart-e0965e8d-e4b5-4249-ae14-3a25cc298cc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=514142817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.514142817
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3322785616
Short name T550
Test name
Test status
Simulation time 8383214968 ps
CPU time 8.85 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204412 kb
Host smart-ccf84532-334e-41fd-b525-b5bb206c2aff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3322785616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3322785616
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.2143525618
Short name T589
Test name
Test status
Simulation time 8388643547 ps
CPU time 7.74 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 204444 kb
Host smart-201cb06f-e336-401b-9d50-8052899614fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
25618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.2143525618
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.735576949
Short name T558
Test name
Test status
Simulation time 8388601978 ps
CPU time 7.3 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 204396 kb
Host smart-9b47868f-be19-4a95-8073-c316eba4db3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73557
6949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.735576949
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3280415778
Short name T221
Test name
Test status
Simulation time 9271061541 ps
CPU time 14.34 seconds
Started May 12 12:57:03 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 204756 kb
Host smart-4f7c96bc-e90f-4c45-89b0-ec2650862965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
15778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3280415778
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_enable.186749551
Short name T606
Test name
Test status
Simulation time 8386328567 ps
CPU time 7.75 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204364 kb
Host smart-369c0da2-5b3d-4757-9a58-95afc474af36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18674
9551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.186749551
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1085691754
Short name T795
Test name
Test status
Simulation time 50527705 ps
CPU time 1.38 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 204588 kb
Host smart-c4df2067-44cb-4591-bbdd-7bbdedfbb88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10856
91754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1085691754
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.347142376
Short name T468
Test name
Test status
Simulation time 8398492408 ps
CPU time 8.93 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204380 kb
Host smart-746625a9-ee68-4efe-be1c-3935aeedff55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34714
2376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.347142376
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3193375402
Short name T195
Test name
Test status
Simulation time 8372080877 ps
CPU time 9.4 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204456 kb
Host smart-9292486a-73e1-49d5-b0d4-ac97c37fbfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31933
75402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3193375402
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2262495164
Short name T1194
Test name
Test status
Simulation time 8446366321 ps
CPU time 7.91 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:17 PM PDT 24
Peak memory 204408 kb
Host smart-c8e94f51-ef63-4d7e-8b8d-a380f3df08cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22624
95164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2262495164
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2215312506
Short name T1240
Test name
Test status
Simulation time 8415656204 ps
CPU time 9.99 seconds
Started May 12 12:57:00 PM PDT 24
Finished May 12 12:57:10 PM PDT 24
Peak memory 204368 kb
Host smart-1dd24464-8561-4da6-bfb5-5e7ac3fb6dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
12506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2215312506
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2308265307
Short name T644
Test name
Test status
Simulation time 8422764535 ps
CPU time 7.65 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204460 kb
Host smart-81e2cf7a-79e0-42da-b28a-6205aad82ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082
65307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2308265307
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2249085072
Short name T847
Test name
Test status
Simulation time 8426164134 ps
CPU time 7.91 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204456 kb
Host smart-e9d6df99-d8ca-4f72-a114-fd647275bd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
85072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2249085072
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1199961319
Short name T1219
Test name
Test status
Simulation time 8414125984 ps
CPU time 7.77 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204412 kb
Host smart-6e530820-085c-4359-95a2-8c343e31948e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11999
61319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1199961319
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1332079789
Short name T1344
Test name
Test status
Simulation time 8423610747 ps
CPU time 7.95 seconds
Started May 12 12:57:17 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204452 kb
Host smart-f21c5c5b-e40b-4d2f-8d80-c64bd1311aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
79789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1332079789
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1366924239
Short name T830
Test name
Test status
Simulation time 8431539004 ps
CPU time 8.55 seconds
Started May 12 12:57:17 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204448 kb
Host smart-4e15d4ec-0794-4e2c-80d5-5590d576346f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
24239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1366924239
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1530673770
Short name T1415
Test name
Test status
Simulation time 8395910717 ps
CPU time 7.45 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204384 kb
Host smart-557e02cb-a86d-462c-a69a-d3d60a493ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15306
73770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1530673770
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.462776112
Short name T48
Test name
Test status
Simulation time 30531300 ps
CPU time 0.64 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:14 PM PDT 24
Peak memory 204004 kb
Host smart-93a31d2e-4574-4f52-b45f-a31077e71ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46277
6112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.462776112
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1912690782
Short name T1228
Test name
Test status
Simulation time 30675449481 ps
CPU time 57.9 seconds
Started May 12 12:57:19 PM PDT 24
Finished May 12 12:58:18 PM PDT 24
Peak memory 204676 kb
Host smart-a8908185-f05d-4c63-a40c-9e87c088b117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
90782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1912690782
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3904873421
Short name T576
Test name
Test status
Simulation time 8415082446 ps
CPU time 8.17 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204340 kb
Host smart-03dd6b5e-25b8-4367-83a6-dc40c8a40b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39048
73421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3904873421
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3276920760
Short name T162
Test name
Test status
Simulation time 8454499334 ps
CPU time 7.85 seconds
Started May 12 12:57:08 PM PDT 24
Finished May 12 12:57:17 PM PDT 24
Peak memory 204328 kb
Host smart-0e89daf1-cc22-42e5-9d0c-79ae599e42f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32769
20760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3276920760
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1614834050
Short name T474
Test name
Test status
Simulation time 8410502024 ps
CPU time 8.41 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204388 kb
Host smart-82dd0607-6d76-490d-88ad-14bed76b6a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16148
34050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1614834050
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1971973949
Short name T1357
Test name
Test status
Simulation time 8375237532 ps
CPU time 8.27 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204452 kb
Host smart-24f80625-48ce-4b80-a0d1-65978bd9a2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19719
73949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1971973949
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2473262771
Short name T1282
Test name
Test status
Simulation time 8370114588 ps
CPU time 9.51 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 204412 kb
Host smart-348f2f75-5f72-49ef-83f9-f507607a7ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24732
62771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2473262771
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3885907107
Short name T1023
Test name
Test status
Simulation time 8465857231 ps
CPU time 8.02 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 204420 kb
Host smart-659cdb75-8e33-4dbc-8cc2-dbd06d19cefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38859
07107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3885907107
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.122568322
Short name T1395
Test name
Test status
Simulation time 8405418009 ps
CPU time 7.54 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204452 kb
Host smart-d0fbeda9-77b9-41a0-9bad-df47994c29db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12256
8322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.122568322
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1005439633
Short name T1315
Test name
Test status
Simulation time 8407580486 ps
CPU time 7.63 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204452 kb
Host smart-e19fef50-8789-4e3e-b9fd-84fc5991af87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054
39633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1005439633
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.655935049
Short name T505
Test name
Test status
Simulation time 8469006037 ps
CPU time 8.23 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:57:36 PM PDT 24
Peak memory 204460 kb
Host smart-40d26be4-1e15-47f3-9a69-3817c490e370
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=655935049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.655935049
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.2251006182
Short name T932
Test name
Test status
Simulation time 8391395438 ps
CPU time 8.75 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204424 kb
Host smart-ebdda0bc-338d-47b8-a190-d3ebd52c196a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2251006182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.2251006182
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.4222883904
Short name T1345
Test name
Test status
Simulation time 8400409334 ps
CPU time 9.43 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204336 kb
Host smart-f367ae05-bedc-4f85-ae3a-dcc0c6305b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
83904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.4222883904
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2362496563
Short name T1129
Test name
Test status
Simulation time 8378830494 ps
CPU time 8.01 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204432 kb
Host smart-f7665de9-75ca-4a17-a774-8e8abbe49ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23624
96563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2362496563
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1083585738
Short name T15
Test name
Test status
Simulation time 9415675198 ps
CPU time 13.01 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204676 kb
Host smart-38ed6bc5-4741-4d3b-b77b-42c786bf0fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10835
85738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1083585738
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_enable.1415024509
Short name T920
Test name
Test status
Simulation time 8380605140 ps
CPU time 8.83 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204456 kb
Host smart-2c5e772c-3be5-430a-ad3c-5c6d37f873c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150
24509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1415024509
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2692331509
Short name T824
Test name
Test status
Simulation time 211273069 ps
CPU time 2.27 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:18 PM PDT 24
Peak memory 204636 kb
Host smart-6c97ec77-74b9-4a6f-97e7-80e11b7b63c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
31509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2692331509
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3665222761
Short name T821
Test name
Test status
Simulation time 8461043246 ps
CPU time 8.87 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204456 kb
Host smart-e04ac862-5548-4a8f-8005-676b644a4a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36652
22761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3665222761
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1913948624
Short name T1343
Test name
Test status
Simulation time 8389711697 ps
CPU time 9.6 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204400 kb
Host smart-81395271-621a-4240-8b55-8ea29801a34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139
48624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1913948624
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3685718407
Short name T675
Test name
Test status
Simulation time 8423944096 ps
CPU time 8.3 seconds
Started May 12 12:57:11 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204416 kb
Host smart-c30cd1dc-db0c-4707-834c-9b1a3730a458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36857
18407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3685718407
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2934584069
Short name T892
Test name
Test status
Simulation time 8413173017 ps
CPU time 8.11 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204468 kb
Host smart-a78cf6be-7123-415b-84c9-663a6c42adb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29345
84069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2934584069
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1401264212
Short name T1394
Test name
Test status
Simulation time 8366556056 ps
CPU time 8.01 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204416 kb
Host smart-2040170b-9d9d-407c-9758-a229efbe2e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14012
64212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1401264212
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2727878296
Short name T132
Test name
Test status
Simulation time 8430739025 ps
CPU time 9.76 seconds
Started May 12 12:57:09 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204740 kb
Host smart-6bafc917-7d92-4919-9100-ac7190888bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27278
78296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2727878296
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1949278773
Short name T538
Test name
Test status
Simulation time 8392043727 ps
CPU time 7.75 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:31 PM PDT 24
Peak memory 204344 kb
Host smart-0be6682b-3d81-4ace-b0be-456e15d46d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
78773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1949278773
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.137854408
Short name T528
Test name
Test status
Simulation time 8409471653 ps
CPU time 7.81 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204444 kb
Host smart-f864c3f4-3144-4d89-b82b-5243ec1e6450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13785
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.137854408
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3966790920
Short name T212
Test name
Test status
Simulation time 8405341561 ps
CPU time 7.9 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204376 kb
Host smart-9317d166-b9a6-4d4c-b980-444dead1722c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39667
90920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3966790920
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.575706507
Short name T929
Test name
Test status
Simulation time 8364691423 ps
CPU time 8 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204420 kb
Host smart-0c073c9b-6804-410a-84ea-a23d889a652e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57570
6507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.575706507
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2994386172
Short name T414
Test name
Test status
Simulation time 38803035 ps
CPU time 0.64 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:17 PM PDT 24
Peak memory 204376 kb
Host smart-6e1b7f6a-6205-4133-9862-6811c47104af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29943
86172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2994386172
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1441596207
Short name T798
Test name
Test status
Simulation time 30292436414 ps
CPU time 55.94 seconds
Started May 12 12:57:09 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 204752 kb
Host smart-07928f8d-c7d5-4e18-a3ad-a973b2023a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14415
96207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1441596207
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1076211205
Short name T678
Test name
Test status
Simulation time 8408748208 ps
CPU time 7.43 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204368 kb
Host smart-6bb7c4ca-ac05-46b4-a306-9106768c85f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
11205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1076211205
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2146444984
Short name T686
Test name
Test status
Simulation time 8464945878 ps
CPU time 9.82 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204460 kb
Host smart-63cc0e08-9cce-4a95-9720-021908507169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21464
44984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2146444984
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2653316054
Short name T593
Test name
Test status
Simulation time 8416347580 ps
CPU time 8.14 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204704 kb
Host smart-dfd9c3e9-94fd-477e-b371-cacbf361b55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
16054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2653316054
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.367812907
Short name T1140
Test name
Test status
Simulation time 8381692612 ps
CPU time 7.91 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204372 kb
Host smart-dbe555c9-285f-456e-8c61-f1c4056a5a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36781
2907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.367812907
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2233828432
Short name T567
Test name
Test status
Simulation time 8374418854 ps
CPU time 7.81 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204392 kb
Host smart-37d4d003-46d1-4c7d-bd88-90699625e625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22338
28432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2233828432
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2254352660
Short name T977
Test name
Test status
Simulation time 8444666422 ps
CPU time 8.59 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204468 kb
Host smart-a4eabb46-bf46-42a6-b6b6-6c1f0063ebce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543
52660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2254352660
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2545043464
Short name T31
Test name
Test status
Simulation time 8464596417 ps
CPU time 7.88 seconds
Started May 12 12:57:30 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204380 kb
Host smart-9d91b806-5b68-47b2-a66e-483ea552e351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25450
43464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2545043464
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1820434585
Short name T1396
Test name
Test status
Simulation time 8388044218 ps
CPU time 7.85 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204492 kb
Host smart-f42b9df0-2eda-4072-ab02-01ac75460a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18204
34585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1820434585
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.3649857959
Short name T41
Test name
Test status
Simulation time 8470764940 ps
CPU time 10.17 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:41 PM PDT 24
Peak memory 204412 kb
Host smart-ed7dc01d-f353-4dcb-9c1b-e2cc5d2847f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3649857959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.3649857959
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.2879680703
Short name T390
Test name
Test status
Simulation time 8402287028 ps
CPU time 9.13 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 204420 kb
Host smart-435b2525-7604-40e7-ab25-7e6fa81ebc14
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2879680703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.2879680703
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.262974196
Short name T1087
Test name
Test status
Simulation time 8479933795 ps
CPU time 8.31 seconds
Started May 12 12:57:07 PM PDT 24
Finished May 12 12:57:16 PM PDT 24
Peak memory 204360 kb
Host smart-8267d8b8-f1b3-4e01-b9b3-5ae33e911e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26297
4196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.262974196
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.374721582
Short name T1041
Test name
Test status
Simulation time 8402548474 ps
CPU time 7.77 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204396 kb
Host smart-02fc2678-f6f2-4d89-ab97-1aa52e4236c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37472
1582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.374721582
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1296595191
Short name T526
Test name
Test status
Simulation time 8840980491 ps
CPU time 11.96 seconds
Started May 12 12:57:09 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 204564 kb
Host smart-1e5551f8-5ab4-4514-b74a-944752e6fa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12965
95191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1296595191
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_enable.939059558
Short name T296
Test name
Test status
Simulation time 8375217445 ps
CPU time 8.77 seconds
Started May 12 12:57:20 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204420 kb
Host smart-e03de1ac-b79e-4d7e-83aa-6edacdc8cbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93905
9558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.939059558
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.4203179497
Short name T448
Test name
Test status
Simulation time 256272474 ps
CPU time 2.2 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 204560 kb
Host smart-9c74f7c1-ba2f-476e-afcf-659cf3b8c6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42031
79497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.4203179497
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1352261869
Short name T150
Test name
Test status
Simulation time 8407493149 ps
CPU time 7.64 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204440 kb
Host smart-6dcb9e45-ef42-4006-9257-edf8a249d3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13522
61869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1352261869
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1850308979
Short name T200
Test name
Test status
Simulation time 8368473316 ps
CPU time 8.76 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204384 kb
Host smart-0ed7b601-628f-4784-b165-499fe1942f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18503
08979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1850308979
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2146308624
Short name T969
Test name
Test status
Simulation time 8420067516 ps
CPU time 7.52 seconds
Started May 12 12:57:21 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204400 kb
Host smart-ecc946e5-688f-4695-af56-f1d1512ba094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21463
08624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2146308624
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.267706143
Short name T799
Test name
Test status
Simulation time 8428337331 ps
CPU time 8.18 seconds
Started May 12 12:57:17 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204472 kb
Host smart-09e3f3e5-dd75-4cbd-9b06-0ae2f64620e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26770
6143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.267706143
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3332339104
Short name T1238
Test name
Test status
Simulation time 8405075450 ps
CPU time 9.78 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204328 kb
Host smart-b361a7f5-bf3b-4b56-8450-88261efef259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33323
39104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3332339104
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.907015164
Short name T107
Test name
Test status
Simulation time 8417223466 ps
CPU time 8.22 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204444 kb
Host smart-bb9bbc15-f477-49ca-b60e-3bcc07337f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90701
5164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.907015164
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.235984078
Short name T1134
Test name
Test status
Simulation time 8404953740 ps
CPU time 9.32 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204420 kb
Host smart-00aea32f-431f-4e03-948b-a01bdd2092ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
4078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.235984078
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2794259645
Short name T358
Test name
Test status
Simulation time 8460485495 ps
CPU time 8.04 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204356 kb
Host smart-129e27de-9f58-4ace-8667-88f5d7d7d7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
59645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2794259645
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3543649391
Short name T196
Test name
Test status
Simulation time 8403852468 ps
CPU time 10.16 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204432 kb
Host smart-ab8d4916-5671-44d7-902a-480e0b563e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35436
49391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3543649391
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3272272964
Short name T1286
Test name
Test status
Simulation time 8372556011 ps
CPU time 8.32 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204412 kb
Host smart-90493367-eb31-434e-87b0-107b2282649c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32722
72964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3272272964
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4183236254
Short name T844
Test name
Test status
Simulation time 33107087 ps
CPU time 0.64 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204364 kb
Host smart-699ea607-c28a-4c52-8cd5-c8f4ff06b013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41832
36254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4183236254
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2673792617
Short name T623
Test name
Test status
Simulation time 16877971433 ps
CPU time 33.24 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204636 kb
Host smart-dc223b21-057a-493e-ae39-6d63b35bdc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26737
92617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2673792617
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2597158066
Short name T865
Test name
Test status
Simulation time 8414217711 ps
CPU time 7.91 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204452 kb
Host smart-c60581b8-2965-4ff5-a3e5-ea6d315e6930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971
58066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2597158066
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1958287405
Short name T879
Test name
Test status
Simulation time 8427189658 ps
CPU time 9.4 seconds
Started May 12 12:57:10 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204412 kb
Host smart-d607b02f-f2ee-47c1-8882-1ff7d5ddc88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19582
87405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1958287405
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1592822271
Short name T82
Test name
Test status
Simulation time 8439991231 ps
CPU time 7.73 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204436 kb
Host smart-a9607149-e5cf-44c1-99dd-2f3ef6d40436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928
22271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1592822271
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3814467079
Short name T855
Test name
Test status
Simulation time 8371606396 ps
CPU time 8.53 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204428 kb
Host smart-21686e5d-431a-427c-a58e-e96dd44d831b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
67079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3814467079
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.435101955
Short name T382
Test name
Test status
Simulation time 8365681118 ps
CPU time 8.24 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204376 kb
Host smart-0cf3029a-d9b2-4d90-8875-9f8efb4c2ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43510
1955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.435101955
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2634194982
Short name T1338
Test name
Test status
Simulation time 8407206388 ps
CPU time 7.63 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204444 kb
Host smart-72203c42-1c3e-49e9-bb8d-85bac6256e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26341
94982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2634194982
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2652351113
Short name T1084
Test name
Test status
Simulation time 8419932449 ps
CPU time 7.43 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204424 kb
Host smart-71247bef-82fe-4607-a35c-eca397bd0e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26523
51113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2652351113
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.4111067024
Short name T1112
Test name
Test status
Simulation time 8403844686 ps
CPU time 7.59 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204424 kb
Host smart-c1c10ea6-ac13-4700-82ad-6f389dc02788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41110
67024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.4111067024
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3551292861
Short name T537
Test name
Test status
Simulation time 8497462883 ps
CPU time 8.02 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204416 kb
Host smart-20b4304f-e514-494a-b699-d0cb3f846854
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3551292861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3551292861
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.808386278
Short name T1092
Test name
Test status
Simulation time 8394199325 ps
CPU time 8.87 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204428 kb
Host smart-745bd1d6-b80d-4c5e-a711-cf16d509a7bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=808386278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.808386278
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.607975247
Short name T819
Test name
Test status
Simulation time 8424062855 ps
CPU time 8.7 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204396 kb
Host smart-1e27e9da-c66b-4a56-8f05-d2d511c28849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60797
5247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.607975247
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2027633746
Short name T383
Test name
Test status
Simulation time 8389298924 ps
CPU time 8.35 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204432 kb
Host smart-1e61dab1-6717-4c9b-be55-e688b125d303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20276
33746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2027633746
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3993133038
Short name T220
Test name
Test status
Simulation time 8840767596 ps
CPU time 11.65 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204744 kb
Host smart-a4d36762-785a-458e-a93a-276861afdbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
33038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3993133038
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_enable.3806778198
Short name T1048
Test name
Test status
Simulation time 8418356646 ps
CPU time 7.66 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204336 kb
Host smart-653e9d5e-5129-4ad8-9f85-7b9816334e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38067
78198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3806778198
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3704003170
Short name T543
Test name
Test status
Simulation time 57385243 ps
CPU time 1.52 seconds
Started May 12 12:57:19 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204940 kb
Host smart-b02de4a0-a45b-46d0-870f-4df0d1cc458e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
03170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3704003170
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3022070760
Short name T982
Test name
Test status
Simulation time 8395561011 ps
CPU time 8.94 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204372 kb
Host smart-668e5b43-bf4c-4b75-9cc5-9f9f95909853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
70760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3022070760
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2307966292
Short name T1004
Test name
Test status
Simulation time 8369733852 ps
CPU time 8.22 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:31 PM PDT 24
Peak memory 204400 kb
Host smart-b12f6d7b-41ec-45d4-bf37-ccaf07168acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23079
66292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2307966292
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3059589730
Short name T743
Test name
Test status
Simulation time 8405134564 ps
CPU time 7.58 seconds
Started May 12 12:57:20 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204400 kb
Host smart-f11b1e51-ddb6-4d18-822d-b352a86afa9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30595
89730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3059589730
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1781589903
Short name T1062
Test name
Test status
Simulation time 8413255893 ps
CPU time 7.98 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204440 kb
Host smart-55040f5d-5ccb-499b-b21b-409fa0ce0096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17815
89903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1781589903
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1405966103
Short name T826
Test name
Test status
Simulation time 8376370993 ps
CPU time 7.48 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204540 kb
Host smart-f48814c8-7000-4e21-8933-6546c6ce5cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
66103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1405966103
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2896967374
Short name T116
Test name
Test status
Simulation time 8444612737 ps
CPU time 7.75 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204420 kb
Host smart-ebd40c96-8a92-41e3-8032-4cdd9d54f323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
67374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2896967374
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2301111266
Short name T1425
Test name
Test status
Simulation time 8392360953 ps
CPU time 8.08 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204428 kb
Host smart-b3d04a7c-69fa-426e-be02-f67f7d05d79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23011
11266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2301111266
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.244262876
Short name T18
Test name
Test status
Simulation time 8417410517 ps
CPU time 9.83 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204408 kb
Host smart-4a63db74-d212-4e48-b1ac-0aa1cb7d3c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
2876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.244262876
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3564989739
Short name T655
Test name
Test status
Simulation time 8397841580 ps
CPU time 7.74 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:57:36 PM PDT 24
Peak memory 204440 kb
Host smart-a689433d-c084-4609-ae2d-8fd914d2881a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35649
89739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3564989739
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3465925049
Short name T379
Test name
Test status
Simulation time 8375175054 ps
CPU time 8.36 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204440 kb
Host smart-31782453-f2ed-4077-909e-50233a6c6f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659
25049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3465925049
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3798930460
Short name T611
Test name
Test status
Simulation time 44326074 ps
CPU time 0.7 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204248 kb
Host smart-2d8ee629-e21d-416e-8353-8e01764feb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
30460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3798930460
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1480286299
Short name T274
Test name
Test status
Simulation time 31836643321 ps
CPU time 61.92 seconds
Started May 12 12:57:17 PM PDT 24
Finished May 12 12:58:25 PM PDT 24
Peak memory 204636 kb
Host smart-97470459-7130-4e35-be6b-2823500fc1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
86299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1480286299
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3020014424
Short name T359
Test name
Test status
Simulation time 8427405591 ps
CPU time 7.98 seconds
Started May 12 12:57:42 PM PDT 24
Finished May 12 12:57:50 PM PDT 24
Peak memory 204412 kb
Host smart-91d059af-1674-410c-bd0c-2da2cfaec52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
14424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3020014424
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.318145803
Short name T1369
Test name
Test status
Simulation time 8426334466 ps
CPU time 9.62 seconds
Started May 12 12:57:17 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204328 kb
Host smart-55f48f1a-3ee5-4ba7-be1c-a532bc65c05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31814
5803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.318145803
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2232426078
Short name T1330
Test name
Test status
Simulation time 8394800316 ps
CPU time 7.78 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204344 kb
Host smart-216f36b7-da2d-4bc9-9ef7-a198227bd075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22324
26078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2232426078
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3577353157
Short name T1073
Test name
Test status
Simulation time 8439822840 ps
CPU time 8.17 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:23 PM PDT 24
Peak memory 204452 kb
Host smart-2a8b62f2-d676-43e0-9e9e-6c2a4912c21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35773
53157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3577353157
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1415802771
Short name T763
Test name
Test status
Simulation time 8373863145 ps
CPU time 8.37 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:35 PM PDT 24
Peak memory 204492 kb
Host smart-4dade120-b82f-40c1-b413-329bda43af63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14158
02771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1415802771
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.10767880
Short name T1043
Test name
Test status
Simulation time 8428103328 ps
CPU time 9.47 seconds
Started May 12 12:57:30 PM PDT 24
Finished May 12 12:57:41 PM PDT 24
Peak memory 204484 kb
Host smart-d5599be9-841c-4461-9e12-e43b06e3e782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10767
880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.10767880
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2565449575
Short name T801
Test name
Test status
Simulation time 8382231863 ps
CPU time 8.14 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204472 kb
Host smart-9f01affb-0e34-4ba1-808a-8664b5fa09d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
49575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2565449575
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3437384318
Short name T630
Test name
Test status
Simulation time 8420868255 ps
CPU time 10.46 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204472 kb
Host smart-8c7e18c2-16ec-4527-b216-0b932a8dbee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
84318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3437384318
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1163571378
Short name T434
Test name
Test status
Simulation time 8495136397 ps
CPU time 10.07 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:45 PM PDT 24
Peak memory 204480 kb
Host smart-5ee936f8-a614-4b95-bffc-b443a48501aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1163571378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1163571378
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2068348610
Short name T794
Test name
Test status
Simulation time 8380852992 ps
CPU time 8.49 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204456 kb
Host smart-ad5179a3-b1d2-4434-bc6f-e1ae5e9882f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2068348610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2068348610
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.636671927
Short name T1220
Test name
Test status
Simulation time 8456159280 ps
CPU time 10.27 seconds
Started May 12 12:57:38 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204312 kb
Host smart-1c0e4c27-1b25-4144-8744-6f2b040ee370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63667
1927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.636671927
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.587695531
Short name T1021
Test name
Test status
Simulation time 8375219689 ps
CPU time 7.69 seconds
Started May 12 12:57:21 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204488 kb
Host smart-aa3a9a4f-1448-468f-a419-8c3f9d9c6d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58769
5531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.587695531
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1009648172
Short name T1400
Test name
Test status
Simulation time 8834323367 ps
CPU time 14.14 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204584 kb
Host smart-004c7abc-edca-461f-88aa-a8483b8fa104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10096
48172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1009648172
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_enable.3263482221
Short name T758
Test name
Test status
Simulation time 8455404104 ps
CPU time 8.4 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204388 kb
Host smart-47235ca1-4ff2-4883-8528-35b054ebeed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32634
82221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3263482221
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3496106731
Short name T634
Test name
Test status
Simulation time 56135106 ps
CPU time 1.12 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 204492 kb
Host smart-19b76be6-9542-4fba-8366-67ef8da3d869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34961
06731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3496106731
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3221627766
Short name T160
Test name
Test status
Simulation time 8433867423 ps
CPU time 10.33 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:42 PM PDT 24
Peak memory 204348 kb
Host smart-b75455ba-1c0d-4688-b70c-af45e54f2b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
27766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3221627766
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.4144591576
Short name T211
Test name
Test status
Simulation time 8395747157 ps
CPU time 8.06 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204444 kb
Host smart-987b3dcb-318c-4e7b-b34c-6415ff76518b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41445
91576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.4144591576
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1550919597
Short name T39
Test name
Test status
Simulation time 8399364890 ps
CPU time 7.88 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:26 PM PDT 24
Peak memory 204488 kb
Host smart-16f6f80d-98b9-4a33-a551-be376625ea5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15509
19597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1550919597
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3636521033
Short name T1190
Test name
Test status
Simulation time 8422218321 ps
CPU time 7.63 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204436 kb
Host smart-39a08a20-0b82-44a4-b057-03842e500f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36365
21033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3636521033
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3398371632
Short name T1165
Test name
Test status
Simulation time 8371101181 ps
CPU time 7.57 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204380 kb
Host smart-c7320d4f-76b0-44e9-83be-6d0e10c6edff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33983
71632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3398371632
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3781729490
Short name T101
Test name
Test status
Simulation time 8388278405 ps
CPU time 9.56 seconds
Started May 12 12:57:14 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204408 kb
Host smart-fbe8fea2-8d14-40f3-86b7-f9524e243af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37817
29490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3781729490
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1667538600
Short name T1027
Test name
Test status
Simulation time 8399996224 ps
CPU time 9.34 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204428 kb
Host smart-da3ec5a4-7ecb-49a9-a86c-d76faf6d7008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16675
38600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1667538600
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3722531966
Short name T699
Test name
Test status
Simulation time 8377209788 ps
CPU time 7.97 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:31 PM PDT 24
Peak memory 204412 kb
Host smart-809a91a4-013c-43d2-b3bc-3d253508b6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37225
31966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3722531966
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3597289700
Short name T80
Test name
Test status
Simulation time 8377899937 ps
CPU time 7.73 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:35 PM PDT 24
Peak memory 204452 kb
Host smart-89cd1b7b-b25b-411b-b491-08fb14a4cf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35972
89700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3597289700
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.401458452
Short name T869
Test name
Test status
Simulation time 8387834770 ps
CPU time 8.17 seconds
Started May 12 12:57:19 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204540 kb
Host smart-d5bd1042-3044-4246-80ed-91c447958d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40145
8452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.401458452
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.874159386
Short name T770
Test name
Test status
Simulation time 42217338 ps
CPU time 0.68 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204304 kb
Host smart-15b80ef4-dd53-417c-9bc9-21258ad0ba6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87415
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.874159386
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2911573548
Short name T603
Test name
Test status
Simulation time 18462396708 ps
CPU time 32.24 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:58:00 PM PDT 24
Peak memory 204804 kb
Host smart-6e80957c-20e0-4502-88d8-63a70c13903f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29115
73548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2911573548
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.4234566877
Short name T742
Test name
Test status
Simulation time 8380764452 ps
CPU time 8.67 seconds
Started May 12 12:57:33 PM PDT 24
Finished May 12 12:57:42 PM PDT 24
Peak memory 204372 kb
Host smart-06179af6-1f59-4eb0-a0a3-d3eb44665c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
66877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.4234566877
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3794986670
Short name T818
Test name
Test status
Simulation time 8459966695 ps
CPU time 9 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:36 PM PDT 24
Peak memory 204428 kb
Host smart-f4f68b73-4d0c-4b3e-b01b-170ec262a2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37949
86670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3794986670
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2986671942
Short name T924
Test name
Test status
Simulation time 8396300071 ps
CPU time 8.72 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204348 kb
Host smart-cce66cb3-349e-47fc-863f-7d4ef9c94716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29866
71942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2986671942
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1323742210
Short name T190
Test name
Test status
Simulation time 8375700626 ps
CPU time 7.99 seconds
Started May 12 12:57:20 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204672 kb
Host smart-92d88744-ab21-4f8f-a948-04bcf700ab55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13237
42210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1323742210
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3697387254
Short name T863
Test name
Test status
Simulation time 8372464646 ps
CPU time 7.89 seconds
Started May 12 12:57:41 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204408 kb
Host smart-8d0cae36-d71a-4ea6-bc15-e9d0f307e412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36973
87254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3697387254
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2105550027
Short name T151
Test name
Test status
Simulation time 8446380982 ps
CPU time 10.23 seconds
Started May 12 12:57:13 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204396 kb
Host smart-78b7c4b5-ec2e-4d2e-86e7-aa3a6e44655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21055
50027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2105550027
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.4181404651
Short name T353
Test name
Test status
Simulation time 8384444309 ps
CPU time 9.7 seconds
Started May 12 12:57:16 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204440 kb
Host smart-02fd19ef-dd4e-4ea6-a28a-86d037ce2ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
04651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.4181404651
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.505597470
Short name T345
Test name
Test status
Simulation time 8406587047 ps
CPU time 10.04 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 204352 kb
Host smart-bd062146-2c85-4196-8270-f8bc68f4f71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50559
7470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.505597470
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1845985906
Short name T1083
Test name
Test status
Simulation time 8467894206 ps
CPU time 9.32 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 204376 kb
Host smart-9d14e86f-1294-4d06-a700-df1f437d9884
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1845985906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1845985906
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1401746815
Short name T1280
Test name
Test status
Simulation time 8427452408 ps
CPU time 7.53 seconds
Started May 12 12:57:20 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204412 kb
Host smart-660acc91-605f-49fc-8604-f5ccc327efcf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1401746815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1401746815
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.3780880523
Short name T1101
Test name
Test status
Simulation time 8426549488 ps
CPU time 7.47 seconds
Started May 12 12:57:40 PM PDT 24
Finished May 12 12:57:48 PM PDT 24
Peak memory 204444 kb
Host smart-7b386f15-b4bb-457b-b7ee-cc9a0780b991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808
80523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3780880523
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2410212951
Short name T399
Test name
Test status
Simulation time 8375089181 ps
CPU time 8.29 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 204352 kb
Host smart-1e3113db-3995-4976-9d97-2fe9a8bb4687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102
12951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2410212951
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.4290824198
Short name T1085
Test name
Test status
Simulation time 8805182430 ps
CPU time 12.69 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204632 kb
Host smart-ea351db7-31ab-476d-a8c8-0546d9e8ec53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908
24198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.4290824198
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_enable.2943061956
Short name T707
Test name
Test status
Simulation time 8370255149 ps
CPU time 8.06 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204496 kb
Host smart-13cbd450-aaf0-4e20-bca4-45f19e1dabda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29430
61956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2943061956
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.884089199
Short name T888
Test name
Test status
Simulation time 124567354 ps
CPU time 1.77 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:21 PM PDT 24
Peak memory 204496 kb
Host smart-c630efa6-c2ad-4fbe-9fee-10dfffae80a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88408
9199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.884089199
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3989134489
Short name T622
Test name
Test status
Simulation time 8464541448 ps
CPU time 7.79 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204444 kb
Host smart-f2725fbe-4ff9-42a8-87e8-30ee1d4b105f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39891
34489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3989134489
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2171030375
Short name T1350
Test name
Test status
Simulation time 8368393605 ps
CPU time 10.03 seconds
Started May 12 12:57:12 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 204428 kb
Host smart-e0a57c92-587f-47a8-b189-7e2067931497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21710
30375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2171030375
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2525232381
Short name T266
Test name
Test status
Simulation time 8476821625 ps
CPU time 7.83 seconds
Started May 12 12:57:32 PM PDT 24
Finished May 12 12:57:41 PM PDT 24
Peak memory 204460 kb
Host smart-33cee4b7-b95d-44f9-b9de-bd086614190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
32381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2525232381
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3366187373
Short name T1383
Test name
Test status
Simulation time 8418586632 ps
CPU time 7.93 seconds
Started May 12 12:57:21 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204564 kb
Host smart-0d51b5d6-94f7-402b-ad52-ec3aad9404a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
87373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3366187373
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2433730763
Short name T694
Test name
Test status
Simulation time 8368995713 ps
CPU time 7.42 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204388 kb
Host smart-9fa6eb30-2cb9-4512-b6c4-0dad1edb6a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24337
30763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2433730763
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3408296532
Short name T113
Test name
Test status
Simulation time 8386016305 ps
CPU time 7.29 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204452 kb
Host smart-8ea9f797-f15b-4fa8-b622-788d6652acc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34082
96532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3408296532
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.330569748
Short name T429
Test name
Test status
Simulation time 8385132759 ps
CPU time 7.66 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204488 kb
Host smart-dc60dc25-848c-4748-84d6-3379fa16b78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
9748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.330569748
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3496732020
Short name T1235
Test name
Test status
Simulation time 8423898719 ps
CPU time 7.59 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204352 kb
Host smart-cb2cbf33-15d0-40ad-b17e-e53c89a529a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34967
32020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3496732020
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4216626975
Short name T180
Test name
Test status
Simulation time 8380081464 ps
CPU time 7.92 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204440 kb
Host smart-a825060a-6ada-4965-ba66-7e4501e239df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42166
26975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4216626975
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1208209308
Short name T745
Test name
Test status
Simulation time 8371473735 ps
CPU time 9.82 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204436 kb
Host smart-3744fa0b-1079-4c14-8bdb-37e6b921603e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
09308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1208209308
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1432543345
Short name T1082
Test name
Test status
Simulation time 65115135 ps
CPU time 0.68 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:35 PM PDT 24
Peak memory 204260 kb
Host smart-f693a497-e602-4675-8883-6dcf393f83cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14325
43345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1432543345
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.4127678212
Short name T954
Test name
Test status
Simulation time 15671486048 ps
CPU time 28.39 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:51 PM PDT 24
Peak memory 204784 kb
Host smart-ec931b7b-c943-49a9-b4a9-6d24518dc43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41276
78212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.4127678212
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4065551319
Short name T1142
Test name
Test status
Simulation time 8411022740 ps
CPU time 7.81 seconds
Started May 12 12:57:23 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 204424 kb
Host smart-dda6592c-49a6-4874-8e42-bf49d477a8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655
51319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4065551319
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3365721163
Short name T617
Test name
Test status
Simulation time 8380070093 ps
CPU time 10.09 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:45 PM PDT 24
Peak memory 204428 kb
Host smart-c8dd8435-90f0-4916-9459-94d312645379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33657
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3365721163
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1152197213
Short name T89
Test name
Test status
Simulation time 8372690712 ps
CPU time 8.88 seconds
Started May 12 12:57:19 PM PDT 24
Finished May 12 12:57:29 PM PDT 24
Peak memory 204392 kb
Host smart-ec6bd5a3-0cf7-4174-b209-10657b7b448b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11521
97213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1152197213
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1369953134
Short name T175
Test name
Test status
Simulation time 8396039694 ps
CPU time 8.2 seconds
Started May 12 12:57:22 PM PDT 24
Finished May 12 12:57:31 PM PDT 24
Peak memory 204412 kb
Host smart-bee7f586-4c3d-4548-b186-7e6144c6d097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13699
53134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1369953134
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4003717247
Short name T476
Test name
Test status
Simulation time 8401394827 ps
CPU time 7.58 seconds
Started May 12 12:57:47 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 204452 kb
Host smart-64a38b79-e243-413d-bc1e-e7f1d4e16cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40037
17247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4003717247
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1562694001
Short name T1276
Test name
Test status
Simulation time 8410941844 ps
CPU time 7.81 seconds
Started May 12 12:57:21 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204328 kb
Host smart-60820b77-57c9-4c7c-bf04-8d53d9752fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
94001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1562694001
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3409295177
Short name T1245
Test name
Test status
Simulation time 8412344738 ps
CPU time 7.5 seconds
Started May 12 12:57:31 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204336 kb
Host smart-df6090de-8f3a-4afc-9e81-056ee36e7ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34092
95177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3409295177
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.740265536
Short name T626
Test name
Test status
Simulation time 8382451655 ps
CPU time 8.57 seconds
Started May 12 12:57:18 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204348 kb
Host smart-91d07b12-533f-4f38-8c2d-e1c8a76c1b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74026
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.740265536
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.2331347758
Short name T1007
Test name
Test status
Simulation time 8467855605 ps
CPU time 8.02 seconds
Started May 12 12:57:35 PM PDT 24
Finished May 12 12:57:44 PM PDT 24
Peak memory 204400 kb
Host smart-e1455974-7c78-4985-8133-dfb1f5f48579
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2331347758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.2331347758
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.1987506475
Short name T1397
Test name
Test status
Simulation time 8379297733 ps
CPU time 8.47 seconds
Started May 12 12:57:21 PM PDT 24
Finished May 12 12:57:30 PM PDT 24
Peak memory 204368 kb
Host smart-973a4be4-8804-4c15-bd60-f93bb5a58ba8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1987506475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.1987506475
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.3396021348
Short name T848
Test name
Test status
Simulation time 8487923940 ps
CPU time 10.3 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204428 kb
Host smart-98c82ac6-b374-4289-8f04-7b26b37c10bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33960
21348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.3396021348
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.76038020
Short name T1435
Test name
Test status
Simulation time 8434543295 ps
CPU time 7.84 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:34 PM PDT 24
Peak memory 204408 kb
Host smart-bf34b1f0-c9b8-4968-9b5d-1553e931c8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76038
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.76038020
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.816296790
Short name T214
Test name
Test status
Simulation time 8830366147 ps
CPU time 12.45 seconds
Started May 12 12:57:31 PM PDT 24
Finished May 12 12:57:45 PM PDT 24
Peak memory 204580 kb
Host smart-6165f135-1aa8-4161-a8c8-29822176f056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81629
6790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.816296790
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_enable.4003203199
Short name T246
Test name
Test status
Simulation time 8377531626 ps
CPU time 9.28 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204532 kb
Host smart-3ae86097-46ce-4765-87c7-5a721d9af13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40032
03199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.4003203199
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2272628610
Short name T1300
Test name
Test status
Simulation time 62396859 ps
CPU time 1.72 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204544 kb
Host smart-13737bca-9b55-48ca-bfb0-e531f3386008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22726
28610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2272628610
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3479344111
Short name T1248
Test name
Test status
Simulation time 8402377081 ps
CPU time 7.83 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204444 kb
Host smart-3550712e-79c1-40bd-93f9-67bc31cfa1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3479344111
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2572074851
Short name T683
Test name
Test status
Simulation time 8437946855 ps
CPU time 9.52 seconds
Started May 12 12:57:53 PM PDT 24
Finished May 12 12:58:03 PM PDT 24
Peak memory 204460 kb
Host smart-cdd63fac-86dc-463d-82ca-5a0e82f22b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
74851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2572074851
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3382276886
Short name T155
Test name
Test status
Simulation time 8438126528 ps
CPU time 7.67 seconds
Started May 12 12:57:43 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 204488 kb
Host smart-8028d1e7-3d65-499a-94c8-5a78a261adf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33822
76886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3382276886
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3480933911
Short name T91
Test name
Test status
Simulation time 8415382381 ps
CPU time 9.79 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:36 PM PDT 24
Peak memory 204476 kb
Host smart-c32d401d-7b9e-435a-88d7-505db5890e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
33911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3480933911
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2894224472
Short name T24
Test name
Test status
Simulation time 8365453409 ps
CPU time 9.12 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204428 kb
Host smart-8d309c08-77ee-4a42-b687-b85af411839d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
24472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2894224472
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3323214720
Short name T988
Test name
Test status
Simulation time 8440963939 ps
CPU time 9.69 seconds
Started May 12 12:57:15 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204488 kb
Host smart-2b922ed6-4c84-463f-8ff8-4be14a029031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33232
14720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3323214720
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1545472200
Short name T553
Test name
Test status
Simulation time 8444833169 ps
CPU time 10.12 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:35 PM PDT 24
Peak memory 204104 kb
Host smart-1e2d6f79-2e55-4286-9eac-a93ebf3abe01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15454
72200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1545472200
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3345483092
Short name T702
Test name
Test status
Simulation time 8417220731 ps
CPU time 10.07 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204448 kb
Host smart-7baf381d-7044-406c-aa61-f283909e5968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
83092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3345483092
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2906959857
Short name T776
Test name
Test status
Simulation time 8503517159 ps
CPU time 9.04 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:44 PM PDT 24
Peak memory 204472 kb
Host smart-dc28aba2-bfc2-4871-8b87-6c7b84ee2fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29069
59857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2906959857
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2570500755
Short name T872
Test name
Test status
Simulation time 8370010039 ps
CPU time 7.9 seconds
Started May 12 12:57:52 PM PDT 24
Finished May 12 12:58:00 PM PDT 24
Peak memory 204388 kb
Host smart-60fc4e2a-3c83-4913-8497-92f70d3524f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705
00755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2570500755
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3560068288
Short name T1278
Test name
Test status
Simulation time 39574827 ps
CPU time 0.66 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204336 kb
Host smart-3e087d5a-196f-47e5-aedc-6e9b30d1a740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600
68288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3560068288
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3463922883
Short name T970
Test name
Test status
Simulation time 18624310509 ps
CPU time 34.71 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 204636 kb
Host smart-dea57296-7a2e-4196-9dc7-b48702b7453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34639
22883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3463922883
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2171274708
Short name T783
Test name
Test status
Simulation time 8428052800 ps
CPU time 9.76 seconds
Started May 12 12:57:32 PM PDT 24
Finished May 12 12:57:42 PM PDT 24
Peak memory 204472 kb
Host smart-bf1dcb8a-e9ec-4fcb-8288-cd5d33941d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21712
74708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2171274708
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.108944699
Short name T372
Test name
Test status
Simulation time 8430053325 ps
CPU time 8.4 seconds
Started May 12 12:57:41 PM PDT 24
Finished May 12 12:57:50 PM PDT 24
Peak memory 204440 kb
Host smart-8169f668-2dff-4f82-9a16-badc5ed657ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
4699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.108944699
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1986431323
Short name T337
Test name
Test status
Simulation time 8393355250 ps
CPU time 7.99 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204272 kb
Host smart-76dd597d-53bb-4683-a497-18e943783d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864
31323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1986431323
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1863117250
Short name T1146
Test name
Test status
Simulation time 8375057487 ps
CPU time 8.04 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204740 kb
Host smart-fe09e96c-3c87-46ed-84ba-86e865ce19c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18631
17250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1863117250
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2663991973
Short name T1150
Test name
Test status
Simulation time 8365496613 ps
CPU time 8.1 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 204416 kb
Host smart-ba8385a5-e2dd-4141-88b3-20fe7537dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
91973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2663991973
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3197531386
Short name T94
Test name
Test status
Simulation time 8498735047 ps
CPU time 7.73 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:57:36 PM PDT 24
Peak memory 204436 kb
Host smart-a6077ce1-5f18-4b8e-8b0e-f79665342055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
31386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3197531386
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3489674999
Short name T955
Test name
Test status
Simulation time 8413410309 ps
CPU time 8.19 seconds
Started May 12 12:57:31 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204416 kb
Host smart-f2d3463e-6abc-40da-b810-8c66aa8de8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34896
74999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3489674999
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1600920734
Short name T913
Test name
Test status
Simulation time 8385374748 ps
CPU time 10.42 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:45 PM PDT 24
Peak memory 204404 kb
Host smart-a8ba05db-2c34-41c5-862e-fb225d8df6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
20734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1600920734
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3665098930
Short name T1036
Test name
Test status
Simulation time 8467377476 ps
CPU time 8.55 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204452 kb
Host smart-e155c5aa-94b0-4772-8677-f5a34883175a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3665098930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3665098930
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.3097261390
Short name T455
Test name
Test status
Simulation time 8423681891 ps
CPU time 9.19 seconds
Started May 12 12:57:51 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 204332 kb
Host smart-1a29a40d-0a34-4dcc-bb14-761c0df3f80f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3097261390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.3097261390
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3726375090
Short name T1177
Test name
Test status
Simulation time 8449493608 ps
CPU time 9.07 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 204408 kb
Host smart-2eb50aca-9d79-4947-a06a-ad2b1209dd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263
75090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3726375090
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.256825498
Short name T1045
Test name
Test status
Simulation time 8378737773 ps
CPU time 7.74 seconds
Started May 12 12:57:44 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 204464 kb
Host smart-3b763534-1a41-4fdd-865f-a67b9930aa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25682
5498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.256825498
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.372872341
Short name T198
Test name
Test status
Simulation time 9277589881 ps
CPU time 14.09 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:46 PM PDT 24
Peak memory 204684 kb
Host smart-7558907a-1f96-4c2f-8502-c11b601d5e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
2341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.372872341
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_enable.778132211
Short name T524
Test name
Test status
Simulation time 8406738014 ps
CPU time 9.44 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 204436 kb
Host smart-bb896c20-94bd-4a67-9b5c-a3a19c3ad88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77813
2211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.778132211
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.586688375
Short name T816
Test name
Test status
Simulation time 78918747 ps
CPU time 1.69 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:27 PM PDT 24
Peak memory 204512 kb
Host smart-eedbe7e8-e749-436f-a44d-4cd96562a34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58668
8375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.586688375
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2284484704
Short name T709
Test name
Test status
Simulation time 8433916602 ps
CPU time 7.7 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 204424 kb
Host smart-5035cf4e-f683-4022-824e-a4b23ea85613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22844
84704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2284484704
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3774435041
Short name T6
Test name
Test status
Simulation time 8363370564 ps
CPU time 7.92 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:43 PM PDT 24
Peak memory 204420 kb
Host smart-7e03b056-9635-4326-85d4-35a42365c8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744
35041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3774435041
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3931216071
Short name T147
Test name
Test status
Simulation time 8413980889 ps
CPU time 7.79 seconds
Started May 12 12:57:38 PM PDT 24
Finished May 12 12:57:46 PM PDT 24
Peak memory 204344 kb
Host smart-a84cf502-838d-4bd2-a944-f97b259278dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39312
16071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3931216071
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.130934726
Short name T768
Test name
Test status
Simulation time 8429288885 ps
CPU time 10.08 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 204440 kb
Host smart-b954d23f-6407-43c7-b6a7-1bb640d6dffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13093
4726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.130934726
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.783589152
Short name T583
Test name
Test status
Simulation time 8373214706 ps
CPU time 7.35 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204444 kb
Host smart-44e1e682-e4a1-4f74-9063-1c0c62e69b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78358
9152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.783589152
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.149531919
Short name T106
Test name
Test status
Simulation time 8459045129 ps
CPU time 8.15 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204352 kb
Host smart-a0d2e084-5945-41ea-aeba-43a2d4c40c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14953
1919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.149531919
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3109187179
Short name T591
Test name
Test status
Simulation time 8416435279 ps
CPU time 8.54 seconds
Started May 12 12:57:40 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204428 kb
Host smart-b256c7d3-231e-4c39-81d8-9ec9711d5b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31091
87179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3109187179
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3891549876
Short name T1161
Test name
Test status
Simulation time 8383715642 ps
CPU time 7.74 seconds
Started May 12 12:57:24 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 204312 kb
Host smart-1d93dd21-e303-40f8-9286-c7845ee569e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38915
49876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3891549876
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.18146993
Short name T208
Test name
Test status
Simulation time 8392040570 ps
CPU time 10.25 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204484 kb
Host smart-d5755438-797e-4d36-bdfe-5610ea40c47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18146
993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.18146993
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3838787500
Short name T723
Test name
Test status
Simulation time 8382518368 ps
CPU time 9.75 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 204344 kb
Host smart-0451111f-2c05-4300-9737-69495d670368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38387
87500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3838787500
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1503718868
Short name T45
Test name
Test status
Simulation time 30097913 ps
CPU time 0.64 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:48 PM PDT 24
Peak memory 204320 kb
Host smart-843c9bb1-a321-47aa-b5b5-bc1408edbea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15037
18868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1503718868
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3675066936
Short name T958
Test name
Test status
Simulation time 26429223385 ps
CPU time 53.12 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:58:28 PM PDT 24
Peak memory 204588 kb
Host smart-90e15c24-3115-4726-981d-40d034e43f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36750
66936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3675066936
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1302134768
Short name T697
Test name
Test status
Simulation time 8405725881 ps
CPU time 8.89 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:57:59 PM PDT 24
Peak memory 204416 kb
Host smart-b015e7d5-624b-4f2c-8134-9b784a616752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
34768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1302134768
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3348226107
Short name T957
Test name
Test status
Simulation time 8401594129 ps
CPU time 8.19 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204324 kb
Host smart-a4b83a7c-ec11-4353-807c-6b6c5556b91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
26107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3348226107
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2956318810
Short name T985
Test name
Test status
Simulation time 8369895502 ps
CPU time 8.65 seconds
Started May 12 12:57:39 PM PDT 24
Finished May 12 12:57:48 PM PDT 24
Peak memory 204436 kb
Host smart-f5640a0c-c226-494a-b100-ffd4e57b061c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29563
18810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2956318810
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.611861488
Short name T181
Test name
Test status
Simulation time 8379221376 ps
CPU time 9.01 seconds
Started May 12 12:57:39 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204428 kb
Host smart-39318023-8954-47ba-9bee-abccbfe7f412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61186
1488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.611861488
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2512073064
Short name T940
Test name
Test status
Simulation time 8376880668 ps
CPU time 9.94 seconds
Started May 12 12:57:43 PM PDT 24
Finished May 12 12:57:53 PM PDT 24
Peak memory 204416 kb
Host smart-85a0aa61-a1ae-41e1-af40-88aab2b76d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25120
73064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2512073064
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1352659118
Short name T1159
Test name
Test status
Simulation time 8454385593 ps
CPU time 8.32 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204392 kb
Host smart-4dffea59-e98b-432c-832c-ec65c1be5485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
59118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1352659118
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.338290592
Short name T1011
Test name
Test status
Simulation time 8415187040 ps
CPU time 8.14 seconds
Started May 12 12:57:19 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 204412 kb
Host smart-198285f8-5c15-4b6e-85f6-06b86112c038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33829
0592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.338290592
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.681155042
Short name T1123
Test name
Test status
Simulation time 8374539968 ps
CPU time 10.06 seconds
Started May 12 12:57:32 PM PDT 24
Finished May 12 12:57:43 PM PDT 24
Peak memory 204444 kb
Host smart-f84286da-9fa0-4dab-863f-d1274d06a892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68115
5042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.681155042
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.791543059
Short name T1135
Test name
Test status
Simulation time 8506043871 ps
CPU time 7.89 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204556 kb
Host smart-ac6f0bf7-ceb4-4438-a0c4-161d48bcce63
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=791543059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.791543059
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.2377779906
Short name T1128
Test name
Test status
Simulation time 8382586691 ps
CPU time 7.48 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 204416 kb
Host smart-315539c6-1012-4382-bae5-927ced5dda7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2377779906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.2377779906
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1648098024
Short name T1099
Test name
Test status
Simulation time 8440935201 ps
CPU time 7.66 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 204408 kb
Host smart-13ab3544-3b48-4856-b716-9a95a05c34a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16480
98024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1648098024
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1671864844
Short name T793
Test name
Test status
Simulation time 8378545052 ps
CPU time 8.03 seconds
Started May 12 12:57:44 PM PDT 24
Finished May 12 12:57:53 PM PDT 24
Peak memory 204436 kb
Host smart-3701a244-2929-49db-af10-edef2100c796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718
64844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1671864844
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3416739568
Short name T571
Test name
Test status
Simulation time 8623818936 ps
CPU time 12.07 seconds
Started May 12 12:57:42 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 204716 kb
Host smart-6d9e8472-4436-4652-af2f-5e5b485947bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
39568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3416739568
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_enable.4153139212
Short name T1273
Test name
Test status
Simulation time 8374018727 ps
CPU time 8.57 seconds
Started May 12 12:57:32 PM PDT 24
Finished May 12 12:57:41 PM PDT 24
Peak memory 204512 kb
Host smart-10743ae0-d9eb-4d56-a439-a01e95283923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
39212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4153139212
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1214802648
Short name T635
Test name
Test status
Simulation time 241724424 ps
CPU time 1.88 seconds
Started May 12 12:57:30 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 204556 kb
Host smart-8bba7582-dbd7-4b76-bdcd-6816f5b237b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148
02648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1214802648
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3737041072
Short name T53
Test name
Test status
Simulation time 8403096908 ps
CPU time 8.32 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 204396 kb
Host smart-09e2cb66-9f6a-4a2f-8385-db538c1632d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37370
41072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3737041072
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2582053628
Short name T1333
Test name
Test status
Simulation time 8368804593 ps
CPU time 8.93 seconds
Started May 12 12:57:37 PM PDT 24
Finished May 12 12:57:46 PM PDT 24
Peak memory 204420 kb
Host smart-87ba2bc2-6fa7-444d-8f4f-f7bbb0e25b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
53628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2582053628
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.437274982
Short name T1362
Test name
Test status
Simulation time 8452069068 ps
CPU time 7.93 seconds
Started May 12 12:57:39 PM PDT 24
Finished May 12 12:57:47 PM PDT 24
Peak memory 204440 kb
Host smart-968fe764-21e7-4a2c-a743-24d3ac0c7c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43727
4982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.437274982
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3383392198
Short name T690
Test name
Test status
Simulation time 8431866849 ps
CPU time 8.84 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204388 kb
Host smart-1dfa699e-a12b-4f5c-8d29-7f224bd9e37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33833
92198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3383392198
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1471716423
Short name T916
Test name
Test status
Simulation time 8373693352 ps
CPU time 8 seconds
Started May 12 12:57:35 PM PDT 24
Finished May 12 12:57:44 PM PDT 24
Peak memory 204428 kb
Host smart-96e1d011-9bd9-48f3-a3df-88cd6fe6fdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14717
16423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1471716423
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3486189967
Short name T115
Test name
Test status
Simulation time 8398794197 ps
CPU time 8.23 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 204424 kb
Host smart-87ed090f-e559-4fcb-819e-b867261d7629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34861
89967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3486189967
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2242902913
Short name T710
Test name
Test status
Simulation time 8422776429 ps
CPU time 8.93 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 204424 kb
Host smart-861663a6-9be9-42ea-bb5e-fc4e95d038dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
02913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2242902913
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1585196298
Short name T529
Test name
Test status
Simulation time 8391660920 ps
CPU time 8.18 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204412 kb
Host smart-3298ab66-2caa-4743-a086-46c69b6e919b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15851
96298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1585196298
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.248469125
Short name T984
Test name
Test status
Simulation time 8396507242 ps
CPU time 8.54 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:57:59 PM PDT 24
Peak memory 204392 kb
Host smart-b8119862-b2fe-4a21-a78d-7a1a09d0417f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24846
9125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.248469125
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2614244370
Short name T761
Test name
Test status
Simulation time 8384046684 ps
CPU time 7.88 seconds
Started May 12 12:57:32 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204476 kb
Host smart-8a493d12-cd04-47ac-9309-212b39d43fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26142
44370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2614244370
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1926350223
Short name T1013
Test name
Test status
Simulation time 67449328 ps
CPU time 0.67 seconds
Started May 12 12:57:43 PM PDT 24
Finished May 12 12:57:44 PM PDT 24
Peak memory 204340 kb
Host smart-14da33aa-9def-40f7-a491-a0807892b860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263
50223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1926350223
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.854878414
Short name T835
Test name
Test status
Simulation time 29762257492 ps
CPU time 55.74 seconds
Started May 12 12:57:26 PM PDT 24
Finished May 12 12:58:25 PM PDT 24
Peak memory 204776 kb
Host smart-c6804068-3b34-437b-9406-dd291415beb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85487
8414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.854878414
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4118326316
Short name T1339
Test name
Test status
Simulation time 8391192511 ps
CPU time 7.72 seconds
Started May 12 12:57:32 PM PDT 24
Finished May 12 12:57:45 PM PDT 24
Peak memory 204472 kb
Host smart-137cd276-8663-4520-963c-f7bcbf7d0a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41183
26316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4118326316
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3047909784
Short name T1017
Test name
Test status
Simulation time 8445498810 ps
CPU time 8.3 seconds
Started May 12 12:57:47 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 204384 kb
Host smart-b6ee8279-d15d-4537-9e87-8d23b1bea505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
09784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3047909784
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2274546641
Short name T1160
Test name
Test status
Simulation time 8399749018 ps
CPU time 8.94 seconds
Started May 12 12:57:33 PM PDT 24
Finished May 12 12:57:42 PM PDT 24
Peak memory 204436 kb
Host smart-7edc41f5-fc73-4137-a76f-5c5514574875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
46641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2274546641
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.167641205
Short name T1355
Test name
Test status
Simulation time 8374410304 ps
CPU time 8.31 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:43 PM PDT 24
Peak memory 204340 kb
Host smart-be32cd6d-301f-4c40-801b-c366ed1cb682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16764
1205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.167641205
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.4148519373
Short name T1182
Test name
Test status
Simulation time 8374689700 ps
CPU time 7.99 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204360 kb
Host smart-2195d91a-a9e4-495e-a706-5d4077eb4ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41485
19373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.4148519373
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.822090747
Short name T26
Test name
Test status
Simulation time 8446904952 ps
CPU time 9.77 seconds
Started May 12 12:57:25 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204456 kb
Host smart-4ed773fd-7b0d-42aa-9306-746adef729fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82209
0747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.822090747
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.4050238798
Short name T704
Test name
Test status
Simulation time 8401651288 ps
CPU time 7.8 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 204380 kb
Host smart-4b732c5b-4639-41a3-86a8-67661448e124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40502
38798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.4050238798
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1378281289
Short name T738
Test name
Test status
Simulation time 8404566250 ps
CPU time 7.88 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204380 kb
Host smart-7bc0ffac-2aaf-4ce7-a36c-93e9e9bcde8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13782
81289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1378281289
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.1788656787
Short name T716
Test name
Test status
Simulation time 8467299215 ps
CPU time 8.39 seconds
Started May 12 12:57:35 PM PDT 24
Finished May 12 12:57:44 PM PDT 24
Peak memory 204324 kb
Host smart-efe9f9e5-60b5-443d-8ab5-1814fa7a209e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1788656787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.1788656787
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.609440130
Short name T86
Test name
Test status
Simulation time 8387627711 ps
CPU time 7.67 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:58:05 PM PDT 24
Peak memory 204324 kb
Host smart-a7231cca-1d1a-491f-aa72-c0e9e02b4929
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=609440130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.609440130
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2615332442
Short name T386
Test name
Test status
Simulation time 8467276002 ps
CPU time 7.57 seconds
Started May 12 12:57:41 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204428 kb
Host smart-4104b1ba-b4a6-45f0-8852-44ef0d9a0268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26153
32442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2615332442
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3082451576
Short name T1170
Test name
Test status
Simulation time 8387820234 ps
CPU time 8.71 seconds
Started May 12 12:57:43 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 204512 kb
Host smart-070d33f2-0329-413c-954d-bbe8720c7483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
51576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3082451576
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.4283514162
Short name T209
Test name
Test status
Simulation time 8912302744 ps
CPU time 12.07 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 204716 kb
Host smart-63d92bf0-f0d1-4dc5-b27d-d3280cd71cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42835
14162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.4283514162
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_enable.3420348619
Short name T1006
Test name
Test status
Simulation time 8376921967 ps
CPU time 7.91 seconds
Started May 12 12:57:31 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204364 kb
Host smart-b278d1f0-cbe0-4634-8529-48caa42beafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34203
48619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3420348619
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1955136672
Short name T479
Test name
Test status
Simulation time 59825680 ps
CPU time 1.44 seconds
Started May 12 12:57:47 PM PDT 24
Finished May 12 12:57:50 PM PDT 24
Peak memory 204580 kb
Host smart-22207b26-57fa-4e58-a1fe-bf2d66742b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
36672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1955136672
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3581642198
Short name T1114
Test name
Test status
Simulation time 8397788326 ps
CPU time 8.71 seconds
Started May 12 12:57:58 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 204384 kb
Host smart-28ec3150-aea5-42c4-8385-e0ac12b5d48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35816
42198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3581642198
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.154442654
Short name T1284
Test name
Test status
Simulation time 8369990582 ps
CPU time 7.62 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 204460 kb
Host smart-1e5f0c76-f93a-4fd8-8dc4-1ed8513a34b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
2654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.154442654
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1533575774
Short name T299
Test name
Test status
Simulation time 8414370938 ps
CPU time 7.65 seconds
Started May 12 12:57:33 PM PDT 24
Finished May 12 12:57:41 PM PDT 24
Peak memory 204464 kb
Host smart-0ee4e007-2039-4a13-91b0-d64ba7bd78f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335
75774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1533575774
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1729023222
Short name T350
Test name
Test status
Simulation time 8480251036 ps
CPU time 7.52 seconds
Started May 12 12:57:37 PM PDT 24
Finished May 12 12:57:45 PM PDT 24
Peak memory 204476 kb
Host smart-582572ba-c609-42d8-bcd5-66dfa534ed96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17290
23222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1729023222
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3510702604
Short name T1020
Test name
Test status
Simulation time 8422439064 ps
CPU time 7.8 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 204432 kb
Host smart-7c1ef7a1-026e-4669-a86c-fcd22b9f28c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35107
02604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3510702604
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4294343996
Short name T102
Test name
Test status
Simulation time 8450124061 ps
CPU time 7.9 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 204456 kb
Host smart-92ac6aee-23dd-4869-aea3-1005e4d73fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943
43996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4294343996
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.848284273
Short name T405
Test name
Test status
Simulation time 8425554542 ps
CPU time 10.14 seconds
Started May 12 12:57:47 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 204384 kb
Host smart-ef261718-2002-4138-ba8a-59eec16f09aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84828
4273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.848284273
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2040178575
Short name T356
Test name
Test status
Simulation time 8386417473 ps
CPU time 9.13 seconds
Started May 12 12:57:31 PM PDT 24
Finished May 12 12:57:41 PM PDT 24
Peak memory 204496 kb
Host smart-99e899a2-c5b0-4e3a-8672-53a7cb219a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401
78575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2040178575
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2922254236
Short name T25
Test name
Test status
Simulation time 8440558903 ps
CPU time 8.45 seconds
Started May 12 12:57:34 PM PDT 24
Finished May 12 12:57:43 PM PDT 24
Peak memory 204416 kb
Host smart-77e74869-4a55-4e3f-986f-60bd4743ef30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
54236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2922254236
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.14855016
Short name T374
Test name
Test status
Simulation time 8375200789 ps
CPU time 9.4 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:58:00 PM PDT 24
Peak memory 204328 kb
Host smart-d9ebe1a0-e130-4552-a771-7cb6d9974919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14855
016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.14855016
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3321593800
Short name T992
Test name
Test status
Simulation time 55819083 ps
CPU time 0.7 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:57:51 PM PDT 24
Peak memory 204304 kb
Host smart-c5a877e3-c591-4475-a5f1-60dc1ad2b7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33215
93800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3321593800
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.787041994
Short name T301
Test name
Test status
Simulation time 17035992442 ps
CPU time 29.79 seconds
Started May 12 12:57:38 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 204620 kb
Host smart-ac80e335-1e4f-4feb-a6f1-aeac5de72663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78704
1994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.787041994
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.284100404
Short name T1056
Test name
Test status
Simulation time 8376366459 ps
CPU time 7.51 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:37 PM PDT 24
Peak memory 204464 kb
Host smart-ae56599d-918a-4ab0-889a-aaba12b85ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
0404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.284100404
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1138549870
Short name T416
Test name
Test status
Simulation time 8390608375 ps
CPU time 9.78 seconds
Started May 12 12:57:27 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204420 kb
Host smart-5ce90b09-898d-4b1e-94ce-bde362bcceaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
49870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1138549870
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1563834770
Short name T1171
Test name
Test status
Simulation time 8402773270 ps
CPU time 8.01 seconds
Started May 12 12:57:28 PM PDT 24
Finished May 12 12:57:38 PM PDT 24
Peak memory 204388 kb
Host smart-e7eebfab-85e1-4007-93af-04266cd4ae88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
34770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1563834770
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1496335355
Short name T173
Test name
Test status
Simulation time 8379782429 ps
CPU time 9.28 seconds
Started May 12 12:57:58 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 204392 kb
Host smart-7d182952-2b0c-42f8-a21c-1e7b08988959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
35355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1496335355
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1901971286
Short name T703
Test name
Test status
Simulation time 8374016983 ps
CPU time 8.73 seconds
Started May 12 12:57:29 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 204344 kb
Host smart-e88991c8-6848-47b5-9ee9-80031abdd8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
71286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1901971286
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1529696327
Short name T928
Test name
Test status
Simulation time 8464523267 ps
CPU time 7.73 seconds
Started May 12 12:57:41 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 204468 kb
Host smart-8b684c8b-a218-4620-bc60-9df85f0aa104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
96327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1529696327
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4054372433
Short name T1215
Test name
Test status
Simulation time 8389499805 ps
CPU time 8.29 seconds
Started May 12 12:57:47 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 204436 kb
Host smart-cd46229e-b522-4a9c-af11-886465f4d2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40543
72433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4054372433
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2058420501
Short name T715
Test name
Test status
Simulation time 8414822363 ps
CPU time 9.77 seconds
Started May 12 12:57:31 PM PDT 24
Finished May 12 12:57:42 PM PDT 24
Peak memory 204376 kb
Host smart-91574842-da9e-4475-85ae-fa12b36da6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584
20501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2058420501
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.3220981367
Short name T542
Test name
Test status
Simulation time 8466402223 ps
CPU time 8.02 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 204452 kb
Host smart-4b50e57d-70d9-42e2-b728-56f4563c7bd3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3220981367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.3220981367
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.3760517662
Short name T995
Test name
Test status
Simulation time 8382681244 ps
CPU time 8.06 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204480 kb
Host smart-add410a0-f901-455d-a034-c1a65294bb9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3760517662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.3760517662
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2681492581
Short name T1221
Test name
Test status
Simulation time 8413192239 ps
CPU time 8.13 seconds
Started May 12 12:54:44 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204368 kb
Host smart-5226b0b4-fd9b-4807-8781-0d25de7b61af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814
92581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2681492581
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2605794634
Short name T682
Test name
Test status
Simulation time 8386728871 ps
CPU time 9.28 seconds
Started May 12 12:54:52 PM PDT 24
Finished May 12 12:55:02 PM PDT 24
Peak memory 204364 kb
Host smart-df895b40-06ec-4b14-b91c-5a94fee43b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26057
94634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2605794634
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2355747638
Short name T1012
Test name
Test status
Simulation time 8798481831 ps
CPU time 12.52 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204680 kb
Host smart-0524ad9b-bf07-47ed-ac3b-53e951e12eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
47638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2355747638
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_enable.253331884
Short name T727
Test name
Test status
Simulation time 8372216477 ps
CPU time 7.58 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204760 kb
Host smart-1e98feac-b2ae-4b0e-85fb-236ea15a108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25333
1884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.253331884
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2853117621
Short name T1337
Test name
Test status
Simulation time 74803818 ps
CPU time 1.55 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204480 kb
Host smart-9d7abba3-5a78-4134-bdf2-ed4be57da63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28531
17621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2853117621
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2498308359
Short name T1304
Test name
Test status
Simulation time 8370068575 ps
CPU time 9.24 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204384 kb
Host smart-966dfb55-81ee-46a1-820c-091e8d10f769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24983
08359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2498308359
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3724831980
Short name T1371
Test name
Test status
Simulation time 8429454376 ps
CPU time 7.74 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204384 kb
Host smart-f27b914c-f9db-41f3-95ae-3022ad0eb919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
31980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3724831980
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2178120113
Short name T1001
Test name
Test status
Simulation time 8413723530 ps
CPU time 7.87 seconds
Started May 12 12:54:42 PM PDT 24
Finished May 12 12:54:51 PM PDT 24
Peak memory 204352 kb
Host smart-d185c5d9-7bc2-4bb8-bffe-9d537277ec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21781
20113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2178120113
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3067791228
Short name T662
Test name
Test status
Simulation time 8434514550 ps
CPU time 7.93 seconds
Started May 12 12:54:42 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204400 kb
Host smart-41cd171e-3587-4330-878b-07d24d4f22fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30677
91228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3067791228
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2880244229
Short name T118
Test name
Test status
Simulation time 8433176332 ps
CPU time 8.25 seconds
Started May 12 12:54:45 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 204460 kb
Host smart-bc643eee-4da7-4730-88ed-ea9bf75e1fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802
44229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2880244229
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1776548870
Short name T1133
Test name
Test status
Simulation time 8472719657 ps
CPU time 8.53 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204444 kb
Host smart-4381953d-c658-49e2-86f1-66688d67cac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17765
48870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1776548870
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1286057946
Short name T300
Test name
Test status
Simulation time 8418113441 ps
CPU time 8.49 seconds
Started May 12 12:54:39 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 204440 kb
Host smart-5f618a24-efbb-4a35-ae92-4b8601042534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12860
57946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1286057946
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.832849891
Short name T882
Test name
Test status
Simulation time 8472808286 ps
CPU time 7.95 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204440 kb
Host smart-a89a5999-db54-478a-b317-d4d14e9b5ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83284
9891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.832849891
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3697453874
Short name T27
Test name
Test status
Simulation time 8369839611 ps
CPU time 7.98 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 204420 kb
Host smart-615a7b00-3dcd-49b8-96cf-68d9f3661a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36974
53874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3697453874
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.191783079
Short name T1334
Test name
Test status
Simulation time 39949975 ps
CPU time 0.66 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 204388 kb
Host smart-6612f5a5-33cd-4dac-90e5-4180b66d2037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19178
3079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.191783079
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3265132435
Short name T698
Test name
Test status
Simulation time 15382746095 ps
CPU time 25.91 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204656 kb
Host smart-3d13fbea-ee5c-4b11-9e4c-a470767059cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651
32435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3265132435
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1448256371
Short name T737
Test name
Test status
Simulation time 8394530068 ps
CPU time 9.79 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 204444 kb
Host smart-ef83a726-3e4e-4ce3-a54a-c1f9d938f808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14482
56371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1448256371
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3812210788
Short name T656
Test name
Test status
Simulation time 8429000790 ps
CPU time 8.3 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204372 kb
Host smart-90e96b08-4245-48a3-a0ff-46f69b4cf530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38122
10788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3812210788
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.4087576340
Short name T348
Test name
Test status
Simulation time 8430904321 ps
CPU time 9.05 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204372 kb
Host smart-c698c2cc-db30-49a2-8d52-13d28c1bdab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40875
76340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.4087576340
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1869599477
Short name T178
Test name
Test status
Simulation time 8394212522 ps
CPU time 7.96 seconds
Started May 12 12:54:45 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 204512 kb
Host smart-11f4d374-5ddf-41dc-b892-da0420e81752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
99477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1869599477
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.418456228
Short name T1253
Test name
Test status
Simulation time 8375298945 ps
CPU time 9.22 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204372 kb
Host smart-d630295b-d84f-400f-b564-f2e1386c132c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
6228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.418456228
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2684283388
Short name T1149
Test name
Test status
Simulation time 8437751314 ps
CPU time 8.92 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204364 kb
Host smart-36089cbf-f1ab-4a1a-a013-5dbaebc76d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26842
83388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2684283388
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3457399416
Short name T769
Test name
Test status
Simulation time 8395172007 ps
CPU time 7.61 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204368 kb
Host smart-98829b3e-f362-47f0-b4cc-10f9b6dcd7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34573
99416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3457399416
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2366164606
Short name T546
Test name
Test status
Simulation time 8415669604 ps
CPU time 7.6 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 204456 kb
Host smart-e8e32d70-717d-44b7-83a8-a60bd373a861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23661
64606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2366164606
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.712392162
Short name T775
Test name
Test status
Simulation time 8467981488 ps
CPU time 9.84 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 204476 kb
Host smart-7999a87f-1ede-4272-bd13-536fa29b1634
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=712392162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.712392162
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.916924285
Short name T705
Test name
Test status
Simulation time 8392119477 ps
CPU time 7.85 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204340 kb
Host smart-c6c1eea2-55a6-45ec-a740-ce87b232f434
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=916924285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.916924285
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.549163918
Short name T508
Test name
Test status
Simulation time 8400994361 ps
CPU time 8.33 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204448 kb
Host smart-dc376eee-c2d7-4725-b3ff-9596118761f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54916
3918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.549163918
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1950361841
Short name T625
Test name
Test status
Simulation time 8383918416 ps
CPU time 9.97 seconds
Started May 12 12:54:52 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204756 kb
Host smart-595df884-8fdc-4484-a68b-defe7d99356d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
61841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1950361841
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2941737075
Short name T1379
Test name
Test status
Simulation time 9071618387 ps
CPU time 12.12 seconds
Started May 12 12:54:43 PM PDT 24
Finished May 12 12:54:56 PM PDT 24
Peak memory 204704 kb
Host smart-18a44f7b-4929-4cb8-9e7a-215736c9506d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
37075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2941737075
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_enable.3754303128
Short name T908
Test name
Test status
Simulation time 8435912054 ps
CPU time 8.01 seconds
Started May 12 12:54:52 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204432 kb
Host smart-b2cbfe20-203c-44a1-b90f-b9ac971626b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
03128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3754303128
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.962529705
Short name T588
Test name
Test status
Simulation time 186469897 ps
CPU time 1.94 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 204516 kb
Host smart-d8e33d5c-4427-4753-b1cf-84694dd97ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96252
9705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.962529705
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2799511090
Short name T1137
Test name
Test status
Simulation time 8435215998 ps
CPU time 7.77 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204476 kb
Host smart-73f822dc-565d-4c61-9ca2-8489d5d91f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27995
11090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2799511090
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1529553549
Short name T1184
Test name
Test status
Simulation time 8377572290 ps
CPU time 8.25 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204376 kb
Host smart-4803f71a-ad9d-48e1-a291-9b7b08c8f2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15295
53549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1529553549
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2836188121
Short name T539
Test name
Test status
Simulation time 8468589399 ps
CPU time 9.23 seconds
Started May 12 12:54:45 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 204476 kb
Host smart-0db6917c-d16e-48eb-99ea-32e7b14db85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
88121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2836188121
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.4182130400
Short name T58
Test name
Test status
Simulation time 8415902353 ps
CPU time 7.62 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204440 kb
Host smart-93241616-13a1-4d3a-a07a-2b11a85d0578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
30400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.4182130400
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.244177318
Short name T438
Test name
Test status
Simulation time 8379064978 ps
CPU time 8.05 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:57 PM PDT 24
Peak memory 204432 kb
Host smart-fd746d81-5907-4c09-85d5-f226c71e4fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24417
7318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.244177318
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2758087854
Short name T120
Test name
Test status
Simulation time 8457548763 ps
CPU time 7.71 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 204452 kb
Host smart-3cb32559-e452-44a0-ab0c-3f7fc68a853f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
87854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2758087854
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1177120659
Short name T956
Test name
Test status
Simulation time 8403589166 ps
CPU time 8.26 seconds
Started May 12 12:54:51 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204752 kb
Host smart-1f372201-196c-490d-8f01-6f6a776d8087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11771
20659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1177120659
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.830175767
Short name T827
Test name
Test status
Simulation time 8391829236 ps
CPU time 7.68 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204400 kb
Host smart-c0ab204f-c544-4ed1-ab7a-38c2c3539cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83017
5767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.830175767
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.926040609
Short name T219
Test name
Test status
Simulation time 8409444855 ps
CPU time 7.51 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204380 kb
Host smart-6dc5b4eb-b63c-43a6-b21c-e680bd14517e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92604
0609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.926040609
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2061758979
Short name T1407
Test name
Test status
Simulation time 8457671828 ps
CPU time 7.62 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204264 kb
Host smart-0d2e3c8a-31ad-4f93-95c2-a580d68e04f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
58979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2061758979
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3029102935
Short name T734
Test name
Test status
Simulation time 122409819 ps
CPU time 0.75 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 204348 kb
Host smart-f402246e-3d0f-4675-a7bb-71e27f6c490e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
02935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3029102935
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1991213195
Short name T602
Test name
Test status
Simulation time 19885326140 ps
CPU time 35.22 seconds
Started May 12 12:54:48 PM PDT 24
Finished May 12 12:55:25 PM PDT 24
Peak memory 204656 kb
Host smart-7f8a6d0f-98d6-4b9c-8519-440bd1a9b119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19912
13195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1991213195
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2984112587
Short name T464
Test name
Test status
Simulation time 8410429597 ps
CPU time 9.52 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 204468 kb
Host smart-2bb51497-8290-4ed6-98f6-06bdf5a96ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29841
12587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2984112587
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2375902590
Short name T1281
Test name
Test status
Simulation time 8448903875 ps
CPU time 7.97 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204488 kb
Host smart-86502748-082b-4bff-a209-80705e8aea08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
02590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2375902590
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2568780657
Short name T394
Test name
Test status
Simulation time 8370488763 ps
CPU time 8.93 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204504 kb
Host smart-33654db5-4f40-4aa4-8caf-a18519bf5abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25687
80657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2568780657
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3117562089
Short name T1144
Test name
Test status
Simulation time 8371560392 ps
CPU time 8.07 seconds
Started May 12 12:54:51 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204376 kb
Host smart-a2e0db15-a3dd-4120-8a93-58a52c739be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175
62089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3117562089
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.935303820
Short name T462
Test name
Test status
Simulation time 8367245210 ps
CPU time 7.83 seconds
Started May 12 12:54:49 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 204236 kb
Host smart-8c416f42-8f4a-49ff-a71a-11d8885503ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93530
3820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.935303820
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.394157162
Short name T564
Test name
Test status
Simulation time 8478470898 ps
CPU time 8.33 seconds
Started May 12 12:54:46 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 204392 kb
Host smart-341ba498-1e72-462b-b00c-bd24eb961f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39415
7162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.394157162
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2090965810
Short name T534
Test name
Test status
Simulation time 8408731143 ps
CPU time 8.24 seconds
Started May 12 12:54:47 PM PDT 24
Finished May 12 12:54:56 PM PDT 24
Peak memory 204420 kb
Host smart-70f40e1e-76b2-48d2-a41c-07ab314590c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909
65810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2090965810
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2093034873
Short name T688
Test name
Test status
Simulation time 8393944147 ps
CPU time 7.91 seconds
Started May 12 12:54:55 PM PDT 24
Finished May 12 12:55:04 PM PDT 24
Peak memory 204376 kb
Host smart-6cac7696-284c-4009-ac4e-22935ff8489f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20930
34873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2093034873
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.5709570
Short name T1116
Test name
Test status
Simulation time 8458038970 ps
CPU time 8.43 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204512 kb
Host smart-021b97e4-d6eb-4b3e-b799-098cef10622d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=5709570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.5709570
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.3137161760
Short name T1179
Test name
Test status
Simulation time 8380577331 ps
CPU time 9.93 seconds
Started May 12 12:54:55 PM PDT 24
Finished May 12 12:55:05 PM PDT 24
Peak memory 204388 kb
Host smart-dd387f87-069e-493a-a756-fe977da0787c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3137161760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.3137161760
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.37512532
Short name T1342
Test name
Test status
Simulation time 8458045043 ps
CPU time 8.19 seconds
Started May 12 12:54:56 PM PDT 24
Finished May 12 12:55:04 PM PDT 24
Peak memory 203940 kb
Host smart-ef9df8a4-e494-41cd-bbf9-181183c4114c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512
532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.37512532
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3147808548
Short name T1256
Test name
Test status
Simulation time 8376571821 ps
CPU time 8.31 seconds
Started May 12 12:54:56 PM PDT 24
Finished May 12 12:55:04 PM PDT 24
Peak memory 204420 kb
Host smart-90765b2b-5709-4080-a6e9-36df6fc2e9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31478
08548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3147808548
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2746599356
Short name T1249
Test name
Test status
Simulation time 9055599590 ps
CPU time 12.42 seconds
Started May 12 12:54:58 PM PDT 24
Finished May 12 12:55:11 PM PDT 24
Peak memory 204736 kb
Host smart-8b62a889-71b1-44f0-b8c9-7bd3afc402a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
99356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2746599356
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_enable.2898545295
Short name T901
Test name
Test status
Simulation time 8371635111 ps
CPU time 8.66 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204500 kb
Host smart-cb76aa9d-4dd0-4e0a-8ec8-cb8539eb7bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28985
45295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2898545295
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1366344620
Short name T1110
Test name
Test status
Simulation time 252058330 ps
CPU time 1.96 seconds
Started May 12 12:54:58 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204480 kb
Host smart-944b0ca3-56b2-45b1-a772-4558209a9004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663
44620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1366344620
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2943881155
Short name T138
Test name
Test status
Simulation time 8395118483 ps
CPU time 8.56 seconds
Started May 12 12:54:54 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204476 kb
Host smart-3db8f1ec-7711-4032-995f-1ccb21ed9e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
81155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2943881155
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2851912583
Short name T1303
Test name
Test status
Simulation time 8395954061 ps
CPU time 8.95 seconds
Started May 12 12:54:56 PM PDT 24
Finished May 12 12:55:05 PM PDT 24
Peak memory 204012 kb
Host smart-c5c41f39-cb8b-49dd-b43f-b321abfd8e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28519
12583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2851912583
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3010313658
Short name T272
Test name
Test status
Simulation time 8420922992 ps
CPU time 8.04 seconds
Started May 12 12:54:53 PM PDT 24
Finished May 12 12:55:02 PM PDT 24
Peak memory 204488 kb
Host smart-be162b35-77a6-40f3-921c-3b962a76b807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30103
13658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3010313658
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.599458837
Short name T443
Test name
Test status
Simulation time 8473633792 ps
CPU time 7.96 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204428 kb
Host smart-b6d5c242-5155-4d34-947e-48584b8ebd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59945
8837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.599458837
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4016438813
Short name T393
Test name
Test status
Simulation time 8391136292 ps
CPU time 7.72 seconds
Started May 12 12:54:55 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204428 kb
Host smart-37d371be-7cad-48b1-8883-dd897610d617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40164
38813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4016438813
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2834656659
Short name T706
Test name
Test status
Simulation time 8426016849 ps
CPU time 8.15 seconds
Started May 12 12:54:54 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204744 kb
Host smart-23d245b0-5e48-4fea-8a0c-0bb9986870b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28346
56659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2834656659
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3022503855
Short name T1299
Test name
Test status
Simulation time 8411746794 ps
CPU time 8.85 seconds
Started May 12 12:54:56 PM PDT 24
Finished May 12 12:55:05 PM PDT 24
Peak memory 204308 kb
Host smart-1d116df9-ec98-44e9-926c-929b2fd156ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225
03855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3022503855
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3581294942
Short name T1336
Test name
Test status
Simulation time 8390931228 ps
CPU time 8.02 seconds
Started May 12 12:54:53 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 204380 kb
Host smart-64254808-4a76-4fa3-91ea-a6b4156b449d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35812
94942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3581294942
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3551813104
Short name T1356
Test name
Test status
Simulation time 8434171187 ps
CPU time 7.75 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:08 PM PDT 24
Peak memory 204420 kb
Host smart-15aa0d28-bacf-4c5e-83db-078a4fb213d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
13104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3551813104
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.97741691
Short name T772
Test name
Test status
Simulation time 163920769 ps
CPU time 0.76 seconds
Started May 12 12:54:52 PM PDT 24
Finished May 12 12:54:53 PM PDT 24
Peak memory 204380 kb
Host smart-b689f3ac-77d8-4d43-b72f-9b4a65e33ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97741
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.97741691
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2423315586
Short name T907
Test name
Test status
Simulation time 25597986181 ps
CPU time 49.68 seconds
Started May 12 12:54:53 PM PDT 24
Finished May 12 12:55:43 PM PDT 24
Peak memory 204532 kb
Host smart-8ecd0a8f-8cec-4c53-a235-80af9eb34e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
15586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2423315586
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.664523278
Short name T1347
Test name
Test status
Simulation time 8409436057 ps
CPU time 8.8 seconds
Started May 12 12:54:51 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 204456 kb
Host smart-000d5f83-9403-4577-9394-25370f25469c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66452
3278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.664523278
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2240838471
Short name T491
Test name
Test status
Simulation time 8382664215 ps
CPU time 7.94 seconds
Started May 12 12:54:54 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204420 kb
Host smart-9f17366f-8eab-4010-a377-2f0da4ff407f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
38471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2240838471
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2328189970
Short name T720
Test name
Test status
Simulation time 8381661446 ps
CPU time 9.22 seconds
Started May 12 12:54:54 PM PDT 24
Finished May 12 12:55:04 PM PDT 24
Peak memory 204464 kb
Host smart-a0f8a971-b07a-45b2-b624-832ce8d46ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23281
89970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2328189970
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2629147512
Short name T520
Test name
Test status
Simulation time 8394389109 ps
CPU time 8.6 seconds
Started May 12 12:54:55 PM PDT 24
Finished May 12 12:55:04 PM PDT 24
Peak memory 204460 kb
Host smart-7ffaeed4-d740-44dd-ad5a-96ed39247009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291
47512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2629147512
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.175123252
Short name T17
Test name
Test status
Simulation time 8372646962 ps
CPU time 7.94 seconds
Started May 12 12:54:52 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 204440 kb
Host smart-b50d042a-c7d5-4699-8da8-aff3b3bcaa7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17512
3252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.175123252
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3159745337
Short name T1310
Test name
Test status
Simulation time 8463735634 ps
CPU time 7.68 seconds
Started May 12 12:54:50 PM PDT 24
Finished May 12 12:54:59 PM PDT 24
Peak memory 204468 kb
Host smart-c5ee37bf-c621-4859-baea-83f5b31996b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597
45337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3159745337
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1611538169
Short name T569
Test name
Test status
Simulation time 8409928500 ps
CPU time 7.62 seconds
Started May 12 12:54:51 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 204436 kb
Host smart-9e61f177-91a8-4e55-81a8-bb6b951bd860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16115
38169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1611538169
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3996517215
Short name T659
Test name
Test status
Simulation time 8401696259 ps
CPU time 8.8 seconds
Started May 12 12:54:54 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204452 kb
Host smart-e6b570e1-706d-4b55-a2c6-52a1ec5a24e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39965
17215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3996517215
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.3875188456
Short name T580
Test name
Test status
Simulation time 8466255307 ps
CPU time 8.73 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:11 PM PDT 24
Peak memory 204344 kb
Host smart-fab611a1-7590-4f71-b6b6-ffca6d36ea39
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3875188456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.3875188456
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1889255686
Short name T837
Test name
Test status
Simulation time 8385352013 ps
CPU time 7.63 seconds
Started May 12 12:54:58 PM PDT 24
Finished May 12 12:55:07 PM PDT 24
Peak memory 204348 kb
Host smart-eb12e141-d8b1-41de-b14a-a665caff3320
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1889255686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1889255686
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2480374283
Short name T1
Test name
Test status
Simulation time 8389640124 ps
CPU time 10.39 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:11 PM PDT 24
Peak memory 204316 kb
Host smart-0946c812-9c8e-454b-9276-123a655f1d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24803
74283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2480374283
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1913484827
Short name T369
Test name
Test status
Simulation time 8382422890 ps
CPU time 8.87 seconds
Started May 12 12:54:55 PM PDT 24
Finished May 12 12:55:05 PM PDT 24
Peak memory 204456 kb
Host smart-6f275ecd-de21-4b95-91e4-3fda7c5d3bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19134
84827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1913484827
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.455983790
Short name T1264
Test name
Test status
Simulation time 9097670995 ps
CPU time 12.45 seconds
Started May 12 12:54:56 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204632 kb
Host smart-527114c2-b2b6-457f-901e-41e983c0679e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45598
3790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.455983790
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_enable.265752252
Short name T1191
Test name
Test status
Simulation time 8385469297 ps
CPU time 7.81 seconds
Started May 12 12:54:56 PM PDT 24
Finished May 12 12:55:04 PM PDT 24
Peak memory 204532 kb
Host smart-08e8f34a-0b48-4e96-a44e-fb85dc416657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26575
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.265752252
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1781525973
Short name T1029
Test name
Test status
Simulation time 208781606 ps
CPU time 1.76 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:02 PM PDT 24
Peak memory 204516 kb
Host smart-1d2b9b27-77b9-4322-9232-114746a110f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17815
25973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1781525973
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3377725591
Short name T1346
Test name
Test status
Simulation time 8456624170 ps
CPU time 8.11 seconds
Started May 12 12:55:07 PM PDT 24
Finished May 12 12:55:15 PM PDT 24
Peak memory 204364 kb
Host smart-5b77fd5a-6df7-40ae-a516-547927becf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777
25591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3377725591
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1366913882
Short name T1378
Test name
Test status
Simulation time 8408728538 ps
CPU time 8.22 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 204428 kb
Host smart-c19e4c86-abe7-475d-a586-8b46a30b1770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
13882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1366913882
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.4019233878
Short name T240
Test name
Test status
Simulation time 8393496680 ps
CPU time 8.26 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204460 kb
Host smart-2d84cb02-0e31-46e6-952d-58c42e26d0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192
33878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4019233878
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2000421506
Short name T530
Test name
Test status
Simulation time 8453447912 ps
CPU time 7.7 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:55:05 PM PDT 24
Peak memory 204448 kb
Host smart-96fc0310-6e7e-4750-9be4-0baf5c8880b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20004
21506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2000421506
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3488436186
Short name T595
Test name
Test status
Simulation time 8373369667 ps
CPU time 7.76 seconds
Started May 12 12:54:58 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204748 kb
Host smart-a238b241-5d41-456d-813b-da5629c67c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34884
36186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3488436186
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2461283725
Short name T517
Test name
Test status
Simulation time 8413714799 ps
CPU time 7.61 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:08 PM PDT 24
Peak memory 204348 kb
Host smart-dbe68166-b857-4875-9c6c-b1d9c9a280eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24612
83725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2461283725
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2817793016
Short name T334
Test name
Test status
Simulation time 8374340915 ps
CPU time 8.25 seconds
Started May 12 12:55:02 PM PDT 24
Finished May 12 12:55:11 PM PDT 24
Peak memory 204460 kb
Host smart-b2dbfbf2-8b76-4fc1-b634-731b4702ed58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28177
93016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2817793016
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2298874655
Short name T1147
Test name
Test status
Simulation time 8460048907 ps
CPU time 8.25 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 204324 kb
Host smart-00ade70e-5283-45b0-90d7-0f20170944bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22988
74655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2298874655
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3462567334
Short name T1032
Test name
Test status
Simulation time 8405120782 ps
CPU time 7.9 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204480 kb
Host smart-a8037b48-ecae-4373-8838-cf2835ea3afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625
67334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3462567334
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1156017731
Short name T392
Test name
Test status
Simulation time 8365923436 ps
CPU time 9.19 seconds
Started May 12 12:55:07 PM PDT 24
Finished May 12 12:55:17 PM PDT 24
Peak memory 204424 kb
Host smart-a79da776-1ac1-4324-a09c-c24c15790844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11560
17731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1156017731
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3257018565
Short name T1098
Test name
Test status
Simulation time 126983960 ps
CPU time 0.78 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 204380 kb
Host smart-8610437c-5f97-4ffd-8908-2d0f03ec2b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
18565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3257018565
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3161384012
Short name T494
Test name
Test status
Simulation time 29584499398 ps
CPU time 62.33 seconds
Started May 12 12:54:57 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204700 kb
Host smart-0d7e3f88-589e-4997-bdae-41bf734d271a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31613
84012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3161384012
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1267022479
Short name T643
Test name
Test status
Simulation time 8388293600 ps
CPU time 7.98 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 204420 kb
Host smart-a5ba7491-cdfb-4359-ae09-ced2625d057d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
22479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1267022479
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3630412321
Short name T43
Test name
Test status
Simulation time 8417384368 ps
CPU time 8.02 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204424 kb
Host smart-148ec570-1d82-476a-9fee-a4784dc50821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
12321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3630412321
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.414870182
Short name T406
Test name
Test status
Simulation time 8382495759 ps
CPU time 8.19 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 204436 kb
Host smart-1f6d432d-e3c0-44d2-ae48-f62c4eee0086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
0182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.414870182
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1262343860
Short name T833
Test name
Test status
Simulation time 8375182123 ps
CPU time 8.55 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 204380 kb
Host smart-c054376f-c12a-459a-9d3a-39856fffc7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
43860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1262343860
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2146579062
Short name T412
Test name
Test status
Simulation time 8382140453 ps
CPU time 8.14 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204380 kb
Host smart-bb6f9891-03e4-4ba9-81f4-3fde3f4977e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
79062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2146579062
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.658982688
Short name T748
Test name
Test status
Simulation time 8440413064 ps
CPU time 8.1 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:07 PM PDT 24
Peak memory 204436 kb
Host smart-6ebcea91-7fa1-44b9-a574-9e7e963c6415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65898
2688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.658982688
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2629835098
Short name T23
Test name
Test status
Simulation time 8370470242 ps
CPU time 8.04 seconds
Started May 12 12:55:02 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 204412 kb
Host smart-47cf0f2d-d333-4ac0-803f-99fe898bd3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298
35098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2629835098
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2137531696
Short name T987
Test name
Test status
Simulation time 8411605831 ps
CPU time 8.18 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204400 kb
Host smart-db0c8864-6d4d-4247-b795-3dff172cda03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21375
31696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2137531696
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.2638485663
Short name T774
Test name
Test status
Simulation time 8485403330 ps
CPU time 7.98 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204420 kb
Host smart-85b27c0b-049c-49ba-afce-beb7647c820d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2638485663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.2638485663
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.3839218238
Short name T719
Test name
Test status
Simulation time 8383952121 ps
CPU time 9.73 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:16 PM PDT 24
Peak memory 204424 kb
Host smart-0b2f9b98-dd5f-46d0-bb04-d1781f763a3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3839218238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3839218238
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2009575988
Short name T1380
Test name
Test status
Simulation time 8410244397 ps
CPU time 7.44 seconds
Started May 12 12:55:04 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204436 kb
Host smart-55c3274d-c7fd-4d92-805f-9318744dfa9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20095
75988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2009575988
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2528940041
Short name T241
Test name
Test status
Simulation time 8401070637 ps
CPU time 7.6 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:07 PM PDT 24
Peak memory 204428 kb
Host smart-8dd6706f-2daf-4c95-b3e4-844de551c019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
40041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2528940041
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3484721929
Short name T205
Test name
Test status
Simulation time 9417932117 ps
CPU time 13.85 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204688 kb
Host smart-96efe9db-ed6a-4b74-97df-8e6e46638647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
21929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3484721929
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_enable.146263286
Short name T667
Test name
Test status
Simulation time 8381099590 ps
CPU time 8.1 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204412 kb
Host smart-6b63d7e7-be43-4e4b-8a5f-f1d89a451d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14626
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.146263286
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4045740883
Short name T548
Test name
Test status
Simulation time 160050295 ps
CPU time 1.52 seconds
Started May 12 12:54:59 PM PDT 24
Finished May 12 12:55:02 PM PDT 24
Peak memory 204584 kb
Host smart-49ddd5e6-55c8-42e3-bf03-c3bcb7fc3e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
40883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4045740883
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3783564697
Short name T618
Test name
Test status
Simulation time 8458560046 ps
CPU time 8.15 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204476 kb
Host smart-3c28fc86-fac1-4010-8cb6-884de6006368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37835
64697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3783564697
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3203249732
Short name T489
Test name
Test status
Simulation time 8372019120 ps
CPU time 7.83 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:11 PM PDT 24
Peak memory 204376 kb
Host smart-f2e5a9c8-4606-41e0-8ce6-c4d420045c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
49732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3203249732
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4199724179
Short name T136
Test name
Test status
Simulation time 8420606251 ps
CPU time 7.65 seconds
Started May 12 12:55:00 PM PDT 24
Finished May 12 12:55:09 PM PDT 24
Peak memory 204420 kb
Host smart-a9a622d5-f748-4094-9edf-201e0569e60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
24179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4199724179
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1129543205
Short name T986
Test name
Test status
Simulation time 8410496780 ps
CPU time 9.21 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204500 kb
Host smart-6b46baaf-5a3a-4888-8523-9e9e030519f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11295
43205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1129543205
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.892123340
Short name T1148
Test name
Test status
Simulation time 8408176951 ps
CPU time 7.9 seconds
Started May 12 12:55:10 PM PDT 24
Finished May 12 12:55:19 PM PDT 24
Peak memory 204444 kb
Host smart-4ff1a6eb-0e60-486d-872d-24d417ad4d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89212
3340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.892123340
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.844294986
Short name T127
Test name
Test status
Simulation time 8438554038 ps
CPU time 8.4 seconds
Started May 12 12:55:04 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204416 kb
Host smart-501962ce-b300-4189-8ba3-6714966ad293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84429
4986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.844294986
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1630999943
Short name T408
Test name
Test status
Simulation time 8404619941 ps
CPU time 7.91 seconds
Started May 12 12:55:06 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204512 kb
Host smart-45e0ea21-6afd-4cf8-9542-7a9ed41c8489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
99943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1630999943
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1564407707
Short name T807
Test name
Test status
Simulation time 8451528574 ps
CPU time 8.49 seconds
Started May 12 12:55:04 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204324 kb
Host smart-960710b2-b4ac-4aa9-afe8-bb9390453f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
07707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1564407707
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3873119470
Short name T1214
Test name
Test status
Simulation time 8378239293 ps
CPU time 10.19 seconds
Started May 12 12:55:04 PM PDT 24
Finished May 12 12:55:15 PM PDT 24
Peak memory 204456 kb
Host smart-9f7abea5-4dfe-4cdc-9d48-a744f69f695c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38731
19470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3873119470
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.740708684
Short name T453
Test name
Test status
Simulation time 8376075802 ps
CPU time 7.74 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204416 kb
Host smart-54f68bbf-749e-4dbe-b227-bfa91524e268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74070
8684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.740708684
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2163182430
Short name T750
Test name
Test status
Simulation time 47303868 ps
CPU time 0.66 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:06 PM PDT 24
Peak memory 204372 kb
Host smart-649e5b6e-e960-4549-92bd-40ee79202c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
82430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2163182430
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1040751086
Short name T253
Test name
Test status
Simulation time 28242813988 ps
CPU time 54.65 seconds
Started May 12 12:55:04 PM PDT 24
Finished May 12 12:56:00 PM PDT 24
Peak memory 204880 kb
Host smart-40bd0653-28b3-45ba-810a-257e16a8359a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10407
51086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1040751086
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.319397980
Short name T1117
Test name
Test status
Simulation time 8394184528 ps
CPU time 7.71 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204456 kb
Host smart-2a608da8-bb74-492b-88bd-dbf01f105d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31939
7980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.319397980
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3357171568
Short name T148
Test name
Test status
Simulation time 8485932214 ps
CPU time 8.16 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204376 kb
Host smart-dd575c9a-2c3b-42f5-81ae-a846dfdf793a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33571
71568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3357171568
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3530877189
Short name T389
Test name
Test status
Simulation time 8412786857 ps
CPU time 9 seconds
Started May 12 12:55:04 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204424 kb
Host smart-4989d817-8a1d-4600-9aec-84a233b8f31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35308
77189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3530877189
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1576821163
Short name T1230
Test name
Test status
Simulation time 8375332598 ps
CPU time 8.24 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204460 kb
Host smart-602cf3cf-e313-4fba-8c66-f09c8ef3ae71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15768
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1576821163
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4136706209
Short name T574
Test name
Test status
Simulation time 8397442939 ps
CPU time 8.69 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204376 kb
Host smart-a5a6478b-34b9-45b2-8155-fe74117841af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41367
06209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4136706209
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1606510745
Short name T1216
Test name
Test status
Simulation time 8410085743 ps
CPU time 7.55 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 204428 kb
Host smart-55ff67be-fc21-4fff-aeff-330500894c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
10745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1606510745
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3708244662
Short name T1311
Test name
Test status
Simulation time 8392831585 ps
CPU time 8.01 seconds
Started May 12 12:55:05 PM PDT 24
Finished May 12 12:55:14 PM PDT 24
Peak memory 204452 kb
Host smart-47828151-2a91-4637-ac34-a58a67902202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
44662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3708244662
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3432589726
Short name T512
Test name
Test status
Simulation time 8408001149 ps
CPU time 7.89 seconds
Started May 12 12:55:03 PM PDT 24
Finished May 12 12:55:12 PM PDT 24
Peak memory 204460 kb
Host smart-2649d8eb-efc1-4d01-87de-d11763334786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34325
89726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3432589726
Directory /workspace/9.usbdev_stall_trans/latest
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