Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	116263	1		T1	2		T2	3		T3	3
all_values[1]	116263	1		T1	2		T2	3		T3	3
all_values[2]	116263	1		T1	2		T2	3		T3	3
all_values[3]	116263	1		T1	2		T2	3		T3	3
all_values[4]	116263	1		T1	2		T2	3		T3	3
all_values[5]	116263	1		T1	2		T2	3		T3	3
all_values[6]	116263	1		T1	2		T2	3		T3	3
all_values[7]	116263	1		T1	2		T2	3		T3	3
all_values[8]	116263	1		T1	2		T2	3		T3	3
all_values[9]	116263	1		T1	2		T2	3		T3	3
all_values[10]	116263	1		T1	2		T2	3		T3	3
all_values[11]	116263	1		T1	2		T2	3		T3	3
all_values[12]	116263	1		T1	2		T2	3		T3	3
all_values[13]	116263	1		T1	2		T2	3		T3	3
all_values[14]	116263	1		T1	2		T2	3		T3	3
all_values[15]	116263	1		T1	2		T2	3		T3	3
all_values[16]	116263	1		T1	2		T2	3		T3	3
all_values[17]	116263	1		T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2088080	1		T1	36		T2	54		T3	54
auto[1]	4654	1		T4	3		T6	4		T11	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2087832	1		T1	36		T2	54		T3	54
auto[1]	4902	1		T64	117		T65	128		T66	115

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	115623	1		T1	2		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	138	1		T64	6		T65	2		T66	7
all_values[0]	auto[1]	auto[0]	374	1		T4	3		T6	4		T62	4
all_values[0]	auto[1]	auto[1]	128	1		T64	2		T65	5		T66	1
all_values[1]	auto[0]	auto[0]	114834	1		T1	2		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	123	1		T64	1		T65	3		T66	5
all_values[1]	auto[1]	auto[0]	1161	1		T11	14		T17	4		T63	3
all_values[1]	auto[1]	auto[1]	145	1		T64	3		T65	3		T66	2
all_values[2]	auto[0]	auto[0]	115874	1		T1	2		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	125	1		T65	3		T66	6		T67	5
all_values[2]	auto[1]	auto[0]	123	1		T21	2		T23	2		T24	2
all_values[2]	auto[1]	auto[1]	141	1		T64	4		T65	3		T66	2
all_values[3]	auto[0]	auto[0]	115960	1		T1	2		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	128	1		T64	7		T65	3		T66	2
all_values[3]	auto[1]	auto[0]	27	1		T65	1		T68	1		T244	1
all_values[3]	auto[1]	auto[1]	148	1		T64	1		T65	4		T66	6
all_values[4]	auto[0]	auto[0]	115971	1		T1	2		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	124	1		T64	3		T66	4		T68	4
all_values[4]	auto[1]	auto[0]	29	1		T65	1		T66	2		T67	3
all_values[4]	auto[1]	auto[1]	139	1		T64	5		T65	7		T66	2
all_values[5]	auto[0]	auto[0]	115966	1		T1	2		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	119	1		T64	3		T65	2		T68	2
all_values[5]	auto[1]	auto[0]	31	1		T64	1		T66	2		T245	1
all_values[5]	auto[1]	auto[1]	147	1		T64	4		T65	6		T67	5
all_values[6]	auto[0]	auto[0]	115966	1		T1	2		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	123	1		T65	2		T66	2		T67	1
all_values[6]	auto[1]	auto[0]	26	1		T64	2		T245	1		T246	1
all_values[6]	auto[1]	auto[1]	148	1		T64	5		T65	5		T66	6
all_values[7]	auto[0]	auto[0]	115962	1		T1	2		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	132	1		T64	3		T65	5		T66	2
all_values[7]	auto[1]	auto[0]	31	1		T64	2		T66	1		T245	1
all_values[7]	auto[1]	auto[1]	138	1		T64	1		T65	3		T66	5
all_values[8]	auto[0]	auto[0]	115960	1		T1	2		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	133	1		T64	3		T65	4		T66	7
all_values[8]	auto[1]	auto[0]	22	1		T65	1		T66	1		T67	5
all_values[8]	auto[1]	auto[1]	148	1		T64	5		T65	2		T68	4
all_values[9]	auto[0]	auto[0]	115965	1		T1	2		T2	3		T3	3
all_values[9]	auto[0]	auto[1]	137	1		T64	3		T65	6		T66	2
all_values[9]	auto[1]	auto[0]	27	1		T245	1		T246	1		T235	1
all_values[9]	auto[1]	auto[1]	134	1		T64	3		T65	1		T66	6
all_values[10]	auto[0]	auto[0]	115955	1		T1	2		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	135	1		T65	3		T66	4		T68	2
all_values[10]	auto[1]	auto[0]	23	1		T64	3		T245	1		T247	1
all_values[10]	auto[1]	auto[1]	150	1		T64	5		T65	5		T66	1
all_values[11]	auto[0]	auto[0]	115866	1		T1	2		T2	3		T3	3
all_values[11]	auto[0]	auto[1]	138	1		T64	6		T65	1		T66	3
all_values[11]	auto[1]	auto[0]	110	1		T28	2		T29	2		T30	2
all_values[11]	auto[1]	auto[1]	149	1		T64	2		T65	7		T67	5
all_values[12]	auto[0]	auto[0]	115968	1		T1	2		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	119	1		T64	5		T65	5		T66	3
all_values[12]	auto[1]	auto[0]	33	1		T65	2		T66	1		T67	1
all_values[12]	auto[1]	auto[1]	143	1		T64	2		T66	2		T67	1
all_values[13]	auto[0]	auto[0]	115982	1		T1	2		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	122	1		T64	3		T65	4		T66	2
all_values[13]	auto[1]	auto[0]	25	1		T67	1		T248	2		T249	3
all_values[13]	auto[1]	auto[1]	134	1		T64	5		T65	3		T66	5
all_values[14]	auto[0]	auto[0]	115967	1		T1	2		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	150	1		T64	5		T65	3		T66	2
all_values[14]	auto[1]	auto[0]	19	1		T245	1		T246	1		T250	2
all_values[14]	auto[1]	auto[1]	127	1		T64	3		T65	4		T66	5
all_values[15]	auto[0]	auto[0]	115965	1		T1	2		T2	3		T3	3
all_values[15]	auto[0]	auto[1]	136	1		T64	4		T65	1		T66	2
all_values[15]	auto[1]	auto[0]	26	1		T66	1		T245	1		T246	1
all_values[15]	auto[1]	auto[1]	136	1		T64	4		T65	7		T66	5
all_values[16]	auto[0]	auto[0]	115964	1		T1	2		T2	3		T3	3
all_values[16]	auto[0]	auto[1]	148	1		T65	7		T66	6		T67	3
all_values[16]	auto[1]	auto[0]	24	1		T64	2		T66	1		T246	1
all_values[16]	auto[1]	auto[1]	127	1		T64	4		T65	1		T67	2
all_values[17]	auto[0]	auto[0]	115959	1		T1	2		T2	3		T3	3
all_values[17]	auto[0]	auto[1]	143	1		T64	5		T65	2		T66	5
all_values[17]	auto[1]	auto[0]	14	1		T245	1		T246	1		T235	2
all_values[17]	auto[1]	auto[1]	147	1		T64	2		T65	6		T66	3