Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	116263	1		T1	2		T2	3		T3	3
all_pins[1]	116263	1		T1	2		T2	3		T3	3
all_pins[2]	116263	1		T1	2		T2	3		T3	3
all_pins[3]	116263	1		T1	2		T2	3		T3	3
all_pins[4]	116263	1		T1	2		T2	3		T3	3
all_pins[5]	116263	1		T1	2		T2	3		T3	3
all_pins[6]	116263	1		T1	2		T2	3		T3	3
all_pins[7]	116263	1		T1	2		T2	3		T3	3
all_pins[8]	116263	1		T1	2		T2	3		T3	3
all_pins[9]	116263	1		T1	2		T2	3		T3	3
all_pins[10]	116263	1		T1	2		T2	3		T3	3
all_pins[11]	116263	1		T1	2		T2	3		T3	3
all_pins[12]	116263	1		T1	2		T2	3		T3	3
all_pins[13]	116263	1		T1	2		T2	3		T3	3
all_pins[14]	116263	1		T1	2		T2	3		T3	3
all_pins[15]	116263	1		T1	2		T2	3		T3	3
all_pins[16]	116263	1		T1	2		T2	3		T3	3
all_pins[17]	116263	1		T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2090735	1		T1	36		T2	54		T3	54
values[0x1]	1999	1		T6	1		T11	12		T62	1
transitions[0x0=>0x1]	1692	1		T6	1		T11	12		T62	1
transitions[0x1=>0x0]	1707	1		T6	1		T11	12		T62	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	116157	1		T1	2		T2	3		T3	3
all_pins[0]	values[0x1]	106	1		T6	1		T62	1		T93	1
all_pins[0]	transitions[0x0=>0x1]	95	1		T6	1		T62	1		T93	1
all_pins[0]	transitions[0x1=>0x0]	741	1		T11	12		T17	1		T63	1
all_pins[1]	values[0x0]	115511	1		T1	2		T2	3		T3	3
all_pins[1]	values[0x1]	752	1		T11	12		T17	1		T63	1
all_pins[1]	transitions[0x0=>0x1]	738	1		T11	12		T17	1		T63	1
all_pins[1]	transitions[0x1=>0x0]	109	1		T21	1		T23	1		T24	1
all_pins[2]	values[0x0]	116140	1		T1	2		T2	3		T3	3
all_pins[2]	values[0x1]	123	1		T21	1		T23	1		T24	1
all_pins[2]	transitions[0x0=>0x1]	101	1		T21	1		T23	1		T24	1
all_pins[2]	transitions[0x1=>0x0]	34	1		T66	2		T67	1		T68	2
all_pins[3]	values[0x0]	116207	1		T1	2		T2	3		T3	3
all_pins[3]	values[0x1]	56	1		T64	1		T66	2		T67	1
all_pins[3]	transitions[0x0=>0x1]	41	1		T66	2		T67	1		T68	3
all_pins[3]	transitions[0x1=>0x0]	58	1		T65	1		T66	1		T68	2
all_pins[4]	values[0x0]	116190	1		T1	2		T2	3		T3	3
all_pins[4]	values[0x1]	73	1		T64	1		T65	1		T66	1
all_pins[4]	transitions[0x0=>0x1]	53	1		T65	1		T66	1		T68	2
all_pins[4]	transitions[0x1=>0x0]	59	1		T67	2		T68	2		T244	1
all_pins[5]	values[0x0]	116184	1		T1	2		T2	3		T3	3
all_pins[5]	values[0x1]	79	1		T64	1		T67	2		T68	2
all_pins[5]	transitions[0x0=>0x1]	66	1		T67	1		T68	2		T248	2
all_pins[5]	transitions[0x1=>0x0]	46	1		T64	1		T65	1		T66	4
all_pins[6]	values[0x0]	116204	1		T1	2		T2	3		T3	3
all_pins[6]	values[0x1]	59	1		T64	2		T65	1		T66	4
all_pins[6]	transitions[0x0=>0x1]	45	1		T64	1		T66	3		T67	1
all_pins[6]	transitions[0x1=>0x0]	55	1		T66	2		T68	4		T245	2
all_pins[7]	values[0x0]	116194	1		T1	2		T2	3		T3	3
all_pins[7]	values[0x1]	69	1		T64	1		T65	1		T66	3
all_pins[7]	transitions[0x0=>0x1]	49	1		T64	1		T65	1		T66	3
all_pins[7]	transitions[0x1=>0x0]	38	1		T64	2		T65	2		T68	1
all_pins[8]	values[0x0]	116205	1		T1	2		T2	3		T3	3
all_pins[8]	values[0x1]	58	1		T64	2		T65	2		T68	3
all_pins[8]	transitions[0x0=>0x1]	42	1		T64	2		T65	2		T68	1
all_pins[8]	transitions[0x1=>0x0]	51	1		T66	2		T68	1		T245	2
all_pins[9]	values[0x0]	116196	1		T1	2		T2	3		T3	3
all_pins[9]	values[0x1]	67	1		T66	2		T68	3		T245	2
all_pins[9]	transitions[0x0=>0x1]	48	1		T66	2		T68	1		T245	1
all_pins[9]	transitions[0x1=>0x0]	47	1		T64	2		T65	2		T67	2
all_pins[10]	values[0x0]	116197	1		T1	2		T2	3		T3	3
all_pins[10]	values[0x1]	66	1		T64	2		T65	2		T67	2
all_pins[10]	transitions[0x0=>0x1]	51	1		T64	2		T65	1		T67	1
all_pins[10]	transitions[0x1=>0x0]	99	1		T28	1		T29	1		T30	1
all_pins[11]	values[0x0]	116149	1		T1	2		T2	3		T3	3
all_pins[11]	values[0x1]	114	1		T28	1		T29	1		T30	1
all_pins[11]	transitions[0x0=>0x1]	98	1		T28	1		T29	1		T30	1
all_pins[11]	transitions[0x1=>0x0]	52	1		T64	2		T66	2		T67	1
all_pins[12]	values[0x0]	116195	1		T1	2		T2	3		T3	3
all_pins[12]	values[0x1]	68	1		T64	2		T66	2		T67	1
all_pins[12]	transitions[0x0=>0x1]	43	1		T66	1		T67	1		T245	3
all_pins[12]	transitions[0x1=>0x0]	46	1		T64	2		T65	2		T66	3
all_pins[13]	values[0x0]	116192	1		T1	2		T2	3		T3	3
all_pins[13]	values[0x1]	71	1		T64	4		T65	2		T66	4
all_pins[13]	transitions[0x0=>0x1]	53	1		T64	3		T65	1		T66	4
all_pins[13]	transitions[0x1=>0x0]	43	1		T64	1		T67	1		T68	4
all_pins[14]	values[0x0]	116202	1		T1	2		T2	3		T3	3
all_pins[14]	values[0x1]	61	1		T64	2		T65	1		T67	1
all_pins[14]	transitions[0x0=>0x1]	44	1		T64	2		T65	1		T67	1
all_pins[14]	transitions[0x1=>0x0]	39	1		T64	1		T65	3		T66	1
all_pins[15]	values[0x0]	116207	1		T1	2		T2	3		T3	3
all_pins[15]	values[0x1]	56	1		T64	1		T65	3		T66	1
all_pins[15]	transitions[0x0=>0x1]	41	1		T64	1		T65	3		T66	1
all_pins[15]	transitions[0x1=>0x0]	42	1		T64	1		T65	1		T67	1
all_pins[16]	values[0x0]	116206	1		T1	2		T2	3		T3	3
all_pins[16]	values[0x1]	57	1		T64	1		T65	1		T67	2
all_pins[16]	transitions[0x0=>0x1]	43	1		T64	1		T65	1		T67	1
all_pins[16]	transitions[0x1=>0x0]	50	1		T64	1		T65	2		T66	2
all_pins[17]	values[0x0]	116199	1		T1	2		T2	3		T3	3
all_pins[17]	values[0x1]	64	1		T64	1		T65	2		T66	2
all_pins[17]	transitions[0x0=>0x1]	41	1		T64	1		T65	1		T66	1
all_pins[17]	transitions[0x1=>0x0]	98	1		T6	1		T62	1		T93	1