Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	30357	1		T2	2		T3	4		T4	2
all_values[1]	30357	1		T2	2		T3	4		T4	2
all_values[2]	30357	1		T2	2		T3	4		T4	2
all_values[3]	30357	1		T2	2		T3	4		T4	2
all_values[4]	30357	1		T2	2		T3	4		T4	2
all_values[5]	30357	1		T2	2		T3	4		T4	2
all_values[6]	30357	1		T2	2		T3	4		T4	2
all_values[7]	30357	1		T2	2		T3	4		T4	2
all_values[8]	30357	1		T2	2		T3	4		T4	2
all_values[9]	30357	1		T2	2		T3	4		T4	2
all_values[10]	30357	1		T2	2		T3	4		T4	2
all_values[11]	30357	1		T2	2		T3	4		T4	2
all_values[12]	30357	1		T2	2		T3	4		T4	2
all_values[13]	30357	1		T2	2		T3	4		T4	2
all_values[14]	30357	1		T2	2		T3	4		T4	2
all_values[15]	30357	1		T2	2		T3	4		T4	2
all_values[16]	30357	1		T2	2		T3	4		T4	2
all_values[17]	30357	1		T2	2		T3	4		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	541502	1		T2	36		T3	72		T4	36
auto[1]	4924	1		T17	3		T19	3		T28	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	541442	1		T2	36		T3	72		T4	36
auto[1]	4984	1		T68	75		T69	70		T70	128

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29364	1		T2	2		T3	4		T4	2
all_values[0]	auto[0]	auto[1]	129	1		T68	1		T69	5		T70	1
all_values[0]	auto[1]	auto[0]	730	1		T29	3		T66	3		T96	3
all_values[0]	auto[1]	auto[1]	134	1		T68	4		T70	7		T72	1
all_values[1]	auto[0]	auto[0]	28951	1		T2	2		T3	4		T4	2
all_values[1]	auto[0]	auto[1]	176	1		T68	3		T69	1		T70	5
all_values[1]	auto[1]	auto[0]	1115	1		T17	3		T19	3		T28	14
all_values[1]	auto[1]	auto[1]	115	1		T68	1		T69	3		T70	3
all_values[2]	auto[0]	auto[0]	29956	1		T2	2		T3	4		T4	2
all_values[2]	auto[0]	auto[1]	125	1		T68	1		T69	4		T70	6
all_values[2]	auto[1]	auto[0]	135	1		T8	2		T9	2		T10	2
all_values[2]	auto[1]	auto[1]	141	1		T68	4		T69	1		T70	2
all_values[3]	auto[0]	auto[0]	30046	1		T2	2		T3	4		T4	2
all_values[3]	auto[0]	auto[1]	162	1		T68	2		T69	3		T70	5
all_values[3]	auto[1]	auto[0]	22	1		T69	1		T70	1		T270	1
all_values[3]	auto[1]	auto[1]	127	1		T68	3		T70	1		T72	4
all_values[4]	auto[0]	auto[0]	30050	1		T2	2		T3	4		T4	2
all_values[4]	auto[0]	auto[1]	137	1		T68	3		T69	2		T70	5
all_values[4]	auto[1]	auto[0]	27	1		T271	3		T272	1		T273	1
all_values[4]	auto[1]	auto[1]	143	1		T68	2		T69	3		T70	1
all_values[5]	auto[0]	auto[0]	30052	1		T2	2		T3	4		T4	2
all_values[5]	auto[0]	auto[1]	133	1		T69	1		T70	2		T271	4
all_values[5]	auto[1]	auto[0]	24	1		T68	1		T69	1		T72	2
all_values[5]	auto[1]	auto[1]	148	1		T68	4		T69	3		T70	4
all_values[6]	auto[0]	auto[0]	30055	1		T2	2		T3	4		T4	2
all_values[6]	auto[0]	auto[1]	137	1		T68	4		T70	5		T72	1
all_values[6]	auto[1]	auto[0]	25	1		T68	1		T69	3		T267	1
all_values[6]	auto[1]	auto[1]	140	1		T70	3		T72	4		T271	5
all_values[7]	auto[0]	auto[0]	30054	1		T2	2		T3	4		T4	2
all_values[7]	auto[0]	auto[1]	127	1		T68	1		T70	4		T72	1
all_values[7]	auto[1]	auto[0]	30	1		T68	1		T70	1		T271	2
all_values[7]	auto[1]	auto[1]	146	1		T68	3		T69	5		T70	1
all_values[8]	auto[0]	auto[0]	30047	1		T2	2		T3	4		T4	2
all_values[8]	auto[0]	auto[1]	167	1		T68	2		T69	4		T70	3
all_values[8]	auto[1]	auto[0]	12	1		T271	1		T267	1		T270	1
all_values[8]	auto[1]	auto[1]	131	1		T68	3		T69	1		T70	5
all_values[9]	auto[0]	auto[0]	30057	1		T2	2		T3	4		T4	2
all_values[9]	auto[0]	auto[1]	142	1		T69	1		T70	4		T72	3
all_values[9]	auto[1]	auto[0]	21	1		T68	1		T70	2		T273	1
all_values[9]	auto[1]	auto[1]	137	1		T69	4		T70	1		T271	3
all_values[10]	auto[0]	auto[0]	30057	1		T2	2		T3	4		T4	2
all_values[10]	auto[0]	auto[1]	148	1		T68	2		T69	5		T70	4
all_values[10]	auto[1]	auto[0]	23	1		T70	2		T72	1		T274	4
all_values[10]	auto[1]	auto[1]	129	1		T68	3		T70	2		T72	3
all_values[11]	auto[0]	auto[0]	29960	1		T2	2		T3	4		T4	2
all_values[11]	auto[0]	auto[1]	152	1		T68	3		T72	3		T271	7
all_values[11]	auto[1]	auto[0]	125	1		T39	2		T40	2		T41	2
all_values[11]	auto[1]	auto[1]	120	1		T68	2		T70	8		T271	1
all_values[12]	auto[0]	auto[0]	30068	1		T2	2		T3	4		T4	2
all_values[12]	auto[0]	auto[1]	151	1		T69	5		T70	1		T72	4
all_values[12]	auto[1]	auto[0]	30	1		T271	1		T275	1		T274	1
all_values[12]	auto[1]	auto[1]	108	1		T68	5		T70	7		T72	1
all_values[13]	auto[0]	auto[0]	30058	1		T2	2		T3	4		T4	2
all_values[13]	auto[0]	auto[1]	127	1		T68	3		T70	1		T72	4
all_values[13]	auto[1]	auto[0]	19	1		T69	3		T70	1		T273	1
all_values[13]	auto[1]	auto[1]	153	1		T68	2		T70	6		T72	1
all_values[14]	auto[0]	auto[0]	30059	1		T2	2		T3	4		T4	2
all_values[14]	auto[0]	auto[1]	120	1		T69	1		T70	1		T72	2
all_values[14]	auto[1]	auto[0]	18	1		T68	1		T271	1		T272	2
all_values[14]	auto[1]	auto[1]	160	1		T68	4		T69	4		T70	7
all_values[15]	auto[0]	auto[0]	30052	1		T2	2		T3	4		T4	2
all_values[15]	auto[0]	auto[1]	144	1		T68	1		T69	4		T70	3
all_values[15]	auto[1]	auto[0]	30	1		T72	2		T271	2		T275	1
all_values[15]	auto[1]	auto[1]	131	1		T68	4		T69	1		T70	5
all_values[16]	auto[0]	auto[0]	30058	1		T2	2		T3	4		T4	2
all_values[16]	auto[0]	auto[1]	126	1		T69	1		T70	4		T72	1
all_values[16]	auto[1]	auto[0]	45	1		T68	2		T69	1		T271	1
all_values[16]	auto[1]	auto[1]	128	1		T69	3		T70	3		T72	4
all_values[17]	auto[0]	auto[0]	30041	1		T2	2		T3	4		T4	2
all_values[17]	auto[0]	auto[1]	114	1		T68	3		T69	3		T70	2
all_values[17]	auto[1]	auto[0]	26	1		T72	4		T272	1		T276	1
all_values[17]	auto[1]	auto[1]	176	1		T68	2		T69	2		T70	6