Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	30357	1		T2	2		T3	4		T4	2
all_pins[1]	30357	1		T2	2		T3	4		T4	2
all_pins[2]	30357	1		T2	2		T3	4		T4	2
all_pins[3]	30357	1		T2	2		T3	4		T4	2
all_pins[4]	30357	1		T2	2		T3	4		T4	2
all_pins[5]	30357	1		T2	2		T3	4		T4	2
all_pins[6]	30357	1		T2	2		T3	4		T4	2
all_pins[7]	30357	1		T2	2		T3	4		T4	2
all_pins[8]	30357	1		T2	2		T3	4		T4	2
all_pins[9]	30357	1		T2	2		T3	4		T4	2
all_pins[10]	30357	1		T2	2		T3	4		T4	2
all_pins[11]	30357	1		T2	2		T3	4		T4	2
all_pins[12]	30357	1		T2	2		T3	4		T4	2
all_pins[13]	30357	1		T2	2		T3	4		T4	2
all_pins[14]	30357	1		T2	2		T3	4		T4	2
all_pins[15]	30357	1		T2	2		T3	4		T4	2
all_pins[16]	30357	1		T2	2		T3	4		T4	2
all_pins[17]	30357	1		T2	2		T3	4		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	544369	1		T2	36		T3	72		T4	36
values[0x1]	2057	1		T17	1		T19	1		T28	12
transitions[0x0=>0x1]	1727	1		T17	1		T19	1		T28	12
transitions[0x1=>0x0]	1739	1		T17	1		T19	1		T28	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	30193	1		T2	2		T3	4		T4	2
all_pins[0]	values[0x1]	164	1		T67	1		T277	1		T278	1
all_pins[0]	transitions[0x0=>0x1]	149	1		T67	1		T277	1		T278	1
all_pins[0]	transitions[0x1=>0x0]	709	1		T17	1		T19	1		T28	12
all_pins[1]	values[0x0]	29633	1		T2	2		T3	4		T4	2
all_pins[1]	values[0x1]	724	1		T17	1		T19	1		T28	12
all_pins[1]	transitions[0x0=>0x1]	707	1		T17	1		T19	1		T28	12
all_pins[1]	transitions[0x1=>0x0]	110	1		T8	1		T9	1		T10	1
all_pins[2]	values[0x0]	30230	1		T2	2		T3	4		T4	2
all_pins[2]	values[0x1]	127	1		T8	1		T9	1		T10	1
all_pins[2]	transitions[0x0=>0x1]	109	1		T8	1		T9	1		T10	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T70	1		T271	1		T279	2
all_pins[3]	values[0x0]	30295	1		T2	2		T3	4		T4	2
all_pins[3]	values[0x1]	62	1		T70	1		T271	2		T279	2
all_pins[3]	transitions[0x0=>0x1]	43	1		T271	2		T279	2		T273	2
all_pins[3]	transitions[0x1=>0x0]	54	1		T68	2		T72	1		T271	2
all_pins[4]	values[0x0]	30284	1		T2	2		T3	4		T4	2
all_pins[4]	values[0x1]	73	1		T68	2		T70	1		T72	1
all_pins[4]	transitions[0x0=>0x1]	53	1		T68	1		T72	1		T272	1
all_pins[4]	transitions[0x1=>0x0]	57	1		T68	2		T70	2		T72	2
all_pins[5]	values[0x0]	30280	1		T2	2		T3	4		T4	2
all_pins[5]	values[0x1]	77	1		T68	3		T70	3		T72	2
all_pins[5]	transitions[0x0=>0x1]	55	1		T68	3		T70	3		T271	1
all_pins[5]	transitions[0x1=>0x0]	47	1		T70	2		T271	1		T273	1
all_pins[6]	values[0x0]	30288	1		T2	2		T3	4		T4	2
all_pins[6]	values[0x1]	69	1		T70	2		T72	2		T271	3
all_pins[6]	transitions[0x0=>0x1]	50	1		T70	2		T72	1		T271	2
all_pins[6]	transitions[0x1=>0x0]	36	1		T68	1		T69	1		T70	1
all_pins[7]	values[0x0]	30302	1		T2	2		T3	4		T4	2
all_pins[7]	values[0x1]	55	1		T68	1		T69	1		T70	1
all_pins[7]	transitions[0x0=>0x1]	45	1		T68	1		T69	1		T70	1
all_pins[7]	transitions[0x1=>0x0]	39	1		T70	1		T72	1		T271	1
all_pins[8]	values[0x0]	30308	1		T2	2		T3	4		T4	2
all_pins[8]	values[0x1]	49	1		T70	1		T72	1		T271	1
all_pins[8]	transitions[0x0=>0x1]	33	1		T70	1		T72	1		T273	2
all_pins[8]	transitions[0x1=>0x0]	53	1		T69	1		T271	2		T272	2
all_pins[9]	values[0x0]	30288	1		T2	2		T3	4		T4	2
all_pins[9]	values[0x1]	69	1		T69	1		T271	3		T272	2
all_pins[9]	transitions[0x0=>0x1]	49	1		T69	1		T271	2		T272	1
all_pins[9]	transitions[0x1=>0x0]	50	1		T68	2		T70	1		T72	2
all_pins[10]	values[0x0]	30287	1		T2	2		T3	4		T4	2
all_pins[10]	values[0x1]	70	1		T68	2		T70	1		T72	2
all_pins[10]	transitions[0x0=>0x1]	58	1		T68	2		T70	1		T72	2
all_pins[10]	transitions[0x1=>0x0]	94	1		T39	1		T40	1		T41	1
all_pins[11]	values[0x0]	30251	1		T2	2		T3	4		T4	2
all_pins[11]	values[0x1]	106	1		T39	1		T40	1		T41	1
all_pins[11]	transitions[0x0=>0x1]	92	1		T39	1		T40	1		T41	1
all_pins[11]	transitions[0x1=>0x0]	39	1		T68	2		T70	2		T271	1
all_pins[12]	values[0x0]	30304	1		T2	2		T3	4		T4	2
all_pins[12]	values[0x1]	53	1		T68	4		T70	3		T271	1
all_pins[12]	transitions[0x0=>0x1]	30	1		T68	2		T70	1		T271	1
all_pins[12]	transitions[0x1=>0x0]	60	1		T70	2		T72	1		T271	5
all_pins[13]	values[0x0]	30274	1		T2	2		T3	4		T4	2
all_pins[13]	values[0x1]	83	1		T68	2		T70	4		T72	1
all_pins[13]	transitions[0x0=>0x1]	55	1		T68	1		T70	4		T72	1
all_pins[13]	transitions[0x1=>0x0]	47	1		T68	2		T69	1		T70	1
all_pins[14]	values[0x0]	30282	1		T2	2		T3	4		T4	2
all_pins[14]	values[0x1]	75	1		T68	3		T69	1		T70	1
all_pins[14]	transitions[0x0=>0x1]	47	1		T68	1		T70	1		T273	1
all_pins[14]	transitions[0x1=>0x0]	48	1		T68	1		T70	4		T72	2
all_pins[15]	values[0x0]	30281	1		T2	2		T3	4		T4	2
all_pins[15]	values[0x1]	76	1		T68	3		T69	1		T70	4
all_pins[15]	transitions[0x0=>0x1]	62	1		T68	3		T69	1		T70	3
all_pins[15]	transitions[0x1=>0x0]	46	1		T271	2		T272	1		T275	1
all_pins[16]	values[0x0]	30297	1		T2	2		T3	4		T4	2
all_pins[16]	values[0x1]	60	1		T70	1		T271	2		T272	1
all_pins[16]	transitions[0x0=>0x1]	48	1		T70	1		T271	1		T272	1
all_pins[16]	transitions[0x1=>0x0]	53	1		T68	1		T69	2		T271	1
all_pins[17]	values[0x0]	30292	1		T2	2		T3	4		T4	2
all_pins[17]	values[0x1]	65	1		T68	1		T69	2		T271	2
all_pins[17]	transitions[0x0=>0x1]	42	1		T69	1		T271	2		T279	1
all_pins[17]	transitions[0x1=>0x0]	153	1		T67	1		T277	1		T278	1