Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T68	4		T69	4		T70	7
all_values[1]	281	1		T68	4		T69	4		T70	7
all_values[2]	281	1		T68	4		T69	4		T70	7
all_values[3]	281	1		T68	4		T69	4		T70	7
all_values[4]	281	1		T68	4		T69	4		T70	7
all_values[5]	281	1		T68	4		T69	4		T70	7
all_values[6]	281	1		T68	4		T69	4		T70	7
all_values[7]	281	1		T68	4		T69	4		T70	7
all_values[8]	281	1		T68	4		T69	4		T70	7
all_values[9]	281	1		T68	4		T69	4		T70	7
all_values[10]	281	1		T68	4		T69	4		T70	7
all_values[11]	281	1		T68	4		T69	4		T70	7
all_values[12]	281	1		T68	4		T69	4		T70	7
all_values[13]	281	1		T68	4		T69	4		T70	7
all_values[14]	281	1		T68	4		T69	4		T70	7
all_values[15]	281	1		T68	4		T69	4		T70	7
all_values[16]	281	1		T68	4		T69	4		T70	7
all_values[17]	281	1		T68	4		T69	4		T70	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2732	1		T68	39		T69	44		T70	74
auto[1]	2326	1		T68	33		T69	28		T70	52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	908	1		T68	13		T69	17		T70	16
auto[1]	4150	1		T68	59		T69	55		T70	110

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2969	1		T68	40		T69	46		T70	70
auto[1]	2089	1		T68	32		T69	26		T70	56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1		T272	1		T279	1		T275	1
all_values[0]	auto[0]	auto[0]	auto[1]	49	1		T69	1		T72	2		T271	1
all_values[0]	auto[0]	auto[1]	auto[0]	23	1		T267	1		T280	3		T281	2
all_values[0]	auto[0]	auto[1]	auto[1]	52	1		T68	1		T70	3		T72	1
all_values[0]	auto[1]	auto[0]	auto[1]	54	1		T68	2		T69	3		T70	2
all_values[0]	auto[1]	auto[1]	auto[1]	63	1		T68	1		T70	2		T271	2
all_values[1]	auto[0]	auto[0]	auto[0]	29	1		T68	1		T72	2		T272	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1		T68	2		T69	1		T70	2
all_values[1]	auto[0]	auto[1]	auto[0]	9	1		T69	1		T267	1		T281	1
all_values[1]	auto[0]	auto[1]	auto[1]	49	1		T69	1		T271	1		T272	2
all_values[1]	auto[1]	auto[0]	auto[1]	74	1		T68	1		T69	1		T70	3
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T70	2		T271	1		T267	3
all_values[2]	auto[0]	auto[0]	auto[0]	34	1		T275	3		T280	3		T282	3
all_values[2]	auto[0]	auto[0]	auto[1]	43	1		T69	1		T70	1		T72	1
all_values[2]	auto[0]	auto[1]	auto[0]	27	1		T72	1		T273	1		T267	2
all_values[2]	auto[0]	auto[1]	auto[1]	60	1		T68	1		T69	2		T70	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T68	1		T69	1		T70	4
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T68	2		T72	2		T271	3
all_values[3]	auto[0]	auto[0]	auto[0]	26	1		T69	1		T70	2		T72	1
all_values[3]	auto[0]	auto[0]	auto[1]	62	1		T68	1		T69	1		T70	2
all_values[3]	auto[0]	auto[1]	auto[0]	14	1		T69	1		T276	3		T282	1
all_values[3]	auto[0]	auto[1]	auto[1]	51	1		T68	2		T72	2		T271	2
all_values[3]	auto[1]	auto[0]	auto[1]	71	1		T68	1		T69	1		T70	2
all_values[3]	auto[1]	auto[1]	auto[1]	57	1		T70	1		T271	1		T279	1
all_values[4]	auto[0]	auto[0]	auto[0]	28	1		T70	2		T271	2		T272	2
all_values[4]	auto[0]	auto[0]	auto[1]	58	1		T68	1		T69	1		T70	3
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T271	3		T273	1		T280	2
all_values[4]	auto[0]	auto[1]	auto[1]	59	1		T69	1		T271	1		T273	2
all_values[4]	auto[1]	auto[0]	auto[1]	45	1		T68	2		T69	2		T70	2
all_values[4]	auto[1]	auto[1]	auto[1]	70	1		T68	1		T72	2		T271	1
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T68	1		T70	2		T267	3
all_values[5]	auto[0]	auto[0]	auto[1]	44	1		T271	2		T272	1		T273	3
all_values[5]	auto[0]	auto[1]	auto[0]	18	1		T69	1		T72	2		T273	1
all_values[5]	auto[0]	auto[1]	auto[1]	64	1		T68	1		T69	1		T70	1
all_values[5]	auto[1]	auto[0]	auto[1]	69	1		T69	2		T70	3		T271	3
all_values[5]	auto[1]	auto[1]	auto[1]	57	1		T68	2		T70	1		T72	1
all_values[6]	auto[0]	auto[0]	auto[0]	31	1		T68	1		T69	3		T275	1
all_values[6]	auto[0]	auto[0]	auto[1]	54	1		T68	2		T70	4		T271	1
all_values[6]	auto[0]	auto[1]	auto[0]	19	1		T69	1		T267	2		T283	1
all_values[6]	auto[0]	auto[1]	auto[1]	62	1		T70	2		T72	1		T271	3
all_values[6]	auto[1]	auto[0]	auto[1]	66	1		T70	1		T72	2		T271	2
all_values[6]	auto[1]	auto[1]	auto[1]	49	1		T68	1		T72	1		T271	1
all_values[7]	auto[0]	auto[0]	auto[0]	37	1		T68	1		T70	2		T271	4
all_values[7]	auto[0]	auto[0]	auto[1]	54	1		T70	2		T273	4		T267	2
all_values[7]	auto[0]	auto[1]	auto[0]	19	1		T70	1		T271	1		T272	4
all_values[7]	auto[0]	auto[1]	auto[1]	71	1		T68	1		T69	3		T70	1
all_values[7]	auto[1]	auto[0]	auto[1]	55	1		T72	2		T279	1		T273	2
all_values[7]	auto[1]	auto[1]	auto[1]	45	1		T68	2		T69	1		T70	1
all_values[8]	auto[0]	auto[0]	auto[0]	23	1		T271	1		T267	2		T275	1
all_values[8]	auto[0]	auto[0]	auto[1]	75	1		T68	1		T69	1		T70	1
all_values[8]	auto[0]	auto[1]	auto[0]	10	1		T267	2		T281	3		T284	1
all_values[8]	auto[0]	auto[1]	auto[1]	54	1		T68	2		T69	2		T70	2
all_values[8]	auto[1]	auto[0]	auto[1]	71	1		T68	1		T69	1		T70	4
all_values[8]	auto[1]	auto[1]	auto[1]	48	1		T72	2		T271	3		T279	1
all_values[9]	auto[0]	auto[0]	auto[0]	30	1		T68	3		T70	2		T72	2
all_values[9]	auto[0]	auto[0]	auto[1]	60	1		T70	3		T72	1		T271	1
all_values[9]	auto[0]	auto[1]	auto[0]	17	1		T68	1		T70	1		T273	1
all_values[9]	auto[0]	auto[1]	auto[1]	56	1		T69	2		T271	1		T272	2
all_values[9]	auto[1]	auto[0]	auto[1]	60	1		T69	1		T70	1		T72	1
all_values[9]	auto[1]	auto[1]	auto[1]	58	1		T69	1		T271	3		T272	3
all_values[10]	auto[0]	auto[0]	auto[0]	31	1		T70	1		T271	1		T272	1
all_values[10]	auto[0]	auto[0]	auto[1]	62	1		T69	1		T70	1		T271	2
all_values[10]	auto[0]	auto[1]	auto[0]	18	1		T70	1		T72	1		T274	3
all_values[10]	auto[0]	auto[1]	auto[1]	53	1		T68	2		T70	1		T72	1
all_values[10]	auto[1]	auto[0]	auto[1]	71	1		T68	2		T69	3		T70	1
all_values[10]	auto[1]	auto[1]	auto[1]	46	1		T70	2		T72	1		T271	1
all_values[11]	auto[0]	auto[0]	auto[0]	31	1		T69	3		T72	2		T279	1
all_values[11]	auto[0]	auto[0]	auto[1]	61	1		T68	1		T72	1		T271	2
all_values[11]	auto[0]	auto[1]	auto[0]	22	1		T69	1		T280	1		T274	1
all_values[11]	auto[0]	auto[1]	auto[1]	55	1		T70	3		T271	1		T272	2
all_values[11]	auto[1]	auto[0]	auto[1]	68	1		T68	2		T70	1		T72	1
all_values[11]	auto[1]	auto[1]	auto[1]	44	1		T68	1		T70	3		T272	3
all_values[12]	auto[0]	auto[0]	auto[0]	39	1		T271	1		T273	1		T267	2
all_values[12]	auto[0]	auto[0]	auto[1]	65	1		T69	1		T70	1		T72	1
all_values[12]	auto[0]	auto[1]	auto[0]	26	1		T271	1		T275	2		T274	1
all_values[12]	auto[0]	auto[1]	auto[1]	44	1		T68	3		T70	4		T272	1
all_values[12]	auto[1]	auto[0]	auto[1]	70	1		T68	1		T69	3		T70	1
all_values[12]	auto[1]	auto[1]	auto[1]	37	1		T70	1		T72	1		T271	1
all_values[13]	auto[0]	auto[0]	auto[0]	33	1		T69	3		T70	1		T279	1
all_values[13]	auto[0]	auto[0]	auto[1]	48	1		T68	1		T72	1		T272	3
all_values[13]	auto[0]	auto[1]	auto[0]	14	1		T69	1		T273	2		T267	3
all_values[13]	auto[0]	auto[1]	auto[1]	60	1		T70	1		T271	2		T272	1
all_values[13]	auto[1]	auto[0]	auto[1]	66	1		T68	2		T70	1		T72	2
all_values[13]	auto[1]	auto[1]	auto[1]	60	1		T68	1		T70	4		T72	1
all_values[14]	auto[0]	auto[0]	auto[0]	35	1		T68	1		T271	1		T272	3
all_values[14]	auto[0]	auto[0]	auto[1]	46	1		T69	2		T72	2		T271	3
all_values[14]	auto[0]	auto[1]	auto[0]	13	1		T272	1		T270	2		T285	1
all_values[14]	auto[0]	auto[1]	auto[1]	72	1		T68	2		T69	1		T70	3
all_values[14]	auto[1]	auto[0]	auto[1]	67	1		T70	3		T72	1		T271	2
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T68	1		T69	1		T70	1
all_values[15]	auto[0]	auto[0]	auto[0]	36	1		T271	1		T275	1		T270	1
all_values[15]	auto[0]	auto[0]	auto[1]	62	1		T69	3		T271	1		T272	3
all_values[15]	auto[0]	auto[1]	auto[0]	18	1		T72	2		T271	1		T280	2
all_values[15]	auto[0]	auto[1]	auto[1]	52	1		T68	1		T70	1		T72	1
all_values[15]	auto[1]	auto[0]	auto[1]	58	1		T68	1		T70	5		T271	2
all_values[15]	auto[1]	auto[1]	auto[1]	55	1		T68	2		T69	1		T70	1
all_values[16]	auto[0]	auto[0]	auto[0]	42	1		T68	3		T70	1		T271	1
all_values[16]	auto[0]	auto[0]	auto[1]	53	1		T69	1		T70	4		T272	3
all_values[16]	auto[0]	auto[1]	auto[0]	28	1		T68	1		T69	1		T279	2
all_values[16]	auto[0]	auto[1]	auto[1]	50	1		T69	1		T72	2		T271	1
all_values[16]	auto[1]	auto[0]	auto[1]	50	1		T69	1		T70	1		T72	2
all_values[16]	auto[1]	auto[1]	auto[1]	58	1		T70	1		T271	1		T272	1
all_values[17]	auto[0]	auto[0]	auto[0]	16	1		T72	1		T272	1		T279	1
all_values[17]	auto[0]	auto[0]	auto[1]	51	1		T68	1		T69	1		T70	1
all_values[17]	auto[0]	auto[1]	auto[0]	22	1		T72	3		T286	2		T287	3
all_values[17]	auto[0]	auto[1]	auto[1]	73	1		T68	1		T70	5		T271	3
all_values[17]	auto[1]	auto[0]	auto[1]	63	1		T68	2		T70	1		T271	4
all_values[17]	auto[1]	auto[1]	auto[1]	56	1		T69	3		T272	1		T273	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal