Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.58 96.68 90.82 97.00 60.94 94.71 97.35 96.58


Total test records in report: 1869
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T1787 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1964821938 May 19 01:52:01 PM PDT 24 May 19 01:52:05 PM PDT 24 80007018 ps
T280 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3091185877 May 19 01:51:51 PM PDT 24 May 19 01:51:54 PM PDT 24 20470477 ps
T245 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2001187805 May 19 01:51:50 PM PDT 24 May 19 01:51:53 PM PDT 24 90386929 ps
T1788 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2356865818 May 19 01:52:01 PM PDT 24 May 19 01:52:06 PM PDT 24 113181037 ps
T1789 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.811318663 May 19 01:51:57 PM PDT 24 May 19 01:52:00 PM PDT 24 49391942 ps
T270 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3565496414 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 32704690 ps
T246 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.986587041 May 19 01:51:56 PM PDT 24 May 19 01:51:59 PM PDT 24 101876178 ps
T274 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1796112648 May 19 01:52:03 PM PDT 24 May 19 01:52:08 PM PDT 24 45619141 ps
T224 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.274375301 May 19 01:52:06 PM PDT 24 May 19 01:52:13 PM PDT 24 313159468 ps
T1790 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4029991486 May 19 01:52:13 PM PDT 24 May 19 01:52:21 PM PDT 24 118726898 ps
T253 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.977503213 May 19 01:52:01 PM PDT 24 May 19 01:52:06 PM PDT 24 82969489 ps
T292 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4027970390 May 19 01:52:02 PM PDT 24 May 19 01:52:08 PM PDT 24 217808533 ps
T1791 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1549398370 May 19 01:51:54 PM PDT 24 May 19 01:51:57 PM PDT 24 47401215 ps
T1792 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.192609795 May 19 01:52:04 PM PDT 24 May 19 01:52:13 PM PDT 24 694380641 ps
T1793 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.49903473 May 19 01:52:07 PM PDT 24 May 19 01:52:11 PM PDT 24 60309525 ps
T276 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1424392231 May 19 01:51:59 PM PDT 24 May 19 01:52:02 PM PDT 24 34126583 ps
T268 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.698343957 May 19 01:51:50 PM PDT 24 May 19 01:51:56 PM PDT 24 246840862 ps
T285 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2650619197 May 19 01:52:04 PM PDT 24 May 19 01:52:08 PM PDT 24 34117722 ps
T1794 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1748085187 May 19 01:51:48 PM PDT 24 May 19 01:51:50 PM PDT 24 48814429 ps
T281 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1499322247 May 19 01:52:00 PM PDT 24 May 19 01:52:04 PM PDT 24 30798485 ps
T282 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2388364546 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 33683959 ps
T1795 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2383077988 May 19 01:51:56 PM PDT 24 May 19 01:52:00 PM PDT 24 128122207 ps
T263 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3196820476 May 19 01:51:48 PM PDT 24 May 19 01:51:51 PM PDT 24 110098126 ps
T269 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2695547094 May 19 01:52:00 PM PDT 24 May 19 01:52:06 PM PDT 24 249234103 ps
T1796 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1451694947 May 19 01:51:59 PM PDT 24 May 19 01:52:04 PM PDT 24 188906846 ps
T1797 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1088284392 May 19 01:51:48 PM PDT 24 May 19 01:51:51 PM PDT 24 76457236 ps
T264 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4155165346 May 19 01:51:51 PM PDT 24 May 19 01:52:03 PM PDT 24 758661006 ps
T1798 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1506371048 May 19 01:51:54 PM PDT 24 May 19 01:51:59 PM PDT 24 104220672 ps
T1799 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1228553669 May 19 01:52:01 PM PDT 24 May 19 01:52:05 PM PDT 24 37706762 ps
T1800 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.28590626 May 19 01:51:48 PM PDT 24 May 19 01:51:51 PM PDT 24 78532074 ps
T284 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3925645051 May 19 01:52:04 PM PDT 24 May 19 01:52:09 PM PDT 24 33667907 ps
T286 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.40843373 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 39320157 ps
T1801 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3412843088 May 19 01:52:01 PM PDT 24 May 19 01:52:06 PM PDT 24 145908349 ps
T1802 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3362279692 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 65240113 ps
T283 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4151214515 May 19 01:51:54 PM PDT 24 May 19 01:51:57 PM PDT 24 30775571 ps
T288 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1368668947 May 19 01:51:59 PM PDT 24 May 19 01:52:03 PM PDT 24 270922162 ps
T265 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3154849420 May 19 01:52:08 PM PDT 24 May 19 01:52:13 PM PDT 24 148636366 ps
T266 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1364227972 May 19 01:51:48 PM PDT 24 May 19 01:51:54 PM PDT 24 644435678 ps
T1803 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3118073856 May 19 01:52:09 PM PDT 24 May 19 01:52:14 PM PDT 24 84016735 ps
T287 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4270722779 May 19 01:52:02 PM PDT 24 May 19 01:52:06 PM PDT 24 42846677 ps
T1804 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3884318906 May 19 01:51:57 PM PDT 24 May 19 01:51:59 PM PDT 24 27423504 ps
T1805 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2511006026 May 19 01:51:51 PM PDT 24 May 19 01:51:54 PM PDT 24 60270768 ps
T247 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3494541588 May 19 01:51:44 PM PDT 24 May 19 01:51:53 PM PDT 24 1414237833 ps
T1806 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.728086841 May 19 01:52:00 PM PDT 24 May 19 01:52:03 PM PDT 24 33733315 ps
T1807 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1231155289 May 19 01:51:50 PM PDT 24 May 19 01:51:56 PM PDT 24 292926797 ps
T295 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1943035618 May 19 01:52:13 PM PDT 24 May 19 01:52:23 PM PDT 24 814784730 ps
T289 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3117652275 May 19 01:51:54 PM PDT 24 May 19 01:52:01 PM PDT 24 884585377 ps
T1808 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3003901771 May 19 01:51:52 PM PDT 24 May 19 01:51:57 PM PDT 24 67173660 ps
T1809 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3570582549 May 19 01:51:36 PM PDT 24 May 19 01:51:40 PM PDT 24 557999843 ps
T1810 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2361610897 May 19 01:51:54 PM PDT 24 May 19 01:51:59 PM PDT 24 105752891 ps
T1811 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2027298480 May 19 01:52:00 PM PDT 24 May 19 01:52:03 PM PDT 24 39731696 ps
T1812 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1514825003 May 19 01:51:43 PM PDT 24 May 19 01:51:46 PM PDT 24 281928979 ps
T254 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2885490210 May 19 01:51:50 PM PDT 24 May 19 01:51:54 PM PDT 24 37648755 ps
T1813 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2385993247 May 19 01:51:57 PM PDT 24 May 19 01:51:59 PM PDT 24 56264230 ps
T1814 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3506282225 May 19 01:52:10 PM PDT 24 May 19 01:52:22 PM PDT 24 44015146 ps
T1815 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4083653257 May 19 01:51:57 PM PDT 24 May 19 01:52:01 PM PDT 24 123460544 ps
T1816 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1466566140 May 19 01:52:00 PM PDT 24 May 19 01:52:06 PM PDT 24 311477601 ps
T1817 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4255178337 May 19 01:52:06 PM PDT 24 May 19 01:52:11 PM PDT 24 116593649 ps
T248 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.564530785 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 44058131 ps
T1818 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3868531276 May 19 01:51:46 PM PDT 24 May 19 01:51:49 PM PDT 24 73962404 ps
T290 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1643705595 May 19 01:52:05 PM PDT 24 May 19 01:52:14 PM PDT 24 1402337595 ps
T1819 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1126810861 May 19 01:51:37 PM PDT 24 May 19 01:51:39 PM PDT 24 99237335 ps
T1820 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1826413849 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 26547540 ps
T1821 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2394817354 May 19 01:52:05 PM PDT 24 May 19 01:52:11 PM PDT 24 450896441 ps
T1822 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.471179239 May 19 01:51:54 PM PDT 24 May 19 01:51:59 PM PDT 24 253871544 ps
T1823 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3693742608 May 19 01:51:59 PM PDT 24 May 19 01:52:03 PM PDT 24 69312422 ps
T1824 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3819234116 May 19 01:52:06 PM PDT 24 May 19 01:52:11 PM PDT 24 185633863 ps
T1825 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1564805522 May 19 01:51:55 PM PDT 24 May 19 01:51:58 PM PDT 24 82550002 ps
T1826 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3697431876 May 19 01:51:55 PM PDT 24 May 19 01:52:00 PM PDT 24 91973061 ps
T1827 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2334121231 May 19 01:51:55 PM PDT 24 May 19 01:51:58 PM PDT 24 47831756 ps
T1828 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1062664533 May 19 01:51:53 PM PDT 24 May 19 01:52:01 PM PDT 24 769664773 ps
T1829 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3282753196 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 155898102 ps
T249 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2547590220 May 19 01:51:49 PM PDT 24 May 19 01:51:53 PM PDT 24 151089893 ps
T1830 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2879610789 May 19 01:51:54 PM PDT 24 May 19 01:51:59 PM PDT 24 119978099 ps
T1831 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3747961268 May 19 01:52:33 PM PDT 24 May 19 01:52:34 PM PDT 24 37831615 ps
T1832 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4153976913 May 19 01:52:00 PM PDT 24 May 19 01:52:04 PM PDT 24 28453429 ps
T291 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3179874212 May 19 01:52:12 PM PDT 24 May 19 01:52:23 PM PDT 24 1065361950 ps
T1833 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.991213277 May 19 01:52:01 PM PDT 24 May 19 01:52:06 PM PDT 24 67312371 ps
T1834 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1161047467 May 19 01:52:02 PM PDT 24 May 19 01:52:06 PM PDT 24 34365303 ps
T293 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2986282826 May 19 01:51:42 PM PDT 24 May 19 01:51:49 PM PDT 24 2039353401 ps
T1835 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3452283755 May 19 01:52:09 PM PDT 24 May 19 01:52:14 PM PDT 24 77253507 ps
T1836 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2013446972 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 39232755 ps
T1837 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1262015389 May 19 01:51:53 PM PDT 24 May 19 01:51:59 PM PDT 24 284832863 ps
T1838 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2995552156 May 19 01:52:01 PM PDT 24 May 19 01:52:05 PM PDT 24 28560210 ps
T1839 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3285881450 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 35170058 ps
T250 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2543665902 May 19 01:51:53 PM PDT 24 May 19 01:52:00 PM PDT 24 157979120 ps
T1840 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2679990229 May 19 01:51:56 PM PDT 24 May 19 01:52:00 PM PDT 24 202646063 ps
T1841 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3451593212 May 19 01:51:58 PM PDT 24 May 19 01:52:03 PM PDT 24 155881734 ps
T1842 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1645136402 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 124889777 ps
T251 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3127606157 May 19 01:51:58 PM PDT 24 May 19 01:52:03 PM PDT 24 68091449 ps
T1843 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2917418323 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 44209427 ps
T252 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3547883634 May 19 01:51:46 PM PDT 24 May 19 01:51:54 PM PDT 24 414762240 ps
T1844 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2821694202 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 31250913 ps
T1845 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1146961598 May 19 01:52:07 PM PDT 24 May 19 01:52:12 PM PDT 24 149377360 ps
T1846 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1250108347 May 19 01:52:06 PM PDT 24 May 19 01:52:10 PM PDT 24 42562139 ps
T1847 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1606725040 May 19 01:51:47 PM PDT 24 May 19 01:51:50 PM PDT 24 108509516 ps
T1848 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2042555526 May 19 01:52:00 PM PDT 24 May 19 01:52:03 PM PDT 24 32775086 ps
T1849 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1337948130 May 19 01:51:57 PM PDT 24 May 19 01:52:00 PM PDT 24 87111764 ps
T1850 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3414371609 May 19 01:52:05 PM PDT 24 May 19 01:52:09 PM PDT 24 34154521 ps
T1851 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2031217793 May 19 01:52:01 PM PDT 24 May 19 01:52:05 PM PDT 24 31514809 ps
T1852 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2047079059 May 19 01:52:04 PM PDT 24 May 19 01:52:08 PM PDT 24 51085368 ps
T1853 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2571040771 May 19 01:52:06 PM PDT 24 May 19 01:52:10 PM PDT 24 33628584 ps
T1854 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2559519352 May 19 01:51:55 PM PDT 24 May 19 01:51:59 PM PDT 24 305808085 ps
T1855 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1053656156 May 19 01:51:55 PM PDT 24 May 19 01:51:58 PM PDT 24 40385192 ps
T1856 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3732047726 May 19 01:51:46 PM PDT 24 May 19 01:51:51 PM PDT 24 1362967483 ps
T1857 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2666789245 May 19 01:51:50 PM PDT 24 May 19 01:51:53 PM PDT 24 47010167 ps
T1858 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1773604138 May 19 01:51:47 PM PDT 24 May 19 01:51:53 PM PDT 24 511103916 ps
T294 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2491952527 May 19 01:52:03 PM PDT 24 May 19 01:52:11 PM PDT 24 723360225 ps
T1859 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1224249282 May 19 01:52:04 PM PDT 24 May 19 01:52:10 PM PDT 24 109059108 ps
T1860 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3698882041 May 19 01:51:48 PM PDT 24 May 19 01:51:53 PM PDT 24 125225480 ps
T1861 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1238724299 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 133947349 ps
T1862 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2332133244 May 19 01:52:05 PM PDT 24 May 19 01:52:10 PM PDT 24 27426944 ps
T1863 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3024204377 May 19 01:51:54 PM PDT 24 May 19 01:51:58 PM PDT 24 198690498 ps
T1864 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4042182762 May 19 01:51:52 PM PDT 24 May 19 01:51:56 PM PDT 24 112338043 ps
T1865 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.618230689 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 59800878 ps
T1866 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1525700361 May 19 01:51:48 PM PDT 24 May 19 01:51:50 PM PDT 24 117715165 ps
T1867 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.944471322 May 19 01:52:03 PM PDT 24 May 19 01:52:08 PM PDT 24 117329160 ps
T1868 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.877931712 May 19 01:51:50 PM PDT 24 May 19 01:51:54 PM PDT 24 71044204 ps
T1869 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.279054777 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 36542985 ps

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1384353074
Short name T19
Test name
Test status
Simulation time 8397670648 ps
CPU time 12.9 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204856 kb
Host smart-decb17f0-4059-4508-8ed2-6d648a7806fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13843
53074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1384353074
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3073786214
Short name T271
Test name
Test status
Simulation time 80166827 ps
CPU time 0.72 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203524 kb
Host smart-32fd35c6-854e-4dcf-a940-5b36752b3f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3073786214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3073786214
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3245121352
Short name T14
Test name
Test status
Simulation time 23350277178 ps
CPU time 46.36 seconds
Started May 19 02:02:39 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204796 kb
Host smart-d31c3b7b-bd97-44f9-9846-c10fa4f923ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32451
21352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3245121352
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.392561793
Short name T65
Test name
Test status
Simulation time 229597678 ps
CPU time 2.25 seconds
Started May 19 01:51:51 PM PDT 24
Finished May 19 01:51:56 PM PDT 24
Peak memory 204304 kb
Host smart-658160f6-6651-4117-91cf-d68a8af73073
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=392561793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.392561793
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2482272729
Short name T29
Test name
Test status
Simulation time 8447161254 ps
CPU time 10.91 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:20 PM PDT 24
Peak memory 204804 kb
Host smart-2db9611f-99b4-4cb1-998c-1dc324589f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
72729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2482272729
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2212393017
Short name T103
Test name
Test status
Simulation time 8429453383 ps
CPU time 10.67 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204820 kb
Host smart-8eebb77c-7fa9-4285-8810-2181b3935c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22123
93017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2212393017
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2845837890
Short name T20
Test name
Test status
Simulation time 8424474417 ps
CPU time 12.55 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:43 PM PDT 24
Peak memory 204836 kb
Host smart-872a12a2-be78-43ed-b0f8-2871281aceb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28458
37890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2845837890
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.462870916
Short name T9
Test name
Test status
Simulation time 8389907685 ps
CPU time 11.88 seconds
Started May 19 02:04:54 PM PDT 24
Finished May 19 02:05:07 PM PDT 24
Peak memory 204852 kb
Host smart-1cfb7a8d-95a1-4ea1-8534-3db92972f915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46287
0916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.462870916
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1761892550
Short name T267
Test name
Test status
Simulation time 35210622 ps
CPU time 0.67 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 203660 kb
Host smart-b137ead0-a490-49ac-931b-0f845ea582eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1761892550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1761892550
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1324382580
Short name T331
Test name
Test status
Simulation time 11545464155 ps
CPU time 15.41 seconds
Started May 19 02:01:37 PM PDT 24
Finished May 19 02:01:54 PM PDT 24
Peak memory 204820 kb
Host smart-335665f9-9723-4ae1-b2d9-46ca61de4e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13243
82580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1324382580
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2462252492
Short name T18
Test name
Test status
Simulation time 8374130287 ps
CPU time 11.93 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204832 kb
Host smart-e43a39e9-900b-47e5-a6a0-63370c0cf081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622
52492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2462252492
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3316980398
Short name T121
Test name
Test status
Simulation time 8464860324 ps
CPU time 12.18 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204820 kb
Host smart-cd77e361-3f1c-4332-b67a-ca39fe0e7b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33169
80398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3316980398
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1843776021
Short name T59
Test name
Test status
Simulation time 275551102 ps
CPU time 2.68 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204260 kb
Host smart-ae11719f-c61a-4993-b734-b28184063795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1843776021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1843776021
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2305867021
Short name T35
Test name
Test status
Simulation time 8368486700 ps
CPU time 10.4 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:19 PM PDT 24
Peak memory 204772 kb
Host smart-3c4e65aa-9059-45fc-8702-fba7a9e94a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23058
67021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2305867021
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2108794705
Short name T46
Test name
Test status
Simulation time 8830461398 ps
CPU time 14.95 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:15 PM PDT 24
Peak memory 204816 kb
Host smart-3eced738-d4b3-42f5-8104-8005a4c770ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21087
94705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2108794705
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2214135379
Short name T38
Test name
Test status
Simulation time 8413014228 ps
CPU time 11.51 seconds
Started May 19 02:03:42 PM PDT 24
Finished May 19 02:03:55 PM PDT 24
Peak memory 204752 kb
Host smart-7ac1fbc3-ed32-4cfb-aa38-ec44ec52e985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22141
35379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2214135379
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2001187805
Short name T245
Test name
Test status
Simulation time 90386929 ps
CPU time 1 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 204236 kb
Host smart-67c9471a-0583-4589-86a2-c312ad193938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2001187805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2001187805
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2165174520
Short name T57
Test name
Test status
Simulation time 181289388 ps
CPU time 1.01 seconds
Started May 19 02:00:52 PM PDT 24
Finished May 19 02:00:54 PM PDT 24
Peak memory 220484 kb
Host smart-554c6451-470c-49cd-9f2b-13514172674b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2165174520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2165174520
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1451565202
Short name T72
Test name
Test status
Simulation time 29164638 ps
CPU time 0.64 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203528 kb
Host smart-fc6a54ef-fd5f-494b-a414-9de06b0985d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1451565202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1451565202
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.4220170849
Short name T54
Test name
Test status
Simulation time 8387686239 ps
CPU time 10.53 seconds
Started May 19 02:05:04 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 204732 kb
Host smart-254ee3d1-7413-4fc0-95b1-b75b746c02d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
70849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.4220170849
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3594356151
Short name T496
Test name
Test status
Simulation time 8412839649 ps
CPU time 12.29 seconds
Started May 19 02:02:30 PM PDT 24
Finished May 19 02:02:43 PM PDT 24
Peak memory 204752 kb
Host smart-db28544b-8825-45bb-9392-b12a93e200ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
56151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3594356151
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1584494478
Short name T1
Test name
Test status
Simulation time 50835832 ps
CPU time 0.87 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 204124 kb
Host smart-f8047e38-5858-46c2-9615-fb1b8bf174a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1584494478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1584494478
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2388364546
Short name T282
Test name
Test status
Simulation time 33683959 ps
CPU time 0.69 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203664 kb
Host smart-bb5a4d90-e1f8-4864-8600-9041b667352a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2388364546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2388364546
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2455218585
Short name T431
Test name
Test status
Simulation time 8361872872 ps
CPU time 11.59 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:12 PM PDT 24
Peak memory 204804 kb
Host smart-22883a4e-723a-494b-8b75-c8399f22557d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24552
18585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2455218585
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1943035618
Short name T295
Test name
Test status
Simulation time 814784730 ps
CPU time 4.98 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 204284 kb
Host smart-12d3d0d1-7d96-49d4-9f77-037090c43d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1943035618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1943035618
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/13.usbdev_enable.1893971811
Short name T381
Test name
Test status
Simulation time 8373866487 ps
CPU time 12.7 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204872 kb
Host smart-6ebd2585-cea1-46a4-944e-2a872ccec0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
71811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1893971811
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.274375301
Short name T224
Test name
Test status
Simulation time 313159468 ps
CPU time 3.64 seconds
Started May 19 01:52:06 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 204288 kb
Host smart-170f11ae-8997-4737-b3b7-91c40d73ef8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=274375301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.274375301
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2986282826
Short name T293
Test name
Test status
Simulation time 2039353401 ps
CPU time 6.43 seconds
Started May 19 01:51:42 PM PDT 24
Finished May 19 01:51:49 PM PDT 24
Peak memory 204276 kb
Host smart-cd0a6444-05bc-40f6-910e-3b566c35f1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2986282826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2986282826
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2394817354
Short name T1821
Test name
Test status
Simulation time 450896441 ps
CPU time 2.81 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 204256 kb
Host smart-c4018046-a03f-4ba6-b884-de1f0b6d9e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2394817354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2394817354
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3362279692
Short name T1802
Test name
Test status
Simulation time 65240113 ps
CPU time 0.7 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203684 kb
Host smart-5acdfca7-1eee-46f1-a4d2-201f76c7f3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3362279692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3362279692
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3156759205
Short name T256
Test name
Test status
Simulation time 143676229 ps
CPU time 1.63 seconds
Started May 19 01:51:52 PM PDT 24
Finished May 19 01:51:56 PM PDT 24
Peak memory 204172 kb
Host smart-6cba8d5e-55b3-4341-842d-b5c1bb045bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3156759205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3156759205
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3498250540
Short name T114
Test name
Test status
Simulation time 27404082938 ps
CPU time 49.68 seconds
Started May 19 02:02:18 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204796 kb
Host smart-1376a700-49e2-4d40-a49f-720ec0412788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34982
50540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3498250540
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1697662018
Short name T213
Test name
Test status
Simulation time 5108011126 ps
CPU time 33.52 seconds
Started May 19 02:00:49 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204788 kb
Host smart-62f1c043-8775-41ce-bba6-302521c04705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
62018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1697662018
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3890661839
Short name T62
Test name
Test status
Simulation time 133997264 ps
CPU time 0.94 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 204136 kb
Host smart-3c2df104-6498-4b23-940e-626ef8068bc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3890661839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3890661839
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2046473492
Short name T230
Test name
Test status
Simulation time 9129739848 ps
CPU time 13.41 seconds
Started May 19 02:01:51 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204804 kb
Host smart-d97b6c32-7f98-4642-b2c0-9b21c346ba15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20464
73492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2046473492
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.723449531
Short name T215
Test name
Test status
Simulation time 586633994 ps
CPU time 2.66 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 204232 kb
Host smart-8eadae95-9c15-48bc-992c-7526a5a63a50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=723449531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.723449531
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2491688782
Short name T184
Test name
Test status
Simulation time 9503576028 ps
CPU time 14.5 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204884 kb
Host smart-425cc5c7-b01f-4397-bfd9-14f618438d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24916
88782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2491688782
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1163551920
Short name T12
Test name
Test status
Simulation time 8366602969 ps
CPU time 11.08 seconds
Started May 19 02:00:57 PM PDT 24
Finished May 19 02:01:09 PM PDT 24
Peak memory 204812 kb
Host smart-a3aa02c4-5192-42e1-a8b8-66d0d84f7cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635
51920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1163551920
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3558248954
Short name T51
Test name
Test status
Simulation time 8414744487 ps
CPU time 12.82 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204852 kb
Host smart-f9ae51b1-aaf1-4faa-8141-ddedbe236811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582
48954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3558248954
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2875208168
Short name T199
Test name
Test status
Simulation time 8399214442 ps
CPU time 11.25 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 204788 kb
Host smart-3928a935-5b76-460a-abcb-3d06531fab92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28752
08168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2875208168
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3498150650
Short name T157
Test name
Test status
Simulation time 8429980297 ps
CPU time 11.49 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204836 kb
Host smart-2dce730d-3ced-4c42-bfe7-71ca9057f859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34981
50650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3498150650
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1624534192
Short name T2
Test name
Test status
Simulation time 8382529632 ps
CPU time 13.09 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204820 kb
Host smart-beb5f044-af45-403d-8ea4-1f26df2e0332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
34192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1624534192
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.437870272
Short name T193
Test name
Test status
Simulation time 9563907469 ps
CPU time 13.4 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204808 kb
Host smart-7d957bbf-26b1-4924-b8a8-1c52ccae0b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43787
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.437870272
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1195350167
Short name T190
Test name
Test status
Simulation time 8419726407 ps
CPU time 10.07 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 204832 kb
Host smart-27c0420f-4bc0-4f1f-a00a-ea5d16210782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11953
50167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1195350167
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.857403145
Short name T606
Test name
Test status
Simulation time 8385699497 ps
CPU time 14.17 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204776 kb
Host smart-d313d63a-d6c9-4e54-811c-640394d9f575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85740
3145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.857403145
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3966447175
Short name T201
Test name
Test status
Simulation time 8378673554 ps
CPU time 10.31 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204788 kb
Host smart-c8a13fb8-a354-44c8-a823-1cbb7e3633dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
47175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3966447175
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3345722408
Short name T50
Test name
Test status
Simulation time 8376003393 ps
CPU time 10.61 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:17 PM PDT 24
Peak memory 204808 kb
Host smart-ec3dd2c6-a0a2-4b90-8dfd-bfba8e9ed675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457
22408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3345722408
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.4000974854
Short name T198
Test name
Test status
Simulation time 8420976187 ps
CPU time 10.5 seconds
Started May 19 02:03:56 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204836 kb
Host smart-541b3983-d4df-41f8-9a96-aa3c67ca2766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40009
74854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.4000974854
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1784524403
Short name T210
Test name
Test status
Simulation time 8395874000 ps
CPU time 11.05 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204820 kb
Host smart-4e3b9d5d-5fb6-4452-80c3-ca1c0b600c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17845
24403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1784524403
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.752920715
Short name T164
Test name
Test status
Simulation time 8399790347 ps
CPU time 12.08 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204876 kb
Host smart-f45a43a3-be40-403b-9c5e-b98974256102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75292
0715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.752920715
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.155472876
Short name T301
Test name
Test status
Simulation time 8390699682 ps
CPU time 11.91 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 205076 kb
Host smart-46dda6e2-1fa0-463d-afa1-13d87b99c91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15547
2876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.155472876
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.144860201
Short name T87
Test name
Test status
Simulation time 8395870572 ps
CPU time 12.09 seconds
Started May 19 02:00:46 PM PDT 24
Finished May 19 02:00:59 PM PDT 24
Peak memory 204832 kb
Host smart-a6d8449b-f53d-4313-a05f-b032c9ae7359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.144860201
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.791347673
Short name T205
Test name
Test status
Simulation time 9521006228 ps
CPU time 12.71 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204832 kb
Host smart-2fdc4f0a-41dc-4209-9bb6-d587b966b247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79134
7673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.791347673
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3604714111
Short name T222
Test name
Test status
Simulation time 129304011 ps
CPU time 3.2 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:51:55 PM PDT 24
Peak memory 204356 kb
Host smart-826947bb-bdec-4931-9438-378f8775f312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3604714111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3604714111
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3324606663
Short name T1695
Test name
Test status
Simulation time 8412818896 ps
CPU time 11.62 seconds
Started May 19 02:00:51 PM PDT 24
Finished May 19 02:01:03 PM PDT 24
Peak memory 204848 kb
Host smart-a352f0f1-f1a4-4075-8356-fc4b32fd0510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246
06663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3324606663
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1204590992
Short name T96
Test name
Test status
Simulation time 8363498993 ps
CPU time 11.32 seconds
Started May 19 02:00:51 PM PDT 24
Finished May 19 02:01:03 PM PDT 24
Peak memory 204756 kb
Host smart-912163bb-ee74-4e77-a2b2-ec14a860bb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12045
90992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1204590992
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.514207375
Short name T1690
Test name
Test status
Simulation time 8389290077 ps
CPU time 12.14 seconds
Started May 19 02:00:53 PM PDT 24
Finished May 19 02:01:06 PM PDT 24
Peak memory 204756 kb
Host smart-628c3d99-7481-4ad3-b83b-13f2a53abd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51420
7375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.514207375
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3512819884
Short name T144
Test name
Test status
Simulation time 8431948220 ps
CPU time 10.88 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204832 kb
Host smart-db704c2e-56c5-46a5-bfb4-17df6cbe9d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35128
19884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3512819884
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3741383067
Short name T127
Test name
Test status
Simulation time 8407313550 ps
CPU time 11.71 seconds
Started May 19 02:01:52 PM PDT 24
Finished May 19 02:02:04 PM PDT 24
Peak memory 204752 kb
Host smart-713e9ebe-0932-4c53-8ab9-6ccb8c1af53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37413
83067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3741383067
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1373127110
Short name T134
Test name
Test status
Simulation time 8432462700 ps
CPU time 12.37 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204812 kb
Host smart-c7efe435-67f0-4495-97c6-b904ad6769a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13731
27110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1373127110
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2168854561
Short name T151
Test name
Test status
Simulation time 8416124811 ps
CPU time 11.33 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204872 kb
Host smart-0441b56f-4c0f-406c-a61b-81a71359fdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21688
54561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2168854561
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3773979280
Short name T148
Test name
Test status
Simulation time 8520136191 ps
CPU time 11.6 seconds
Started May 19 02:02:11 PM PDT 24
Finished May 19 02:02:27 PM PDT 24
Peak memory 205084 kb
Host smart-56d4ec8b-d5c2-466c-9d89-a92684d8936b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37739
79280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3773979280
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1461179776
Short name T1380
Test name
Test status
Simulation time 9644942308 ps
CPU time 13.26 seconds
Started May 19 02:02:11 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204848 kb
Host smart-6aa9a0f6-adbd-49d3-9337-c55032d4a7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611
79776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1461179776
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2934820638
Short name T143
Test name
Test status
Simulation time 8458284339 ps
CPU time 10.63 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204860 kb
Host smart-783cd754-4741-49d9-a9e3-7e16f8db4c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348
20638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2934820638
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4152583141
Short name T1365
Test name
Test status
Simulation time 8420642484 ps
CPU time 13.19 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:46 PM PDT 24
Peak memory 204796 kb
Host smart-1e8e787a-68df-4821-b4db-71a3337ac52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
83141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4152583141
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3286200634
Short name T122
Test name
Test status
Simulation time 8409401088 ps
CPU time 10.32 seconds
Started May 19 02:02:31 PM PDT 24
Finished May 19 02:02:42 PM PDT 24
Peak memory 204756 kb
Host smart-a950101b-df9e-4693-bbe2-680bf48d2856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32862
00634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3286200634
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1812728830
Short name T126
Test name
Test status
Simulation time 8442155066 ps
CPU time 11.47 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204780 kb
Host smart-d94798f9-c258-43e3-8e62-7ed9ffb5bf74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
28830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1812728830
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2894588169
Short name T138
Test name
Test status
Simulation time 8455111576 ps
CPU time 11.51 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204756 kb
Host smart-870b355c-7bd5-47e6-9536-229f7bb8deb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28945
88169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2894588169
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2734526137
Short name T211
Test name
Test status
Simulation time 8391596654 ps
CPU time 10.51 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204804 kb
Host smart-747e9879-41f2-49b1-b554-394117de4d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27345
26137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2734526137
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.270561258
Short name T135
Test name
Test status
Simulation time 8481956792 ps
CPU time 11.62 seconds
Started May 19 02:04:10 PM PDT 24
Finished May 19 02:04:22 PM PDT 24
Peak memory 204804 kb
Host smart-aef081e9-0d6b-4f86-8c05-47ac8a5740d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27056
1258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.270561258
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.251908173
Short name T241
Test name
Test status
Simulation time 304286179 ps
CPU time 3.67 seconds
Started May 19 01:51:47 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 204292 kb
Host smart-48c50141-8fae-4885-ab24-d996fbad28bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=251908173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.251908173
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3494541588
Short name T247
Test name
Test status
Simulation time 1414237833 ps
CPU time 8.34 seconds
Started May 19 01:51:44 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 204256 kb
Host smart-bc46c97d-85d7-4189-87c4-61a632604dbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3494541588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3494541588
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.902755575
Short name T242
Test name
Test status
Simulation time 145379455 ps
CPU time 0.83 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 204128 kb
Host smart-82453077-130b-42bb-bcfb-6139788a0998
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=902755575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.902755575
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1126810861
Short name T1819
Test name
Test status
Simulation time 99237335 ps
CPU time 1.35 seconds
Started May 19 01:51:37 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 212488 kb
Host smart-29f595a3-2b43-422b-9f98-88c45f0d03f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126810861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1126810861
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1748085187
Short name T1794
Test name
Test status
Simulation time 48814429 ps
CPU time 0.81 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 204168 kb
Host smart-55c125fe-e91b-4dc5-b96a-9f4ef484aabf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1748085187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1748085187
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1346595131
Short name T70
Test name
Test status
Simulation time 63410133 ps
CPU time 0.75 seconds
Started May 19 01:51:42 PM PDT 24
Finished May 19 01:51:43 PM PDT 24
Peak memory 203684 kb
Host smart-82866e3f-db3a-4baa-8814-b9b9b17b6ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346595131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1346595131
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3286033099
Short name T244
Test name
Test status
Simulation time 44243680 ps
CPU time 1.43 seconds
Started May 19 01:51:46 PM PDT 24
Finished May 19 01:51:48 PM PDT 24
Peak memory 212456 kb
Host smart-71f4086b-ef23-43d7-a0a9-668ae4b9278d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3286033099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3286033099
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1514825003
Short name T1812
Test name
Test status
Simulation time 281928979 ps
CPU time 2.6 seconds
Started May 19 01:51:43 PM PDT 24
Finished May 19 01:51:46 PM PDT 24
Peak memory 204256 kb
Host smart-5f38db28-9957-4382-864f-0a594e3e25f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1514825003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1514825003
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.68255869
Short name T1784
Test name
Test status
Simulation time 51303568 ps
CPU time 1.08 seconds
Started May 19 01:51:40 PM PDT 24
Finished May 19 01:51:42 PM PDT 24
Peak memory 204156 kb
Host smart-3c7b3884-623f-4990-a104-d893318f23ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=68255869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.68255869
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2651356816
Short name T1779
Test name
Test status
Simulation time 162572673 ps
CPU time 2.06 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:07 PM PDT 24
Peak memory 204188 kb
Host smart-6032ed96-041f-4aeb-9ed9-29cd827d2590
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2651356816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2651356816
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1062664533
Short name T1828
Test name
Test status
Simulation time 769664773 ps
CPU time 4.76 seconds
Started May 19 01:51:53 PM PDT 24
Finished May 19 01:52:01 PM PDT 24
Peak memory 204244 kb
Host smart-3378b4a3-8af9-4923-84c9-efa3d0d3fc2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1062664533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1062664533
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.564531330
Short name T73
Test name
Test status
Simulation time 44069678 ps
CPU time 0.79 seconds
Started May 19 01:51:37 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 204124 kb
Host smart-d73fd0cf-c956-4fc9-b22e-81e4aaff4e5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=564531330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.564531330
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3868531276
Short name T1818
Test name
Test status
Simulation time 73962404 ps
CPU time 2.12 seconds
Started May 19 01:51:46 PM PDT 24
Finished May 19 01:51:49 PM PDT 24
Peak memory 212448 kb
Host smart-af3a70a7-18cd-4040-a07d-9a34469f5836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868531276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3868531276
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4286759400
Short name T1782
Test name
Test status
Simulation time 36158266 ps
CPU time 0.79 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 204132 kb
Host smart-2f9c8685-ffda-457c-ae8f-d06db1442701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4286759400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4286759400
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1525700361
Short name T1866
Test name
Test status
Simulation time 117715165 ps
CPU time 0.75 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 203652 kb
Host smart-bebad236-3a69-47eb-9c93-daf5e40cb04d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1525700361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1525700361
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2547590220
Short name T249
Test name
Test status
Simulation time 151089893 ps
CPU time 2.2 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 212408 kb
Host smart-fd39dc1a-7b14-486e-89c7-375e9273e4c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2547590220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2547590220
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.192609795
Short name T1792
Test name
Test status
Simulation time 694380641 ps
CPU time 4.68 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 204196 kb
Host smart-ba6cd8b1-3b19-40db-8da7-6207298bfbbd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=192609795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.192609795
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1088284392
Short name T1797
Test name
Test status
Simulation time 76457236 ps
CPU time 1.83 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 204280 kb
Host smart-9c98f65d-afbb-486e-b046-7068de6c0f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1088284392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1088284392
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3570582549
Short name T1809
Test name
Test status
Simulation time 557999843 ps
CPU time 2.87 seconds
Started May 19 01:51:36 PM PDT 24
Finished May 19 01:51:40 PM PDT 24
Peak memory 204300 kb
Host smart-e626da6f-1eea-47fe-a21a-021e2fba8c28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3570582549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3570582549
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1337948130
Short name T1849
Test name
Test status
Simulation time 87111764 ps
CPU time 1.22 seconds
Started May 19 01:51:57 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 213652 kb
Host smart-85b6c554-8f14-45b9-b197-425b63f9b86f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337948130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1337948130
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2332133244
Short name T1862
Test name
Test status
Simulation time 27426944 ps
CPU time 0.81 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 204132 kb
Host smart-6c4e4ee9-e3b0-4098-958b-c482a58dbe71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2332133244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2332133244
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1053656156
Short name T1855
Test name
Test status
Simulation time 40385192 ps
CPU time 0.67 seconds
Started May 19 01:51:55 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 203672 kb
Host smart-684732d4-b251-47e7-aa8f-2b3fda1947f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1053656156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1053656156
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2559519352
Short name T1854
Test name
Test status
Simulation time 305808085 ps
CPU time 1.69 seconds
Started May 19 01:51:55 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204200 kb
Host smart-9e51626d-6edf-4c66-aa06-b1ae96bfe20b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2559519352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2559519352
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2695547094
Short name T269
Test name
Test status
Simulation time 249234103 ps
CPU time 2.67 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204288 kb
Host smart-0c4f4770-29a4-411e-bab0-52aa3959b383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2695547094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2695547094
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2860085095
Short name T61
Test name
Test status
Simulation time 84296035 ps
CPU time 2.33 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 212540 kb
Host smart-ccba29b6-a753-406c-91b5-42af59d7999e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860085095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2860085095
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1964821938
Short name T1787
Test name
Test status
Simulation time 80007018 ps
CPU time 0.98 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 204288 kb
Host smart-01c48de4-1ed8-4c33-a855-e09d8a051790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1964821938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1964821938
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1499322247
Short name T281
Test name
Test status
Simulation time 30798485 ps
CPU time 0.66 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:04 PM PDT 24
Peak memory 203740 kb
Host smart-1fb718da-8e3c-40eb-80d7-2f2d2ec74bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1499322247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1499322247
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3536822761
Short name T63
Test name
Test status
Simulation time 107134073 ps
CPU time 1.17 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 204304 kb
Host smart-ea6f4333-e65b-4095-a718-cc47c21f457b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3536822761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3536822761
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2555436397
Short name T226
Test name
Test status
Simulation time 216117727 ps
CPU time 2.87 seconds
Started May 19 01:51:59 PM PDT 24
Finished May 19 01:52:04 PM PDT 24
Peak memory 204260 kb
Host smart-9e4fd284-2f23-405f-95ae-32f7555a7c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555436397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2555436397
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2679990229
Short name T1840
Test name
Test status
Simulation time 202646063 ps
CPU time 2.12 seconds
Started May 19 01:51:56 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 212544 kb
Host smart-e7a7ed08-ccbc-428f-9501-4667db9b6d82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679990229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2679990229
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3333905760
Short name T240
Test name
Test status
Simulation time 80877601 ps
CPU time 1 seconds
Started May 19 01:51:56 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204288 kb
Host smart-4a3b89da-3678-49c2-9ec8-2a9b6bccec22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3333905760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3333905760
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2821694202
Short name T1844
Test name
Test status
Simulation time 31250913 ps
CPU time 0.65 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203692 kb
Host smart-c7fe6917-259d-49c4-bd21-70a0b198eeab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2821694202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2821694202
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2383077988
Short name T1795
Test name
Test status
Simulation time 128122207 ps
CPU time 1.47 seconds
Started May 19 01:51:56 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 204292 kb
Host smart-9947d685-709d-4abf-aaad-af2def265168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2383077988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2383077988
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3767725673
Short name T223
Test name
Test status
Simulation time 116293016 ps
CPU time 1.34 seconds
Started May 19 01:52:17 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 204228 kb
Host smart-2cab78cd-4bfc-4e5c-b027-63d92e493b20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3767725673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3767725673
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3814880042
Short name T120
Test name
Test status
Simulation time 63410770 ps
CPU time 1.72 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 212544 kb
Host smart-c1a7b03f-19b2-4e05-9fbf-02db883247cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814880042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3814880042
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2511006026
Short name T1805
Test name
Test status
Simulation time 60270768 ps
CPU time 0.91 seconds
Started May 19 01:51:51 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 204308 kb
Host smart-2205a0ee-08fd-4722-b03a-278c006009e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2511006026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2511006026
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1238724299
Short name T1861
Test name
Test status
Simulation time 133947349 ps
CPU time 1.09 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 204244 kb
Host smart-d8478f0f-8482-4a87-bc19-8a7ae7bbd753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1238724299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1238724299
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3493807569
Short name T217
Test name
Test status
Simulation time 168398204 ps
CPU time 2.1 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204448 kb
Host smart-0e52212a-43bd-4f2b-a0f8-01447264ee1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3493807569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3493807569
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3249867892
Short name T118
Test name
Test status
Simulation time 488582613 ps
CPU time 3.97 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 204172 kb
Host smart-e1658578-e37d-403d-8efa-2d808b752fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3249867892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3249867892
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2727092894
Short name T117
Test name
Test status
Simulation time 77525966 ps
CPU time 1.25 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 212560 kb
Host smart-5685165e-9d7c-4e81-87bf-4ec485e61455
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727092894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2727092894
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2493541608
Short name T257
Test name
Test status
Simulation time 51852901 ps
CPU time 0.79 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:01 PM PDT 24
Peak memory 204112 kb
Host smart-0b5232cf-e197-4586-8523-6d0925ca3ba7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2493541608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2493541608
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.944471322
Short name T1867
Test name
Test status
Simulation time 117329160 ps
CPU time 0.74 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 203684 kb
Host smart-b8ff2a52-c2b0-46f3-a1d7-69a5afd65688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=944471322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.944471322
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2356865818
Short name T1788
Test name
Test status
Simulation time 113181037 ps
CPU time 1.52 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204320 kb
Host smart-b920c2d0-4e89-46c4-a429-f64cd8c87584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2356865818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2356865818
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3451593212
Short name T1841
Test name
Test status
Simulation time 155881734 ps
CPU time 2.16 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 204464 kb
Host smart-aa8aa179-c314-4dfe-bea6-ea30697bf6d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3451593212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3451593212
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1368668947
Short name T288
Test name
Test status
Simulation time 270922162 ps
CPU time 2.43 seconds
Started May 19 01:51:59 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 204208 kb
Host smart-7878eb45-c0d7-487b-98ce-c187d178f393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1368668947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1368668947
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.49903473
Short name T1793
Test name
Test status
Simulation time 60309525 ps
CPU time 1.65 seconds
Started May 19 01:52:07 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 212456 kb
Host smart-a83a1d12-62e5-4bbe-929d-2a209dff798e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49903473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev
_csr_mem_rw_with_rand_reset.49903473
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.564530785
Short name T248
Test name
Test status
Simulation time 44058131 ps
CPU time 0.82 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 204120 kb
Host smart-2a32ca2a-5898-4e5f-8ec6-f415fc44ac0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=564530785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.564530785
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1826413849
Short name T1820
Test name
Test status
Simulation time 26547540 ps
CPU time 0.61 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203672 kb
Host smart-10053fad-e779-47de-be29-444933b2cd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1826413849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1826413849
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3824894123
Short name T64
Test name
Test status
Simulation time 88987492 ps
CPU time 1.14 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 204256 kb
Host smart-07f0d679-41db-401b-8708-c2ae1804d482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3824894123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3824894123
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3412843088
Short name T1801
Test name
Test status
Simulation time 145908349 ps
CPU time 1.96 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204304 kb
Host smart-ade78fca-99f3-4c48-ac81-001df9989e92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412843088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3412843088
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3356813564
Short name T60
Test name
Test status
Simulation time 73825157 ps
CPU time 1.18 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:01 PM PDT 24
Peak memory 212532 kb
Host smart-0e4d50ae-448f-4199-9e17-f55d65ec0b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356813564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3356813564
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.986587041
Short name T246
Test name
Test status
Simulation time 101876178 ps
CPU time 0.98 seconds
Started May 19 01:51:56 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204260 kb
Host smart-564dca39-04a8-4727-9414-fe5dac0a59d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=986587041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.986587041
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4153976913
Short name T1832
Test name
Test status
Simulation time 28453429 ps
CPU time 0.63 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:04 PM PDT 24
Peak memory 203744 kb
Host smart-a18bc045-794b-40c6-9aef-013c63a82a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4153976913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4153976913
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.469437668
Short name T1783
Test name
Test status
Simulation time 65301830 ps
CPU time 1.4 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:07 PM PDT 24
Peak memory 204232 kb
Host smart-aa2ccc2f-285a-4993-855b-8af48e3a7c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=469437668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.469437668
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1146961598
Short name T1845
Test name
Test status
Simulation time 149377360 ps
CPU time 1.96 seconds
Started May 19 01:52:07 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 204280 kb
Host smart-02adcd00-90ad-4ff3-8feb-6a5432e27a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1146961598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1146961598
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3371290034
Short name T228
Test name
Test status
Simulation time 951741212 ps
CPU time 5.44 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 204272 kb
Host smart-b66ea80c-7702-4f70-88e7-81175821ba1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3371290034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3371290034
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3154849420
Short name T265
Test name
Test status
Simulation time 148636366 ps
CPU time 1.54 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 212440 kb
Host smart-253a60bf-19e4-416a-a801-d767804efed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154849420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3154849420
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1528732758
Short name T116
Test name
Test status
Simulation time 37294822 ps
CPU time 0.86 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 204084 kb
Host smart-f4eb790d-c6cb-4059-85e0-32c9ce2e4259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1528732758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1528732758
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.40843373
Short name T286
Test name
Test status
Simulation time 39320157 ps
CPU time 0.64 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203700 kb
Host smart-8489f19e-7a51-48ee-ac46-42b8d0de68b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=40843373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.40843373
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3819234116
Short name T1824
Test name
Test status
Simulation time 185633863 ps
CPU time 1.64 seconds
Started May 19 01:52:06 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 204208 kb
Host smart-68c8a4ce-c336-4459-a109-8bc42e526199
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3819234116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3819234116
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2669525657
Short name T221
Test name
Test status
Simulation time 58042460 ps
CPU time 1.58 seconds
Started May 19 01:51:57 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 204320 kb
Host smart-affa8f4d-b6db-45e4-b741-02878157c333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2669525657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2669525657
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2491952527
Short name T294
Test name
Test status
Simulation time 723360225 ps
CPU time 4.91 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 204284 kb
Host smart-0dced91f-51d6-4562-a757-608f66b162b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2491952527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2491952527
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.991213277
Short name T1833
Test name
Test status
Simulation time 67312371 ps
CPU time 1.78 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 212472 kb
Host smart-3844f6a9-fda2-4715-96cc-b9fdb3bc50a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991213277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.991213277
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3959309542
Short name T243
Test name
Test status
Simulation time 68346895 ps
CPU time 0.96 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 204288 kb
Host smart-fa6eaa72-6215-4508-8cd4-e22805714a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3959309542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3959309542
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1218298199
Short name T272
Test name
Test status
Simulation time 54891582 ps
CPU time 0.68 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203636 kb
Host smart-cd1061fb-edf7-4cee-90dd-b6da5c788a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1218298199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1218298199
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2764158126
Short name T258
Test name
Test status
Simulation time 77336544 ps
CPU time 1.12 seconds
Started May 19 01:51:55 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 204220 kb
Host smart-d6c04f64-520a-484b-8eef-53b4a496114f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2764158126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2764158126
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.908389699
Short name T225
Test name
Test status
Simulation time 244941562 ps
CPU time 2.1 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 204320 kb
Host smart-152b91f4-94b5-4e02-b364-02864f444fec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=908389699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.908389699
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3179874212
Short name T291
Test name
Test status
Simulation time 1065361950 ps
CPU time 4.81 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 204240 kb
Host smart-163d2e3c-3165-4d96-8257-d8c0629341fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3179874212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3179874212
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3118073856
Short name T1803
Test name
Test status
Simulation time 84016735 ps
CPU time 1.33 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 213916 kb
Host smart-637f8b24-5005-4e08-9197-087266c01e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118073856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3118073856
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.977503213
Short name T253
Test name
Test status
Simulation time 82969489 ps
CPU time 1.04 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204240 kb
Host smart-9e63ad75-443d-41f1-9b20-adde45005592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=977503213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.977503213
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2995552156
Short name T1838
Test name
Test status
Simulation time 28560210 ps
CPU time 0.69 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 203636 kb
Host smart-7fc03d9a-0640-4082-823f-e58afaca8b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2995552156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2995552156
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3282753196
Short name T1829
Test name
Test status
Simulation time 155898102 ps
CPU time 1.52 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 204004 kb
Host smart-4c0f1204-54b2-4c27-838f-c2e581b66fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3282753196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3282753196
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2138397333
Short name T220
Test name
Test status
Simulation time 126955773 ps
CPU time 1.51 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 204316 kb
Host smart-7a08df17-a3bf-4917-bed0-1115330af47a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2138397333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2138397333
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.240900031
Short name T262
Test name
Test status
Simulation time 343056781 ps
CPU time 2.88 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 204292 kb
Host smart-7c19bae0-fa5b-4011-aab7-da9d8ba9601c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=240900031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.240900031
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3024204377
Short name T1863
Test name
Test status
Simulation time 198690498 ps
CPU time 2.13 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 204276 kb
Host smart-cbb1b618-042c-45e3-a21f-81c1c765f7b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3024204377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3024204377
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3547883634
Short name T252
Test name
Test status
Simulation time 414762240 ps
CPU time 7.39 seconds
Started May 19 01:51:46 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 204288 kb
Host smart-12a47612-6587-4e4b-92dc-e02f0a5e3425
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3547883634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3547883634
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3500097504
Short name T71
Test name
Test status
Simulation time 38663863 ps
CPU time 0.77 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:04 PM PDT 24
Peak memory 204100 kb
Host smart-d52e8672-3f22-4628-b786-14d5b02d10da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3500097504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3500097504
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3003901771
Short name T1808
Test name
Test status
Simulation time 67173660 ps
CPU time 1.73 seconds
Started May 19 01:51:52 PM PDT 24
Finished May 19 01:51:57 PM PDT 24
Peak memory 212488 kb
Host smart-00516156-d194-419a-ade5-170cf9745130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003901771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3003901771
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2590115879
Short name T255
Test name
Test status
Simulation time 30686009 ps
CPU time 0.83 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:51:52 PM PDT 24
Peak memory 204120 kb
Host smart-970e8052-a8eb-453a-81da-568a09bc4c56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2590115879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2590115879
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1211400700
Short name T273
Test name
Test status
Simulation time 27362094 ps
CPU time 0.66 seconds
Started May 19 01:51:45 PM PDT 24
Finished May 19 01:51:46 PM PDT 24
Peak memory 203748 kb
Host smart-a2d03533-65bb-4688-90ba-c587370f2703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1211400700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1211400700
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1224249282
Short name T1859
Test name
Test status
Simulation time 109059108 ps
CPU time 2.16 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 212468 kb
Host smart-46c614c4-90d4-4ffc-ba4d-dc2202c349c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1224249282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1224249282
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2361610897
Short name T1810
Test name
Test status
Simulation time 105752891 ps
CPU time 2.28 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204264 kb
Host smart-e2b43c5b-df0e-4b0a-8591-7d0b6323365d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2361610897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2361610897
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3119246604
Short name T214
Test name
Test status
Simulation time 163610224 ps
CPU time 1.65 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 204264 kb
Host smart-d3c72f2b-cf03-41a4-9d2f-5dbb54a51cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3119246604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3119246604
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2879610789
Short name T1830
Test name
Test status
Simulation time 119978099 ps
CPU time 1.82 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204256 kb
Host smart-73a5d371-f027-45e7-9b34-bc7f9334e9f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2879610789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2879610789
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4155165346
Short name T264
Test name
Test status
Simulation time 758661006 ps
CPU time 5.39 seconds
Started May 19 01:51:51 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 204304 kb
Host smart-d0ad42b1-3d97-4c29-a957-6cd3757da982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4155165346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4155165346
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2137390660
Short name T275
Test name
Test status
Simulation time 48763813 ps
CPU time 0.7 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203776 kb
Host smart-adfd18a9-cfb7-43f1-b2e9-1e7ffb42e2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2137390660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2137390660
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.618230689
Short name T1865
Test name
Test status
Simulation time 59800878 ps
CPU time 0.69 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203624 kb
Host smart-7668787f-0517-406d-965d-d5648c8dde68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=618230689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.618230689
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2650619197
Short name T285
Test name
Test status
Simulation time 34117722 ps
CPU time 0.65 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 203668 kb
Host smart-12db6622-1aac-4f50-8eaf-e3ddf6d1c601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2650619197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2650619197
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2031217793
Short name T1851
Test name
Test status
Simulation time 31514809 ps
CPU time 0.67 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 203664 kb
Host smart-b473ca02-e805-4a74-a6fc-27fb5814965e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2031217793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2031217793
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3452283755
Short name T1835
Test name
Test status
Simulation time 77253507 ps
CPU time 0.7 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 203708 kb
Host smart-d9d4763e-dc98-4642-8bba-1e06eebeae65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452283755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3452283755
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2042555526
Short name T1848
Test name
Test status
Simulation time 32775086 ps
CPU time 0.66 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 203760 kb
Host smart-d445b77d-8f91-4839-843d-4589cec5b7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2042555526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2042555526
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.246413005
Short name T69
Test name
Test status
Simulation time 37089383 ps
CPU time 0.68 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 203660 kb
Host smart-368f35b8-293a-46e4-8802-a0d4dc0abd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=246413005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.246413005
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3747961268
Short name T1831
Test name
Test status
Simulation time 37831615 ps
CPU time 0.67 seconds
Started May 19 01:52:33 PM PDT 24
Finished May 19 01:52:34 PM PDT 24
Peak memory 203824 kb
Host smart-a9f67922-986f-4be7-ba8a-340227d8b573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3747961268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3747961268
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2027298480
Short name T1811
Test name
Test status
Simulation time 39731696 ps
CPU time 0.72 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 203664 kb
Host smart-9b0e8705-04ac-4382-a2e8-bbe49a42f53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2027298480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2027298480
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1451694947
Short name T1796
Test name
Test status
Simulation time 188906846 ps
CPU time 2.16 seconds
Started May 19 01:51:59 PM PDT 24
Finished May 19 01:52:04 PM PDT 24
Peak memory 204252 kb
Host smart-cb5a380b-17ac-48a0-a18a-58bc17a449fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1451694947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1451694947
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1231155289
Short name T1807
Test name
Test status
Simulation time 292926797 ps
CPU time 4.03 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:56 PM PDT 24
Peak memory 204268 kb
Host smart-a8c51a55-4006-42f2-bfea-49a18b79986d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1231155289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1231155289
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1506371048
Short name T1798
Test name
Test status
Simulation time 104220672 ps
CPU time 2.33 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 212496 kb
Host smart-a38fe98d-f775-4440-bfc8-ffbda303ef4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506371048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1506371048
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2885490210
Short name T254
Test name
Test status
Simulation time 37648755 ps
CPU time 0.78 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 204164 kb
Host smart-000bd3bc-c423-4ca3-898f-d8d507488de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2885490210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2885490210
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2990273552
Short name T68
Test name
Test status
Simulation time 32258234 ps
CPU time 0.67 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 203692 kb
Host smart-0cc40553-af56-40a3-906b-7090236a8820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2990273552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2990273552
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3127606157
Short name T251
Test name
Test status
Simulation time 68091449 ps
CPU time 2.19 seconds
Started May 19 01:51:58 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 212436 kb
Host smart-c0eb289b-97ff-43fa-8afc-51be0603865b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3127606157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3127606157
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1334784440
Short name T1780
Test name
Test status
Simulation time 162005664 ps
CPU time 2.41 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 204268 kb
Host smart-918f6413-c65a-4fd3-8548-5681615cd1fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1334784440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1334784440
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.28590626
Short name T1800
Test name
Test status
Simulation time 78532074 ps
CPU time 1.05 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 204252 kb
Host smart-e144079a-6324-4b2a-8d80-10d143b764fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=28590626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.28590626
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.698343957
Short name T268
Test name
Test status
Simulation time 246840862 ps
CPU time 2.57 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:56 PM PDT 24
Peak memory 204292 kb
Host smart-fa4ae9d3-c10d-4b2e-9459-5169eb5328af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=698343957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.698343957
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3732047726
Short name T1856
Test name
Test status
Simulation time 1362967483 ps
CPU time 5.04 seconds
Started May 19 01:51:46 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 204232 kb
Host smart-b7a93376-7665-4cfc-b40c-00f3ea9d08ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3732047726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3732047726
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1645136402
Short name T1842
Test name
Test status
Simulation time 124889777 ps
CPU time 0.75 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203680 kb
Host smart-35231dc4-f605-4a5f-83e7-c6b620e08f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1645136402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1645136402
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1796112648
Short name T274
Test name
Test status
Simulation time 45619141 ps
CPU time 0.68 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 203708 kb
Host smart-1c9a3b65-dbb1-4e35-bf98-e91922e32d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1796112648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1796112648
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1161047467
Short name T1834
Test name
Test status
Simulation time 34365303 ps
CPU time 0.65 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 203660 kb
Host smart-c31b7684-31ae-4f11-9687-c625305f820f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1161047467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1161047467
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2917418323
Short name T1843
Test name
Test status
Simulation time 44209427 ps
CPU time 0.67 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203640 kb
Host smart-bcf9a94b-4863-4142-9742-585da51d41e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2917418323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2917418323
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2385993247
Short name T1813
Test name
Test status
Simulation time 56264230 ps
CPU time 0.68 seconds
Started May 19 01:51:57 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 203444 kb
Host smart-5f791cc9-fcf9-485e-be77-8ec22acd6764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2385993247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2385993247
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.728086841
Short name T1806
Test name
Test status
Simulation time 33733315 ps
CPU time 0.7 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 203676 kb
Host smart-32af4c77-ad78-46fd-bcb3-2adfc4b3595f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=728086841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.728086841
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.279054777
Short name T1869
Test name
Test status
Simulation time 36542985 ps
CPU time 0.71 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203728 kb
Host smart-6c656247-e4cd-4a18-aa4f-a43e053a6fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=279054777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.279054777
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4270722779
Short name T287
Test name
Test status
Simulation time 42846677 ps
CPU time 0.7 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 203668 kb
Host smart-0fc85737-d0f6-4528-b426-ad9faf0b6a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4270722779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4270722779
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3555096925
Short name T279
Test name
Test status
Simulation time 124230709 ps
CPU time 0.73 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 203660 kb
Host smart-44ddf7ef-82d3-4a28-bcc9-ff304d8dd627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3555096925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3555096925
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3925645051
Short name T284
Test name
Test status
Simulation time 33667907 ps
CPU time 0.66 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 203656 kb
Host smart-a97263db-775e-492b-8e92-e5e24ded9ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3925645051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3925645051
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3698882041
Short name T1860
Test name
Test status
Simulation time 125225480 ps
CPU time 3.16 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 204324 kb
Host smart-b3da78b8-b4ba-4c25-ac59-1ca2c59d4821
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3698882041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3698882041
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2543665902
Short name T250
Test name
Test status
Simulation time 157979120 ps
CPU time 3.76 seconds
Started May 19 01:51:53 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 204212 kb
Host smart-89240f02-b397-4ba3-9e62-90935886671a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2543665902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2543665902
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.279703306
Short name T1785
Test name
Test status
Simulation time 75139948 ps
CPU time 1.23 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 212452 kb
Host smart-5aca2ae1-256a-42da-8a31-9a1a83347180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279703306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.279703306
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1564805522
Short name T1825
Test name
Test status
Simulation time 82550002 ps
CPU time 0.86 seconds
Started May 19 01:51:55 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 204112 kb
Host smart-0b595e14-a1a5-473f-bfb9-ac8953ef7c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1564805522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1564805522
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3091185877
Short name T280
Test name
Test status
Simulation time 20470477 ps
CPU time 0.66 seconds
Started May 19 01:51:51 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 203720 kb
Host smart-54a8c41a-f8a6-4579-8d67-bcfc7af0625b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3091185877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3091185877
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4042182762
Short name T1864
Test name
Test status
Simulation time 112338043 ps
CPU time 1.51 seconds
Started May 19 01:51:52 PM PDT 24
Finished May 19 01:51:56 PM PDT 24
Peak memory 212448 kb
Host smart-c77cc816-f4f0-4413-8fc0-7d798b7dd86b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4042182762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4042182762
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.471179239
Short name T1822
Test name
Test status
Simulation time 253871544 ps
CPU time 2.52 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204264 kb
Host smart-d429f8b2-bd1b-45be-9078-fa75caf398c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=471179239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.471179239
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.877931712
Short name T1868
Test name
Test status
Simulation time 71044204 ps
CPU time 1.49 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 204216 kb
Host smart-97981321-3cb0-463f-971a-12b8ae20461e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=877931712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.877931712
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1606725040
Short name T1847
Test name
Test status
Simulation time 108509516 ps
CPU time 3.11 seconds
Started May 19 01:51:47 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 204308 kb
Host smart-37abca01-ad55-4a8a-ba55-1487f7ab0682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606725040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1606725040
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1364227972
Short name T266
Test name
Test status
Simulation time 644435678 ps
CPU time 4.63 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 204248 kb
Host smart-23fa5520-d587-416a-86fb-c2aed9855a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1364227972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1364227972
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3506282225
Short name T1814
Test name
Test status
Simulation time 44015146 ps
CPU time 0.66 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203684 kb
Host smart-39f27216-2073-4d3f-8006-777c68498ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3506282225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3506282225
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3414371609
Short name T1850
Test name
Test status
Simulation time 34154521 ps
CPU time 0.67 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 203648 kb
Host smart-be8dbcbd-1d4e-488c-b8b0-68cb757099bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3414371609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3414371609
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3884318906
Short name T1804
Test name
Test status
Simulation time 27423504 ps
CPU time 0.65 seconds
Started May 19 01:51:57 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 203432 kb
Host smart-2167c285-74fc-42f4-8ea7-5233d9ca3195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3884318906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3884318906
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1250108347
Short name T1846
Test name
Test status
Simulation time 42562139 ps
CPU time 0.69 seconds
Started May 19 01:52:06 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 203624 kb
Host smart-1bb78dd8-da1b-4057-8e08-9cccf48b63a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1250108347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1250108347
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2571040771
Short name T1853
Test name
Test status
Simulation time 33628584 ps
CPU time 0.65 seconds
Started May 19 01:52:06 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 203620 kb
Host smart-55a6c1af-e6ff-4f24-9419-9243381e8349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2571040771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2571040771
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2013446972
Short name T1836
Test name
Test status
Simulation time 39232755 ps
CPU time 0.63 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203720 kb
Host smart-64935d68-024e-453b-b627-333bfb486980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2013446972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2013446972
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3285881450
Short name T1839
Test name
Test status
Simulation time 35170058 ps
CPU time 0.68 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203636 kb
Host smart-0f9ad8d2-d8fc-467c-b421-7cc725f8bfec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3285881450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3285881450
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3565496414
Short name T270
Test name
Test status
Simulation time 32704690 ps
CPU time 0.64 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203732 kb
Host smart-a5800eff-d4ea-4259-8685-0212b312ad32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3565496414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3565496414
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2925890217
Short name T1786
Test name
Test status
Simulation time 179105499 ps
CPU time 1.28 seconds
Started May 19 01:51:56 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 212504 kb
Host smart-1c01d92e-81b7-4205-a1a5-33b45d59f64b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925890217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2925890217
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4151214515
Short name T283
Test name
Test status
Simulation time 30775571 ps
CPU time 0.68 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:57 PM PDT 24
Peak memory 203772 kb
Host smart-604eb17d-39d3-434a-94d3-9c38c6c3e991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4151214515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.4151214515
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3196820476
Short name T263
Test name
Test status
Simulation time 110098126 ps
CPU time 1.13 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 204260 kb
Host smart-4b7b9e7f-b051-4f20-b706-6578dc151805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196820476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3196820476
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1262015389
Short name T1837
Test name
Test status
Simulation time 284832863 ps
CPU time 2.97 seconds
Started May 19 01:51:53 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204308 kb
Host smart-0c9fb534-30ed-4e88-a744-248d5a8ece8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1262015389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1262015389
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.420981194
Short name T218
Test name
Test status
Simulation time 727173212 ps
CPU time 3.04 seconds
Started May 19 01:51:51 PM PDT 24
Finished May 19 01:51:56 PM PDT 24
Peak memory 204248 kb
Host smart-cce2791c-6b36-42dc-b85f-a0e05c5778f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=420981194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.420981194
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1821730877
Short name T216
Test name
Test status
Simulation time 101474870 ps
CPU time 2.52 seconds
Started May 19 01:51:52 PM PDT 24
Finished May 19 01:51:57 PM PDT 24
Peak memory 212512 kb
Host smart-e7aafde8-9e22-4f16-9921-2b911e94eab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821730877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1821730877
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.320415534
Short name T119
Test name
Test status
Simulation time 51679489 ps
CPU time 0.93 seconds
Started May 19 01:51:56 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 204288 kb
Host smart-d0f13033-8cb5-473a-a56c-b3fc31460559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=320415534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.320415534
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4083653257
Short name T1815
Test name
Test status
Simulation time 123460544 ps
CPU time 1.15 seconds
Started May 19 01:51:57 PM PDT 24
Finished May 19 01:52:01 PM PDT 24
Peak memory 204308 kb
Host smart-6b0a7f81-6815-4242-937a-f31e46d97537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4083653257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4083653257
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1773604138
Short name T1858
Test name
Test status
Simulation time 511103916 ps
CPU time 4.82 seconds
Started May 19 01:51:47 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 204304 kb
Host smart-d243b603-783f-424e-ae8a-d9726b8680cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1773604138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1773604138
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3693742608
Short name T1823
Test name
Test status
Simulation time 69312422 ps
CPU time 1.56 seconds
Started May 19 01:51:59 PM PDT 24
Finished May 19 01:52:03 PM PDT 24
Peak memory 212476 kb
Host smart-aa4516ec-4462-447c-9f9e-123ccadb2336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693742608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3693742608
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2666789245
Short name T1857
Test name
Test status
Simulation time 47010167 ps
CPU time 0.78 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:53 PM PDT 24
Peak memory 204140 kb
Host smart-f8561452-7951-4ff5-82be-c44939cddb25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2666789245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2666789245
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1549398370
Short name T1791
Test name
Test status
Simulation time 47401215 ps
CPU time 0.66 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:51:57 PM PDT 24
Peak memory 203680 kb
Host smart-2aeccb5d-dca8-4185-b0b0-c47271783015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1549398370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1549398370
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.811318663
Short name T1789
Test name
Test status
Simulation time 49391942 ps
CPU time 1.01 seconds
Started May 19 01:51:57 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 204264 kb
Host smart-3b4fe880-98c9-4de0-a191-24416fad8996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=811318663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.811318663
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3117652275
Short name T289
Test name
Test status
Simulation time 884585377 ps
CPU time 4.86 seconds
Started May 19 01:51:54 PM PDT 24
Finished May 19 01:52:01 PM PDT 24
Peak memory 204304 kb
Host smart-dfa57cd0-d049-40d1-8bb8-350ed857d4d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3117652275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3117652275
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2619108031
Short name T227
Test name
Test status
Simulation time 85756524 ps
CPU time 1.33 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 212428 kb
Host smart-53ed9607-a964-44d3-a7fa-dad8012e8b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619108031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2619108031
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1228553669
Short name T1799
Test name
Test status
Simulation time 37706762 ps
CPU time 0.77 seconds
Started May 19 01:52:01 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 204264 kb
Host smart-c39c4c9a-b8aa-4730-a9cc-c2d469e34bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1228553669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1228553669
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2334121231
Short name T1827
Test name
Test status
Simulation time 47831756 ps
CPU time 0.69 seconds
Started May 19 01:51:55 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 203756 kb
Host smart-4c0f1ace-05ed-4e79-ae13-7c9274715e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2334121231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2334121231
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4029991486
Short name T1790
Test name
Test status
Simulation time 118726898 ps
CPU time 1.52 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 204312 kb
Host smart-8543aca7-480e-4443-9a0e-87246206df7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4029991486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4029991486
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4255178337
Short name T1817
Test name
Test status
Simulation time 116593649 ps
CPU time 1.44 seconds
Started May 19 01:52:06 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 204296 kb
Host smart-24dedb13-3f08-43f9-9c51-cfb80fbcdeff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4255178337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4255178337
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1643705595
Short name T290
Test name
Test status
Simulation time 1402337595 ps
CPU time 5.31 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 204468 kb
Host smart-f1fd4cdc-8d43-4a02-94ec-d0b4c72c16e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1643705595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1643705595
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3697431876
Short name T1826
Test name
Test status
Simulation time 91973061 ps
CPU time 2.59 seconds
Started May 19 01:51:55 PM PDT 24
Finished May 19 01:52:00 PM PDT 24
Peak memory 212480 kb
Host smart-65895c58-4add-4a00-970e-96ca80431ad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697431876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3697431876
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2047079059
Short name T1852
Test name
Test status
Simulation time 51085368 ps
CPU time 0.91 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 204112 kb
Host smart-188251d4-9f03-416a-82a9-7889ab8a05ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2047079059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2047079059
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1424392231
Short name T276
Test name
Test status
Simulation time 34126583 ps
CPU time 0.69 seconds
Started May 19 01:51:59 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 203752 kb
Host smart-0c8d8d8e-203d-4f2c-b3cf-dab2826bebf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1424392231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1424392231
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3695343926
Short name T1781
Test name
Test status
Simulation time 153963582 ps
CPU time 1.56 seconds
Started May 19 01:51:53 PM PDT 24
Finished May 19 01:51:57 PM PDT 24
Peak memory 204232 kb
Host smart-5e72350c-0881-42f2-9d27-4784a9bbee69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3695343926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3695343926
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1466566140
Short name T1816
Test name
Test status
Simulation time 311477601 ps
CPU time 3.26 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 212488 kb
Host smart-89447978-f3a8-4ff6-baa1-93065b72baf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1466566140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1466566140
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4027970390
Short name T292
Test name
Test status
Simulation time 217808533 ps
CPU time 2.33 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 204304 kb
Host smart-85b806ab-7441-407f-84c5-5ec2224a5768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4027970390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4027970390
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.245555992
Short name T518
Test name
Test status
Simulation time 8511123208 ps
CPU time 11.38 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204800 kb
Host smart-ef15c3b8-765f-4fd9-b89d-55548eaa62f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=245555992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.245555992
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.3308109894
Short name T385
Test name
Test status
Simulation time 8380541029 ps
CPU time 10.97 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204876 kb
Host smart-5c12825c-c11a-4f4a-8328-3b42683e64b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3308109894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.3308109894
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.2591331734
Short name T520
Test name
Test status
Simulation time 8481948576 ps
CPU time 12.43 seconds
Started May 19 02:00:51 PM PDT 24
Finished May 19 02:01:05 PM PDT 24
Peak memory 204776 kb
Host smart-f4712b78-b480-425d-bd72-93dc8d8e9e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
31734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.2591331734
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.934572892
Short name T1582
Test name
Test status
Simulation time 8373267329 ps
CPU time 10.75 seconds
Started May 19 02:00:54 PM PDT 24
Finished May 19 02:01:05 PM PDT 24
Peak memory 204812 kb
Host smart-cb982e66-8e28-4e86-9f84-ce4e272e068c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93457
2892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.934572892
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.1241812330
Short name T1267
Test name
Test status
Simulation time 8388611710 ps
CPU time 11.84 seconds
Started May 19 02:00:48 PM PDT 24
Finished May 19 02:01:00 PM PDT 24
Peak memory 204872 kb
Host smart-c43863ef-2778-4eec-9f28-fee275d5cf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418
12330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1241812330
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.697235827
Short name T1666
Test name
Test status
Simulation time 9151023163 ps
CPU time 14.22 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204804 kb
Host smart-1da07b76-1bfe-4657-927a-db9d481b33ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69723
5827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.697235827
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2535107396
Short name T1625
Test name
Test status
Simulation time 8525059025 ps
CPU time 13.03 seconds
Started May 19 02:00:52 PM PDT 24
Finished May 19 02:01:05 PM PDT 24
Peak memory 204828 kb
Host smart-15d4e795-3624-4e1a-af80-dbe5e8e48eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25351
07396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2535107396
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.400503317
Short name T881
Test name
Test status
Simulation time 8453899033 ps
CPU time 10.9 seconds
Started May 19 02:00:50 PM PDT 24
Finished May 19 02:01:02 PM PDT 24
Peak memory 204864 kb
Host smart-dc2fe0bf-7081-461c-9c9f-22fbab68fbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40050
3317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.400503317
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.4071307523
Short name T81
Test name
Test status
Simulation time 8390203803 ps
CPU time 10.88 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204764 kb
Host smart-a71aa30c-9c6a-429b-855c-cacea7a8228c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40713
07523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.4071307523
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1325710340
Short name T322
Test name
Test status
Simulation time 8391722263 ps
CPU time 11.37 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 204848 kb
Host smart-9a5daa09-0e81-4baa-8ae7-b6f35aa82d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13257
10340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1325710340
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.4219519537
Short name T1125
Test name
Test status
Simulation time 8406445800 ps
CPU time 11.59 seconds
Started May 19 02:00:47 PM PDT 24
Finished May 19 02:00:59 PM PDT 24
Peak memory 204856 kb
Host smart-6d57e156-08de-4e83-9a8c-ec089151ae97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42195
19537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.4219519537
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.909746914
Short name T583
Test name
Test status
Simulation time 11531762234 ps
CPU time 14.27 seconds
Started May 19 02:00:51 PM PDT 24
Finished May 19 02:01:06 PM PDT 24
Peak memory 204872 kb
Host smart-3160a3b2-4e24-4f38-9a6a-556d5b5aadee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90974
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.909746914
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.742280154
Short name T1518
Test name
Test status
Simulation time 8417477741 ps
CPU time 11.11 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 204680 kb
Host smart-dab3aeac-c01e-4a24-8540-03c7e1e50f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74228
0154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.742280154
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1384134629
Short name T1641
Test name
Test status
Simulation time 8374363946 ps
CPU time 11.56 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 204808 kb
Host smart-57ee9ebd-41be-42c9-87c2-4f539cf75a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13841
34629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1384134629
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1740379739
Short name T1346
Test name
Test status
Simulation time 8425174011 ps
CPU time 10.92 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 204836 kb
Host smart-d9b601dc-6d87-4798-95f8-1ff442ea121f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17403
79739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1740379739
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2492766161
Short name T1416
Test name
Test status
Simulation time 8387752478 ps
CPU time 11.7 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204888 kb
Host smart-30a91e57-3a5a-48bc-8d2a-aa737e4b4e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24927
66161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2492766161
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2656759526
Short name T1568
Test name
Test status
Simulation time 8379756925 ps
CPU time 11.04 seconds
Started May 19 02:01:03 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 204864 kb
Host smart-d2fdde84-4090-4d76-af03-d8d7022ad240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26567
59526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2656759526
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3974273314
Short name T1131
Test name
Test status
Simulation time 8397817444 ps
CPU time 11.1 seconds
Started May 19 02:00:52 PM PDT 24
Finished May 19 02:01:04 PM PDT 24
Peak memory 204804 kb
Host smart-15da2b43-9767-4898-a101-23c15249c327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
73314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3974273314
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.987979744
Short name T359
Test name
Test status
Simulation time 8393504040 ps
CPU time 11.53 seconds
Started May 19 02:00:52 PM PDT 24
Finished May 19 02:01:04 PM PDT 24
Peak memory 204816 kb
Host smart-f1feab7f-2e0e-40c9-a83b-118ce9166fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98797
9744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.987979744
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.771321232
Short name T1099
Test name
Test status
Simulation time 8371729890 ps
CPU time 11.26 seconds
Started May 19 02:00:57 PM PDT 24
Finished May 19 02:01:09 PM PDT 24
Peak memory 204804 kb
Host smart-2df6341c-4b09-4e2e-b43b-b41d199cbf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77132
1232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.771321232
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1893044909
Short name T1351
Test name
Test status
Simulation time 8393460102 ps
CPU time 13.1 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 204844 kb
Host smart-10b13080-e193-4519-86c8-5d109c5a5101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18930
44909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1893044909
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3686570973
Short name T1465
Test name
Test status
Simulation time 19645335342 ps
CPU time 40.27 seconds
Started May 19 02:00:53 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204780 kb
Host smart-d8cafef1-b664-4d2b-b0f3-09e68c97df55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865
70973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3686570973
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.992420764
Short name T665
Test name
Test status
Simulation time 8389582140 ps
CPU time 11.06 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 204844 kb
Host smart-afe4d77f-5c58-415b-8af8-d46175f18bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99242
0764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.992420764
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.27486714
Short name T430
Test name
Test status
Simulation time 8459752056 ps
CPU time 11.4 seconds
Started May 19 02:00:51 PM PDT 24
Finished May 19 02:01:04 PM PDT 24
Peak memory 204752 kb
Host smart-4abaeaca-b015-467a-b0df-4bbf113f0bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27486
714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.27486714
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.4162638266
Short name T806
Test name
Test status
Simulation time 8387511851 ps
CPU time 10.53 seconds
Started May 19 02:00:53 PM PDT 24
Finished May 19 02:01:05 PM PDT 24
Peak memory 204744 kb
Host smart-f861a7a8-e61a-48cf-aa1c-f19c95e7940d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41626
38266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.4162638266
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.4268451854
Short name T1260
Test name
Test status
Simulation time 8365392525 ps
CPU time 10.95 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204848 kb
Host smart-1d97247e-6841-4f9c-8306-fdd99d791ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42684
51854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.4268451854
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2262244053
Short name T1023
Test name
Test status
Simulation time 8382578373 ps
CPU time 10.79 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 204856 kb
Host smart-f395496b-2faa-4579-8fbf-a1822219025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22622
44053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2262244053
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1075648719
Short name T1661
Test name
Test status
Simulation time 8455572405 ps
CPU time 11.87 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:12 PM PDT 24
Peak memory 204708 kb
Host smart-1fe3be3c-0628-4940-942d-7371ccfc80c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10756
48719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1075648719
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1150087758
Short name T1054
Test name
Test status
Simulation time 8417504047 ps
CPU time 12.52 seconds
Started May 19 02:00:58 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 204840 kb
Host smart-01ce5beb-1672-4e14-9337-adf5f15a75e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11500
87758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1150087758
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.720122386
Short name T1640
Test name
Test status
Simulation time 8421016744 ps
CPU time 12.78 seconds
Started May 19 02:00:58 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 204864 kb
Host smart-f97e9194-d5a7-4d4b-8858-8d378c4a19d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72012
2386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.720122386
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3618319782
Short name T1276
Test name
Test status
Simulation time 8468646468 ps
CPU time 13.8 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204828 kb
Host smart-bb0e5ffa-5028-494b-9370-76afad860540
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3618319782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3618319782
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.780072941
Short name T1310
Test name
Test status
Simulation time 8426961718 ps
CPU time 11.35 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 204848 kb
Host smart-7f129364-9c71-4875-a6ef-bf06d06ac8df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=780072941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.780072941
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.2569374095
Short name T1403
Test name
Test status
Simulation time 8391796550 ps
CPU time 13.14 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:21 PM PDT 24
Peak memory 204772 kb
Host smart-a84cacd7-57e0-4fbf-ac74-d95e0068f5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
74095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.2569374095
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.474897585
Short name T695
Test name
Test status
Simulation time 8391637343 ps
CPU time 10.43 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204856 kb
Host smart-65ec5943-535b-41ff-99ab-24b8ef3438ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47489
7585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.474897585
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3082838744
Short name T47
Test name
Test status
Simulation time 8928185961 ps
CPU time 12.01 seconds
Started May 19 02:00:53 PM PDT 24
Finished May 19 02:01:06 PM PDT 24
Peak memory 204788 kb
Host smart-908ae46a-fab9-4d23-8f70-d50baccb47f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
38744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3082838744
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.281608751
Short name T860
Test name
Test status
Simulation time 8377964996 ps
CPU time 11.51 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204820 kb
Host smart-28c34421-336e-4c3a-8aa2-7f3352693738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28160
8751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.281608751
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3098425602
Short name T763
Test name
Test status
Simulation time 8387119571 ps
CPU time 12.38 seconds
Started May 19 02:00:53 PM PDT 24
Finished May 19 02:01:06 PM PDT 24
Peak memory 204820 kb
Host smart-55b76ae8-4788-4549-a619-791769f6d7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
25602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3098425602
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2367831168
Short name T1656
Test name
Test status
Simulation time 8943280881 ps
CPU time 12.81 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 204820 kb
Host smart-5b8eaf13-05cd-4f0c-b445-794609f67192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23678
31168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2367831168
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1661770776
Short name T1209
Test name
Test status
Simulation time 8564218325 ps
CPU time 13.62 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204832 kb
Host smart-7e4cea51-6a66-48bd-92ca-3976a2794faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617
70776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1661770776
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.4061512418
Short name T1445
Test name
Test status
Simulation time 8469822949 ps
CPU time 11.41 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204780 kb
Host smart-70d058ce-700a-4a95-99e4-4d283b733f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40615
12418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.4061512418
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2571426713
Short name T678
Test name
Test status
Simulation time 8370487619 ps
CPU time 12.1 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 204800 kb
Host smart-818ce4b0-5659-469f-9b5c-36546282cd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25714
26713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2571426713
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.201423986
Short name T153
Test name
Test status
Simulation time 8383839469 ps
CPU time 11.93 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 204868 kb
Host smart-cc6bf3cc-88da-45cd-b17b-efc801fdf7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.201423986
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3512080213
Short name T1192
Test name
Test status
Simulation time 8433404186 ps
CPU time 11.16 seconds
Started May 19 02:00:58 PM PDT 24
Finished May 19 02:01:10 PM PDT 24
Peak memory 204852 kb
Host smart-549b46a2-f223-46cf-82cc-6622e9dd0410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35120
80213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3512080213
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2276019636
Short name T1396
Test name
Test status
Simulation time 11498759209 ps
CPU time 13.1 seconds
Started May 19 02:01:03 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 204824 kb
Host smart-b3f140d6-17a1-4be4-b601-775be45d80cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22760
19636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2276019636
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4203485973
Short name T1754
Test name
Test status
Simulation time 8436133918 ps
CPU time 11.46 seconds
Started May 19 02:00:58 PM PDT 24
Finished May 19 02:01:10 PM PDT 24
Peak memory 204808 kb
Host smart-ed773feb-496d-44bb-92cc-7287b556c68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
85973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4203485973
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2734315290
Short name T1288
Test name
Test status
Simulation time 8372845994 ps
CPU time 11.66 seconds
Started May 19 02:01:10 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204620 kb
Host smart-0939e402-f6f5-4c03-836d-b65d0368aee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27343
15290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2734315290
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2611397015
Short name T948
Test name
Test status
Simulation time 8406858291 ps
CPU time 11.07 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204884 kb
Host smart-7c9d4576-14cb-439b-8c55-5b0f50c436b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
97015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2611397015
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2999138234
Short name T489
Test name
Test status
Simulation time 8423171513 ps
CPU time 11.47 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204696 kb
Host smart-d7482f8e-113a-4026-8077-4ddba74acd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29991
38234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2999138234
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3509071233
Short name T558
Test name
Test status
Simulation time 8417420899 ps
CPU time 10.75 seconds
Started May 19 02:01:00 PM PDT 24
Finished May 19 02:01:12 PM PDT 24
Peak memory 204800 kb
Host smart-ec855636-c3c9-47fb-b369-93aa3b6ff5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090
71233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3509071233
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1573345293
Short name T532
Test name
Test status
Simulation time 8405099045 ps
CPU time 12.51 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:15 PM PDT 24
Peak memory 204816 kb
Host smart-ce1b37db-5153-427f-8efc-fc0a2887c2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15733
45293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1573345293
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.3714959741
Short name T522
Test name
Test status
Simulation time 8409660562 ps
CPU time 11.66 seconds
Started May 19 02:00:58 PM PDT 24
Finished May 19 02:01:10 PM PDT 24
Peak memory 204776 kb
Host smart-18b95a45-07b9-4a5c-aa55-746fc9273804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37149
59741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.3714959741
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2458845103
Short name T53
Test name
Test status
Simulation time 8380422706 ps
CPU time 11.08 seconds
Started May 19 02:00:56 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 204772 kb
Host smart-06612808-d487-4ee6-91e4-c9ebe4f6ad94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24588
45103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2458845103
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1253893937
Short name T1311
Test name
Test status
Simulation time 18065201600 ps
CPU time 30.55 seconds
Started May 19 02:00:56 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204768 kb
Host smart-e2a5d57d-b5e7-49ae-9a29-225a6645c467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538
93937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1253893937
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.650604732
Short name T850
Test name
Test status
Simulation time 8478493803 ps
CPU time 10.67 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204796 kb
Host smart-a6adba68-4652-464f-bb4e-77f5f0f5787e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65060
4732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.650604732
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.154245030
Short name T906
Test name
Test status
Simulation time 8471410101 ps
CPU time 12.42 seconds
Started May 19 02:01:10 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204768 kb
Host smart-92d6e297-2a85-48b8-b09a-f0763325c403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
5030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.154245030
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1107774236
Short name T1481
Test name
Test status
Simulation time 8381398104 ps
CPU time 10.86 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204756 kb
Host smart-46af3bf9-0462-47a5-aba2-f69d26c1ae62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11077
74236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1107774236
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1870340073
Short name T75
Test name
Test status
Simulation time 357507678 ps
CPU time 1.22 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:09 PM PDT 24
Peak memory 221572 kb
Host smart-1555d309-0217-498a-9595-42c89a9139b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1870340073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1870340073
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.875756280
Short name T1144
Test name
Test status
Simulation time 8401522877 ps
CPU time 11.61 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:19 PM PDT 24
Peak memory 204844 kb
Host smart-72c250a0-0320-48a7-ab87-679538c01cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87575
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.875756280
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2897481510
Short name T1243
Test name
Test status
Simulation time 8380925373 ps
CPU time 10.15 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 204776 kb
Host smart-72419c43-214d-4444-b1e6-e42e1596c383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
81510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2897481510
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1241913011
Short name T1088
Test name
Test status
Simulation time 8421683450 ps
CPU time 11.34 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 204812 kb
Host smart-2670e77d-62bd-45f2-8835-f30804089e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419
13011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1241913011
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1628691189
Short name T501
Test name
Test status
Simulation time 8413882460 ps
CPU time 11.46 seconds
Started May 19 02:00:59 PM PDT 24
Finished May 19 02:01:12 PM PDT 24
Peak memory 204872 kb
Host smart-7d84a0f5-094f-44fb-97cb-3348176480b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16286
91189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1628691189
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3926972091
Short name T1423
Test name
Test status
Simulation time 8376968931 ps
CPU time 10.75 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 204744 kb
Host smart-e5cbea51-7deb-4e3c-b5cb-3966941f3d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
72091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3926972091
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.2492809352
Short name T791
Test name
Test status
Simulation time 8472303992 ps
CPU time 11.71 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204776 kb
Host smart-5fb3e0cb-2936-4329-8cf9-09c5f065e553
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2492809352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.2492809352
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.3039716958
Short name T1118
Test name
Test status
Simulation time 8408109787 ps
CPU time 11.33 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 205016 kb
Host smart-85d1f2fa-c161-485f-b791-80addf076c3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3039716958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3039716958
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.163460621
Short name T706
Test name
Test status
Simulation time 8379387054 ps
CPU time 10.45 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204816 kb
Host smart-bba83412-ae73-435a-a7e9-fa406216eba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16346
0621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.163460621
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2271136786
Short name T597
Test name
Test status
Simulation time 8384405086 ps
CPU time 11.46 seconds
Started May 19 02:01:52 PM PDT 24
Finished May 19 02:02:04 PM PDT 24
Peak memory 204804 kb
Host smart-8906c4f7-1698-4254-a797-03d61a51a33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22711
36786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2271136786
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1753275155
Short name T1453
Test name
Test status
Simulation time 8792122063 ps
CPU time 13.24 seconds
Started May 19 02:01:51 PM PDT 24
Finished May 19 02:02:06 PM PDT 24
Peak memory 204816 kb
Host smart-7bd645af-402c-4cf3-8a13-ea7f2f348093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532
75155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1753275155
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1992882041
Short name T1657
Test name
Test status
Simulation time 8365207944 ps
CPU time 12.34 seconds
Started May 19 02:01:48 PM PDT 24
Finished May 19 02:02:01 PM PDT 24
Peak memory 204796 kb
Host smart-5225ee9f-3310-417a-9ec6-5f1daafb8e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19928
82041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1992882041
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1654673012
Short name T825
Test name
Test status
Simulation time 8380932563 ps
CPU time 10.61 seconds
Started May 19 02:01:51 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 204832 kb
Host smart-2654a98f-3d5f-4185-9f61-c687759ffdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
73012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1654673012
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1223184614
Short name T550
Test name
Test status
Simulation time 8543188746 ps
CPU time 12.28 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:10 PM PDT 24
Peak memory 205048 kb
Host smart-421a59d2-3fb0-4ca4-81d9-e3c3eb1523c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12231
84614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1223184614
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.4022366149
Short name T1268
Test name
Test status
Simulation time 8386115472 ps
CPU time 11.75 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:06 PM PDT 24
Peak memory 204796 kb
Host smart-a95fd371-7534-42f6-98f6-677250228ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40223
66149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.4022366149
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.623791941
Short name T82
Test name
Test status
Simulation time 8366188993 ps
CPU time 11.35 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204400 kb
Host smart-fce8da79-cc27-4e55-9b80-bcfbf52dda5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62379
1941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.623791941
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.206422182
Short name T637
Test name
Test status
Simulation time 8408548449 ps
CPU time 10.5 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204788 kb
Host smart-89ba3a3b-96b3-4e4e-812d-77822ec735df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20642
2182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.206422182
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1595461755
Short name T1604
Test name
Test status
Simulation time 11563692463 ps
CPU time 15.7 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204828 kb
Host smart-0129d139-1a62-467f-8069-556866d8479e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15954
61755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1595461755
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1683315206
Short name T1563
Test name
Test status
Simulation time 8415832788 ps
CPU time 11.52 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204800 kb
Host smart-4e2c0d13-6730-43f5-add2-50f885fee134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16833
15206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1683315206
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3422678762
Short name T1436
Test name
Test status
Simulation time 8375418984 ps
CPU time 11.45 seconds
Started May 19 02:01:43 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204812 kb
Host smart-b245e7f0-f11d-418f-a52f-98493b3bddcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34226
78762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3422678762
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1991721952
Short name T884
Test name
Test status
Simulation time 8436568041 ps
CPU time 11.48 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:06 PM PDT 24
Peak memory 204828 kb
Host smart-4ad9c342-e7c0-4e07-861f-50d9615f0a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19917
21952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1991721952
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1549549710
Short name T896
Test name
Test status
Simulation time 8408537675 ps
CPU time 10.94 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204832 kb
Host smart-3df8365d-e04c-48e6-8f69-b8bf2013e99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15495
49710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1549549710
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3802782751
Short name T1561
Test name
Test status
Simulation time 8374669280 ps
CPU time 12.32 seconds
Started May 19 02:01:51 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204868 kb
Host smart-0ba887c6-2502-423f-932d-6ace763af2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027
82751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3802782751
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.3472825053
Short name T562
Test name
Test status
Simulation time 8379078497 ps
CPU time 10.92 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204788 kb
Host smart-98fe384c-0b1e-4a91-938a-7dd6276c5c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34728
25053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.3472825053
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1428891415
Short name T812
Test name
Test status
Simulation time 8375718255 ps
CPU time 12.22 seconds
Started May 19 02:01:56 PM PDT 24
Finished May 19 02:02:10 PM PDT 24
Peak memory 204812 kb
Host smart-3c5dc47f-fefd-4921-adcc-9ecffedb5d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
91415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1428891415
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4030942565
Short name T1219
Test name
Test status
Simulation time 8369090257 ps
CPU time 11.36 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204788 kb
Host smart-74eef9da-e951-4ba2-94ec-6141eb97214a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
42565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4030942565
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.425289374
Short name T16
Test name
Test status
Simulation time 26926842207 ps
CPU time 55.3 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 204784 kb
Host smart-99a73d61-a137-4e93-bd51-b8cd687ceee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42528
9374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.425289374
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1940115337
Short name T1301
Test name
Test status
Simulation time 8403469205 ps
CPU time 10.96 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204472 kb
Host smart-768e6f84-899c-47a4-b1e2-d8579761c0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19401
15337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1940115337
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.16567719
Short name T997
Test name
Test status
Simulation time 8390732774 ps
CPU time 11.61 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 204780 kb
Host smart-63da621b-99c7-4073-ab45-531a5fc6441c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16567
719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.16567719
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3422750415
Short name T1418
Test name
Test status
Simulation time 8373784075 ps
CPU time 11.39 seconds
Started May 19 02:01:56 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 204992 kb
Host smart-4408f3b1-f18a-41f7-8617-f94dc9ba8820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34227
50415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3422750415
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.802129973
Short name T1760
Test name
Test status
Simulation time 8364210266 ps
CPU time 10.73 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204760 kb
Host smart-aaa50d43-d51a-436a-b6c3-1e5b9582053d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80212
9973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.802129973
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1030729984
Short name T1013
Test name
Test status
Simulation time 8370002468 ps
CPU time 13.54 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204808 kb
Host smart-2305a78a-e847-408e-872b-8b3d55171065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10307
29984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1030729984
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2788890978
Short name T171
Test name
Test status
Simulation time 8492329327 ps
CPU time 10.72 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 205080 kb
Host smart-c1e99e85-d6bc-4989-a992-85516d23196c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27888
90978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2788890978
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1005928558
Short name T870
Test name
Test status
Simulation time 8399323181 ps
CPU time 11.15 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204756 kb
Host smart-aa0a7d1d-506b-4f28-96f2-eba42b626582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10059
28558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1005928558
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3088028263
Short name T603
Test name
Test status
Simulation time 8397493451 ps
CPU time 11.29 seconds
Started May 19 02:01:50 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 204844 kb
Host smart-fc903d74-c45e-4777-bcb3-08c607cec559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
28263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3088028263
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3356228776
Short name T872
Test name
Test status
Simulation time 8513767619 ps
CPU time 12.66 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204696 kb
Host smart-001fe612-4130-4df2-9caf-34f68dbfdf16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3356228776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3356228776
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1054259611
Short name T955
Test name
Test status
Simulation time 8387145552 ps
CPU time 11.19 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204696 kb
Host smart-1878db6c-2f9c-4600-845f-b1c4b9969e27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1054259611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1054259611
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1245095571
Short name T634
Test name
Test status
Simulation time 8448129009 ps
CPU time 10.67 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204820 kb
Host smart-b8af529f-2e91-4bd8-9691-b285a9a55772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12450
95571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1245095571
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3226218703
Short name T1655
Test name
Test status
Simulation time 8384662739 ps
CPU time 11.05 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204788 kb
Host smart-78137629-b328-46bf-aac4-e99027b2a2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32262
18703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3226218703
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1328660232
Short name T362
Test name
Test status
Simulation time 8369108454 ps
CPU time 10.6 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204756 kb
Host smart-af50e0f2-4de0-49e5-91ee-e585b6805c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13286
60232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1328660232
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2595961625
Short name T1124
Test name
Test status
Simulation time 8381034341 ps
CPU time 11.53 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204840 kb
Host smart-a2ef04f1-cccc-43db-97e4-2f45d4ee902e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25959
61625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2595961625
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.766605305
Short name T1218
Test name
Test status
Simulation time 9041883380 ps
CPU time 12.37 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204844 kb
Host smart-e92e35dd-a199-454d-8631-7c64f21f7b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76660
5305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.766605305
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.305875033
Short name T1102
Test name
Test status
Simulation time 8470545824 ps
CPU time 11.4 seconds
Started May 19 02:02:05 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204792 kb
Host smart-afc23b61-890d-4b60-ae88-11d477c9f5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30587
5033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.305875033
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.722653058
Short name T830
Test name
Test status
Simulation time 8376180765 ps
CPU time 10.79 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204788 kb
Host smart-51f2e42d-8c29-4bd5-810b-3eba945519e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72265
3058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.722653058
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.529576460
Short name T1202
Test name
Test status
Simulation time 8495814382 ps
CPU time 12.25 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:12 PM PDT 24
Peak memory 204840 kb
Host smart-b146136b-3748-47b7-8c0b-8d2aad06239d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52957
6460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.529576460
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.716354801
Short name T3
Test name
Test status
Simulation time 8410625173 ps
CPU time 11.31 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204852 kb
Host smart-345accf1-da11-49bf-b103-c7dd93ba2375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71635
4801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.716354801
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.487142496
Short name T361
Test name
Test status
Simulation time 11525503137 ps
CPU time 14.26 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204612 kb
Host smart-4b2ea292-694b-405c-a27b-5846d59b9d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48714
2496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.487142496
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2435702345
Short name T1716
Test name
Test status
Simulation time 8432492989 ps
CPU time 10.99 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204744 kb
Host smart-290a1a1b-6970-4719-9926-19e3baacafda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24357
02345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2435702345
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3368679450
Short name T981
Test name
Test status
Simulation time 8373301121 ps
CPU time 10.84 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:06 PM PDT 24
Peak memory 204828 kb
Host smart-9bd151f5-8401-4ff0-923e-4a9c092b4052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33686
79450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3368679450
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1088740578
Short name T701
Test name
Test status
Simulation time 8418262070 ps
CPU time 11.68 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204820 kb
Host smart-c369bc20-10a3-469e-8733-e35ccf494750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10887
40578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1088740578
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.471883302
Short name T1602
Test name
Test status
Simulation time 8438152664 ps
CPU time 11.03 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:15 PM PDT 24
Peak memory 204856 kb
Host smart-801ed2b0-d8b4-4350-91e1-064c21f74b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47188
3302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.471883302
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2656950565
Short name T1676
Test name
Test status
Simulation time 8399280374 ps
CPU time 11.11 seconds
Started May 19 02:02:06 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204868 kb
Host smart-8be42f41-db81-4bb1-a630-ccee918b7ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26569
50565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2656950565
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.312403952
Short name T1117
Test name
Test status
Simulation time 8378460178 ps
CPU time 11.55 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204820 kb
Host smart-ec454dae-eda5-4805-adef-42d3126efe99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240
3952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.312403952
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1280891985
Short name T774
Test name
Test status
Simulation time 8455116224 ps
CPU time 11.35 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204720 kb
Host smart-da6dc757-fb7e-4bed-b8f9-cebb94b2177d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12808
91985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1280891985
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3517349612
Short name T946
Test name
Test status
Simulation time 8366141605 ps
CPU time 10.09 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204784 kb
Host smart-73b12b4a-b0fd-4d2a-b6d3-5d9446993de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35173
49612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3517349612
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1473963535
Short name T1171
Test name
Test status
Simulation time 8452381712 ps
CPU time 13.76 seconds
Started May 19 02:01:56 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204872 kb
Host smart-46474da4-011a-43d0-83ce-d00b7813a23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
63535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1473963535
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1002712779
Short name T1030
Test name
Test status
Simulation time 8399667938 ps
CPU time 10.67 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204808 kb
Host smart-77389bd5-4ff8-42c4-bcea-9b8897556c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10027
12779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1002712779
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.566157048
Short name T1694
Test name
Test status
Simulation time 8363893427 ps
CPU time 11.1 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:06 PM PDT 24
Peak memory 204776 kb
Host smart-b239d327-8c13-4305-acf5-ece126648418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56615
7048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.566157048
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4271973355
Short name T1577
Test name
Test status
Simulation time 8379882309 ps
CPU time 11.02 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:15 PM PDT 24
Peak memory 204796 kb
Host smart-f794c906-53a8-4a63-a6e4-c057e8c424b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42719
73355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4271973355
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3471008187
Short name T1056
Test name
Test status
Simulation time 8395810192 ps
CPU time 12.19 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 204836 kb
Host smart-ab6ca974-fa30-42c1-88c3-29ca45721723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34710
08187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3471008187
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1044415710
Short name T179
Test name
Test status
Simulation time 8454434693 ps
CPU time 11.3 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204820 kb
Host smart-5eb9333e-7e38-481f-9c8a-7520f8b24664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10444
15710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1044415710
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1172054250
Short name T1458
Test name
Test status
Simulation time 8394512045 ps
CPU time 12.57 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204784 kb
Host smart-37fca7b4-8afd-4030-b2a9-473f3de1eaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720
54250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1172054250
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1357471721
Short name T1605
Test name
Test status
Simulation time 8434980988 ps
CPU time 11.19 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204836 kb
Host smart-a153dcdc-f11b-4080-8452-d7f0c0ebc5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13574
71721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1357471721
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.913656372
Short name T1444
Test name
Test status
Simulation time 8473477472 ps
CPU time 11.25 seconds
Started May 19 02:02:14 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204868 kb
Host smart-1e329488-d9bc-4d15-a655-8e04de24b3c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=913656372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.913656372
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.2279753670
Short name T1371
Test name
Test status
Simulation time 8390348624 ps
CPU time 10.61 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:10 PM PDT 24
Peak memory 204788 kb
Host smart-3bc74a69-31de-4167-86f2-99d6dd718256
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2279753670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2279753670
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.3929408504
Short name T1130
Test name
Test status
Simulation time 8454634966 ps
CPU time 10.8 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204708 kb
Host smart-8ec34a72-dc00-455d-9d65-84b14d6c9d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39294
08504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.3929408504
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2079623687
Short name T453
Test name
Test status
Simulation time 8378138952 ps
CPU time 10.15 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204820 kb
Host smart-ba43bb87-a000-4abc-9fc7-90683e0f48f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20796
23687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2079623687
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2714274103
Short name T1182
Test name
Test status
Simulation time 8384742417 ps
CPU time 11.23 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204788 kb
Host smart-a4742453-84c1-4b7f-84c1-1429c8b6a98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27142
74103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2714274103
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1295094460
Short name T1249
Test name
Test status
Simulation time 8427825383 ps
CPU time 11.23 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204868 kb
Host smart-44df4403-868e-41ed-9974-796a631774e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
94460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1295094460
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.422339396
Short name T789
Test name
Test status
Simulation time 8379527561 ps
CPU time 12.28 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204712 kb
Host smart-d704afd1-ce88-4c2e-89ef-3de30e4b936c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
9396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.422339396
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2906836818
Short name T1126
Test name
Test status
Simulation time 8401914981 ps
CPU time 11.64 seconds
Started May 19 02:02:04 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204852 kb
Host smart-84e0ae05-7c7d-4ab7-9a63-aad014bb97e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
36818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2906836818
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.143875651
Short name T1683
Test name
Test status
Simulation time 8992883067 ps
CPU time 11.56 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204820 kb
Host smart-87fc07d2-9571-4b83-86cc-e763a55d345d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
5651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.143875651
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.959686084
Short name T1047
Test name
Test status
Simulation time 8518304780 ps
CPU time 13.9 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:23 PM PDT 24
Peak memory 204776 kb
Host smart-1e10bc37-2026-4342-8ed9-572deaab21c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95968
6084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.959686084
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.727015830
Short name T1289
Test name
Test status
Simulation time 8463585859 ps
CPU time 10.81 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204688 kb
Host smart-5e06aa77-58e7-4075-b8d2-9814a2206bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72701
5830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.727015830
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4247844610
Short name T1388
Test name
Test status
Simulation time 8373425799 ps
CPU time 11.18 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:14 PM PDT 24
Peak memory 204780 kb
Host smart-0639b415-bc51-48c1-b569-21499fee1f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
44610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4247844610
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2170774443
Short name T317
Test name
Test status
Simulation time 8479893287 ps
CPU time 11.08 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204816 kb
Host smart-7932786c-7429-4d32-8d4a-662a3a6ea6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21707
74443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2170774443
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3030727860
Short name T961
Test name
Test status
Simulation time 8431155349 ps
CPU time 13.4 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204864 kb
Host smart-2bb55660-875a-460c-9ea6-2d5322e7798c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30307
27860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3030727860
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2511055967
Short name T1201
Test name
Test status
Simulation time 11498395394 ps
CPU time 13.89 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:27 PM PDT 24
Peak memory 204844 kb
Host smart-6a316c2e-75d5-43a3-8819-55b6070bcc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25110
55967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2511055967
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3394782480
Short name T1122
Test name
Test status
Simulation time 8412785051 ps
CPU time 12.95 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204796 kb
Host smart-4f149d63-6edd-4015-8043-e45d3c34f1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33947
82480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3394782480
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.948760488
Short name T1044
Test name
Test status
Simulation time 8393804936 ps
CPU time 13.17 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204776 kb
Host smart-af4b064e-b058-4be1-836f-83ca64a4e3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94876
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.948760488
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1761060356
Short name T1080
Test name
Test status
Simulation time 8387931525 ps
CPU time 11.46 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:14 PM PDT 24
Peak memory 204772 kb
Host smart-44236c5c-fd42-4343-be1e-de9d4ff140fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
60356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1761060356
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1641056797
Short name T1350
Test name
Test status
Simulation time 8381657994 ps
CPU time 11.2 seconds
Started May 19 02:02:05 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204832 kb
Host smart-46a3844d-b377-4eef-8677-f7eee4b27e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16410
56797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1641056797
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2470537170
Short name T967
Test name
Test status
Simulation time 8449636862 ps
CPU time 11.98 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204864 kb
Host smart-c5ae03c3-7fbb-4d2f-8758-5175a9f457aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24705
37170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2470537170
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.3351669186
Short name T1714
Test name
Test status
Simulation time 8427417659 ps
CPU time 10.47 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204796 kb
Host smart-a9c889bf-8d7c-4a85-8ba1-7bc4bcdfcf32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33516
69186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.3351669186
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3040669189
Short name T561
Test name
Test status
Simulation time 8370643160 ps
CPU time 11.43 seconds
Started May 19 02:02:04 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204776 kb
Host smart-bd0dff78-bf37-4a27-8b54-6a06d2bad41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
69189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3040669189
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2723113365
Short name T1748
Test name
Test status
Simulation time 8365105694 ps
CPU time 10.99 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204788 kb
Host smart-5c9d42e5-f13d-4d1c-a77c-1a8bfd142c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27231
13365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2723113365
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3398735656
Short name T1321
Test name
Test status
Simulation time 28445603769 ps
CPU time 53.72 seconds
Started May 19 02:02:25 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204804 kb
Host smart-b80c45d7-827d-4f89-b85a-27762e1c6438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
35656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3398735656
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3122087828
Short name T1300
Test name
Test status
Simulation time 8392483473 ps
CPU time 11.12 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204844 kb
Host smart-94dd61f8-e270-4aa8-8d03-c75d799fe133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31220
87828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3122087828
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2848501780
Short name T784
Test name
Test status
Simulation time 8383645321 ps
CPU time 10.86 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204872 kb
Host smart-42b8b535-8a1d-4e57-9fba-7b0a64cfbe13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
01780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2848501780
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.663552169
Short name T80
Test name
Test status
Simulation time 8394614857 ps
CPU time 10.97 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204712 kb
Host smart-1d0b2f2c-128c-48d3-a6fa-f1338b49eef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66355
2169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.663552169
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1596425043
Short name T768
Test name
Test status
Simulation time 8370401246 ps
CPU time 12.52 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204832 kb
Host smart-54a213ff-edb7-4ffc-acdd-4071ff91da4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
25043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1596425043
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1718452270
Short name T169
Test name
Test status
Simulation time 8414350698 ps
CPU time 13.14 seconds
Started May 19 02:02:05 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204856 kb
Host smart-5051401f-ecb6-442b-88f1-f0ee758a62ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
52270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1718452270
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1616880892
Short name T1619
Test name
Test status
Simulation time 8369954515 ps
CPU time 12.05 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:15 PM PDT 24
Peak memory 204768 kb
Host smart-e066b818-178a-42f0-a6c3-f9d69c2948c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16168
80892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1616880892
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.380925084
Short name T1060
Test name
Test status
Simulation time 8441469538 ps
CPU time 11.2 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204796 kb
Host smart-ec10e8ae-20ad-4929-9b20-a1df579a0305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
5084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.380925084
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3117712275
Short name T1543
Test name
Test status
Simulation time 8429239483 ps
CPU time 11.9 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204840 kb
Host smart-c61e8aac-fde1-4951-9925-db471a81e3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177
12275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3117712275
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2215596213
Short name T1479
Test name
Test status
Simulation time 8389805290 ps
CPU time 11.13 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204832 kb
Host smart-21bbdc74-673c-4994-b945-79a893878c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22155
96213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2215596213
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.3854440956
Short name T548
Test name
Test status
Simulation time 8486137739 ps
CPU time 12.29 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204800 kb
Host smart-a18d759c-abfe-4303-afa0-45cfaa973e33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3854440956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.3854440956
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.378320267
Short name T824
Test name
Test status
Simulation time 8397962010 ps
CPU time 10.93 seconds
Started May 19 02:02:13 PM PDT 24
Finished May 19 02:02:27 PM PDT 24
Peak memory 204800 kb
Host smart-cf384dc6-d2c2-4dc8-b308-8a1179377b31
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=378320267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.378320267
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1165352985
Short name T506
Test name
Test status
Simulation time 8399412533 ps
CPU time 10.98 seconds
Started May 19 02:02:15 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204832 kb
Host smart-88565cd2-69ef-4530-ac12-78199bf5cefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11653
52985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1165352985
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1152090905
Short name T714
Test name
Test status
Simulation time 8381159338 ps
CPU time 11.55 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204824 kb
Host smart-7da0964f-e339-4b12-b313-7c313ee2580c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
90905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1152090905
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3374040985
Short name T105
Test name
Test status
Simulation time 8418020127 ps
CPU time 12.98 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204816 kb
Host smart-5295b48f-d3bb-418c-b8d7-8b29aaa40ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740
40985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3374040985
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3551210349
Short name T10
Test name
Test status
Simulation time 8403053609 ps
CPU time 11.2 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:17 PM PDT 24
Peak memory 204728 kb
Host smart-a4712178-581e-4eac-b1d6-06aa8ac24c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35512
10349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3551210349
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1416112154
Short name T1058
Test name
Test status
Simulation time 9061740369 ps
CPU time 12.42 seconds
Started May 19 02:02:10 PM PDT 24
Finished May 19 02:02:27 PM PDT 24
Peak memory 205088 kb
Host smart-ffc10b4c-50bd-47be-860b-47eefa5a514c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14161
12154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1416112154
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2316773778
Short name T1156
Test name
Test status
Simulation time 8536569098 ps
CPU time 13.17 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204796 kb
Host smart-54bc41c3-d6aa-4fdd-874d-0f869f5c4957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
73778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2316773778
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2341568556
Short name T1464
Test name
Test status
Simulation time 8465854934 ps
CPU time 11.75 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204808 kb
Host smart-0ad9188d-1d82-4ddf-8300-681bac4feeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23415
68556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2341568556
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1273168720
Short name T1342
Test name
Test status
Simulation time 8368553704 ps
CPU time 10.84 seconds
Started May 19 02:02:10 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204856 kb
Host smart-98867401-db77-4fd8-8b4c-a511a9bc928c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12731
68720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1273168720
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4282387291
Short name T697
Test name
Test status
Simulation time 8408617741 ps
CPU time 10.52 seconds
Started May 19 02:02:12 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204760 kb
Host smart-94221189-21fb-4c3d-b03c-85d133acf9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
87291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4282387291
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1865429908
Short name T1612
Test name
Test status
Simulation time 8391718867 ps
CPU time 10.5 seconds
Started May 19 02:02:05 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204772 kb
Host smart-96256034-f40c-4a86-9441-9204c32d4992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18654
29908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1865429908
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.254562756
Short name T5
Test name
Test status
Simulation time 11528298102 ps
CPU time 13.03 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204772 kb
Host smart-d8930ea3-af8e-4391-8a28-d63992cc6554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25456
2756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.254562756
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3650293936
Short name T452
Test name
Test status
Simulation time 8465759708 ps
CPU time 12.61 seconds
Started May 19 02:02:12 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204808 kb
Host smart-de20a833-f68f-4394-a41c-2afbeab72edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
93936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3650293936
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.597831094
Short name T76
Test name
Test status
Simulation time 8379908045 ps
CPU time 11.03 seconds
Started May 19 02:02:01 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 204796 kb
Host smart-2c9e9e19-747a-4d44-a4c8-b7e534d42986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59783
1094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.597831094
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.596267415
Short name T1085
Test name
Test status
Simulation time 8417272874 ps
CPU time 10.92 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 205124 kb
Host smart-144c1ae2-fe7f-407e-ad35-1351f31fd731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59626
7415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.596267415
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3487808190
Short name T927
Test name
Test status
Simulation time 8370407185 ps
CPU time 11.42 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204772 kb
Host smart-187b3164-89fc-409c-b418-7808b8200782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34878
08190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3487808190
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3794449635
Short name T540
Test name
Test status
Simulation time 8397502281 ps
CPU time 11.06 seconds
Started May 19 02:02:12 PM PDT 24
Finished May 19 02:02:27 PM PDT 24
Peak memory 204744 kb
Host smart-d7264014-470d-43bd-9520-9153bbb6c287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37944
49635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3794449635
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3139630403
Short name T1055
Test name
Test status
Simulation time 8448763502 ps
CPU time 11.33 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204804 kb
Host smart-cdffbbd8-eb11-4b5b-8e5d-669ad1638b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31396
30403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3139630403
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.4026218375
Short name T1051
Test name
Test status
Simulation time 8413872808 ps
CPU time 11.59 seconds
Started May 19 02:02:04 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204756 kb
Host smart-10e65340-9a44-43e2-8241-aeb4e6103b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262
18375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.4026218375
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2890728363
Short name T882
Test name
Test status
Simulation time 8367037042 ps
CPU time 13.26 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204652 kb
Host smart-aa9d2972-6135-4c0e-be2e-7bc665396993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28907
28363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2890728363
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2579577540
Short name T647
Test name
Test status
Simulation time 8364463124 ps
CPU time 11.72 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204744 kb
Host smart-656e8342-309a-4356-b91a-93fc30fdbc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25795
77540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2579577540
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1269303812
Short name T236
Test name
Test status
Simulation time 16858999441 ps
CPU time 28.29 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204676 kb
Host smart-f726ee8c-43d0-4ae3-a620-908b79571fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12693
03812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1269303812
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2755505365
Short name T461
Test name
Test status
Simulation time 8417602600 ps
CPU time 11.82 seconds
Started May 19 02:02:05 PM PDT 24
Finished May 19 02:02:23 PM PDT 24
Peak memory 204756 kb
Host smart-bac8ff4b-d401-453e-9496-897943f2fda1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27555
05365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2755505365
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1379750752
Short name T608
Test name
Test status
Simulation time 8456389397 ps
CPU time 13.03 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204772 kb
Host smart-6aeac178-d6b3-49a3-ab5f-142778f0dc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13797
50752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1379750752
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.766881918
Short name T394
Test name
Test status
Simulation time 8372598286 ps
CPU time 13.73 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204992 kb
Host smart-5056c71b-b73f-4072-af34-debee6cc58bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76688
1918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.766881918
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1056379809
Short name T521
Test name
Test status
Simulation time 8382638099 ps
CPU time 11.15 seconds
Started May 19 02:02:11 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 205052 kb
Host smart-b426876b-8f2e-4c5d-970c-1072967c1be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10563
79809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1056379809
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.663429084
Short name T661
Test name
Test status
Simulation time 8368866550 ps
CPU time 12.46 seconds
Started May 19 02:02:12 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204800 kb
Host smart-47a70af9-265b-4011-8718-95daf6e48671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66342
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.663429084
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.729748616
Short name T879
Test name
Test status
Simulation time 8468182199 ps
CPU time 11.32 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:11 PM PDT 24
Peak memory 204756 kb
Host smart-c39eb852-be15-4470-9c68-0d145aa3552b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72974
8616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.729748616
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2044435625
Short name T1540
Test name
Test status
Simulation time 8385540809 ps
CPU time 11.94 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204844 kb
Host smart-ca2dfcf1-0743-4f8a-b128-1d131a876872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
35625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2044435625
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.707468951
Short name T653
Test name
Test status
Simulation time 8416979004 ps
CPU time 10.65 seconds
Started May 19 02:02:10 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 205084 kb
Host smart-1196b93f-13e7-419f-8cf7-00373b9a9a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70746
8951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.707468951
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.2439809839
Short name T90
Test name
Test status
Simulation time 8467474775 ps
CPU time 10.89 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204828 kb
Host smart-0fd39b45-0cca-4062-ad5c-aabe1b0e254a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2439809839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.2439809839
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.488998141
Short name T910
Test name
Test status
Simulation time 8381449662 ps
CPU time 11.3 seconds
Started May 19 02:02:15 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204836 kb
Host smart-747206d6-9b4e-4125-b162-d8248f19faf8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=488998141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.488998141
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.1192398397
Short name T746
Test name
Test status
Simulation time 8462763674 ps
CPU time 11.25 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204816 kb
Host smart-20357881-fc9e-44e9-bb3f-7f2213ca6088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11923
98397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.1192398397
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2925383264
Short name T1390
Test name
Test status
Simulation time 8386123685 ps
CPU time 11.59 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:15 PM PDT 24
Peak memory 204848 kb
Host smart-9db9a064-c4d5-4f02-80b5-ffaa9239c4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29253
83264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2925383264
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1462479125
Short name T1029
Test name
Test status
Simulation time 8642087247 ps
CPU time 13.5 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:19 PM PDT 24
Peak memory 204856 kb
Host smart-013d13bf-7f16-43de-b083-37584c434155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624
79125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1462479125
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2144232346
Short name T1324
Test name
Test status
Simulation time 8365543695 ps
CPU time 10.93 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:15 PM PDT 24
Peak memory 204792 kb
Host smart-38811225-b0e7-44a7-9221-e3c2187d59a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21442
32346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2144232346
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1873534535
Short name T1472
Test name
Test status
Simulation time 8419582235 ps
CPU time 11.38 seconds
Started May 19 02:02:06 PM PDT 24
Finished May 19 02:02:23 PM PDT 24
Peak memory 204852 kb
Host smart-d02c49f5-9f88-4ec3-a91f-a52307eadd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18735
34535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1873534535
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1075497683
Short name T1143
Test name
Test status
Simulation time 9031935353 ps
CPU time 11.38 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204820 kb
Host smart-739f5695-da55-4a0b-ba40-68aee92bd375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10754
97683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1075497683
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1172236923
Short name T1196
Test name
Test status
Simulation time 8458746865 ps
CPU time 11.97 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204852 kb
Host smart-16f44794-9201-4654-b05b-0248596fd176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
36923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1172236923
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1322354671
Short name T1500
Test name
Test status
Simulation time 8431336364 ps
CPU time 11.35 seconds
Started May 19 02:02:04 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 205040 kb
Host smart-9222c90e-ad4a-452a-b3f7-28b09bb20e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13223
54671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1322354671
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.4058655042
Short name T954
Test name
Test status
Simulation time 8366886761 ps
CPU time 10.79 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204812 kb
Host smart-cbbe7f54-c849-4171-93d7-c68e885ae063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40586
55042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.4058655042
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2436430219
Short name T1286
Test name
Test status
Simulation time 8406064535 ps
CPU time 10.97 seconds
Started May 19 02:02:11 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 205084 kb
Host smart-3049d304-a0d2-4600-a74d-72c57ba45ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24364
30219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2436430219
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1781815039
Short name T1455
Test name
Test status
Simulation time 11556595032 ps
CPU time 16.33 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204820 kb
Host smart-a79b60ad-956b-4007-a040-758ef694ddc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
15039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1781815039
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.314588290
Short name T742
Test name
Test status
Simulation time 8495989414 ps
CPU time 13.4 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:02:42 PM PDT 24
Peak memory 205008 kb
Host smart-c2c0f39b-4fb4-4c1e-8382-8859552819b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458
8290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.314588290
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1621058962
Short name T23
Test name
Test status
Simulation time 8372357715 ps
CPU time 11.88 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 205024 kb
Host smart-637768c0-fb21-49a6-9363-da75a40e7623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16210
58962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1621058962
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3384619569
Short name T662
Test name
Test status
Simulation time 8440036995 ps
CPU time 13.48 seconds
Started May 19 02:02:02 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204852 kb
Host smart-0b6bb373-737e-41a2-a511-20bfb9faeaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
19569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3384619569
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3192537605
Short name T1046
Test name
Test status
Simulation time 8395749388 ps
CPU time 14.83 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204860 kb
Host smart-99cf4559-82eb-4a84-b36a-2598d3d14649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31925
37605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3192537605
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1908691413
Short name T200
Test name
Test status
Simulation time 8389459076 ps
CPU time 13.55 seconds
Started May 19 02:02:17 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204776 kb
Host smart-a0d969e2-415e-4b3f-94e2-77aed6dd0991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19086
91413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1908691413
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.2970623300
Short name T1752
Test name
Test status
Simulation time 8433041043 ps
CPU time 11.76 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204788 kb
Host smart-3ae6457f-db8a-47ff-8aac-9e0f4222e926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
23300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.2970623300
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2289205225
Short name T1496
Test name
Test status
Simulation time 8401327468 ps
CPU time 13.88 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204784 kb
Host smart-d23fead7-1aa5-4fe5-a61a-75efa7802a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
05225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2289205225
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3770297320
Short name T1755
Test name
Test status
Simulation time 8365739127 ps
CPU time 11.79 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204732 kb
Host smart-d91a8720-ac82-4d75-a33f-2c32146c9de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37702
97320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3770297320
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4249157412
Short name T278
Test name
Test status
Simulation time 8413306682 ps
CPU time 10.87 seconds
Started May 19 02:02:08 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204724 kb
Host smart-f195bde2-6c1a-4177-ab41-b7c75d280d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42491
57412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4249157412
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.438065150
Short name T1776
Test name
Test status
Simulation time 8403494090 ps
CPU time 10.9 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204880 kb
Host smart-a4adaf56-f46d-4ebc-a00f-198add561f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43806
5150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.438065150
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3063317065
Short name T687
Test name
Test status
Simulation time 8398724881 ps
CPU time 10.75 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204776 kb
Host smart-06072d5f-be3f-455c-a607-5d9af06bdb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30633
17065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3063317065
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2657876972
Short name T899
Test name
Test status
Simulation time 8365827551 ps
CPU time 11.55 seconds
Started May 19 02:02:04 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204796 kb
Host smart-67c1e514-137f-4769-aa86-2fc9a388b34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26578
76972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2657876972
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1844164394
Short name T1765
Test name
Test status
Simulation time 8378262422 ps
CPU time 11.02 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204796 kb
Host smart-2489ecab-6185-4bf1-a28e-75c7ecab560b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
64394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1844164394
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.974931960
Short name T1119
Test name
Test status
Simulation time 8402110321 ps
CPU time 10.35 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 204740 kb
Host smart-2a0805dc-c2e5-4b78-ab75-f28b092876d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97493
1960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.974931960
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4263326060
Short name T1067
Test name
Test status
Simulation time 8405052911 ps
CPU time 10.74 seconds
Started May 19 02:02:12 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204804 kb
Host smart-9f879b6a-780b-4571-a764-451f96c367ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42633
26060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4263326060
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2909340596
Short name T1100
Test name
Test status
Simulation time 8407713640 ps
CPU time 11.04 seconds
Started May 19 02:02:14 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 205020 kb
Host smart-42af84f7-c0a4-4f33-8e7a-c3d22ec8eed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
40596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2909340596
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1182828703
Short name T380
Test name
Test status
Simulation time 8415638895 ps
CPU time 10.79 seconds
Started May 19 02:02:04 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 204844 kb
Host smart-02c50e83-f506-4cc2-94d4-bc1d558e4ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828
28703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1182828703
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1941771033
Short name T1373
Test name
Test status
Simulation time 8503024272 ps
CPU time 11.25 seconds
Started May 19 02:02:26 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204788 kb
Host smart-125d34e9-1e0c-4a84-876f-51459c1cb745
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1941771033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1941771033
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1703547404
Short name T1459
Test name
Test status
Simulation time 8410324389 ps
CPU time 12.31 seconds
Started May 19 02:02:35 PM PDT 24
Finished May 19 02:02:49 PM PDT 24
Peak memory 204784 kb
Host smart-f716b03d-5911-481e-b958-8d52d4c6c4c9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1703547404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1703547404
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2259898166
Short name T1240
Test name
Test status
Simulation time 8387339132 ps
CPU time 13.32 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204816 kb
Host smart-5d9802a6-cafe-4578-bfa2-169f95af1681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
98166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2259898166
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3591106036
Short name T1549
Test name
Test status
Simulation time 8393892060 ps
CPU time 12.05 seconds
Started May 19 02:02:16 PM PDT 24
Finished May 19 02:02:29 PM PDT 24
Peak memory 204784 kb
Host smart-a2032dd4-57c7-4643-b6a5-59c1423d045e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35911
06036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3591106036
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2266313357
Short name T1720
Test name
Test status
Simulation time 8372154170 ps
CPU time 12.63 seconds
Started May 19 02:02:07 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204728 kb
Host smart-b2a28bbf-6a20-4dec-b39a-a15268929fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
13357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2266313357
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2354728005
Short name T196
Test name
Test status
Simulation time 9056147924 ps
CPU time 11.77 seconds
Started May 19 02:02:05 PM PDT 24
Finished May 19 02:02:23 PM PDT 24
Peak memory 204864 kb
Host smart-a3c1ad07-111d-4cd9-872b-748e6d6a64d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
28005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2354728005
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2205101323
Short name T953
Test name
Test status
Simulation time 8361366209 ps
CPU time 11.28 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204764 kb
Host smart-f58f16e3-b167-4bff-a8e7-fd392f196448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22051
01323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2205101323
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2041619425
Short name T1384
Test name
Test status
Simulation time 8385754541 ps
CPU time 11.82 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204840 kb
Host smart-0bf7b063-da73-4da6-9a1a-702b380f42be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20416
19425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2041619425
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.706008002
Short name T371
Test name
Test status
Simulation time 9099280409 ps
CPU time 13.52 seconds
Started May 19 02:02:03 PM PDT 24
Finished May 19 02:02:23 PM PDT 24
Peak memory 204804 kb
Host smart-07f47bf3-2100-4c8f-93bf-731f3cec8e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70600
8002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.706008002
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1293089771
Short name T1687
Test name
Test status
Simulation time 8431808445 ps
CPU time 11.15 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204792 kb
Host smart-c3db552f-dfa0-43d8-a342-40a4529d84c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
89771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1293089771
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.908841633
Short name T643
Test name
Test status
Simulation time 8451387816 ps
CPU time 12 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204800 kb
Host smart-375df2f9-259d-48d9-9599-2681caf0dca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90884
1633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.908841633
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.480061836
Short name T92
Test name
Test status
Simulation time 8422724759 ps
CPU time 12.49 seconds
Started May 19 02:02:11 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204772 kb
Host smart-6e174415-adfb-403b-8ff2-2f206573e8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48006
1836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.480061836
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2863220452
Short name T404
Test name
Test status
Simulation time 8496337746 ps
CPU time 11.54 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204748 kb
Host smart-d89b2fae-f1d9-4920-b7aa-45a8bd99309d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
20452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2863220452
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1155645658
Short name T1435
Test name
Test status
Simulation time 8420997521 ps
CPU time 10.97 seconds
Started May 19 02:02:12 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204760 kb
Host smart-ccf49e31-02b1-4cbd-b924-e3a8d05212ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11556
45658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1155645658
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2839601864
Short name T1274
Test name
Test status
Simulation time 11525932713 ps
CPU time 14.24 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204688 kb
Host smart-f93945ee-526f-49ed-a2f2-4c32c1a5abb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28396
01864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2839601864
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3184813633
Short name T1059
Test name
Test status
Simulation time 8428931528 ps
CPU time 11.25 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:32 PM PDT 24
Peak memory 204768 kb
Host smart-75bd78ac-c703-4f93-bdfa-2c0ac92a7dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31848
13633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3184813633
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1078466931
Short name T358
Test name
Test status
Simulation time 8375269988 ps
CPU time 11.73 seconds
Started May 19 02:02:17 PM PDT 24
Finished May 19 02:02:30 PM PDT 24
Peak memory 204772 kb
Host smart-80379b3c-6771-4169-a3bf-05039a5102d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10784
66931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1078466931
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4168409769
Short name T1414
Test name
Test status
Simulation time 8429578732 ps
CPU time 10.97 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:31 PM PDT 24
Peak memory 204592 kb
Host smart-e603fa04-e608-4761-9d8a-1386e8c454d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41684
09769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4168409769
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2978523445
Short name T1738
Test name
Test status
Simulation time 8416394257 ps
CPU time 12.29 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204856 kb
Host smart-802a2886-d36f-47de-ad7c-d6fb079f7127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29785
23445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2978523445
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2253118352
Short name T1544
Test name
Test status
Simulation time 8393389368 ps
CPU time 13.7 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204852 kb
Host smart-cf3f0ac4-c832-45b8-b90a-ff510db56afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
18352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2253118352
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3502216437
Short name T366
Test name
Test status
Simulation time 8379248593 ps
CPU time 11.31 seconds
Started May 19 02:02:06 PM PDT 24
Finished May 19 02:02:23 PM PDT 24
Peak memory 204772 kb
Host smart-14004ce5-83c8-4d85-bd7b-aff50cbe3743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35022
16437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3502216437
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1163573859
Short name T315
Test name
Test status
Simulation time 8438884822 ps
CPU time 11.71 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204736 kb
Host smart-13fbadd3-3ce5-4a5d-a7a4-6b7d14dd8471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635
73859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1163573859
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2210335066
Short name T1349
Test name
Test status
Simulation time 8370100728 ps
CPU time 10.92 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:31 PM PDT 24
Peak memory 204776 kb
Host smart-c70857e1-098c-4968-9f72-9f917af6aa2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
35066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2210335066
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3921871739
Short name T1109
Test name
Test status
Simulation time 8397236776 ps
CPU time 11.21 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204824 kb
Host smart-3c9ae146-2e40-4689-833f-ed4eecc78f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
71739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3921871739
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3812336531
Short name T1521
Test name
Test status
Simulation time 8417265902 ps
CPU time 12.75 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204780 kb
Host smart-256c2d23-afe8-4462-b31f-493dcda48c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38123
36531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3812336531
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3947346580
Short name T592
Test name
Test status
Simulation time 8445066565 ps
CPU time 11.27 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:31 PM PDT 24
Peak memory 204864 kb
Host smart-5d095e27-afef-44cb-b6e5-b28ce47e07e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39473
46580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3947346580
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3790470041
Short name T585
Test name
Test status
Simulation time 8436355972 ps
CPU time 11.95 seconds
Started May 19 02:02:16 PM PDT 24
Finished May 19 02:02:29 PM PDT 24
Peak memory 204764 kb
Host smart-c175f01a-0d11-425c-9414-4825fdac9abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37904
70041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3790470041
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3960820495
Short name T1006
Test name
Test status
Simulation time 8407211780 ps
CPU time 10.91 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204856 kb
Host smart-a5ec0cfb-30d9-4fd4-bffc-2eaaba13421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
20495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3960820495
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1070163632
Short name T113
Test name
Test status
Simulation time 8383135760 ps
CPU time 11.33 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204764 kb
Host smart-b26f834a-cb90-4115-98d1-79d76209b69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
63632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1070163632
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1509282245
Short name T720
Test name
Test status
Simulation time 8388120555 ps
CPU time 12.27 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204700 kb
Host smart-3d220515-741b-4ac9-a63a-fd0709e18050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15092
82245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1509282245
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3402347798
Short name T165
Test name
Test status
Simulation time 8418903275 ps
CPU time 11.37 seconds
Started May 19 02:02:11 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204800 kb
Host smart-8fd8a72b-b802-440d-91ef-3f4dadbc2a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34023
47798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3402347798
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3878142068
Short name T1256
Test name
Test status
Simulation time 8397471682 ps
CPU time 11.17 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:31 PM PDT 24
Peak memory 204852 kb
Host smart-645ede56-3766-4345-9ddd-3d80f19275bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
42068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3878142068
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2407032606
Short name T1574
Test name
Test status
Simulation time 8404888361 ps
CPU time 10.93 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204812 kb
Host smart-1b621914-c6dc-4142-85bf-172b76ccb4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24070
32606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2407032606
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.1118828095
Short name T1377
Test name
Test status
Simulation time 8470570040 ps
CPU time 10.95 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204788 kb
Host smart-f8458974-be8d-45ea-86ad-4d0407093f58
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1118828095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.1118828095
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.4105959989
Short name T326
Test name
Test status
Simulation time 8382193430 ps
CPU time 11.1 seconds
Started May 19 02:02:29 PM PDT 24
Finished May 19 02:02:40 PM PDT 24
Peak memory 204804 kb
Host smart-c16f8146-afbc-412d-a99d-fd7595da222b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4105959989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.4105959989
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.232651294
Short name T354
Test name
Test status
Simulation time 8427489869 ps
CPU time 11.6 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204868 kb
Host smart-dc612bf3-388d-41d5-9399-251ed790c34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23265
1294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.232651294
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3564551345
Short name T353
Test name
Test status
Simulation time 8392301082 ps
CPU time 12.9 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204788 kb
Host smart-4f890f9e-f720-4594-a875-268a8a97ff53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35645
51345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3564551345
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2697096148
Short name T1038
Test name
Test status
Simulation time 8366254227 ps
CPU time 10.98 seconds
Started May 19 02:02:08 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 205012 kb
Host smart-14d6beef-a837-410d-92fa-3caed2a95fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
96148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2697096148
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1984342521
Short name T1520
Test name
Test status
Simulation time 8382107295 ps
CPU time 11.39 seconds
Started May 19 02:02:25 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204848 kb
Host smart-da67e15f-e763-461b-b7db-dc592f1df7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19843
42521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1984342521
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3334532275
Short name T840
Test name
Test status
Simulation time 8562019908 ps
CPU time 12.54 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:27 PM PDT 24
Peak memory 204824 kb
Host smart-4d5495db-1ae0-4faf-8441-f2d488795972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33345
32275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3334532275
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.272608319
Short name T1296
Test name
Test status
Simulation time 8463309420 ps
CPU time 11 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204820 kb
Host smart-5729688d-fe96-4d23-b006-6ab680427d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27260
8319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.272608319
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1320289902
Short name T1097
Test name
Test status
Simulation time 8394192859 ps
CPU time 11.57 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204756 kb
Host smart-970448a3-c26b-4a6c-a9f4-94215a36e35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13202
89902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1320289902
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4245441647
Short name T1230
Test name
Test status
Simulation time 8459990176 ps
CPU time 12.04 seconds
Started May 19 02:02:10 PM PDT 24
Finished May 19 02:02:26 PM PDT 24
Peak memory 204860 kb
Host smart-a08b1d14-cc3b-4ec4-8902-2439f0517dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42454
41647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4245441647
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1119658642
Short name T313
Test name
Test status
Simulation time 8410611998 ps
CPU time 10.29 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204832 kb
Host smart-383452e6-1492-46bf-9aee-24530cdea886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
58642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1119658642
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.584109182
Short name T959
Test name
Test status
Simulation time 11500512081 ps
CPU time 15.85 seconds
Started May 19 02:02:33 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204828 kb
Host smart-cfe73578-952b-4a82-9ec9-b55e34f6025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58410
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.584109182
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1858197077
Short name T683
Test name
Test status
Simulation time 8476203924 ps
CPU time 11.64 seconds
Started May 19 02:02:34 PM PDT 24
Finished May 19 02:02:47 PM PDT 24
Peak memory 204772 kb
Host smart-edccc59b-8a84-427a-beda-f01fe967f878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18581
97077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1858197077
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1119527545
Short name T1705
Test name
Test status
Simulation time 8378023001 ps
CPU time 10.83 seconds
Started May 19 02:02:09 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204828 kb
Host smart-2cae32a2-51a5-49c3-8a35-8207f2a717d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11195
27545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1119527545
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2881116193
Short name T781
Test name
Test status
Simulation time 8421410994 ps
CPU time 11.06 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204884 kb
Host smart-c0b35271-64b6-4191-85fc-f8b2e6a0cc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
16193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2881116193
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3355320469
Short name T1454
Test name
Test status
Simulation time 8432988294 ps
CPU time 11.86 seconds
Started May 19 02:02:25 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204848 kb
Host smart-09cf2d2a-7705-426d-89a9-73995e8f373f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
20469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3355320469
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1284015760
Short name T976
Test name
Test status
Simulation time 8400983976 ps
CPU time 10.95 seconds
Started May 19 02:02:13 PM PDT 24
Finished May 19 02:02:32 PM PDT 24
Peak memory 204856 kb
Host smart-69f1c031-f363-4333-aefe-e1e121dd0c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12840
15760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1284015760
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.2235961589
Short name T923
Test name
Test status
Simulation time 8424843904 ps
CPU time 14.03 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:47 PM PDT 24
Peak memory 204812 kb
Host smart-ca14735a-b4c9-4c3c-9638-52b0a8eb9628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22359
61589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.2235961589
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3198994241
Short name T600
Test name
Test status
Simulation time 8367993490 ps
CPU time 11.2 seconds
Started May 19 02:02:25 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204796 kb
Host smart-9b124386-fe53-4b68-92ad-47596214f5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
94241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3198994241
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.684337264
Short name T868
Test name
Test status
Simulation time 8375046089 ps
CPU time 11.72 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204836 kb
Host smart-e98edd0b-31cf-44cf-b314-3b647e75cdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68433
7264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.684337264
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3379104068
Short name T387
Test name
Test status
Simulation time 8375305422 ps
CPU time 11.94 seconds
Started May 19 02:02:08 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 204816 kb
Host smart-8e8fdcbd-4db0-4e56-955f-695a79ee11d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33791
04068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3379104068
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.905467340
Short name T960
Test name
Test status
Simulation time 8415189035 ps
CPU time 11.66 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204848 kb
Host smart-09b6f174-65aa-4af0-932b-8450676e5195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90546
7340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.905467340
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3713050513
Short name T1727
Test name
Test status
Simulation time 8414835514 ps
CPU time 12.7 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204812 kb
Host smart-56fc6654-f7c1-4053-bf6b-1a7a49259cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37130
50513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3713050513
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1041738766
Short name T1103
Test name
Test status
Simulation time 8368913302 ps
CPU time 11.19 seconds
Started May 19 02:02:19 PM PDT 24
Finished May 19 02:02:31 PM PDT 24
Peak memory 204832 kb
Host smart-41f38961-8d49-415d-8946-70ae5c652575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10417
38766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1041738766
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3321381985
Short name T764
Test name
Test status
Simulation time 8385212494 ps
CPU time 10.51 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204764 kb
Host smart-ef94cf59-b8a1-4e06-8ca0-bfc150a06a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33213
81985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3321381985
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2727945082
Short name T1709
Test name
Test status
Simulation time 8379185729 ps
CPU time 10.77 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204840 kb
Host smart-f21a4f93-a9d5-4ca3-b89f-5e87bf6be7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27279
45082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2727945082
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.322830014
Short name T875
Test name
Test status
Simulation time 8465071386 ps
CPU time 10.94 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204708 kb
Host smart-ac6ec0e3-e2dc-4dc6-b926-c14d5f0f7be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
0014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.322830014
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.870258084
Short name T898
Test name
Test status
Simulation time 8400216682 ps
CPU time 12.89 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204788 kb
Host smart-749ceb8c-9cb0-448b-9f4f-f1fd76a1bb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87025
8084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.870258084
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2376907839
Short name T1167
Test name
Test status
Simulation time 8413907713 ps
CPU time 11.41 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204776 kb
Host smart-edef2fe4-265e-44d1-ac3c-9eef4357b435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23769
07839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2376907839
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2129349781
Short name T947
Test name
Test status
Simulation time 8382744892 ps
CPU time 10.75 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:56 PM PDT 24
Peak memory 204820 kb
Host smart-b3c45d05-a806-410a-8cea-32c5e03e11b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2129349781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2129349781
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.2274859061
Short name T1750
Test name
Test status
Simulation time 8408239844 ps
CPU time 11.3 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 204840 kb
Host smart-d1f4563d-b2d2-46ab-b254-e00b5f337cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22748
59061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.2274859061
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.172417885
Short name T1555
Test name
Test status
Simulation time 8398213270 ps
CPU time 13.44 seconds
Started May 19 02:02:38 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204884 kb
Host smart-8b9fb628-484b-40df-862e-1c5ad80fbf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
7885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.172417885
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2261106397
Short name T1138
Test name
Test status
Simulation time 8405607936 ps
CPU time 10.82 seconds
Started May 19 02:02:16 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204752 kb
Host smart-dcc03bf6-df66-4f01-8bb3-9c7122d93d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
06397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2261106397
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1355132444
Short name T546
Test name
Test status
Simulation time 8572845987 ps
CPU time 12.04 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 204816 kb
Host smart-b9c88464-c5b5-4cf6-b200-f24500d3b6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
32444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1355132444
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3402574396
Short name T1166
Test name
Test status
Simulation time 8378842014 ps
CPU time 11.38 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204756 kb
Host smart-2e632534-99b4-4241-b6b9-54652a73e7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
74396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3402574396
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2334508636
Short name T1174
Test name
Test status
Simulation time 8386982697 ps
CPU time 12.54 seconds
Started May 19 02:02:33 PM PDT 24
Finished May 19 02:02:46 PM PDT 24
Peak memory 204784 kb
Host smart-c963fa72-eff2-4fb9-8918-85ebdb356d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23345
08636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2334508636
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.473791057
Short name T1297
Test name
Test status
Simulation time 8994493303 ps
CPU time 12.06 seconds
Started May 19 02:02:25 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204712 kb
Host smart-204ddde0-c4fe-46af-8f50-97b4943b69fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47379
1057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.473791057
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2447541606
Short name T810
Test name
Test status
Simulation time 8477081010 ps
CPU time 12.21 seconds
Started May 19 02:02:31 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204848 kb
Host smart-1d0e231d-37c9-4051-9e2b-60e8aefe9d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24475
41606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2447541606
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1467844226
Short name T425
Test name
Test status
Simulation time 8376941809 ps
CPU time 11.31 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204868 kb
Host smart-71159c5a-2bc3-48ed-a3e7-5ebf9339a797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14678
44226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1467844226
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3254532229
Short name T1101
Test name
Test status
Simulation time 8487607008 ps
CPU time 12.3 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204776 kb
Host smart-6a3e59d3-a2f5-4ef8-b2eb-a0e8b54a5621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32545
32229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3254532229
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3522649629
Short name T853
Test name
Test status
Simulation time 8402701890 ps
CPU time 10.72 seconds
Started May 19 02:02:35 PM PDT 24
Finished May 19 02:02:47 PM PDT 24
Peak memory 204884 kb
Host smart-69d070c9-daa4-4b4b-8a03-6b23956e78f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35226
49629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3522649629
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.535379943
Short name T6
Test name
Test status
Simulation time 11520759276 ps
CPU time 15.02 seconds
Started May 19 02:02:33 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204864 kb
Host smart-07ff35e3-2c4d-499f-b907-a09f0ce94a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53537
9943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.535379943
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.45935720
Short name T1361
Test name
Test status
Simulation time 8466000338 ps
CPU time 10.61 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:52 PM PDT 24
Peak memory 204776 kb
Host smart-e0540d36-5e85-4c5e-9aa5-af45a095588d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45935
720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.45935720
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.244804164
Short name T1057
Test name
Test status
Simulation time 8371010653 ps
CPU time 11.37 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204724 kb
Host smart-615ae31a-aa5a-41aa-9edd-5b64482d81be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24480
4164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.244804164
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.672301885
Short name T149
Test name
Test status
Simulation time 8414833412 ps
CPU time 11.15 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204980 kb
Host smart-3829a8e0-790a-4f90-a28f-3f3ec1aa4b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67230
1885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.672301885
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1257500968
Short name T102
Test name
Test status
Simulation time 8471109049 ps
CPU time 14.02 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204784 kb
Host smart-b0bbaa1c-9a61-44a5-bbe7-d4e63caffd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575
00968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1257500968
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3198752472
Short name T1509
Test name
Test status
Simulation time 8375320410 ps
CPU time 10.95 seconds
Started May 19 02:02:16 PM PDT 24
Finished May 19 02:02:28 PM PDT 24
Peak memory 204844 kb
Host smart-a3e9616c-617a-437a-98e3-0115124c4447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31987
52472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3198752472
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2838990797
Short name T624
Test name
Test status
Simulation time 8414189600 ps
CPU time 11.39 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204848 kb
Host smart-7597fca4-d332-496a-9338-797ca82824d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28389
90797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2838990797
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.530615679
Short name T365
Test name
Test status
Simulation time 8412109928 ps
CPU time 12.69 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204752 kb
Host smart-8e76d756-ffc2-4503-96fb-bea8d67067b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53061
5679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.530615679
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3187907590
Short name T1331
Test name
Test status
Simulation time 8375958754 ps
CPU time 11 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204796 kb
Host smart-4268293a-6f7a-4506-bb85-7e3e8f972535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
07590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3187907590
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.841717595
Short name T902
Test name
Test status
Simulation time 8377069598 ps
CPU time 12.43 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 205008 kb
Host smart-f64626ba-66ce-405f-a9fb-790fef1b80de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84171
7595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.841717595
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1579987832
Short name T15
Test name
Test status
Simulation time 14486775169 ps
CPU time 26.2 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204788 kb
Host smart-ab015a7e-0779-4f72-8213-e1719289a8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
87832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1579987832
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2250052813
Short name T1152
Test name
Test status
Simulation time 8407833607 ps
CPU time 11.63 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204696 kb
Host smart-b3fe631c-b2f6-434f-b22c-a923c209eb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
52813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2250052813
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3057902248
Short name T1098
Test name
Test status
Simulation time 8441599611 ps
CPU time 12.75 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204852 kb
Host smart-a7d37a36-72d3-4491-8bc2-02061e6629b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
02248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3057902248
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1712511238
Short name T1715
Test name
Test status
Simulation time 8392957479 ps
CPU time 10.97 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204796 kb
Host smart-3fa0f341-23bb-4ee9-a712-7f4e24a687ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17125
11238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1712511238
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1823943113
Short name T1718
Test name
Test status
Simulation time 8369362680 ps
CPU time 12.29 seconds
Started May 19 02:02:22 PM PDT 24
Finished May 19 02:02:37 PM PDT 24
Peak memory 205016 kb
Host smart-476fe6ad-5975-401d-ad44-0d5a8f3dfa26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18239
43113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1823943113
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3233828172
Short name T1312
Test name
Test status
Simulation time 8387567483 ps
CPU time 10.58 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204852 kb
Host smart-2400a84b-b663-45c6-8381-f1c3703a5ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32338
28172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3233828172
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2365639269
Short name T702
Test name
Test status
Simulation time 8362650085 ps
CPU time 11.02 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:35 PM PDT 24
Peak memory 204804 kb
Host smart-f8202b10-0b39-46e5-9831-5d3a9b4b9da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23656
39269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2365639269
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3164802141
Short name T1071
Test name
Test status
Simulation time 8419738973 ps
CPU time 13.93 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:40 PM PDT 24
Peak memory 204756 kb
Host smart-36fa486e-066e-4af0-b187-5b0b1334983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31648
02141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3164802141
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.675759262
Short name T511
Test name
Test status
Simulation time 8390796284 ps
CPU time 10.89 seconds
Started May 19 02:02:36 PM PDT 24
Finished May 19 02:02:48 PM PDT 24
Peak memory 204788 kb
Host smart-722c6438-08ef-48a2-befa-fc54ab7a1158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67575
9262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.675759262
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.939064036
Short name T625
Test name
Test status
Simulation time 8396507607 ps
CPU time 12.08 seconds
Started May 19 02:02:25 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204720 kb
Host smart-bf723cb7-6fd0-44bb-8aa0-7992deb1cb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93906
4036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.939064036
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.1526000710
Short name T1499
Test name
Test status
Simulation time 8466707769 ps
CPU time 11.44 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204868 kb
Host smart-9cd3c560-7b74-44ac-a9ae-a15d3ddcd569
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1526000710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.1526000710
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2231098518
Short name T1699
Test name
Test status
Simulation time 8401667909 ps
CPU time 11.21 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:56 PM PDT 24
Peak memory 204776 kb
Host smart-557df47c-d474-404f-816f-8141a164e6f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2231098518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2231098518
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.2764019611
Short name T865
Test name
Test status
Simulation time 8434028859 ps
CPU time 11.52 seconds
Started May 19 02:02:42 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 204788 kb
Host smart-1dd56f77-a0c6-426a-a3af-78d1e9790446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
19611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.2764019611
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.4278378996
Short name T641
Test name
Test status
Simulation time 8383521853 ps
CPU time 10.99 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:36 PM PDT 24
Peak memory 204820 kb
Host smart-b5adfc60-2776-464c-a803-752099b1efd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42783
78996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.4278378996
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3448064094
Short name T487
Test name
Test status
Simulation time 8397603048 ps
CPU time 12.31 seconds
Started May 19 02:02:35 PM PDT 24
Finished May 19 02:02:48 PM PDT 24
Peak memory 204748 kb
Host smart-324a21bc-1e8b-437c-b1c4-dbf421a83fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34480
64094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3448064094
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3951549226
Short name T755
Test name
Test status
Simulation time 8373979229 ps
CPU time 14.8 seconds
Started May 19 02:02:36 PM PDT 24
Finished May 19 02:02:52 PM PDT 24
Peak memory 204856 kb
Host smart-cbed7c00-ca6b-4083-bd31-8e355d7b6ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
49226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3951549226
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.4062959632
Short name T1360
Test name
Test status
Simulation time 9190315643 ps
CPU time 13.45 seconds
Started May 19 02:02:23 PM PDT 24
Finished May 19 02:02:39 PM PDT 24
Peak memory 204856 kb
Host smart-4ad187f9-2bf1-4951-8fbd-b5a08aa11c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40629
59632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.4062959632
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3734854964
Short name T1252
Test name
Test status
Simulation time 8451205222 ps
CPU time 12.17 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:45 PM PDT 24
Peak memory 204836 kb
Host smart-2defc702-7d8f-4a7c-b82c-44c169e40b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37348
54964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3734854964
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.349766150
Short name T1135
Test name
Test status
Simulation time 8385248896 ps
CPU time 11.36 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:02:59 PM PDT 24
Peak memory 204804 kb
Host smart-13ee390c-f305-4cdb-a5cb-d1f2943a2b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34976
6150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.349766150
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3319094992
Short name T859
Test name
Test status
Simulation time 8364358649 ps
CPU time 12.67 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204852 kb
Host smart-3d9d7d81-893a-4ccd-8a5d-20e6453a78a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33190
94992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3319094992
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1684261313
Short name T1383
Test name
Test status
Simulation time 8437342984 ps
CPU time 12.63 seconds
Started May 19 02:02:39 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204844 kb
Host smart-0ffdcf16-a49b-4eb0-923b-f19a6f2af7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
61313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1684261313
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3597577625
Short name T1470
Test name
Test status
Simulation time 8414454249 ps
CPU time 11.96 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204812 kb
Host smart-c6200eb4-8741-4b40-9035-dfb5209b46c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35975
77625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3597577625
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.4197161334
Short name T486
Test name
Test status
Simulation time 11527063275 ps
CPU time 15.44 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 204760 kb
Host smart-590129eb-bc19-4e7c-9b40-e6be7d2371ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41971
61334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.4197161334
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2384237749
Short name T935
Test name
Test status
Simulation time 8438923731 ps
CPU time 11.14 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204776 kb
Host smart-845edcc6-e3a0-4e0d-8cc2-409a1b069dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
37749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2384237749
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.4141065269
Short name T1578
Test name
Test status
Simulation time 8395386961 ps
CPU time 10.48 seconds
Started May 19 02:02:21 PM PDT 24
Finished May 19 02:02:33 PM PDT 24
Peak memory 204768 kb
Host smart-4d74c34e-8e88-4dec-a81d-d1f357a0487e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
65269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.4141065269
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.905012605
Short name T139
Test name
Test status
Simulation time 8454675659 ps
CPU time 12.46 seconds
Started May 19 02:02:34 PM PDT 24
Finished May 19 02:02:47 PM PDT 24
Peak memory 204848 kb
Host smart-b33e7745-3511-404e-a30a-485430690a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90501
2605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.905012605
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3318764827
Short name T428
Test name
Test status
Simulation time 8410112442 ps
CPU time 11.12 seconds
Started May 19 02:02:42 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 205016 kb
Host smart-d53fdf0f-9546-4b08-a5f6-2e43b80ace58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33187
64827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3318764827
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4147605396
Short name T1188
Test name
Test status
Simulation time 8428347666 ps
CPU time 11.44 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204736 kb
Host smart-bade68e9-e7c7-412a-a26f-81aee680810d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41476
05396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4147605396
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1380275548
Short name T351
Test name
Test status
Simulation time 8382347256 ps
CPU time 11.07 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:33 PM PDT 24
Peak memory 204816 kb
Host smart-49ee1300-839e-4f61-b523-0bd4764ae4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13802
75548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1380275548
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.4040306410
Short name T734
Test name
Test status
Simulation time 8399115446 ps
CPU time 10.93 seconds
Started May 19 02:02:42 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 204824 kb
Host smart-6d0e9ad3-d8e7-4e0e-929e-585d1fb3f170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40403
06410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.4040306410
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.1028252588
Short name T340
Test name
Test status
Simulation time 8421343540 ps
CPU time 11.59 seconds
Started May 19 02:02:34 PM PDT 24
Finished May 19 02:02:47 PM PDT 24
Peak memory 204780 kb
Host smart-ee326418-6f46-4256-a3a1-0cb4928d7863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
52588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.1028252588
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1432452600
Short name T866
Test name
Test status
Simulation time 8375258749 ps
CPU time 11.83 seconds
Started May 19 02:02:47 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204800 kb
Host smart-29bc9d39-0a4a-48b1-bd42-d4f7589b8a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
52600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1432452600
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3182649007
Short name T727
Test name
Test status
Simulation time 8383289419 ps
CPU time 10.93 seconds
Started May 19 02:02:35 PM PDT 24
Finished May 19 02:02:48 PM PDT 24
Peak memory 204772 kb
Host smart-14387d0a-2860-43e7-be83-f3eb90b82d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826
49007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3182649007
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1549226381
Short name T1190
Test name
Test status
Simulation time 23710813218 ps
CPU time 45.08 seconds
Started May 19 02:02:27 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 204832 kb
Host smart-cd0671fa-53fd-42e1-b51a-10b7b52e2759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
26381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1549226381
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1250184163
Short name T1111
Test name
Test status
Simulation time 8405270807 ps
CPU time 13.38 seconds
Started May 19 02:02:36 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204860 kb
Host smart-3d2896f0-53a2-47c9-892b-9542c1cedb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12501
84163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1250184163
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2574269147
Short name T1096
Test name
Test status
Simulation time 8433515231 ps
CPU time 13.76 seconds
Started May 19 02:02:38 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204776 kb
Host smart-35ceca25-cd96-434e-9fbf-6552f139ec71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25742
69147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2574269147
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2643101569
Short name T1374
Test name
Test status
Simulation time 8379039570 ps
CPU time 11.14 seconds
Started May 19 02:02:39 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204824 kb
Host smart-67f876f6-0367-4979-bc65-7eda3d2b8a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26431
01569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2643101569
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2275845037
Short name T767
Test name
Test status
Simulation time 8381859985 ps
CPU time 12.09 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:45 PM PDT 24
Peak memory 204768 kb
Host smart-1747d042-875f-4983-a336-59147d544dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22758
45037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2275845037
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3024517938
Short name T1389
Test name
Test status
Simulation time 8401093322 ps
CPU time 11.25 seconds
Started May 19 02:02:36 PM PDT 24
Finished May 19 02:02:49 PM PDT 24
Peak memory 204720 kb
Host smart-cdce4d91-b30a-40b0-94a6-16125cb1518f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30245
17938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3024517938
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1156630957
Short name T528
Test name
Test status
Simulation time 8386328357 ps
CPU time 11.01 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204768 kb
Host smart-b045ae8d-4822-4285-ac85-3ed8c4e4b961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11566
30957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1156630957
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2458518582
Short name T1221
Test name
Test status
Simulation time 8445279781 ps
CPU time 12.71 seconds
Started May 19 02:02:20 PM PDT 24
Finished May 19 02:02:34 PM PDT 24
Peak memory 204800 kb
Host smart-44f9cae1-d98f-49b3-9fec-c8dfc9e3b108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24585
18582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2458518582
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1257824849
Short name T1163
Test name
Test status
Simulation time 8401549510 ps
CPU time 10.45 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204796 kb
Host smart-1aad986d-e5ba-497e-8a9c-1823d31c6eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12578
24849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1257824849
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.379579962
Short name T535
Test name
Test status
Simulation time 8410556956 ps
CPU time 13.38 seconds
Started May 19 02:02:30 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204884 kb
Host smart-fb663ad9-5b37-4665-87d4-e68e3d33b0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
9962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.379579962
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.2307370441
Short name T762
Test name
Test status
Simulation time 8490013593 ps
CPU time 11.01 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:59 PM PDT 24
Peak memory 204796 kb
Host smart-5e048488-dbd2-419f-8c2b-6b8d82d689b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2307370441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.2307370441
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2326993593
Short name T1409
Test name
Test status
Simulation time 8378328968 ps
CPU time 10.62 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:55 PM PDT 24
Peak memory 204812 kb
Host smart-d00cbf4c-4c7d-46a1-947f-897b44df0f29
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2326993593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2326993593
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.4076033648
Short name T1763
Test name
Test status
Simulation time 8459170939 ps
CPU time 11.04 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204848 kb
Host smart-46715eb2-ba5b-4b58-af77-475ac3116d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40760
33648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.4076033648
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.4141388097
Short name T1684
Test name
Test status
Simulation time 8382250304 ps
CPU time 11.23 seconds
Started May 19 02:02:33 PM PDT 24
Finished May 19 02:02:46 PM PDT 24
Peak memory 204700 kb
Host smart-92b8d8c7-9ad9-44e3-b268-017beddabaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41413
88097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.4141388097
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.23018290
Short name T206
Test name
Test status
Simulation time 9121634896 ps
CPU time 14.69 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:56 PM PDT 24
Peak memory 204848 kb
Host smart-9e4502df-23a4-4170-a87d-1525ef0f41a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23018
290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.23018290
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2157439235
Short name T232
Test name
Test status
Simulation time 8364207366 ps
CPU time 11.6 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204776 kb
Host smart-76abe6cd-7157-4b5b-ac0e-46e9ac52a2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21574
39235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2157439235
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4182037726
Short name T949
Test name
Test status
Simulation time 8381896325 ps
CPU time 13.48 seconds
Started May 19 02:02:24 PM PDT 24
Finished May 19 02:02:43 PM PDT 24
Peak memory 204860 kb
Host smart-05ad1f98-5a31-4efc-a39a-683d8e1a38e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41820
37726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4182037726
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3123870255
Short name T783
Test name
Test status
Simulation time 9084180494 ps
CPU time 12.5 seconds
Started May 19 02:02:34 PM PDT 24
Finished May 19 02:02:48 PM PDT 24
Peak memory 204864 kb
Host smart-7d5bf847-1e78-4af6-b1fe-0ea96e48e902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31238
70255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3123870255
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2368241338
Short name T44
Test name
Test status
Simulation time 8471477610 ps
CPU time 12.9 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204832 kb
Host smart-230b9c5f-02ab-4722-ba9d-a23b3abedbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23682
41338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2368241338
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.642411653
Short name T844
Test name
Test status
Simulation time 8391728680 ps
CPU time 11.85 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204800 kb
Host smart-abf44be7-ea04-49af-9c8c-5aff7841fdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64241
1653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.642411653
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.538304220
Short name T538
Test name
Test status
Simulation time 8386572031 ps
CPU time 12.09 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:59 PM PDT 24
Peak memory 204824 kb
Host smart-b15d285c-72a0-405f-87ed-3dea5141b1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53830
4220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.538304220
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.467275126
Short name T705
Test name
Test status
Simulation time 8452474411 ps
CPU time 11.87 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204860 kb
Host smart-3c2fd019-205a-4e8f-bbc3-ecd3102487fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46727
5126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.467275126
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.980383470
Short name T951
Test name
Test status
Simulation time 8406217297 ps
CPU time 11.12 seconds
Started May 19 02:02:32 PM PDT 24
Finished May 19 02:02:44 PM PDT 24
Peak memory 204828 kb
Host smart-15943ec1-b1ea-4373-936b-9cafba127143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98038
3470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.980383470
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2212676178
Short name T1489
Test name
Test status
Simulation time 11511389221 ps
CPU time 13.59 seconds
Started May 19 02:02:36 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204792 kb
Host smart-e4beb5a8-6776-4ad5-a218-055b6ed1b1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126
76178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2212676178
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1982227065
Short name T708
Test name
Test status
Simulation time 8420417785 ps
CPU time 11.18 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:52 PM PDT 24
Peak memory 204816 kb
Host smart-4ee5ad36-1249-4ff0-aa05-aff816a3a756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
27065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1982227065
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2954425980
Short name T1769
Test name
Test status
Simulation time 8380215618 ps
CPU time 12.88 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204776 kb
Host smart-8d794bc2-b827-427d-a79a-6360c3ee0fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29544
25980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2954425980
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2844053397
Short name T1062
Test name
Test status
Simulation time 8420621391 ps
CPU time 13.89 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204800 kb
Host smart-63b1ba58-23fa-43ca-9969-af27e4add25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
53397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2844053397
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3709055115
Short name T1515
Test name
Test status
Simulation time 8397713048 ps
CPU time 11.06 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204852 kb
Host smart-77330ef6-92a5-463c-ba18-82f4bc31bf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
55115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3709055115
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2514037082
Short name T918
Test name
Test status
Simulation time 8399149470 ps
CPU time 11.84 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 205032 kb
Host smart-6d58716a-9061-4b35-9e55-b266f6bc589f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25140
37082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2514037082
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3938049401
Short name T203
Test name
Test status
Simulation time 8418714044 ps
CPU time 11.23 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:50 PM PDT 24
Peak memory 204884 kb
Host smart-cfaf7ef6-31c8-4c55-be77-84cd0ea1cd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
49401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3938049401
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.3985417883
Short name T552
Test name
Test status
Simulation time 8424696934 ps
CPU time 12.49 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204808 kb
Host smart-e587e252-cbe5-45fe-bae8-34b83954c462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39854
17883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.3985417883
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.119351475
Short name T829
Test name
Test status
Simulation time 8366498985 ps
CPU time 11.27 seconds
Started May 19 02:02:35 PM PDT 24
Finished May 19 02:02:48 PM PDT 24
Peak memory 204772 kb
Host smart-d3f596e2-7d04-422a-820b-6114f8476d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11935
1475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.119351475
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2120451593
Short name T545
Test name
Test status
Simulation time 8363451435 ps
CPU time 11.77 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204840 kb
Host smart-6bcd873c-c44e-4432-9107-d95933247094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
51593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2120451593
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.4125813685
Short name T1439
Test name
Test status
Simulation time 8372803458 ps
CPU time 13.7 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:59 PM PDT 24
Peak memory 204796 kb
Host smart-7b76b217-17d3-4306-8e89-78e03a2b106a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41258
13685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.4125813685
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.4279662874
Short name T922
Test name
Test status
Simulation time 8486792224 ps
CPU time 11.48 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204892 kb
Host smart-dda59e36-d1f7-43db-b973-2477451be886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42796
62874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.4279662874
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3361677388
Short name T633
Test name
Test status
Simulation time 8442605397 ps
CPU time 11.28 seconds
Started May 19 02:02:41 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204824 kb
Host smart-e69b6ef2-d364-4df2-95f5-9f29ffc41fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33616
77388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3361677388
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1359563960
Short name T406
Test name
Test status
Simulation time 8370225094 ps
CPU time 12.56 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:53 PM PDT 24
Peak memory 204744 kb
Host smart-5cebbe2a-fb94-4a48-af33-9eb68fb5fd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
63960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1359563960
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1349923577
Short name T1385
Test name
Test status
Simulation time 8386835841 ps
CPU time 10.72 seconds
Started May 19 02:02:50 PM PDT 24
Finished May 19 02:03:02 PM PDT 24
Peak memory 204780 kb
Host smart-de291708-c9c0-4fe3-9251-c856d09e1888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
23577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1349923577
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1422359643
Short name T1719
Test name
Test status
Simulation time 8377870045 ps
CPU time 10.4 seconds
Started May 19 02:02:54 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204760 kb
Host smart-4e3c13a2-1b8b-46af-b585-5deda1583a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14223
59643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1422359643
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4136479132
Short name T1398
Test name
Test status
Simulation time 8419966244 ps
CPU time 11.11 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204712 kb
Host smart-f7304849-b561-4100-b074-354027b817c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41364
79132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4136479132
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3528478847
Short name T1158
Test name
Test status
Simulation time 8396948628 ps
CPU time 11.4 seconds
Started May 19 02:02:39 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204856 kb
Host smart-38457131-97c2-4ff9-9136-78864f2d151c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35284
78847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3528478847
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1172335412
Short name T1646
Test name
Test status
Simulation time 8405669314 ps
CPU time 12.53 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204744 kb
Host smart-337e8317-fdcc-4b51-a710-4926ba4338c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
35412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1172335412
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.3911956387
Short name T373
Test name
Test status
Simulation time 8468175107 ps
CPU time 11.47 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204844 kb
Host smart-c72b94a2-a2de-41e4-a056-189367a1b0c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3911956387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.3911956387
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3293900539
Short name T986
Test name
Test status
Simulation time 8377116258 ps
CPU time 11.63 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 204844 kb
Host smart-94b76521-c0b4-42d7-b187-b746f066d8e6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3293900539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3293900539
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.132951847
Short name T1352
Test name
Test status
Simulation time 8461869104 ps
CPU time 13.67 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 204832 kb
Host smart-8ee2a4e7-077c-480f-b5b3-ee987b428553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13295
1847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.132951847
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1345295981
Short name T747
Test name
Test status
Simulation time 8384810515 ps
CPU time 11.67 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:19 PM PDT 24
Peak memory 204840 kb
Host smart-fb03abc5-c7e8-4f57-9a3c-5aaea24b2e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
95981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1345295981
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1039394503
Short name T212
Test name
Test status
Simulation time 8434388831 ps
CPU time 12.29 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204824 kb
Host smart-295313ed-14bb-4b94-835a-d0c0b25ed859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393
94503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1039394503
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1863328018
Short name T1275
Test name
Test status
Simulation time 8495486248 ps
CPU time 13.45 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 204792 kb
Host smart-2de3c479-3de2-433f-94be-83debd0390ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18633
28018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1863328018
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1212996485
Short name T1000
Test name
Test status
Simulation time 8413700651 ps
CPU time 11.13 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204824 kb
Host smart-bec651ab-be69-450c-9ec6-584ae8495b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12129
96485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1212996485
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3527717731
Short name T67
Test name
Test status
Simulation time 8410490766 ps
CPU time 10.76 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:19 PM PDT 24
Peak memory 204780 kb
Host smart-df316a8b-7781-4c04-a473-b59813a392ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35277
17731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3527717731
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2640616003
Short name T1686
Test name
Test status
Simulation time 9196394154 ps
CPU time 13.33 seconds
Started May 19 02:01:03 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204848 kb
Host smart-737b8e51-077d-4b59-9e62-39c0b5f0cb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
16003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2640616003
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1586744066
Short name T1491
Test name
Test status
Simulation time 8379602359 ps
CPU time 10.98 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204992 kb
Host smart-9a18366a-53c9-4c27-b38a-a446fc4492f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
44066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1586744066
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1887794681
Short name T966
Test name
Test status
Simulation time 8381138868 ps
CPU time 11.97 seconds
Started May 19 02:01:03 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 204840 kb
Host smart-2522b623-a43e-492e-929f-2598b9819684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18877
94681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1887794681
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.449611146
Short name T1593
Test name
Test status
Simulation time 8376278945 ps
CPU time 12.55 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204804 kb
Host smart-1f7af79b-6301-48b2-baa0-9ee37341170e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44961
1146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.449611146
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2144817201
Short name T1744
Test name
Test status
Simulation time 8495845606 ps
CPU time 12.18 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204792 kb
Host smart-9eb974d9-3c9f-41c0-be08-8a94583e87f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21448
17201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2144817201
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1794777790
Short name T1545
Test name
Test status
Simulation time 8388961642 ps
CPU time 12.57 seconds
Started May 19 02:01:02 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 204772 kb
Host smart-07435ed9-c45d-4720-b039-26fe272acae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17947
77790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1794777790
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1572467655
Short name T707
Test name
Test status
Simulation time 11559945211 ps
CPU time 14.42 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:21 PM PDT 24
Peak memory 204780 kb
Host smart-4542b705-8a62-4571-97d2-71375e336a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15724
67655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1572467655
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3563657154
Short name T838
Test name
Test status
Simulation time 8427296878 ps
CPU time 11.58 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 204808 kb
Host smart-c0f31f1a-0ccd-448e-a23c-5d5faf8bc1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35636
57154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3563657154
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.715539864
Short name T1495
Test name
Test status
Simulation time 8371405952 ps
CPU time 10.76 seconds
Started May 19 02:01:03 PM PDT 24
Finished May 19 02:01:15 PM PDT 24
Peak memory 204848 kb
Host smart-38b9b92b-936e-4667-9c53-f6884e1b6688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71553
9864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.715539864
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1272965511
Short name T1429
Test name
Test status
Simulation time 8399959970 ps
CPU time 10.49 seconds
Started May 19 02:01:11 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204800 kb
Host smart-9a96d856-b540-4d72-b563-8a779ac88604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12729
65511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1272965511
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2146616813
Short name T471
Test name
Test status
Simulation time 8413513499 ps
CPU time 11.14 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 204752 kb
Host smart-8dbe179b-f22a-4816-854e-779b12e8fb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21466
16813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2146616813
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.108504659
Short name T703
Test name
Test status
Simulation time 8449111071 ps
CPU time 13.09 seconds
Started May 19 02:01:03 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204776 kb
Host smart-53ea0665-4bf1-4dee-bd72-175c336a4ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10850
4659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.108504659
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1908237284
Short name T1546
Test name
Test status
Simulation time 8438226726 ps
CPU time 11.83 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:21 PM PDT 24
Peak memory 204824 kb
Host smart-32afc103-63c0-438c-9155-86d3591e9ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19082
37284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1908237284
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3970633788
Short name T172
Test name
Test status
Simulation time 8389158996 ps
CPU time 11.74 seconds
Started May 19 02:01:11 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204836 kb
Host smart-d2c08b2d-70d6-45ca-8c45-cea9ab0ea017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39706
33788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3970633788
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.1127713911
Short name T1132
Test name
Test status
Simulation time 8408328597 ps
CPU time 11.21 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 204764 kb
Host smart-0e398eb8-b254-4b0a-bb6d-5519855ecca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
13911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.1127713911
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1836561911
Short name T55
Test name
Test status
Simulation time 8377092001 ps
CPU time 12.72 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 204812 kb
Host smart-93ede8e6-3879-48b9-b81f-8e51112c93b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18365
61911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1836561911
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2704784304
Short name T893
Test name
Test status
Simulation time 8385331727 ps
CPU time 11.99 seconds
Started May 19 02:01:10 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204800 kb
Host smart-83f98b59-1333-4426-bbc3-1d35d2434124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27047
84304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2704784304
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1769779120
Short name T1283
Test name
Test status
Simulation time 8409263512 ps
CPU time 11.44 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 204576 kb
Host smart-700ebd1a-9849-4e85-a859-556ba54ea7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17697
79120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1769779120
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3648974561
Short name T1142
Test name
Test status
Simulation time 8436616073 ps
CPU time 13.34 seconds
Started May 19 02:01:10 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 204844 kb
Host smart-3f54e84e-aecc-4e59-8ddb-b4cdb090b2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36489
74561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3648974561
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.412963664
Short name T1658
Test name
Test status
Simulation time 8408664978 ps
CPU time 13.74 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204544 kb
Host smart-3a90d80b-ba56-4d43-9396-6fc89b51d9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
3664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.412963664
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.4292582531
Short name T1575
Test name
Test status
Simulation time 8407705501 ps
CPU time 10.86 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:19 PM PDT 24
Peak memory 204764 kb
Host smart-0867797e-0ff1-43a8-bb54-19e153068457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925
82531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.4292582531
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1176388865
Short name T74
Test name
Test status
Simulation time 362776987 ps
CPU time 1.2 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:12 PM PDT 24
Peak memory 221588 kb
Host smart-5621e59c-c96e-4970-9b74-333fb4ea9d25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1176388865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1176388865
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3548634269
Short name T45
Test name
Test status
Simulation time 8407040500 ps
CPU time 10.86 seconds
Started May 19 02:01:11 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204824 kb
Host smart-af06f892-b1fb-4778-bb65-3b0f535004cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35486
34269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3548634269
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2212765752
Short name T100
Test name
Test status
Simulation time 8386609123 ps
CPU time 11.95 seconds
Started May 19 02:01:01 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 204848 kb
Host smart-fd1ab601-27b0-4527-ac1f-da82c3e50af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22127
65752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2212765752
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.776753830
Short name T973
Test name
Test status
Simulation time 8467940452 ps
CPU time 11.65 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:18 PM PDT 24
Peak memory 204724 kb
Host smart-6be96af0-b3cd-4b96-a894-57d32cb7685f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77675
3830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.776753830
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3933287812
Short name T555
Test name
Test status
Simulation time 8404242478 ps
CPU time 11.37 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 204872 kb
Host smart-38a3ece2-b860-4014-b652-2503426bcc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39332
87812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3933287812
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3925582490
Short name T1413
Test name
Test status
Simulation time 8408587981 ps
CPU time 10.39 seconds
Started May 19 02:01:04 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 204652 kb
Host smart-87877d39-eb62-467e-9cfc-61eb6adcb08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39255
82490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3925582490
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.3808123976
Short name T1632
Test name
Test status
Simulation time 8489086816 ps
CPU time 10.64 seconds
Started May 19 02:03:00 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204816 kb
Host smart-b1b652cb-6c1a-4399-800a-61c56250377c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3808123976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.3808123976
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.2631939227
Short name T300
Test name
Test status
Simulation time 8385485486 ps
CPU time 12.58 seconds
Started May 19 02:02:49 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204836 kb
Host smart-048f1702-1b30-48e2-8020-6073fda4e67e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2631939227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.2631939227
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.3878576425
Short name T811
Test name
Test status
Simulation time 8458346158 ps
CPU time 10.85 seconds
Started May 19 02:02:54 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204816 kb
Host smart-247d2c30-ef91-4029-834a-a76f7cc752a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38785
76425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.3878576425
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2679821485
Short name T709
Test name
Test status
Simulation time 8441809023 ps
CPU time 10.45 seconds
Started May 19 02:02:37 PM PDT 24
Finished May 19 02:02:49 PM PDT 24
Peak memory 204868 kb
Host smart-8b627e19-5722-499c-be3a-91d981e632d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798
21485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2679821485
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1126033328
Short name T192
Test name
Test status
Simulation time 9081912730 ps
CPU time 12.03 seconds
Started May 19 02:02:41 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 204836 kb
Host smart-5849613b-88bc-428e-8cdb-6332876f5a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11260
33328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1126033328
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2325560509
Short name T1347
Test name
Test status
Simulation time 8366246178 ps
CPU time 11.16 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204748 kb
Host smart-330af6fa-6b9e-4dd4-bb96-f153c8496bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23255
60509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2325560509
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.4111123246
Short name T1740
Test name
Test status
Simulation time 8380357653 ps
CPU time 11.14 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:56 PM PDT 24
Peak memory 204800 kb
Host smart-3bab1148-2721-4794-8918-dd3aaa825a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41111
23246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4111123246
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2425551102
Short name T346
Test name
Test status
Simulation time 9253391856 ps
CPU time 12.55 seconds
Started May 19 02:02:51 PM PDT 24
Finished May 19 02:03:05 PM PDT 24
Peak memory 204820 kb
Host smart-2c93b560-cfa9-4140-94f3-98d297cceb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24255
51102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2425551102
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1290964197
Short name T1179
Test name
Test status
Simulation time 8513968144 ps
CPU time 12.03 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204856 kb
Host smart-263edea7-9f88-4446-8699-283c77150122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12909
64197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1290964197
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.4243864059
Short name T1294
Test name
Test status
Simulation time 8468592005 ps
CPU time 11 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204732 kb
Host smart-c3fd04b0-d40e-4e61-b8a0-0fdacc9dc7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
64059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.4243864059
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.902857677
Short name T1282
Test name
Test status
Simulation time 8376887838 ps
CPU time 13.28 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204820 kb
Host smart-6f82431c-83b5-47f7-a22a-4d3b4304b5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90285
7677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.902857677
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3863975420
Short name T1713
Test name
Test status
Simulation time 8430861284 ps
CPU time 11.96 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204884 kb
Host smart-75773331-0e88-4d00-9a5e-4242113c701d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38639
75420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3863975420
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.4055573219
Short name T1280
Test name
Test status
Simulation time 8473948467 ps
CPU time 11.1 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204796 kb
Host smart-f91a4642-2ed9-4b54-881e-da7fd4db955a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555
73219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.4055573219
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.459566322
Short name T1482
Test name
Test status
Simulation time 11558796421 ps
CPU time 14.71 seconds
Started May 19 02:02:42 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204792 kb
Host smart-82a7d8ca-88c3-4774-9037-ca80c0f6537a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45956
6322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.459566322
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.495575768
Short name T788
Test name
Test status
Simulation time 8432417645 ps
CPU time 11.83 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204828 kb
Host smart-2d4ee3d9-9758-4670-a92c-da08dc0289c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49557
5768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.495575768
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.558218700
Short name T987
Test name
Test status
Simulation time 8377043135 ps
CPU time 10.89 seconds
Started May 19 02:02:50 PM PDT 24
Finished May 19 02:03:02 PM PDT 24
Peak memory 204812 kb
Host smart-60bafcc2-a77d-4571-89f4-80a61ff3917b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55821
8700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.558218700
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.722905543
Short name T965
Test name
Test status
Simulation time 8429430674 ps
CPU time 10.77 seconds
Started May 19 02:02:51 PM PDT 24
Finished May 19 02:03:04 PM PDT 24
Peak memory 204784 kb
Host smart-dd1307e5-d53d-4735-bbc9-6e03b485893e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72290
5543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.722905543
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3206692462
Short name T488
Test name
Test status
Simulation time 8438553474 ps
CPU time 12.94 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204800 kb
Host smart-a3776e12-fbaa-4843-b8f7-349687f6bc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
92462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3206692462
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1883523396
Short name T302
Test name
Test status
Simulation time 8402077554 ps
CPU time 10.98 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204748 kb
Host smart-a967f13d-3f43-4ffa-a585-206118d1ee8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
23396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1883523396
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1049462830
Short name T441
Test name
Test status
Simulation time 8367424042 ps
CPU time 10.78 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204800 kb
Host smart-d85c6316-c90c-4a56-98f6-ee45c53018bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494
62830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1049462830
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1237970680
Short name T871
Test name
Test status
Simulation time 8408430340 ps
CPU time 10.64 seconds
Started May 19 02:02:51 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204764 kb
Host smart-43a361e8-a3fc-4309-8fd9-c7b002d4448c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12379
70680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1237970680
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.3665388271
Short name T593
Test name
Test status
Simulation time 8401916897 ps
CPU time 11.21 seconds
Started May 19 02:02:44 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204780 kb
Host smart-945cf099-cee7-4d31-828b-0a2f2c27dffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36653
88271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.3665388271
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3756995687
Short name T1231
Test name
Test status
Simulation time 8428125310 ps
CPU time 12.06 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204776 kb
Host smart-b9cd2354-41ab-42d5-8fc9-fc8490b7363e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37569
95687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3756995687
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2022564182
Short name T1631
Test name
Test status
Simulation time 8364453515 ps
CPU time 11.15 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204764 kb
Host smart-def38416-af40-4bf4-a19b-852578ffd976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20225
64182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2022564182
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2784776015
Short name T716
Test name
Test status
Simulation time 25242655791 ps
CPU time 49.1 seconds
Started May 19 02:02:38 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204828 kb
Host smart-11d89f8a-86f9-4231-81db-2c3f8bdc5975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27847
76015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2784776015
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2191945972
Short name T355
Test name
Test status
Simulation time 8437707934 ps
CPU time 13.47 seconds
Started May 19 02:02:47 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204848 kb
Host smart-30e5a79a-1a03-4519-936f-7a303facb08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21919
45972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2191945972
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3948898628
Short name T1050
Test name
Test status
Simulation time 8432490388 ps
CPU time 11.73 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:52 PM PDT 24
Peak memory 204868 kb
Host smart-ae869e13-9320-423f-9aca-33397ef024ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39488
98628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3948898628
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3147705355
Short name T795
Test name
Test status
Simulation time 8431527515 ps
CPU time 10.77 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204776 kb
Host smart-0b6f35f7-148a-4dbe-a78b-69fda34ef007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
05355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3147705355
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.996473297
Short name T1772
Test name
Test status
Simulation time 8427501470 ps
CPU time 11.71 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204720 kb
Host smart-a55ff1b5-3041-4c74-bad9-f4001e3e3344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99647
3297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.996473297
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.257596756
Short name T112
Test name
Test status
Simulation time 8385006294 ps
CPU time 11.8 seconds
Started May 19 02:02:38 PM PDT 24
Finished May 19 02:02:51 PM PDT 24
Peak memory 204764 kb
Host smart-87a1687c-28c3-4da2-83e5-a1ea67551300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
6756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.257596756
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1221677477
Short name T547
Test name
Test status
Simulation time 8373655703 ps
CPU time 11.69 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204820 kb
Host smart-0e2c297a-c3c0-4fc0-94ce-8251d10e3ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12216
77477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1221677477
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2450453924
Short name T178
Test name
Test status
Simulation time 8454661019 ps
CPU time 11.61 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 205016 kb
Host smart-0d64dadb-f83b-4c73-acbe-3f055ff5b72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504
53924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2450453924
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.90750714
Short name T1460
Test name
Test status
Simulation time 8399755558 ps
CPU time 11.67 seconds
Started May 19 02:02:40 PM PDT 24
Finished May 19 02:02:54 PM PDT 24
Peak memory 204856 kb
Host smart-1fb2170a-fe4c-4bec-8c40-82361e270554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90750
714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.90750714
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3767335959
Short name T1768
Test name
Test status
Simulation time 8379940597 ps
CPU time 12.01 seconds
Started May 19 02:02:43 PM PDT 24
Finished May 19 02:02:57 PM PDT 24
Peak memory 204812 kb
Host smart-1d71d797-fcdc-4d21-8994-1c3e4b8d4a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
35959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3767335959
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.1112207664
Short name T1662
Test name
Test status
Simulation time 8462331321 ps
CPU time 11.49 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204744 kb
Host smart-72bcd5b6-f9d8-4cce-aeae-7743d384468f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1112207664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.1112207664
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2027191831
Short name T958
Test name
Test status
Simulation time 8378248979 ps
CPU time 11.59 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204760 kb
Host smart-a7b4898a-a0ec-4993-a167-f887624cbf7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2027191831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2027191831
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3631576753
Short name T733
Test name
Test status
Simulation time 8415053405 ps
CPU time 10.72 seconds
Started May 19 02:02:47 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204804 kb
Host smart-eed61a73-d859-4eac-9ccc-59910d2635e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315
76753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3631576753
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2779230011
Short name T1277
Test name
Test status
Simulation time 8381227319 ps
CPU time 11.72 seconds
Started May 19 02:02:49 PM PDT 24
Finished May 19 02:03:02 PM PDT 24
Peak memory 204644 kb
Host smart-b6c13f75-2928-4d7d-9a0b-1edf1358d69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27792
30011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2779230011
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3713431552
Short name T1271
Test name
Test status
Simulation time 8375767037 ps
CPU time 12.1 seconds
Started May 19 02:02:54 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204748 kb
Host smart-286879e2-962a-430e-9868-7f2f3504d299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37134
31552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3713431552
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3886375770
Short name T1771
Test name
Test status
Simulation time 8891082043 ps
CPU time 11.99 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204868 kb
Host smart-e818187d-d746-4ebd-bf49-0da33098b8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
75770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3886375770
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.382315273
Short name T1340
Test name
Test status
Simulation time 8367460329 ps
CPU time 11.73 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204840 kb
Host smart-5a8c4d92-7d5d-468f-9c19-c0608ff8f7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38231
5273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.382315273
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.4126369275
Short name T1031
Test name
Test status
Simulation time 8397802489 ps
CPU time 11.64 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 205072 kb
Host smart-4696480a-2af3-4876-82cd-4263de7df10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
69275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.4126369275
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3412643168
Short name T1434
Test name
Test status
Simulation time 8961020962 ps
CPU time 12.2 seconds
Started May 19 02:02:49 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204796 kb
Host smart-3178015a-11c2-4cc4-83c7-934a5ad2994a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
43168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3412643168
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2479547745
Short name T530
Test name
Test status
Simulation time 8509066853 ps
CPU time 13.02 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204772 kb
Host smart-dc5ae6ec-2a67-4a84-b1e1-c534bf5b510d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
47745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2479547745
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2683214774
Short name T356
Test name
Test status
Simulation time 8460623540 ps
CPU time 11.26 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204872 kb
Host smart-b9be4b8c-3cf4-4320-9ba9-505f2a2db020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
14774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2683214774
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2998550603
Short name T93
Test name
Test status
Simulation time 8373543742 ps
CPU time 11.05 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 204820 kb
Host smart-e2757f8f-0435-424b-8a84-bb1ef6fb78fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
50603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2998550603
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1862236492
Short name T1536
Test name
Test status
Simulation time 8475628935 ps
CPU time 12.7 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204788 kb
Host smart-69520476-0328-4de5-bf87-164241eccd5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18622
36492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1862236492
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3142261103
Short name T839
Test name
Test status
Simulation time 8415828549 ps
CPU time 11.78 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 204860 kb
Host smart-ab55ad08-c2a2-4ca2-9feb-ef0c845e72cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31422
61103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3142261103
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3618653498
Short name T1417
Test name
Test status
Simulation time 11519238706 ps
CPU time 13.48 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204780 kb
Host smart-31f51d3e-b074-4934-ae6b-925b9edf30b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
53498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3618653498
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2244516346
Short name T1645
Test name
Test status
Simulation time 8420485501 ps
CPU time 11.09 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204728 kb
Host smart-e0ca6e00-6dd2-473d-8244-8ebb0ba539a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445
16346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2244516346
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3890261088
Short name T684
Test name
Test status
Simulation time 8378399692 ps
CPU time 10.78 seconds
Started May 19 02:02:47 PM PDT 24
Finished May 19 02:02:59 PM PDT 24
Peak memory 204788 kb
Host smart-18f575b4-8f2f-421e-855e-8edaf62ae58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
61088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3890261088
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.4048524029
Short name T140
Test name
Test status
Simulation time 8439222746 ps
CPU time 11.29 seconds
Started May 19 02:03:00 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204848 kb
Host smart-35e001f1-edce-4669-b3bc-3b08225d82be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
24029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.4048524029
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1582714357
Short name T576
Test name
Test status
Simulation time 8418637682 ps
CPU time 12.32 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204856 kb
Host smart-453ebc52-c058-449e-96ba-b1305203a184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15827
14357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1582714357
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1518150109
Short name T1327
Test name
Test status
Simulation time 8380352954 ps
CPU time 11.06 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 204872 kb
Host smart-321a7623-fd96-49f9-8a19-87bb01b77c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15181
50109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1518150109
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1185483314
Short name T1005
Test name
Test status
Simulation time 8382253880 ps
CPU time 10.41 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204800 kb
Host smart-84f8e001-d91d-4743-b69e-29eb43647716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11854
83314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1185483314
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3278640372
Short name T1559
Test name
Test status
Simulation time 8471538346 ps
CPU time 11.66 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204788 kb
Host smart-b4218205-51c7-420e-8ca9-0e61d80b1ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32786
40372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3278640372
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.2606019558
Short name T577
Test name
Test status
Simulation time 8421106299 ps
CPU time 11.24 seconds
Started May 19 02:02:50 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204796 kb
Host smart-2041d75a-b398-4c85-9a20-6112fb84b238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26060
19558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.2606019558
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1654840240
Short name T985
Test name
Test status
Simulation time 8379752647 ps
CPU time 12.43 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204760 kb
Host smart-d1cd2aa6-f08d-4a08-8ded-62bfb5e86885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16548
40240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1654840240
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.429151528
Short name T1770
Test name
Test status
Simulation time 8394937882 ps
CPU time 10.56 seconds
Started May 19 02:02:50 PM PDT 24
Finished May 19 02:03:02 PM PDT 24
Peak memory 204800 kb
Host smart-be9dc6f0-c2b0-4d57-9912-14ce1c055bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42915
1528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.429151528
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2640168019
Short name T1558
Test name
Test status
Simulation time 19233078431 ps
CPU time 35.37 seconds
Started May 19 02:02:49 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204804 kb
Host smart-c712f025-e198-4da5-88d2-0497e8f780fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401
68019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2640168019
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1832901385
Short name T1362
Test name
Test status
Simulation time 8382443942 ps
CPU time 13.43 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204868 kb
Host smart-0dfb2ce5-bb14-4204-86fb-3f9412c62956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18329
01385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1832901385
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3721536250
Short name T1477
Test name
Test status
Simulation time 8466652350 ps
CPU time 12.1 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204884 kb
Host smart-3c770fb3-3e25-4eda-aedc-27e16ae09378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215
36250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3721536250
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.284869582
Short name T1039
Test name
Test status
Simulation time 8382002684 ps
CPU time 10.94 seconds
Started May 19 02:02:45 PM PDT 24
Finished May 19 02:02:58 PM PDT 24
Peak memory 204816 kb
Host smart-9ea749a4-5e0e-4c79-82dc-6dc52326de34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.284869582
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2390994971
Short name T39
Test name
Test status
Simulation time 8365280808 ps
CPU time 11.48 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204852 kb
Host smart-95258c6f-c831-4adf-a30e-0bcab8559d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
94971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2390994971
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2687466551
Short name T1583
Test name
Test status
Simulation time 8375252152 ps
CPU time 11.51 seconds
Started May 19 02:02:51 PM PDT 24
Finished May 19 02:03:04 PM PDT 24
Peak memory 204708 kb
Host smart-b3fc9f71-d527-47fb-9bb9-a3fd69d618c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26874
66551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2687466551
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1064649293
Short name T526
Test name
Test status
Simulation time 8400699360 ps
CPU time 12.64 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204836 kb
Host smart-cd0978e2-928f-447f-be46-52683354dfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10646
49293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1064649293
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1020802003
Short name T167
Test name
Test status
Simulation time 8488764962 ps
CPU time 11.71 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 204900 kb
Host smart-9bbbb178-8dc3-4de9-8a1d-eacca07ddb18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10208
02003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1020802003
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2904327921
Short name T1437
Test name
Test status
Simulation time 8406231538 ps
CPU time 10.9 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204804 kb
Host smart-43414892-6c77-4305-ae38-a5fac8022db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
27921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2904327921
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1188283444
Short name T332
Test name
Test status
Simulation time 8409824217 ps
CPU time 11.89 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:02 PM PDT 24
Peak memory 204752 kb
Host smart-b0c990ac-02a5-4d96-9179-3cd9188439d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11882
83444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1188283444
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.3672634492
Short name T1638
Test name
Test status
Simulation time 8469971893 ps
CPU time 11.16 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204888 kb
Host smart-465a26c2-6849-4ced-ba76-fbe36209ea65
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3672634492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.3672634492
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.4111888727
Short name T964
Test name
Test status
Simulation time 8377948873 ps
CPU time 10.96 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204800 kb
Host smart-bb4ffa53-6d40-4fe7-9103-72821978b5ad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4111888727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.4111888727
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.4014834194
Short name T1186
Test name
Test status
Simulation time 8458269935 ps
CPU time 11.37 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204800 kb
Host smart-0dcc9279-cda8-44a2-80b0-41614ddbed2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40148
34194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.4014834194
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.235869869
Short name T618
Test name
Test status
Simulation time 8376321572 ps
CPU time 10.63 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204832 kb
Host smart-736556c3-4e74-4fdc-9ea9-447e92ab371f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23586
9869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.235869869
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3591148472
Short name T1622
Test name
Test status
Simulation time 8522547836 ps
CPU time 10.83 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204844 kb
Host smart-c317567b-3928-4ac6-8901-c7a07e26a425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35911
48472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3591148472
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1935070269
Short name T8
Test name
Test status
Simulation time 8374207691 ps
CPU time 11.43 seconds
Started May 19 02:02:50 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204740 kb
Host smart-fc6f8ea7-ea1c-4d29-9555-ae38f7692a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19350
70269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1935070269
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.133749950
Short name T456
Test name
Test status
Simulation time 8380841669 ps
CPU time 12.02 seconds
Started May 19 02:02:49 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 205000 kb
Host smart-e18dbea1-4b8f-43ee-b3c7-27c75a3a7e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13374
9950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.133749950
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2407358886
Short name T438
Test name
Test status
Simulation time 9143751365 ps
CPU time 12.23 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204844 kb
Host smart-9aa73fe0-a5d6-48ec-8e0e-739e4b34c1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
58886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2407358886
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3993368316
Short name T754
Test name
Test status
Simulation time 8529600541 ps
CPU time 12.04 seconds
Started May 19 02:03:23 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 205076 kb
Host smart-ffd57600-7108-4a93-b02d-580aed1d615a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39933
68316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3993368316
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1159371564
Short name T1660
Test name
Test status
Simulation time 8401473645 ps
CPU time 11.79 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204800 kb
Host smart-a40fc895-6653-4813-acce-bebe7726a21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11593
71564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1159371564
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3230393740
Short name T1353
Test name
Test status
Simulation time 8364870710 ps
CPU time 13.72 seconds
Started May 19 02:02:49 PM PDT 24
Finished May 19 02:03:05 PM PDT 24
Peak memory 204840 kb
Host smart-c8eedfd6-5407-49a2-9246-1db83a506100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32303
93740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3230393740
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3337910687
Short name T30
Test name
Test status
Simulation time 8378713220 ps
CPU time 11.53 seconds
Started May 19 02:02:46 PM PDT 24
Finished May 19 02:02:59 PM PDT 24
Peak memory 204776 kb
Host smart-0967d851-d875-4904-b127-3e40bf08cd1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
10687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3337910687
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3418263073
Short name T1634
Test name
Test status
Simulation time 8435743808 ps
CPU time 14.55 seconds
Started May 19 02:02:48 PM PDT 24
Finished May 19 02:03:05 PM PDT 24
Peak memory 204800 kb
Host smart-e55815f5-acca-4485-b86c-d4783aee4ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
63073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3418263073
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.244458210
Short name T822
Test name
Test status
Simulation time 11516716837 ps
CPU time 13.95 seconds
Started May 19 02:02:54 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204884 kb
Host smart-f1e9b5d6-6435-4b08-a78f-1fc14a91b943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24445
8210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.244458210
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.444410507
Short name T1526
Test name
Test status
Simulation time 8421042862 ps
CPU time 11.17 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204704 kb
Host smart-caa3efd7-dfe7-4905-991a-cb81e75c9733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44441
0507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.444410507
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.646828003
Short name T1242
Test name
Test status
Simulation time 8373339459 ps
CPU time 10.53 seconds
Started May 19 02:02:51 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 204680 kb
Host smart-614ba886-962d-46a8-81cd-74d7f2ee17a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64682
8003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.646828003
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.807054354
Short name T132
Test name
Test status
Simulation time 8466259219 ps
CPU time 12.66 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204824 kb
Host smart-e2a0f23b-0056-4e46-b6c5-3cf86d5ef1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80705
4354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.807054354
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2874536404
Short name T479
Test name
Test status
Simulation time 8410823753 ps
CPU time 11.78 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204848 kb
Host smart-87f89889-f5c7-4e49-853c-cff87d1deb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
36404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2874536404
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1973872402
Short name T444
Test name
Test status
Simulation time 8416307360 ps
CPU time 10.89 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204852 kb
Host smart-336dbeae-fec4-4f8e-9dcc-99952a883d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19738
72402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1973872402
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2484890420
Short name T991
Test name
Test status
Simulation time 8417975847 ps
CPU time 11.01 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204816 kb
Host smart-60936a5c-7cac-4ecb-8e5a-c86c6d900ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
90420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2484890420
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2788088205
Short name T1524
Test name
Test status
Simulation time 8403091972 ps
CPU time 11.56 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204800 kb
Host smart-0a75aca1-ae6e-4758-bd34-081fc88d8c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27880
88205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2788088205
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.2661801661
Short name T978
Test name
Test status
Simulation time 8427834136 ps
CPU time 11.95 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204740 kb
Host smart-bf502cbf-0cde-4597-b912-1d2b0bc35cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26618
01661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.2661801661
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2674452307
Short name T475
Test name
Test status
Simulation time 8370033012 ps
CPU time 11.45 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204796 kb
Host smart-058a93ee-718a-44cd-9d46-44d607d8721a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
52307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2674452307
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.4112324380
Short name T25
Test name
Test status
Simulation time 8362688988 ps
CPU time 11.1 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 204732 kb
Host smart-1a1ed6dc-0275-4d9a-b1f0-29f5b2fa9d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41123
24380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.4112324380
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.803923473
Short name T1547
Test name
Test status
Simulation time 8392276828 ps
CPU time 10.67 seconds
Started May 19 02:03:12 PM PDT 24
Finished May 19 02:03:24 PM PDT 24
Peak memory 205020 kb
Host smart-ee3575e7-986e-46dd-b3e3-71e5937b50d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80392
3473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.803923473
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1032103365
Short name T1478
Test name
Test status
Simulation time 8399408930 ps
CPU time 11.97 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204800 kb
Host smart-f33f3668-83cf-4ae4-9914-3e8b61f5d374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321
03365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1032103365
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3780543915
Short name T1112
Test name
Test status
Simulation time 8384589494 ps
CPU time 11.7 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204784 kb
Host smart-30451277-eea3-4fd7-a56e-293682005fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37805
43915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3780543915
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2943835431
Short name T480
Test name
Test status
Simulation time 8373060572 ps
CPU time 10.89 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 205068 kb
Host smart-6c348819-9ae2-44e7-b0b7-964282c14120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
35431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2943835431
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2758908600
Short name T1376
Test name
Test status
Simulation time 8381302157 ps
CPU time 11.41 seconds
Started May 19 02:03:24 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204796 kb
Host smart-50b47f12-e667-4b7b-a7d8-270eacbe3b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27589
08600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2758908600
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2922436995
Short name T416
Test name
Test status
Simulation time 8437734648 ps
CPU time 11.16 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204812 kb
Host smart-d67903a3-b033-471d-abc1-7e7b1b0619fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29224
36995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2922436995
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1351476074
Short name T181
Test name
Test status
Simulation time 8467864466 ps
CPU time 13.53 seconds
Started May 19 02:02:50 PM PDT 24
Finished May 19 02:03:05 PM PDT 24
Peak memory 204888 kb
Host smart-fd350234-1c46-4fd4-87f5-509d693464f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13514
76074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1351476074
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3634409632
Short name T320
Test name
Test status
Simulation time 8404358850 ps
CPU time 10.32 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204776 kb
Host smart-92692db9-e5ed-4d7c-bff5-25a8bb13eb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344
09632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3634409632
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3650128897
Short name T1105
Test name
Test status
Simulation time 8413585147 ps
CPU time 11.64 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204764 kb
Host smart-d9459594-1d13-42aa-a877-fa830b0736ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
28897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3650128897
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1958857259
Short name T1617
Test name
Test status
Simulation time 8485341812 ps
CPU time 13.65 seconds
Started May 19 02:03:29 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204836 kb
Host smart-c693de33-28c2-40e5-86db-3128a42354b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1958857259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1958857259
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.2446273860
Short name T510
Test name
Test status
Simulation time 8385024599 ps
CPU time 10.41 seconds
Started May 19 02:03:02 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204828 kb
Host smart-922a042b-74ee-4a95-bfbd-94e58bd9b8f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2446273860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.2446273860
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.1799888883
Short name T644
Test name
Test status
Simulation time 8434200712 ps
CPU time 10.95 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204792 kb
Host smart-2289964d-c003-484d-9903-e87d1e0137a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17998
88883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.1799888883
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2409355299
Short name T22
Test name
Test status
Simulation time 8396970431 ps
CPU time 10.97 seconds
Started May 19 02:03:10 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204696 kb
Host smart-6cd60021-8a18-4f5d-a796-f453b2f025f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24093
55299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2409355299
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1448614047
Short name T1264
Test name
Test status
Simulation time 8981080876 ps
CPU time 14.41 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204820 kb
Host smart-1584a979-285d-429c-b3dc-60c90b46053a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486
14047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1448614047
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2759765431
Short name T311
Test name
Test status
Simulation time 8368958887 ps
CPU time 13.48 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204852 kb
Host smart-49cc9945-721a-4cba-9906-666aca5fb5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
65431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2759765431
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2419251688
Short name T1355
Test name
Test status
Simulation time 8395145084 ps
CPU time 13.9 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204860 kb
Host smart-124999fc-3632-4c2b-9b09-0393e64a9d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24192
51688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2419251688
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.891771482
Short name T1532
Test name
Test status
Simulation time 9139596060 ps
CPU time 12.49 seconds
Started May 19 02:03:00 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 204788 kb
Host smart-011ddc9d-6add-4dc4-b5ee-a987eda008df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89177
1482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.891771482
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3276730957
Short name T463
Test name
Test status
Simulation time 8576569001 ps
CPU time 12.63 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 204828 kb
Host smart-ea5af044-4e3a-45a3-8c56-67eec6f70401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32767
30957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3276730957
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.909383088
Short name T1627
Test name
Test status
Simulation time 8428086193 ps
CPU time 12.41 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204700 kb
Host smart-27378f66-e554-4f1e-b2fe-5a61680e535d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90938
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.909383088
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3559463318
Short name T1370
Test name
Test status
Simulation time 8364991252 ps
CPU time 11.86 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 204840 kb
Host smart-7950432f-c41c-44d9-baa6-5f582c1ab36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
63318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3559463318
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2541342654
Short name T1494
Test name
Test status
Simulation time 8397618612 ps
CPU time 11.98 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204788 kb
Host smart-041228bf-39b3-4d10-a394-f927e77467e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25413
42654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2541342654
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.691090792
Short name T567
Test name
Test status
Simulation time 8422885984 ps
CPU time 12.81 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:20 PM PDT 24
Peak memory 204884 kb
Host smart-887af335-dedc-4d16-a6c0-2060006182b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69109
0792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.691090792
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2324677313
Short name T439
Test name
Test status
Simulation time 11581532706 ps
CPU time 14.55 seconds
Started May 19 02:03:02 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204812 kb
Host smart-09a36150-2936-4f87-809b-2b4b3524cfa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23246
77313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2324677313
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3739657237
Short name T303
Test name
Test status
Simulation time 8419068975 ps
CPU time 10.86 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204784 kb
Host smart-63b6e517-f4cb-44e9-93d5-693426c03b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37396
57237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3739657237
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1201088827
Short name T671
Test name
Test status
Simulation time 8383661400 ps
CPU time 10.76 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204804 kb
Host smart-a76a3a7a-037c-49b9-8fb6-eb08d376d59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12010
88827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1201088827
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.889982508
Short name T152
Test name
Test status
Simulation time 8431929338 ps
CPU time 11.41 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:07 PM PDT 24
Peak memory 204752 kb
Host smart-9c247a17-6969-4663-b443-c5bbc40660aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88998
2508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.889982508
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2051343153
Short name T466
Test name
Test status
Simulation time 8419815794 ps
CPU time 11.03 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 204852 kb
Host smart-11b830da-4139-4424-b148-544aef36841c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20513
43153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2051343153
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3995385097
Short name T704
Test name
Test status
Simulation time 8385756816 ps
CPU time 11.02 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204784 kb
Host smart-aec06f73-34a6-4e46-8219-94742ab75dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39953
85097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3995385097
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.928109685
Short name T984
Test name
Test status
Simulation time 8422068926 ps
CPU time 10.93 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204840 kb
Host smart-8a342ef0-2be2-49cf-9e5b-8b882dddc749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92810
9685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.928109685
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.1487035685
Short name T500
Test name
Test status
Simulation time 8389285842 ps
CPU time 11.62 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204792 kb
Host smart-95e16908-fc58-4d3b-aee8-8f1d3703d2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14870
35685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.1487035685
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.446252210
Short name T1579
Test name
Test status
Simulation time 8383455556 ps
CPU time 12.23 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204736 kb
Host smart-a1fb9f66-8a13-4a4b-9587-6b1e233f73e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44625
2210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.446252210
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2789986915
Short name T571
Test name
Test status
Simulation time 8379086796 ps
CPU time 12.19 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 205044 kb
Host smart-d5e9d4de-7b01-4afc-bd92-cd2a7ad954a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27899
86915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2789986915
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2610295401
Short name T237
Test name
Test status
Simulation time 25423422594 ps
CPU time 49.01 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:51 PM PDT 24
Peak memory 205028 kb
Host smart-89e5e741-e79a-4638-ae6e-5a8920352c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
95401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2610295401
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2634554667
Short name T549
Test name
Test status
Simulation time 8368338213 ps
CPU time 13.28 seconds
Started May 19 02:03:29 PM PDT 24
Finished May 19 02:03:43 PM PDT 24
Peak memory 204764 kb
Host smart-579a0b0d-3148-4099-b15e-0f31f33ce062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26345
54667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2634554667
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.718539355
Short name T856
Test name
Test status
Simulation time 8466808370 ps
CPU time 10.75 seconds
Started May 19 02:02:57 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 205076 kb
Host smart-693c4cb8-cefe-461b-96aa-a1755b98f3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71853
9355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.718539355
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.1984641160
Short name T1305
Test name
Test status
Simulation time 8397455212 ps
CPU time 10.66 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204760 kb
Host smart-4747e75d-8e42-4991-8e9e-3e9a486a3663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846
41160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.1984641160
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.68306027
Short name T1630
Test name
Test status
Simulation time 8365660881 ps
CPU time 11.32 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204824 kb
Host smart-78a48bde-9ef7-4cf2-9c1e-9bf70c15d125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68306
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.68306027
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.649224553
Short name T173
Test name
Test status
Simulation time 8383483261 ps
CPU time 13.14 seconds
Started May 19 02:03:10 PM PDT 24
Finished May 19 02:03:24 PM PDT 24
Peak memory 204648 kb
Host smart-656dd813-af73-49e4-b53f-b7bab802dd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64922
4553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.649224553
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2429237555
Short name T808
Test name
Test status
Simulation time 8374970608 ps
CPU time 12.74 seconds
Started May 19 02:02:54 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204760 kb
Host smart-c9cff51e-5538-43c7-a2c3-9dc16b2fa3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24292
37555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2429237555
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1661418843
Short name T1225
Test name
Test status
Simulation time 8430591786 ps
CPU time 13.21 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 204836 kb
Host smart-72be3212-3ecf-4824-a5e3-0ff853e9330b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16614
18843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1661418843
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1209412466
Short name T1611
Test name
Test status
Simulation time 8422782979 ps
CPU time 10.49 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204840 kb
Host smart-f022de5b-b3a7-4f3f-a2bc-1a38bc14c406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12094
12466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1209412466
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2725808630
Short name T1688
Test name
Test status
Simulation time 8404690303 ps
CPU time 11.83 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204748 kb
Host smart-468b8c5e-357f-4351-8599-8ac9808018e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27258
08630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2725808630
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1178949182
Short name T1129
Test name
Test status
Simulation time 8468477308 ps
CPU time 11.48 seconds
Started May 19 02:03:27 PM PDT 24
Finished May 19 02:03:39 PM PDT 24
Peak memory 204744 kb
Host smart-ee0f32fc-9fcc-4dba-b3e3-da0b22e32447
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1178949182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1178949182
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.359260007
Short name T352
Test name
Test status
Simulation time 8428334933 ps
CPU time 13.25 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204796 kb
Host smart-735eee69-f184-4b5e-b619-73d39db5af28
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=359260007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.359260007
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.26001776
Short name T996
Test name
Test status
Simulation time 8449800506 ps
CPU time 10.59 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:20 PM PDT 24
Peak memory 204780 kb
Host smart-2968c0d3-26c5-4c99-9e03-457e6c4bef60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.26001776
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2465865382
Short name T924
Test name
Test status
Simulation time 8402741473 ps
CPU time 12.57 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204848 kb
Host smart-1b2d2ea6-f217-4489-9e81-5792241c5353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
65382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2465865382
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2309296968
Short name T977
Test name
Test status
Simulation time 9333186771 ps
CPU time 13.13 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204832 kb
Host smart-42cb0312-61e1-4175-9088-b63ff1843142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23092
96968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2309296968
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.891951238
Short name T1173
Test name
Test status
Simulation time 8384646649 ps
CPU time 10.77 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204788 kb
Host smart-5cd829dd-4b3a-45b8-93f9-73eecae9cfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89195
1238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.891951238
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2409606700
Short name T805
Test name
Test status
Simulation time 8378470881 ps
CPU time 12.75 seconds
Started May 19 02:02:55 PM PDT 24
Finished May 19 02:03:10 PM PDT 24
Peak memory 204840 kb
Host smart-565d2116-0bd6-4774-b273-b714706d4c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
06700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2409606700
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1052632509
Short name T876
Test name
Test status
Simulation time 8950022786 ps
CPU time 11.02 seconds
Started May 19 02:02:52 PM PDT 24
Finished May 19 02:03:05 PM PDT 24
Peak memory 204784 kb
Host smart-eb79eafd-7562-479d-9c00-31437e1d5d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
32509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1052632509
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1618213155
Short name T1082
Test name
Test status
Simulation time 8395818611 ps
CPU time 11.53 seconds
Started May 19 02:03:18 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204792 kb
Host smart-cab4b907-4447-4aef-befe-f17a2c2dcaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16182
13155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1618213155
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3697196662
Short name T1675
Test name
Test status
Simulation time 8408036093 ps
CPU time 11.87 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204788 kb
Host smart-377406ea-d8fa-4dea-8166-158f0bf34f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36971
96662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3697196662
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1287963718
Short name T1319
Test name
Test status
Simulation time 8367941161 ps
CPU time 11.43 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204852 kb
Host smart-baeca64a-3459-414e-8a8b-8ec303787fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12879
63718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1287963718
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1409654308
Short name T1644
Test name
Test status
Simulation time 8444632855 ps
CPU time 11.56 seconds
Started May 19 02:03:03 PM PDT 24
Finished May 19 02:03:15 PM PDT 24
Peak memory 204816 kb
Host smart-0cb09b7e-db01-44eb-a72d-62c73d884663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14096
54308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1409654308
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1700102374
Short name T760
Test name
Test status
Simulation time 8394831642 ps
CPU time 11.48 seconds
Started May 19 02:03:32 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204696 kb
Host smart-848874f6-22e0-41db-8d44-eb9104d49977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17001
02374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1700102374
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1048137760
Short name T7
Test name
Test status
Simulation time 11502396225 ps
CPU time 13.22 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:13 PM PDT 24
Peak memory 204868 kb
Host smart-6c72f1f2-f525-42bf-898b-2479dea6cb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10481
37760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1048137760
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1656640172
Short name T329
Test name
Test status
Simulation time 8428490706 ps
CPU time 11.1 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:24 PM PDT 24
Peak memory 204836 kb
Host smart-7f961374-a8ce-4f5c-8f21-fe7136632b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566
40172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1656640172
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3543978224
Short name T1493
Test name
Test status
Simulation time 8382645622 ps
CPU time 12.52 seconds
Started May 19 02:03:01 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 204816 kb
Host smart-32091474-c7d5-49d6-b355-12d64ed0b66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
78224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3543978224
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2330386968
Short name T1523
Test name
Test status
Simulation time 8420335711 ps
CPU time 11.69 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204828 kb
Host smart-0b595b69-6777-4662-8897-ad6500da8d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
86968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2330386968
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3355236492
Short name T1669
Test name
Test status
Simulation time 8457345788 ps
CPU time 12.41 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204868 kb
Host smart-4270e697-aeeb-41c2-9745-e236cbaf7a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33552
36492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3355236492
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3562894375
Short name T769
Test name
Test status
Simulation time 8474641097 ps
CPU time 11.52 seconds
Started May 19 02:03:23 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204820 kb
Host smart-b86bb78a-26a3-49c7-9a6f-9cf036e262a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
94375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3562894375
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2592573405
Short name T174
Test name
Test status
Simulation time 8493581341 ps
CPU time 13.24 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204852 kb
Host smart-f7630bb2-dda7-455e-a099-1dc9492caa6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25925
73405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2592573405
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.1173010896
Short name T834
Test name
Test status
Simulation time 8424187365 ps
CPU time 12.09 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 204792 kb
Host smart-763b8280-3a72-4464-a8e7-5ea8e9589a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
10896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.1173010896
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3460468284
Short name T414
Test name
Test status
Simulation time 8373820118 ps
CPU time 10.42 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204796 kb
Host smart-3c175aea-e84b-4f67-9be8-76dee73f12bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
68284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3460468284
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2631205161
Short name T33
Test name
Test status
Simulation time 8364944285 ps
CPU time 12.56 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204840 kb
Host smart-6a863409-f25a-4b09-9ced-527b5c31a8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26312
05161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2631205161
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.855915803
Short name T1040
Test name
Test status
Simulation time 26590303150 ps
CPU time 48.71 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:57 PM PDT 24
Peak memory 204796 kb
Host smart-1022e686-c3f0-418b-b47c-37e02f9a7692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85591
5803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.855915803
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3397294185
Short name T411
Test name
Test status
Simulation time 8406087976 ps
CPU time 11 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204784 kb
Host smart-61d6086a-6dc1-4b4e-a80f-bfea90e382eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33972
94185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3397294185
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1741836393
Short name T468
Test name
Test status
Simulation time 8488166455 ps
CPU time 10.68 seconds
Started May 19 02:03:10 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204884 kb
Host smart-e472ff31-7243-433b-aad3-97beeaf080d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17418
36393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1741836393
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.3320465119
Short name T307
Test name
Test status
Simulation time 8458788449 ps
CPU time 11.03 seconds
Started May 19 02:03:00 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204748 kb
Host smart-392a30e4-48b8-4b06-9753-987de5187806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204
65119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.3320465119
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.872686751
Short name T1187
Test name
Test status
Simulation time 8418193359 ps
CPU time 11.5 seconds
Started May 19 02:03:07 PM PDT 24
Finished May 19 02:03:20 PM PDT 24
Peak memory 204808 kb
Host smart-97817948-ba36-4c68-9547-5a2cde96921a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87268
6751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.872686751
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3215407134
Short name T1594
Test name
Test status
Simulation time 8382778345 ps
CPU time 10.96 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:24 PM PDT 24
Peak memory 204768 kb
Host smart-d76270e3-4009-4c7f-a8d6-8a4bd9a04558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
07134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3215407134
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.579461346
Short name T1626
Test name
Test status
Simulation time 8366735213 ps
CPU time 11.32 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204396 kb
Host smart-eadfd5ae-5274-44a8-b33b-5aeb5dfcd6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57946
1346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.579461346
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2647413401
Short name T1238
Test name
Test status
Simulation time 8420705348 ps
CPU time 11.29 seconds
Started May 19 02:02:53 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 204912 kb
Host smart-df8997c0-c331-47d9-8ec4-0a002f292b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26474
13401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2647413401
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.241831433
Short name T4
Test name
Test status
Simulation time 8373384615 ps
CPU time 11.24 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204868 kb
Host smart-184ea513-e06d-45c3-99d8-d53899ade7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24183
1433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.241831433
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.4074883085
Short name T1741
Test name
Test status
Simulation time 8409477269 ps
CPU time 10.85 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204884 kb
Host smart-aab4fbfb-0670-42cc-82ed-3a0af4c464ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
83085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.4074883085
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.2064106082
Short name T455
Test name
Test status
Simulation time 8462108544 ps
CPU time 12.15 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204804 kb
Host smart-6a5ab344-114a-4955-8f85-05b5ce528944
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2064106082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.2064106082
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.2513565424
Short name T926
Test name
Test status
Simulation time 8382573392 ps
CPU time 13.36 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204832 kb
Host smart-9e9b8a31-4781-4351-9917-628cc72f86ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2513565424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.2513565424
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.3665870438
Short name T1452
Test name
Test status
Simulation time 8425396302 ps
CPU time 10.86 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204820 kb
Host smart-8ebdc380-f53a-49be-899c-06dba8d42eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
70438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.3665870438
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3528983024
Short name T364
Test name
Test status
Simulation time 8373337776 ps
CPU time 10.84 seconds
Started May 19 02:02:58 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204836 kb
Host smart-90c437a3-fc24-4786-9c12-c8e1d7d94d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35289
83024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3528983024
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3051924450
Short name T261
Test name
Test status
Simulation time 8386554433 ps
CPU time 11.94 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204716 kb
Host smart-29220b41-8512-4f70-a59a-b8d64a0c0729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30519
24450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3051924450
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1122244141
Short name T1214
Test name
Test status
Simulation time 9448794484 ps
CPU time 13.98 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204804 kb
Host smart-7b7f2419-f807-48f9-b159-c4770cf31d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
44141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1122244141
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.307365866
Short name T1486
Test name
Test status
Simulation time 8367599564 ps
CPU time 10.91 seconds
Started May 19 02:03:18 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204744 kb
Host smart-7405d4ac-e64b-42e6-8587-7ee736b735fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30736
5866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.307365866
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3177943982
Short name T390
Test name
Test status
Simulation time 8397144764 ps
CPU time 10.98 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204792 kb
Host smart-0524c9d2-0a95-4633-b80f-24c358769d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31779
43982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3177943982
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.8030692
Short name T1222
Test name
Test status
Simulation time 9084196364 ps
CPU time 12.38 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204468 kb
Host smart-5693fe94-d0a2-4524-9922-f1792de3893e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80306
92 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.8030692
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2025026171
Short name T1336
Test name
Test status
Simulation time 8410158964 ps
CPU time 11.62 seconds
Started May 19 02:03:23 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204764 kb
Host smart-3b5654d4-aaa4-4d9e-ab85-5c03a37a949e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20250
26171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2025026171
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3267403248
Short name T94
Test name
Test status
Simulation time 8465895709 ps
CPU time 12.03 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204800 kb
Host smart-5f86d181-f58d-4d34-834d-4e6eaafac3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
03248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3267403248
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2427646101
Short name T776
Test name
Test status
Simulation time 8390799226 ps
CPU time 10.65 seconds
Started May 19 02:03:07 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204712 kb
Host smart-5b769f1c-acc7-4198-bff1-eb607b701785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24276
46101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2427646101
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.746140682
Short name T1405
Test name
Test status
Simulation time 8428503853 ps
CPU time 12.4 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:20 PM PDT 24
Peak memory 204744 kb
Host smart-774d21b1-b365-4d36-9fec-85064667129c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74614
0682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.746140682
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.708220601
Short name T1016
Test name
Test status
Simulation time 8395392430 ps
CPU time 11.82 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204732 kb
Host smart-a6aa7fcd-8d40-423c-8846-6d0d28a790d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70822
0601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.708220601
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1671166660
Short name T980
Test name
Test status
Simulation time 11557269312 ps
CPU time 17.3 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204788 kb
Host smart-b64096de-0de1-4c5e-90c5-edb7fd130160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16711
66660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1671166660
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4084623677
Short name T713
Test name
Test status
Simulation time 8435702055 ps
CPU time 11.67 seconds
Started May 19 02:03:12 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204800 kb
Host smart-7f835731-d7ee-4143-8f14-481096f03c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40846
23677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4084623677
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3497857782
Short name T761
Test name
Test status
Simulation time 8397904656 ps
CPU time 11.28 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204748 kb
Host smart-91935a6d-c6f8-408f-aca1-95957bdf279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34978
57782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3497857782
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1314704786
Short name T128
Test name
Test status
Simulation time 8423200404 ps
CPU time 11.16 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 204732 kb
Host smart-1f05319a-152a-4a8d-a660-0d7170c52bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13147
04786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1314704786
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3485570096
Short name T913
Test name
Test status
Simulation time 8421664624 ps
CPU time 11.05 seconds
Started May 19 02:03:04 PM PDT 24
Finished May 19 02:03:15 PM PDT 24
Peak memory 204816 kb
Host smart-185bc62e-8dba-46a0-b972-139ee04d59ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34855
70096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3485570096
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2670766435
Short name T297
Test name
Test status
Simulation time 8406584477 ps
CPU time 13.82 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204784 kb
Host smart-dcb70233-65a0-4e35-b9f5-6416624eeea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707
66435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2670766435
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.628065949
Short name T1433
Test name
Test status
Simulation time 8411783176 ps
CPU time 11 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204784 kb
Host smart-ea612749-7233-4f2c-92a8-ff16181cfb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62806
5949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.628065949
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.1434164776
Short name T514
Test name
Test status
Simulation time 8413032782 ps
CPU time 11.72 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:17 PM PDT 24
Peak memory 204736 kb
Host smart-122539fd-c1ff-4e91-9ea1-81dfdf62bae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14341
64776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.1434164776
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1168616283
Short name T499
Test name
Test status
Simulation time 8382257306 ps
CPU time 11.94 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204784 kb
Host smart-ac6be950-425c-4092-8595-7d4fd67d4b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11686
16283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1168616283
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4011900196
Short name T1113
Test name
Test status
Simulation time 8367241358 ps
CPU time 12.2 seconds
Started May 19 02:03:23 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204816 kb
Host smart-465f72e0-c9dc-4641-8f24-6dffe409d8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40119
00196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4011900196
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2808751382
Short name T895
Test name
Test status
Simulation time 17986500235 ps
CPU time 31.65 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:50 PM PDT 24
Peak memory 204744 kb
Host smart-6da49b57-8d36-40a8-bb54-7901463fd866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28087
51382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2808751382
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1007861484
Short name T572
Test name
Test status
Simulation time 8407640601 ps
CPU time 11.05 seconds
Started May 19 02:02:59 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 204716 kb
Host smart-7eee13da-9ce1-4cc4-8307-f92d71c69e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
61484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1007861484
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2962504351
Short name T1343
Test name
Test status
Simulation time 8417226996 ps
CPU time 13.52 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204872 kb
Host smart-e2e188c0-97dc-46bc-b8a4-31ba0c408c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29625
04351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2962504351
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.3693347652
Short name T1554
Test name
Test status
Simulation time 8416346142 ps
CPU time 11.53 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204748 kb
Host smart-c6cc03a5-29dd-4efc-bcd3-55e874f9eab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36933
47652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.3693347652
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3124001638
Short name T1028
Test name
Test status
Simulation time 8377383033 ps
CPU time 10.85 seconds
Started May 19 02:03:05 PM PDT 24
Finished May 19 02:03:18 PM PDT 24
Peak memory 204764 kb
Host smart-76f64140-0fdc-4663-ad79-e2c0f1dba159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240
01638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3124001638
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2084251724
Short name T1066
Test name
Test status
Simulation time 8377968809 ps
CPU time 12.95 seconds
Started May 19 02:03:01 PM PDT 24
Finished May 19 02:03:15 PM PDT 24
Peak memory 204812 kb
Host smart-1d202a6a-e196-4c1b-a3f5-1e8030a1afe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20842
51724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2084251724
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1204168764
Short name T1033
Test name
Test status
Simulation time 8391999380 ps
CPU time 12.81 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 204824 kb
Host smart-7c4b2587-258c-4778-b20d-023ada3da923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12041
68764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1204168764
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.11760397
Short name T1185
Test name
Test status
Simulation time 8414747427 ps
CPU time 11.15 seconds
Started May 19 02:02:56 PM PDT 24
Finished May 19 02:03:09 PM PDT 24
Peak memory 204800 kb
Host smart-772dae05-3853-4d95-9b98-854e3f088dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.11760397
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3353299065
Short name T451
Test name
Test status
Simulation time 8389368367 ps
CPU time 10.48 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204816 kb
Host smart-ce9d28ff-4bbe-4297-8b0a-05f91416ce94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33532
99065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3353299065
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3515868700
Short name T1457
Test name
Test status
Simulation time 8493583782 ps
CPU time 10.76 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204840 kb
Host smart-ae613d8d-f074-4fbf-956b-ed049c045418
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3515868700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3515868700
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.378810593
Short name T908
Test name
Test status
Simulation time 8383633021 ps
CPU time 11.57 seconds
Started May 19 02:03:27 PM PDT 24
Finished May 19 02:03:39 PM PDT 24
Peak memory 204824 kb
Host smart-9a1eca72-66b6-4747-beab-00e0929e1490
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=378810593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.378810593
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.3936104534
Short name T566
Test name
Test status
Simulation time 8434691646 ps
CPU time 10.66 seconds
Started May 19 02:03:13 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204796 kb
Host smart-7fa7036d-2718-45d1-a96d-1011ffeb6dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
04534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.3936104534
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.4198329302
Short name T1106
Test name
Test status
Simulation time 8383714062 ps
CPU time 13 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204832 kb
Host smart-300b016f-7f4a-445d-aaaa-99daa75d21e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41983
29302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4198329302
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3845282853
Short name T1606
Test name
Test status
Simulation time 9206228420 ps
CPU time 12.38 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204864 kb
Host smart-5bd90c55-a18e-4ce1-b169-8227801c268f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
82853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3845282853
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3486382180
Short name T675
Test name
Test status
Simulation time 8367315076 ps
CPU time 13.47 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:24 PM PDT 24
Peak memory 204824 kb
Host smart-2ff9722b-f34d-4dd7-bd86-4583a3e19deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
82180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3486382180
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3857207855
Short name T335
Test name
Test status
Simulation time 8385530582 ps
CPU time 10.72 seconds
Started May 19 02:03:10 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204872 kb
Host smart-bae1fbc8-3703-4b82-893d-53b8402d7c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38572
07855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3857207855
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.372603718
Short name T952
Test name
Test status
Simulation time 9066897657 ps
CPU time 12.56 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204808 kb
Host smart-5abd62dc-1eba-42ff-80ba-8934becd0f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
3718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.372603718
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2297760269
Short name T874
Test name
Test status
Simulation time 8579431613 ps
CPU time 13.78 seconds
Started May 19 02:03:13 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204820 kb
Host smart-22039b54-9e15-4e64-8bbc-de02d9bd2bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22977
60269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2297760269
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1892856659
Short name T445
Test name
Test status
Simulation time 8435794803 ps
CPU time 12.98 seconds
Started May 19 02:03:28 PM PDT 24
Finished May 19 02:03:42 PM PDT 24
Peak memory 204836 kb
Host smart-8fc7a175-bc0b-4e10-a57f-fbb65c574242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
56659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1892856659
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.767172265
Short name T1002
Test name
Test status
Simulation time 8413416729 ps
CPU time 10.87 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204944 kb
Host smart-949e5ec1-5114-4a23-810b-b84ca0211bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76717
2265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.767172265
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3823271809
Short name T1257
Test name
Test status
Simulation time 8416203029 ps
CPU time 11.61 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204744 kb
Host smart-f55a3783-f705-4359-b5a3-81cb33b67afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
71809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3823271809
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2309329445
Short name T367
Test name
Test status
Simulation time 8417790582 ps
CPU time 11.71 seconds
Started May 19 02:03:29 PM PDT 24
Finished May 19 02:03:42 PM PDT 24
Peak memory 204868 kb
Host smart-315e0f62-86e1-4a48-8388-7d74970f0288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23093
29445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2309329445
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1657955914
Short name T845
Test name
Test status
Simulation time 11510698791 ps
CPU time 13.75 seconds
Started May 19 02:03:25 PM PDT 24
Finished May 19 02:03:40 PM PDT 24
Peak memory 204816 kb
Host smart-7db37df8-4456-4fa9-839f-25bfb66a1f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16579
55914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1657955914
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3888849806
Short name T396
Test name
Test status
Simulation time 8417107909 ps
CPU time 11.65 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204800 kb
Host smart-1f9328d1-0077-4314-85d4-6c837e6c71a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38888
49806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3888849806
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1936380790
Short name T1250
Test name
Test status
Simulation time 8374169492 ps
CPU time 10.67 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204776 kb
Host smart-5a568137-fa3f-4dd2-ac33-025da54cc672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
80790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1936380790
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1403827761
Short name T1461
Test name
Test status
Simulation time 8444269188 ps
CPU time 11.33 seconds
Started May 19 02:03:07 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204788 kb
Host smart-296c5bfe-5c70-43bf-8062-a29788be2432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14038
27761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1403827761
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.367523371
Short name T968
Test name
Test status
Simulation time 8448749274 ps
CPU time 10.84 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204808 kb
Host smart-c8d438d6-61c2-43f3-b1f2-f0eec981465b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
3371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.367523371
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2259382121
Short name T296
Test name
Test status
Simulation time 8395470099 ps
CPU time 13.12 seconds
Started May 19 02:03:26 PM PDT 24
Finished May 19 02:03:39 PM PDT 24
Peak memory 204848 kb
Host smart-aa415371-cc73-48ca-ac69-75080b5af121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
82121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2259382121
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1503065601
Short name T1624
Test name
Test status
Simulation time 8392783755 ps
CPU time 11.01 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204832 kb
Host smart-8b3ccc44-c62d-4a49-b02e-0b5f5305c93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
65601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1503065601
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3653805934
Short name T187
Test name
Test status
Simulation time 8377432561 ps
CPU time 11.62 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204780 kb
Host smart-990bb635-a5f7-4e5a-83e5-2ab98a8bdc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36538
05934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3653805934
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.3492711587
Short name T542
Test name
Test status
Simulation time 8433481341 ps
CPU time 10.84 seconds
Started May 19 02:03:10 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204776 kb
Host smart-ad42f8fd-44f5-4851-a7eb-604c5658a6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34927
11587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.3492711587
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.743701701
Short name T1075
Test name
Test status
Simulation time 8390016525 ps
CPU time 11.69 seconds
Started May 19 02:03:08 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204792 kb
Host smart-87a15737-4be4-47ce-9113-292c0db9b514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74370
1701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.743701701
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2698319505
Short name T415
Test name
Test status
Simulation time 8376917443 ps
CPU time 11.7 seconds
Started May 19 02:03:06 PM PDT 24
Finished May 19 02:03:19 PM PDT 24
Peak memory 204744 kb
Host smart-585e0d53-876c-49c4-86f2-9c96474b1d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26983
19505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2698319505
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1216050830
Short name T629
Test name
Test status
Simulation time 24134839540 ps
CPU time 43.47 seconds
Started May 19 02:03:23 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204804 kb
Host smart-638dba52-e020-4497-b734-a9333796416d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
50830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1216050830
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2288083253
Short name T575
Test name
Test status
Simulation time 8385825678 ps
CPU time 10.53 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204784 kb
Host smart-b57a01bd-f823-474f-b393-180c0b0425d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22880
83253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2288083253
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.81541959
Short name T837
Test name
Test status
Simulation time 8422736522 ps
CPU time 11.35 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204704 kb
Host smart-86ce0269-b206-49df-84e7-89589f4368ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81541
959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.81541959
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.845003834
Short name T412
Test name
Test status
Simulation time 8410335614 ps
CPU time 11.73 seconds
Started May 19 02:03:07 PM PDT 24
Finished May 19 02:03:21 PM PDT 24
Peak memory 204844 kb
Host smart-8217c7d3-0979-4bf0-ac35-6f9f6d3ef9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84500
3834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.845003834
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1665322797
Short name T1643
Test name
Test status
Simulation time 8375764778 ps
CPU time 10.79 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204772 kb
Host smart-57e8942e-32b4-42f3-9f58-7679089dfd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16653
22797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1665322797
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3737863465
Short name T911
Test name
Test status
Simulation time 8380127192 ps
CPU time 11.27 seconds
Started May 19 02:03:22 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204780 kb
Host smart-92bb3f5d-eff3-4767-86f3-abb514e2877e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37378
63465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3737863465
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3374741373
Short name T682
Test name
Test status
Simulation time 8387601033 ps
CPU time 10.66 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204760 kb
Host smart-218c3596-ca4e-4a7d-a6c8-4a26f94a70b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33747
41373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3374741373
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.115063167
Short name T1511
Test name
Test status
Simulation time 8472002681 ps
CPU time 12.89 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 205120 kb
Host smart-a8e586be-9934-4867-85b0-84379de2bb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11506
3167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.115063167
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3330924968
Short name T564
Test name
Test status
Simulation time 8400455655 ps
CPU time 12.58 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204748 kb
Host smart-157cf7c1-2898-4f45-969a-217fc3ff3b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33309
24968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3330924968
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.528438907
Short name T1076
Test name
Test status
Simulation time 8375921262 ps
CPU time 10.64 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204800 kb
Host smart-f0a92d24-5967-4c5a-809c-2642db515f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52843
8907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.528438907
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.3733299184
Short name T1322
Test name
Test status
Simulation time 8467633295 ps
CPU time 11.23 seconds
Started May 19 02:03:31 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204696 kb
Host smart-fa689bb5-9d7a-4ca2-bf50-3f3fde64739e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3733299184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.3733299184
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2831955280
Short name T869
Test name
Test status
Simulation time 8379671077 ps
CPU time 11.11 seconds
Started May 19 02:03:27 PM PDT 24
Finished May 19 02:03:39 PM PDT 24
Peak memory 205048 kb
Host smart-8366db97-3dd2-425f-b829-4f362e9e67cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2831955280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2831955280
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.1280406736
Short name T323
Test name
Test status
Simulation time 8384427377 ps
CPU time 11.43 seconds
Started May 19 02:03:31 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 205084 kb
Host smart-4efca8b7-1b7f-48d0-9024-cb765c760623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12804
06736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.1280406736
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.4237379562
Short name T1483
Test name
Test status
Simulation time 8394305768 ps
CPU time 11.11 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204832 kb
Host smart-b77255ec-29ac-46a8-b9ff-60608cb95f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42373
79562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.4237379562
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3652450306
Short name T481
Test name
Test status
Simulation time 8371042408 ps
CPU time 11.57 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 205012 kb
Host smart-e70ac05b-7ba2-4c79-90a3-3a3827edd6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36524
50306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3652450306
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3359017503
Short name T1637
Test name
Test status
Simulation time 8717818125 ps
CPU time 11.34 seconds
Started May 19 02:03:10 PM PDT 24
Finished May 19 02:03:23 PM PDT 24
Peak memory 204800 kb
Host smart-d29972fc-b741-4af5-a8b1-a762021e3843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590
17503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3359017503
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1535490420
Short name T1110
Test name
Test status
Simulation time 8378407888 ps
CPU time 11.46 seconds
Started May 19 02:03:18 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204812 kb
Host smart-b17e8bf6-04bf-4686-b357-99a82fcbc89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15354
90420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1535490420
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1070165475
Short name T368
Test name
Test status
Simulation time 8393953785 ps
CPU time 11.94 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204840 kb
Host smart-d4fa4b12-0f1c-4299-b33a-20c432e81e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
65475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1070165475
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.4168431149
Short name T1618
Test name
Test status
Simulation time 9063771311 ps
CPU time 12.63 seconds
Started May 19 02:03:13 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204840 kb
Host smart-6f98da30-c64d-422c-ae4b-0e2bf39c92f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41684
31149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.4168431149
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1333470650
Short name T1550
Test name
Test status
Simulation time 8397140226 ps
CPU time 11.85 seconds
Started May 19 02:03:09 PM PDT 24
Finished May 19 02:03:22 PM PDT 24
Peak memory 204772 kb
Host smart-d0199e6a-1378-4689-a562-68b8589570b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
70650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1333470650
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1069407302
Short name T1116
Test name
Test status
Simulation time 8469329101 ps
CPU time 13.81 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204792 kb
Host smart-21864752-90ac-42ae-b91a-fac8f7cf774f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10694
07302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1069407302
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2509827200
Short name T848
Test name
Test status
Simulation time 8372134517 ps
CPU time 10.74 seconds
Started May 19 02:03:13 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204852 kb
Host smart-49599630-9ead-4ce8-a743-082fc3ae3dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25098
27200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2509827200
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3599171612
Short name T1092
Test name
Test status
Simulation time 8445123747 ps
CPU time 11.04 seconds
Started May 19 02:03:13 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204884 kb
Host smart-97e2533f-4785-4cbc-9559-6a6d787c10ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35991
71612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3599171612
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2844006854
Short name T909
Test name
Test status
Simulation time 8402211415 ps
CPU time 11.48 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204888 kb
Host smart-72296084-bb5e-465d-b6bb-9e143e5eeaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
06854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2844006854
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1287324051
Short name T847
Test name
Test status
Simulation time 11506550151 ps
CPU time 13.83 seconds
Started May 19 02:03:25 PM PDT 24
Finished May 19 02:03:39 PM PDT 24
Peak memory 205076 kb
Host smart-cb481a77-9bd6-478a-a65b-d1508bbbef9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12873
24051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1287324051
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3236125527
Short name T1147
Test name
Test status
Simulation time 8474508300 ps
CPU time 11.73 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204772 kb
Host smart-56087f4e-990a-4fe0-baa5-6b27081690d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32361
25527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3236125527
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.998497207
Short name T460
Test name
Test status
Simulation time 8376628859 ps
CPU time 12.67 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204792 kb
Host smart-e55e9eb8-c049-454d-a3cf-b9d72db16e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99849
7207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.998497207
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1249351924
Short name T1560
Test name
Test status
Simulation time 8427846676 ps
CPU time 11.94 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204852 kb
Host smart-b8f9801e-7bc5-4b78-9b52-b8471d88d62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12493
51924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1249351924
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3559623231
Short name T104
Test name
Test status
Simulation time 8428394463 ps
CPU time 10.66 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204736 kb
Host smart-60193525-53cd-41f5-8896-bd19bfaf9773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
23231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3559623231
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.61453759
Short name T1011
Test name
Test status
Simulation time 8413295005 ps
CPU time 10.72 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204860 kb
Host smart-5ff2d589-3ac1-40ce-b362-4228109c0252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61453
759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.61453759
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3984482920
Short name T915
Test name
Test status
Simulation time 8398616497 ps
CPU time 10.62 seconds
Started May 19 02:03:19 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204760 kb
Host smart-2abdf11b-57ba-42b7-9b6e-073c7bd76366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39844
82920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3984482920
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1977947594
Short name T49
Test name
Test status
Simulation time 8401239533 ps
CPU time 12.98 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204888 kb
Host smart-197f2054-8663-4b76-9881-444504413c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19779
47594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1977947594
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.463710230
Short name T1507
Test name
Test status
Simulation time 8402945261 ps
CPU time 12.93 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204740 kb
Host smart-22fe2b17-ff2b-4977-b222-bce29704f939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46371
0230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.463710230
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1307441515
Short name T711
Test name
Test status
Simulation time 8374622625 ps
CPU time 11.79 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204796 kb
Host smart-288f9316-87b5-4ac9-b74e-57739b91b140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13074
41515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1307441515
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3079747884
Short name T413
Test name
Test status
Simulation time 8368786342 ps
CPU time 11.68 seconds
Started May 19 02:03:22 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 204708 kb
Host smart-8fe834e4-0f39-4a25-99b8-98d20a9fbc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30797
47884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3079747884
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.31132616
Short name T1471
Test name
Test status
Simulation time 25414711074 ps
CPU time 54.66 seconds
Started May 19 02:03:11 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 204800 kb
Host smart-0a746f44-1b28-492c-b0be-4cfb50cd45bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.31132616
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2352306711
Short name T497
Test name
Test status
Simulation time 8378095325 ps
CPU time 11.22 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204812 kb
Host smart-222b254e-f96b-46d4-b5e5-68eaa00c1cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23523
06711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2352306711
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3944637962
Short name T688
Test name
Test status
Simulation time 8427563284 ps
CPU time 12.21 seconds
Started May 19 02:03:30 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204832 kb
Host smart-dc414469-e258-4dec-9b69-ac2b7d3ac173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
37962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3944637962
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.702034143
Short name T1115
Test name
Test status
Simulation time 8391350261 ps
CPU time 10.65 seconds
Started May 19 02:03:03 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 204812 kb
Host smart-c5a70012-a036-4889-b356-e2ade9c48a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70203
4143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.702034143
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3683026075
Short name T1248
Test name
Test status
Simulation time 8370729200 ps
CPU time 10.91 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204768 kb
Host smart-dc33150c-ccc6-4107-b7a2-aa0c021f832b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36830
26075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3683026075
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1033051783
Short name T831
Test name
Test status
Simulation time 8372382361 ps
CPU time 11.61 seconds
Started May 19 02:03:12 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204780 kb
Host smart-156fad2e-d379-418f-aaba-8342e6487562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
51783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1033051783
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.472364386
Short name T1691
Test name
Test status
Simulation time 8372073961 ps
CPU time 12.61 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204820 kb
Host smart-1015cb31-7704-41fc-b02c-e5358744bb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47236
4386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.472364386
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.4167515419
Short name T1468
Test name
Test status
Simulation time 8485498101 ps
CPU time 11.87 seconds
Started May 19 02:03:28 PM PDT 24
Finished May 19 02:03:41 PM PDT 24
Peak memory 204844 kb
Host smart-9f7e8e87-70e1-4ecd-8b68-487715ec412d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41675
15419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.4167515419
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2500423413
Short name T579
Test name
Test status
Simulation time 8394300165 ps
CPU time 11.31 seconds
Started May 19 02:03:21 PM PDT 24
Finished May 19 02:03:38 PM PDT 24
Peak memory 204792 kb
Host smart-1359a477-4bb6-4b8f-b392-b30e206a9258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
23413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2500423413
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2838443959
Short name T495
Test name
Test status
Simulation time 8376004798 ps
CPU time 11.11 seconds
Started May 19 02:03:29 PM PDT 24
Finished May 19 02:03:42 PM PDT 24
Peak memory 205020 kb
Host smart-202a644b-ccc0-4360-a1b7-a0d4787fac08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28384
43959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2838443959
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.387626319
Short name T740
Test name
Test status
Simulation time 8484528442 ps
CPU time 11.21 seconds
Started May 19 02:03:34 PM PDT 24
Finished May 19 02:03:47 PM PDT 24
Peak memory 204736 kb
Host smart-904db173-7fc7-4282-a9a4-2ffcf2646a29
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=387626319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.387626319
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.2358487923
Short name T1438
Test name
Test status
Simulation time 8403254978 ps
CPU time 11.81 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204720 kb
Host smart-b880f510-27db-491d-ba40-799725710a11
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2358487923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.2358487923
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.1787659542
Short name T1262
Test name
Test status
Simulation time 8450759516 ps
CPU time 11.2 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204840 kb
Host smart-e3df334f-9089-401d-a33f-42bfeee0cd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17876
59542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.1787659542
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.848469522
Short name T389
Test name
Test status
Simulation time 8402600289 ps
CPU time 11.09 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204816 kb
Host smart-d363a93a-7ce5-48bb-a088-7cff4105e2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84846
9522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.848469522
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3475597584
Short name T1017
Test name
Test status
Simulation time 8487190780 ps
CPU time 11.09 seconds
Started May 19 02:03:35 PM PDT 24
Finished May 19 02:03:47 PM PDT 24
Peak memory 204772 kb
Host smart-7ae3d0cb-13ff-4532-b5fc-8ddbb89eade8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34755
97584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3475597584
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1603147883
Short name T1084
Test name
Test status
Simulation time 8364496458 ps
CPU time 11.17 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204748 kb
Host smart-d63a5107-d1d1-494c-a3f8-e35a29385d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
47883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1603147883
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1884523861
Short name T818
Test name
Test status
Simulation time 8376861059 ps
CPU time 12.53 seconds
Started May 19 02:03:35 PM PDT 24
Finished May 19 02:03:49 PM PDT 24
Peak memory 204788 kb
Host smart-d10c8154-49b4-4a8a-bdf1-b83d3c9d56e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
23861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1884523861
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2487770964
Short name T42
Test name
Test status
Simulation time 8471355916 ps
CPU time 12.33 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204792 kb
Host smart-9ba16ea2-be92-4b55-a4d6-1389b66d9914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24877
70964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2487770964
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.372079346
Short name T934
Test name
Test status
Simulation time 8393288771 ps
CPU time 10.74 seconds
Started May 19 02:03:34 PM PDT 24
Finished May 19 02:03:46 PM PDT 24
Peak memory 204732 kb
Host smart-6cd56f46-d42e-49f1-acd5-31dfa2948f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37207
9346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.372079346
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3409251791
Short name T1673
Test name
Test status
Simulation time 8373378620 ps
CPU time 10.23 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204664 kb
Host smart-2eddf5ce-7e9a-4174-88ca-374051ccb466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34092
51791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3409251791
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2932183223
Short name T1485
Test name
Test status
Simulation time 8486917282 ps
CPU time 11.33 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204816 kb
Host smart-2423e9cc-a893-4b20-8305-5c06f8a1ee22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29321
83223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2932183223
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3559797598
Short name T314
Test name
Test status
Simulation time 8405280526 ps
CPU time 11.31 seconds
Started May 19 02:03:18 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204860 kb
Host smart-ffa16daa-cee4-4703-b4f0-d98c995485ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
97598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3559797598
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1799302572
Short name T925
Test name
Test status
Simulation time 11525480829 ps
CPU time 13.51 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204728 kb
Host smart-3921a017-95a8-40ac-8f07-fe7caf73ea8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17993
02572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1799302572
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1361071612
Short name T1678
Test name
Test status
Simulation time 8419908501 ps
CPU time 11.36 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204772 kb
Host smart-4fbf0eec-52c7-4d49-a333-b9b0c5732dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610
71612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1361071612
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3105694290
Short name T1123
Test name
Test status
Simulation time 8405573827 ps
CPU time 11.07 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204796 kb
Host smart-8b40c318-d6b4-4837-b71c-5c9e2c7bc8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31056
94290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3105694290
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.970254816
Short name T794
Test name
Test status
Simulation time 8403241775 ps
CPU time 10.79 seconds
Started May 19 02:03:12 PM PDT 24
Finished May 19 02:03:24 PM PDT 24
Peak memory 204800 kb
Host smart-05691cbb-82bd-4ff8-b7ee-f7d9560969f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97025
4816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.970254816
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1333855662
Short name T594
Test name
Test status
Simulation time 8417120078 ps
CPU time 12.15 seconds
Started May 19 02:03:30 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204824 kb
Host smart-b62b1a79-f78b-4328-9743-c5943f64e3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
55662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1333855662
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.271312197
Short name T1497
Test name
Test status
Simulation time 8425957780 ps
CPU time 11.29 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204800 kb
Host smart-b33b370d-4d18-4432-b72d-072ab2aeef3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27131
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.271312197
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.166078654
Short name T483
Test name
Test status
Simulation time 8394389683 ps
CPU time 11.91 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204840 kb
Host smart-5bc129b2-ff0b-4a1e-81f8-6ada246ec4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
8654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.166078654
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1551030926
Short name T191
Test name
Test status
Simulation time 8416187442 ps
CPU time 11.02 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204724 kb
Host smart-0bfe28c6-b1d8-425f-b310-903203f3ba4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15510
30926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1551030926
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.1824737956
Short name T1747
Test name
Test status
Simulation time 8408746124 ps
CPU time 11.37 seconds
Started May 19 02:03:29 PM PDT 24
Finished May 19 02:03:42 PM PDT 24
Peak memory 204764 kb
Host smart-bf479e0e-513b-436e-afbe-3c5465ed5fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
37956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.1824737956
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.886867337
Short name T534
Test name
Test status
Simulation time 8377115597 ps
CPU time 12.48 seconds
Started May 19 02:03:31 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 204576 kb
Host smart-6a0e88ef-150b-4df6-8907-1f568022b6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88686
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.886867337
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1540462437
Short name T699
Test name
Test status
Simulation time 8360869283 ps
CPU time 10.76 seconds
Started May 19 02:03:33 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 204804 kb
Host smart-e1cfab0d-8b9c-4ea8-83fd-b16a24374cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
62437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1540462437
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.729052845
Short name T939
Test name
Test status
Simulation time 26332699577 ps
CPU time 50.02 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 204736 kb
Host smart-1d37da64-c7ec-4ca7-9881-4d0d3af98386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72905
2845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.729052845
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.677159043
Short name T1259
Test name
Test status
Simulation time 8412245036 ps
CPU time 11.23 seconds
Started May 19 02:03:13 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 204768 kb
Host smart-d6a253e8-893c-4df1-98c0-aa20763424ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67715
9043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.677159043
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.298191753
Short name T512
Test name
Test status
Simulation time 8423123892 ps
CPU time 11.32 seconds
Started May 19 02:03:29 PM PDT 24
Finished May 19 02:03:41 PM PDT 24
Peak memory 204808 kb
Host smart-ed6bc136-55d6-4821-b7f0-e0ef17a223b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819
1753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.298191753
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2481537704
Short name T1531
Test name
Test status
Simulation time 8479826894 ps
CPU time 11.73 seconds
Started May 19 02:03:22 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204800 kb
Host smart-37fe82e3-e1b4-47f5-959e-5aa6a692c6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
37704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2481537704
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2205318757
Short name T787
Test name
Test status
Simulation time 8425624618 ps
CPU time 11.18 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 204852 kb
Host smart-5df917e0-e3ad-4c72-8f43-9d5ac68bdc27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22053
18757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2205318757
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1292968332
Short name T801
Test name
Test status
Simulation time 8377203584 ps
CPU time 11.37 seconds
Started May 19 02:03:35 PM PDT 24
Finished May 19 02:03:47 PM PDT 24
Peak memory 204720 kb
Host smart-e1686169-318b-40d6-89a1-e8b52b96cfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12929
68332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1292968332
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1578289860
Short name T650
Test name
Test status
Simulation time 8367263332 ps
CPU time 12.21 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:34 PM PDT 24
Peak memory 204768 kb
Host smart-b308c5b6-2441-4e24-aad5-9fea89fbb15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15782
89860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1578289860
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.113597033
Short name T1194
Test name
Test status
Simulation time 8476101163 ps
CPU time 13.86 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 204764 kb
Host smart-fc9faa38-8b2b-4a19-99a0-1bd7e91e1280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11359
7033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.113597033
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2721330862
Short name T1035
Test name
Test status
Simulation time 8408660647 ps
CPU time 11.09 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204808 kb
Host smart-06ecf392-e06c-4c35-ada2-28ecda3f2135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27213
30862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2721330862
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.812481120
Short name T478
Test name
Test status
Simulation time 8414664034 ps
CPU time 12.49 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204752 kb
Host smart-63fd42a0-c3ce-4e0d-92cd-36906e710a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81248
1120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.812481120
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3769635378
Short name T664
Test name
Test status
Simulation time 8488347208 ps
CPU time 13.76 seconds
Started May 19 02:03:37 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204832 kb
Host smart-7ca6a2ae-4b3b-473f-b0ef-39176863d89e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3769635378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3769635378
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.3446822011
Short name T516
Test name
Test status
Simulation time 8374306262 ps
CPU time 12.98 seconds
Started May 19 02:03:30 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204740 kb
Host smart-2913c8c0-4852-4a39-9219-5fe7c0aff7c4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3446822011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.3446822011
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.1908168473
Short name T1061
Test name
Test status
Simulation time 8409984429 ps
CPU time 11.86 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:49 PM PDT 24
Peak memory 204792 kb
Host smart-2fca8277-dd49-4df0-a234-59827704c3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19081
68473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.1908168473
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4016662488
Short name T1026
Test name
Test status
Simulation time 8375880956 ps
CPU time 10.66 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 204840 kb
Host smart-8e942bbc-15fc-4a9a-8a61-9cb850f88108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40166
62488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4016662488
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1921492702
Short name T1774
Test name
Test status
Simulation time 8587327873 ps
CPU time 12.45 seconds
Started May 19 02:03:42 PM PDT 24
Finished May 19 02:03:57 PM PDT 24
Peak memory 204836 kb
Host smart-0e0ce5ac-6bea-4685-bbb4-c79e62ead244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
92702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1921492702
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.4120403975
Short name T99
Test name
Test status
Simulation time 8366066358 ps
CPU time 11.04 seconds
Started May 19 02:03:33 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 204756 kb
Host smart-e595cac3-9a9e-4e8c-ad71-e84a6d2d350f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
03975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.4120403975
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.126261277
Short name T1335
Test name
Test status
Simulation time 8417720742 ps
CPU time 12.99 seconds
Started May 19 02:03:17 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 205120 kb
Host smart-d98779d6-8a80-4be9-83ab-ad7832dcc55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12626
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.126261277
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1056354637
Short name T1737
Test name
Test status
Simulation time 9129930111 ps
CPU time 13.8 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 205112 kb
Host smart-d454ceb9-ca47-45d2-b279-9063e28603f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10563
54637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1056354637
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1047784233
Short name T43
Test name
Test status
Simulation time 8545273084 ps
CPU time 12.98 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204784 kb
Host smart-0b2a5353-dd9a-48cb-97f9-fab7684d3ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10477
84233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1047784233
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.823683617
Short name T1522
Test name
Test status
Simulation time 8436879984 ps
CPU time 11.45 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 204836 kb
Host smart-810be0f2-62c7-4738-997b-97979dc9b762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82368
3617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.823683617
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.198755986
Short name T1229
Test name
Test status
Simulation time 8487161767 ps
CPU time 12.1 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204796 kb
Host smart-03c52da4-2b2f-425b-8fbc-0f23ba649f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19875
5986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.198755986
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2640118121
Short name T681
Test name
Test status
Simulation time 8388851674 ps
CPU time 11.18 seconds
Started May 19 02:03:37 PM PDT 24
Finished May 19 02:03:49 PM PDT 24
Peak memory 204872 kb
Host smart-895acbb9-85ae-46aa-a784-33d7fb7abf92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401
18121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2640118121
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3490139521
Short name T1079
Test name
Test status
Simulation time 11525519895 ps
CPU time 13.91 seconds
Started May 19 02:04:03 PM PDT 24
Finished May 19 02:04:19 PM PDT 24
Peak memory 204812 kb
Host smart-06e52123-3b49-45c8-8162-a46bf1b6b927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901
39521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3490139521
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3406555923
Short name T1184
Test name
Test status
Simulation time 8419812287 ps
CPU time 13.61 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204828 kb
Host smart-2dcfcaef-399e-4789-a1be-12a79040b81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
55923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3406555923
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2641129422
Short name T1608
Test name
Test status
Simulation time 8368883470 ps
CPU time 11.26 seconds
Started May 19 02:03:27 PM PDT 24
Finished May 19 02:03:39 PM PDT 24
Peak memory 204796 kb
Host smart-c572cd57-20e7-424c-b954-9dbafc12ca71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
29422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2641129422
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.470392310
Short name T124
Test name
Test status
Simulation time 8408931055 ps
CPU time 11.51 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204832 kb
Host smart-d2c8517e-96a0-4757-98ef-5c07a91e0d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47039
2310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.470392310
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.506651787
Short name T880
Test name
Test status
Simulation time 8418314090 ps
CPU time 14.29 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204852 kb
Host smart-aefd54b0-cf20-4c7e-87c8-02f7eaa40049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50665
1787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.506651787
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.771554716
Short name T663
Test name
Test status
Simulation time 8414478649 ps
CPU time 10.86 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204784 kb
Host smart-fadfac48-f069-4230-bad0-9aa7b96bb1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77155
4716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.771554716
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.447425921
Short name T563
Test name
Test status
Simulation time 8384157748 ps
CPU time 12.51 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204724 kb
Host smart-ef1276bc-60a8-4303-a7c6-b3dd8d842e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44742
5921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.447425921
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2637905790
Short name T1348
Test name
Test status
Simulation time 8378061697 ps
CPU time 10.95 seconds
Started May 19 02:03:30 PM PDT 24
Finished May 19 02:03:47 PM PDT 24
Peak memory 204744 kb
Host smart-8562f55b-a0a7-46de-8044-f17831f60ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26379
05790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2637905790
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.3692642110
Short name T1476
Test name
Test status
Simulation time 8414411502 ps
CPU time 10.86 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:56 PM PDT 24
Peak memory 204720 kb
Host smart-1a46ba06-25b4-43d3-88f5-6203d87558eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36926
42110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.3692642110
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.4198508272
Short name T963
Test name
Test status
Simulation time 8367412331 ps
CPU time 13.27 seconds
Started May 19 02:03:14 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204788 kb
Host smart-1ff89723-e869-426f-b803-8f990a741136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41985
08272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.4198508272
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1545385498
Short name T1698
Test name
Test status
Simulation time 8367562953 ps
CPU time 11.89 seconds
Started May 19 02:03:19 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204708 kb
Host smart-0cf723c7-32cb-4f9a-a1c9-7c7301e57846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
85498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1545385498
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2446355906
Short name T235
Test name
Test status
Simulation time 17372590882 ps
CPU time 32.03 seconds
Started May 19 02:03:34 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204684 kb
Host smart-51d9e6a9-1d91-4e08-a4fb-ab91f3693779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
55906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2446355906
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2622611903
Short name T1443
Test name
Test status
Simulation time 8406275739 ps
CPU time 11.9 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204868 kb
Host smart-5bcbbada-845c-4117-88ef-68e87586a32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26226
11903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2622611903
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.119381220
Short name T694
Test name
Test status
Simulation time 8430103532 ps
CPU time 13.89 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:33 PM PDT 24
Peak memory 204860 kb
Host smart-532262ce-524d-4993-95e0-e2fa1cc10a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11938
1220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.119381220
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.902591008
Short name T635
Test name
Test status
Simulation time 8415039478 ps
CPU time 10.82 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:29 PM PDT 24
Peak memory 204788 kb
Host smart-4ea35014-a3d5-44df-a422-428a0897a000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90259
1008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.902591008
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2789247285
Short name T1726
Test name
Test status
Simulation time 8376251723 ps
CPU time 13.19 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:50 PM PDT 24
Peak memory 204732 kb
Host smart-2a471b3c-b303-4c8d-a51a-70204589e09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27892
47285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2789247285
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2920682270
Short name T1729
Test name
Test status
Simulation time 8373931040 ps
CPU time 11.37 seconds
Started May 19 02:03:32 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 204816 kb
Host smart-7244ba5a-2be4-4ddc-95bf-714bd3fd777e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29206
82270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2920682270
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1466373819
Short name T858
Test name
Test status
Simulation time 8367918533 ps
CPU time 10.6 seconds
Started May 19 02:03:20 PM PDT 24
Finished May 19 02:03:32 PM PDT 24
Peak memory 204804 kb
Host smart-da0fee87-0432-45ef-9301-f2d9b6cabc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14663
73819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1466373819
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2324728918
Short name T66
Test name
Test status
Simulation time 8450344958 ps
CPU time 13.62 seconds
Started May 19 02:03:15 PM PDT 24
Finished May 19 02:03:31 PM PDT 24
Peak memory 204872 kb
Host smart-f20fc1d9-7b18-4f0d-a143-c6ad2d307e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247
28918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2324728918
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3421553351
Short name T827
Test name
Test status
Simulation time 8419580040 ps
CPU time 11.62 seconds
Started May 19 02:03:32 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204784 kb
Host smart-c3bfb460-cb9f-45c5-9474-52baccd41afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34215
53351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3421553351
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1176544172
Short name T796
Test name
Test status
Simulation time 8418009859 ps
CPU time 11.45 seconds
Started May 19 02:03:16 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 204884 kb
Host smart-32c08b92-25c6-4379-82bc-637f469ca042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
44172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1176544172
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.2727018849
Short name T446
Test name
Test status
Simulation time 8544881010 ps
CPU time 11.12 seconds
Started May 19 02:01:15 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204796 kb
Host smart-3f29fa93-c07e-43a8-b8b2-5e041a772356
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2727018849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.2727018849
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.758015288
Short name T304
Test name
Test status
Simulation time 8380034035 ps
CPU time 10.54 seconds
Started May 19 02:01:23 PM PDT 24
Finished May 19 02:01:35 PM PDT 24
Peak memory 204788 kb
Host smart-7dd25502-d8ad-4798-84ad-d6fc9b649db3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=758015288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.758015288
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3080643142
Short name T1584
Test name
Test status
Simulation time 8468747392 ps
CPU time 11.02 seconds
Started May 19 02:01:18 PM PDT 24
Finished May 19 02:01:30 PM PDT 24
Peak memory 204832 kb
Host smart-c8a63889-8030-4e0a-8bbc-79e2dddc7012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
43142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3080643142
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.332596042
Short name T1069
Test name
Test status
Simulation time 8403305010 ps
CPU time 11.26 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 204812 kb
Host smart-6790a312-a32f-4715-88ac-dd33f5b2bdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
6042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.332596042
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3957316225
Short name T888
Test name
Test status
Simulation time 8378095217 ps
CPU time 13.2 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204828 kb
Host smart-e8b34341-091c-4e72-9af0-2fded02a2b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
16225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3957316225
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.4052502953
Short name T613
Test name
Test status
Simulation time 8374060174 ps
CPU time 11.21 seconds
Started May 19 02:01:15 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204776 kb
Host smart-6374bb13-5e10-4766-b6f5-9f30f692550f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
02953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.4052502953
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1229303290
Short name T1233
Test name
Test status
Simulation time 8432820050 ps
CPU time 10.85 seconds
Started May 19 02:01:13 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204872 kb
Host smart-ba7fac66-0c0f-4c8b-aa41-2ac8f2d57a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293
03290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1229303290
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.4054537835
Short name T450
Test name
Test status
Simulation time 8890068805 ps
CPU time 12.28 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204788 kb
Host smart-37da3a51-d3a2-41e3-9540-ffe81b7dbe90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40545
37835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.4054537835
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.274960609
Short name T1045
Test name
Test status
Simulation time 8437216851 ps
CPU time 11.63 seconds
Started May 19 02:01:14 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204872 kb
Host smart-1c4061c7-c6a0-46dd-bbb9-7ddae7fff5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27496
0609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.274960609
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2734219122
Short name T1150
Test name
Test status
Simulation time 8433687018 ps
CPU time 11.09 seconds
Started May 19 02:01:14 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 204816 kb
Host smart-00b1290c-c79f-4dba-b55a-7ff7e5e985a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27342
19122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2734219122
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3679395814
Short name T1279
Test name
Test status
Simulation time 8366489402 ps
CPU time 11.95 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204732 kb
Host smart-e05fa665-ed4d-44ff-9b1b-6d9283b2c2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36793
95814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3679395814
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1369473963
Short name T527
Test name
Test status
Simulation time 8467847547 ps
CPU time 13.8 seconds
Started May 19 02:01:10 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204840 kb
Host smart-26bca95f-656f-4d31-a219-49adc622eb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
73963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1369473963
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2412532069
Short name T370
Test name
Test status
Simulation time 8395788675 ps
CPU time 11.79 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204688 kb
Host smart-7ab97bbf-1b69-428e-b329-510c56a52475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24125
32069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2412532069
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1625633074
Short name T421
Test name
Test status
Simulation time 11529486905 ps
CPU time 13.4 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204780 kb
Host smart-42b021b8-ffb6-498c-b271-739a05625bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
33074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1625633074
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1546796055
Short name T646
Test name
Test status
Simulation time 8425481153 ps
CPU time 11.6 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204824 kb
Host smart-b9d2730e-28a3-421d-a7f4-33ae9cc54feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467
96055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1546796055
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2153503372
Short name T1410
Test name
Test status
Simulation time 8400064590 ps
CPU time 11.37 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 204932 kb
Host smart-3d3118b4-1d1a-4bc6-989b-4b509ff43ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21535
03372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2153503372
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.4272189891
Short name T141
Test name
Test status
Simulation time 8453919965 ps
CPU time 11.19 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204816 kb
Host smart-22b5d02e-0469-4165-a658-926c770a8620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
89891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.4272189891
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2229201402
Short name T779
Test name
Test status
Simulation time 8412600822 ps
CPU time 11.1 seconds
Started May 19 02:01:13 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 204852 kb
Host smart-e70b14fe-b717-4be2-a3b6-e6cc8fa59f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
01402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2229201402
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1550427951
Short name T1535
Test name
Test status
Simulation time 8398147825 ps
CPU time 10.81 seconds
Started May 19 02:01:10 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204800 kb
Host smart-411ac15d-3660-4107-bcf2-ad4a64bc2abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15504
27951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1550427951
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.4126953319
Short name T803
Test name
Test status
Simulation time 8403609639 ps
CPU time 11.74 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204756 kb
Host smart-d769b139-7415-4c4d-8adf-d33c440d0ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
53319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.4126953319
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2642836817
Short name T1510
Test name
Test status
Simulation time 8402537158 ps
CPU time 11.57 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204740 kb
Host smart-9f229b43-8dfb-4680-ba7d-b78fd9278b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26428
36817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2642836817
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.3391562948
Short name T557
Test name
Test status
Simulation time 8437253537 ps
CPU time 11.6 seconds
Started May 19 02:01:12 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204820 kb
Host smart-4f12eb01-423e-4eb1-9cf6-887443877d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
62948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.3391562948
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2959219262
Short name T1663
Test name
Test status
Simulation time 8374450013 ps
CPU time 12.07 seconds
Started May 19 02:01:11 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204800 kb
Host smart-823e0033-4620-4394-a165-f9679655a82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29592
19262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2959219262
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3516289473
Short name T1424
Test name
Test status
Simulation time 8371779554 ps
CPU time 10.74 seconds
Started May 19 02:01:26 PM PDT 24
Finished May 19 02:01:38 PM PDT 24
Peak memory 204808 kb
Host smart-d4f8603d-22ca-4809-910b-c2c69dd3de76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
89473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3516289473
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.284860260
Short name T1104
Test name
Test status
Simulation time 8409128962 ps
CPU time 12.75 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204860 kb
Host smart-2036029c-127f-4a60-9c0a-ece752835679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
0260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.284860260
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2203267528
Short name T536
Test name
Test status
Simulation time 8402075146 ps
CPU time 10.76 seconds
Started May 19 02:01:05 PM PDT 24
Finished May 19 02:01:19 PM PDT 24
Peak memory 204748 kb
Host smart-c10f9167-49a1-49eb-8dfe-2dde88981d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22032
67528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2203267528
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.4171272790
Short name T1284
Test name
Test status
Simulation time 8409887054 ps
CPU time 10.97 seconds
Started May 19 02:01:08 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 205080 kb
Host smart-773b3a82-a964-44ba-aad5-bdc980e3f4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41712
72790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.4171272790
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1702539628
Short name T58
Test name
Test status
Simulation time 150923842 ps
CPU time 1.05 seconds
Started May 19 02:01:14 PM PDT 24
Finished May 19 02:01:16 PM PDT 24
Peak memory 220356 kb
Host smart-5881a29f-d782-4516-8c21-08cd95348340
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1702539628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1702539628
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2920156213
Short name T91
Test name
Test status
Simulation time 8376581027 ps
CPU time 10.61 seconds
Started May 19 02:01:11 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 204804 kb
Host smart-b69c9eaf-25fc-41b8-8428-a5c8eb864f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
56213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2920156213
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1097982442
Short name T852
Test name
Test status
Simulation time 8360185568 ps
CPU time 10.53 seconds
Started May 19 02:01:07 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 204748 kb
Host smart-48a68b7c-b105-4f77-b0ea-29f5b4df5ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10979
82442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1097982442
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3292186394
Short name T1652
Test name
Test status
Simulation time 8463749618 ps
CPU time 11.06 seconds
Started May 19 02:01:09 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 204800 kb
Host smart-7e0169e1-1ebb-43b5-83e8-18cfec46006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32921
86394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3292186394
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1821402070
Short name T1722
Test name
Test status
Simulation time 8417344161 ps
CPU time 10.89 seconds
Started May 19 02:01:06 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 204840 kb
Host smart-627f8218-695b-4612-b5bb-49a2664846cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18214
02070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1821402070
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1173334002
Short name T804
Test name
Test status
Simulation time 8398482059 ps
CPU time 12.35 seconds
Started May 19 02:01:23 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204860 kb
Host smart-d3fc5bb4-d03f-42f8-8b6d-8e029e0ff3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11733
34002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1173334002
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.3824141915
Short name T1589
Test name
Test status
Simulation time 8466511272 ps
CPU time 11.83 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:49 PM PDT 24
Peak memory 204844 kb
Host smart-01c8efd5-5cf0-4d95-a639-5467ce7ede57
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3824141915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.3824141915
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2551598268
Short name T219
Test name
Test status
Simulation time 8387036406 ps
CPU time 11.42 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204668 kb
Host smart-6a82f7cc-37c7-4c2c-af2a-41ee07882ecf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2551598268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2551598268
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3678021010
Short name T836
Test name
Test status
Simulation time 8439771214 ps
CPU time 11.02 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204844 kb
Host smart-b305b182-99b0-436b-962f-b9070c8215a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36780
21010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3678021010
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3676083390
Short name T886
Test name
Test status
Simulation time 8425995605 ps
CPU time 10.93 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:50 PM PDT 24
Peak memory 204752 kb
Host smart-7385846d-0a7d-440a-8342-ebc0705d31fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36760
83390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3676083390
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3966534248
Short name T36
Test name
Test status
Simulation time 8407587647 ps
CPU time 12.1 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204832 kb
Host smart-0d73193d-607d-4744-84dc-94f682d04e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39665
34248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3966534248
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.398249712
Short name T1208
Test name
Test status
Simulation time 8417860765 ps
CPU time 12.95 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204816 kb
Host smart-870ec45e-4bad-4bb5-a22a-22e3d5c036ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
9712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.398249712
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2128537584
Short name T1564
Test name
Test status
Simulation time 8399238762 ps
CPU time 10.44 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204820 kb
Host smart-a28cdd46-7d04-4aca-8a0b-1f997cdd3f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
37584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2128537584
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.245916521
Short name T1751
Test name
Test status
Simulation time 8375226370 ps
CPU time 13.39 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:51 PM PDT 24
Peak memory 204840 kb
Host smart-26e94ab0-7fe2-40fb-b302-a3166b9a24ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24591
6521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.245916521
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3356589178
Short name T591
Test name
Test status
Simulation time 8389778845 ps
CPU time 11.4 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204788 kb
Host smart-1cf8bff7-cf62-4582-a400-217ee1cf7d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
89178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3356589178
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1753597895
Short name T553
Test name
Test status
Simulation time 8467766192 ps
CPU time 11.31 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 205072 kb
Host smart-8f16bd16-e0c7-4fa7-84df-3cd8cf2b2cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
97895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1753597895
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3402921247
Short name T1586
Test name
Test status
Simulation time 8369547958 ps
CPU time 10.93 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:57 PM PDT 24
Peak memory 204760 kb
Host smart-091e22f7-6048-4f55-9a1d-ad98cac91589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34029
21247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3402921247
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1438024017
Short name T1581
Test name
Test status
Simulation time 8432308603 ps
CPU time 12.02 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 205084 kb
Host smart-fc6f3e34-e84e-4e9c-9da4-f03220ca0912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14380
24017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1438024017
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2078533710
Short name T1140
Test name
Test status
Simulation time 8439089844 ps
CPU time 10.85 seconds
Started May 19 02:03:35 PM PDT 24
Finished May 19 02:03:47 PM PDT 24
Peak memory 204864 kb
Host smart-94987979-fa99-4889-af4d-d516c4f5cc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20785
33710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2078533710
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2027881274
Short name T1404
Test name
Test status
Simulation time 11570611310 ps
CPU time 13.94 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204808 kb
Host smart-5b2c7da6-6102-4f0d-ac13-1b497d0e49e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20278
81274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2027881274
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.824983435
Short name T476
Test name
Test status
Simulation time 8414023842 ps
CPU time 13.13 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204820 kb
Host smart-7eb5a5d6-5453-4ab5-b39b-1f61cdaa4116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82498
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.824983435
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.398854187
Short name T623
Test name
Test status
Simulation time 8394094978 ps
CPU time 11.4 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204772 kb
Host smart-ae4425fe-df8f-40c6-82b6-f95a596efc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
4187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.398854187
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3830904027
Short name T145
Test name
Test status
Simulation time 8433329547 ps
CPU time 11.01 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 204800 kb
Host smart-cb786ea9-56c5-40a7-9f83-976a3b6ccc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309
04027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3830904027
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.5575982
Short name T710
Test name
Test status
Simulation time 8415759055 ps
CPU time 11.76 seconds
Started May 19 02:03:35 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 204852 kb
Host smart-bb019f76-21a2-401c-897e-94079eb700d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55759
82 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.5575982
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.4101012034
Short name T1599
Test name
Test status
Simulation time 8369485134 ps
CPU time 11.08 seconds
Started May 19 02:03:30 PM PDT 24
Finished May 19 02:03:42 PM PDT 24
Peak memory 204800 kb
Host smart-c6e73b90-49f2-4d91-98bc-92b1eadd556d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41010
12034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.4101012034
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1846381341
Short name T864
Test name
Test status
Simulation time 8385813173 ps
CPU time 10.17 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 204816 kb
Host smart-a2542db0-bcca-4be4-aaba-747a36ae2bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18463
81341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1846381341
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2433562540
Short name T208
Test name
Test status
Simulation time 8415114992 ps
CPU time 10.35 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204808 kb
Host smart-9022b527-5ccb-43a6-bd0e-8a6b8003bc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24335
62540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2433562540
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.3358662999
Short name T1513
Test name
Test status
Simulation time 8377582051 ps
CPU time 11.91 seconds
Started May 19 02:03:52 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 204808 kb
Host smart-07c8fea7-7f02-41b0-8ff8-b45c7a8ddf48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33586
62999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.3358662999
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.728482324
Short name T474
Test name
Test status
Simulation time 8371106901 ps
CPU time 10.46 seconds
Started May 19 02:03:34 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 204812 kb
Host smart-1bf50ca1-af57-48b6-933c-a309d922ad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72848
2324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.728482324
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1514271002
Short name T1553
Test name
Test status
Simulation time 8381700255 ps
CPU time 11.22 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204752 kb
Host smart-b4fe8318-3009-42db-8bdf-77f5e5b1baed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15142
71002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1514271002
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.816637449
Short name T259
Test name
Test status
Simulation time 15075787868 ps
CPU time 28.47 seconds
Started May 19 02:03:42 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204820 kb
Host smart-f0fd8620-5491-49a1-8953-79b144953838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81663
7449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.816637449
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1233639340
Short name T1216
Test name
Test status
Simulation time 8428318430 ps
CPU time 10.79 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:57 PM PDT 24
Peak memory 204844 kb
Host smart-69e22997-3627-48df-9fd8-c93f6af1acac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12336
39340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1233639340
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.66085256
Short name T1685
Test name
Test status
Simulation time 8387699359 ps
CPU time 11.02 seconds
Started May 19 02:03:40 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204848 kb
Host smart-0019ad0f-4031-4d86-9466-b7567f4f5c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66085
256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.66085256
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2732687787
Short name T819
Test name
Test status
Simulation time 8373943739 ps
CPU time 11.35 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:51 PM PDT 24
Peak memory 204992 kb
Host smart-33bba7a4-7ff4-4f2c-80cf-80b0b5b2104d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27326
87787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2732687787
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.4229717300
Short name T386
Test name
Test status
Simulation time 8368870977 ps
CPU time 12.06 seconds
Started May 19 02:03:32 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 204812 kb
Host smart-c8a3e5a5-f05f-4cb7-bcba-9e076000a27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42297
17300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.4229717300
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.842701502
Short name T721
Test name
Test status
Simulation time 8385912618 ps
CPU time 12.02 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204764 kb
Host smart-ed79b622-2321-44ab-9a8f-00e21afd9e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84270
1502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.842701502
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.718050747
Short name T1211
Test name
Test status
Simulation time 8368229439 ps
CPU time 10.73 seconds
Started May 19 02:03:36 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 204832 kb
Host smart-0cc95746-b5cd-4172-8bac-85f837718cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71805
0747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.718050747
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2745482044
Short name T1052
Test name
Test status
Simulation time 8448288872 ps
CPU time 12.31 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204816 kb
Host smart-c78bcdf3-a214-4ab4-a5a7-ae7dce94c9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27454
82044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2745482044
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2015321755
Short name T306
Test name
Test status
Simulation time 8396438365 ps
CPU time 11.44 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 205052 kb
Host smart-1cea10ae-5ea4-43cd-bac1-0f93a8735fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
21755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2015321755
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2204690955
Short name T298
Test name
Test status
Simulation time 8379681294 ps
CPU time 11.63 seconds
Started May 19 02:03:31 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204844 kb
Host smart-20a23947-1b1c-43be-82b0-4355a98b5da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22046
90955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2204690955
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.889711920
Short name T309
Test name
Test status
Simulation time 8462667959 ps
CPU time 11.33 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204852 kb
Host smart-947e44f0-41ea-4c98-a69d-e88a4eef816d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=889711920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.889711920
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.3433117702
Short name T1157
Test name
Test status
Simulation time 8378253397 ps
CPU time 13.66 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204852 kb
Host smart-77d77fc6-4c11-473c-bad5-93777e5a2277
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3433117702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.3433117702
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.1102203614
Short name T1265
Test name
Test status
Simulation time 8459250105 ps
CPU time 10.81 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:50 PM PDT 24
Peak memory 204856 kb
Host smart-3e0bc37b-29c8-41e5-8032-69683dfaeb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
03614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.1102203614
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.784959687
Short name T1421
Test name
Test status
Simulation time 8375387487 ps
CPU time 11.23 seconds
Started May 19 02:03:32 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204824 kb
Host smart-21038f41-5874-4927-9b2e-8ed6fc28309c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78495
9687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.784959687
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1121685276
Short name T86
Test name
Test status
Simulation time 8407927425 ps
CPU time 11.55 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204820 kb
Host smart-453ca94d-7e9d-4f21-a6fc-30493d996105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
85276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1121685276
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.40620735
Short name T1316
Test name
Test status
Simulation time 8371347437 ps
CPU time 10.92 seconds
Started May 19 02:03:35 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 204836 kb
Host smart-6cd24003-fdf8-4c54-ac9c-6474f6cdb15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40620
735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.40620735
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1756774488
Short name T1341
Test name
Test status
Simulation time 8408310573 ps
CPU time 11.1 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204828 kb
Host smart-464a4a69-b1ae-4f0c-b0aa-eee823937772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17567
74488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1756774488
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1262209080
Short name T894
Test name
Test status
Simulation time 9059971274 ps
CPU time 12.28 seconds
Started May 19 02:03:31 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 204824 kb
Host smart-9659dc80-9515-46af-86c8-f918e4949921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
09080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1262209080
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3201547007
Short name T424
Test name
Test status
Simulation time 8419114927 ps
CPU time 11.74 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:50 PM PDT 24
Peak memory 204628 kb
Host smart-a25841d7-a95f-452c-8dd1-5eff32913df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
47007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3201547007
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2123107344
Short name T330
Test name
Test status
Simulation time 8431363425 ps
CPU time 10.58 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:51 PM PDT 24
Peak memory 204828 kb
Host smart-b4540856-cd62-4cff-810b-2f99db0c53de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21231
07344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2123107344
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.850166179
Short name T508
Test name
Test status
Simulation time 8399086599 ps
CPU time 11.57 seconds
Started May 19 02:04:06 PM PDT 24
Finished May 19 02:04:19 PM PDT 24
Peak memory 204808 kb
Host smart-446b6516-af4d-411f-b36c-dc8aa35d91bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85016
6179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.850166179
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2385564485
Short name T324
Test name
Test status
Simulation time 8457827437 ps
CPU time 12.09 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204868 kb
Host smart-cb9b27f0-4db7-4f5d-8883-2194244b2e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23855
64485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2385564485
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3580334567
Short name T321
Test name
Test status
Simulation time 8390805509 ps
CPU time 12.04 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204808 kb
Host smart-44a4f8b3-6b18-43ca-9fa5-13e79ed45175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35803
34567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3580334567
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3553077859
Short name T1697
Test name
Test status
Simulation time 11554048635 ps
CPU time 14.97 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204856 kb
Host smart-49e32e96-52b5-4855-89f7-25b66304a56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35530
77859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3553077859
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.463353148
Short name T325
Test name
Test status
Simulation time 8414306588 ps
CPU time 12.17 seconds
Started May 19 02:03:40 PM PDT 24
Finished May 19 02:03:55 PM PDT 24
Peak memory 204824 kb
Host smart-7f7b5a75-a49e-4a29-a3f1-d6d68d067c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46335
3148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.463353148
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1040235455
Short name T504
Test name
Test status
Simulation time 8377613690 ps
CPU time 13.16 seconds
Started May 19 02:03:42 PM PDT 24
Finished May 19 02:03:56 PM PDT 24
Peak memory 204816 kb
Host smart-cb403ef7-f1fd-4ec0-ac58-b3574217fd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10402
35455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1040235455
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1810852259
Short name T21
Test name
Test status
Simulation time 8396013590 ps
CPU time 11.11 seconds
Started May 19 02:03:38 PM PDT 24
Finished May 19 02:03:49 PM PDT 24
Peak memory 204812 kb
Host smart-3ab6d184-a563-4d5f-86c8-90c606773769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108
52259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1810852259
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.456322142
Short name T97
Test name
Test status
Simulation time 8416162350 ps
CPU time 13.03 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:56 PM PDT 24
Peak memory 204828 kb
Host smart-f42e7e84-bd2a-455b-b587-beac92c99bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45632
2142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.456322142
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1201324772
Short name T189
Test name
Test status
Simulation time 8402236527 ps
CPU time 10.85 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:51 PM PDT 24
Peak memory 204888 kb
Host smart-97a1a0d9-feb0-48be-bd42-f675b79863d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12013
24772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1201324772
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.2229833600
Short name T636
Test name
Test status
Simulation time 8392678005 ps
CPU time 10.96 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:56 PM PDT 24
Peak memory 204816 kb
Host smart-73d0b6f9-5e0c-436b-976f-9fc734024d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22298
33600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.2229833600
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.89550837
Short name T1490
Test name
Test status
Simulation time 8371232562 ps
CPU time 10.88 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204760 kb
Host smart-1256614e-8f4e-4c0b-80f4-5cb8a87a5862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89550
837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.89550837
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2815487371
Short name T1588
Test name
Test status
Simulation time 8369074055 ps
CPU time 11.38 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204788 kb
Host smart-c61575d0-1847-4941-90f9-a852bb00e92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28154
87371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2815487371
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.672998789
Short name T1745
Test name
Test status
Simulation time 8380265469 ps
CPU time 11.42 seconds
Started May 19 02:03:52 PM PDT 24
Finished May 19 02:04:05 PM PDT 24
Peak memory 204812 kb
Host smart-3a1f4502-d76b-47ae-bf28-26d5ee331fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67299
8789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.672998789
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2822696495
Short name T1556
Test name
Test status
Simulation time 8446250971 ps
CPU time 13.32 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204760 kb
Host smart-49f09bc4-7b69-4108-ab79-6e5f92c38fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28226
96495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2822696495
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3114278961
Short name T1024
Test name
Test status
Simulation time 8393814564 ps
CPU time 11.13 seconds
Started May 19 02:03:46 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204796 kb
Host smart-dd3944a2-12ac-462b-9f84-4cf5a7471d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31142
78961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3114278961
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1148844305
Short name T835
Test name
Test status
Simulation time 8377971387 ps
CPU time 10.93 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204772 kb
Host smart-94d3c9b1-4060-4fd5-8cb8-9dd8bb3ac063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11488
44305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1148844305
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3488248250
Short name T1328
Test name
Test status
Simulation time 8375683920 ps
CPU time 10.78 seconds
Started May 19 02:03:46 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204744 kb
Host smart-ffb413e0-69d2-4631-baee-c74e22e047d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
48250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3488248250
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.735564126
Short name T667
Test name
Test status
Simulation time 8370701764 ps
CPU time 10.9 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 204784 kb
Host smart-1ec94be3-d749-4f91-9140-68208b2490bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73556
4126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.735564126
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2812510716
Short name T914
Test name
Test status
Simulation time 8441201982 ps
CPU time 12.05 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204756 kb
Host smart-5558bb9c-7392-434a-b953-0f3296759f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
10716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2812510716
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.446132033
Short name T891
Test name
Test status
Simulation time 8400800095 ps
CPU time 11.46 seconds
Started May 19 02:03:40 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204876 kb
Host smart-3fc3a219-6cc4-4980-a1c4-4334fda6dea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44613
2033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.446132033
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2945104564
Short name T109
Test name
Test status
Simulation time 8378978435 ps
CPU time 10.6 seconds
Started May 19 02:03:40 PM PDT 24
Finished May 19 02:03:52 PM PDT 24
Peak memory 204856 kb
Host smart-99023d63-eac5-45e0-8f37-36c1bfc7d381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
04564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2945104564
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.4145821729
Short name T657
Test name
Test status
Simulation time 8460939445 ps
CPU time 11.09 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204852 kb
Host smart-50eabbab-ba82-4202-8581-8b00735ffc1e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4145821729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.4145821729
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.3918192153
Short name T1128
Test name
Test status
Simulation time 8396536797 ps
CPU time 11.56 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204868 kb
Host smart-f15066b3-1b0b-4f2e-8ff1-b4aa5201c496
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3918192153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.3918192153
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1483834901
Short name T611
Test name
Test status
Simulation time 8453195823 ps
CPU time 11.05 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204832 kb
Host smart-d333e148-006d-42ba-937a-dfc7dfd9c559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14838
34901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1483834901
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2990121747
Short name T1239
Test name
Test status
Simulation time 8395347862 ps
CPU time 11.07 seconds
Started May 19 02:03:40 PM PDT 24
Finished May 19 02:03:53 PM PDT 24
Peak memory 204776 kb
Host smart-ef9efc98-e5c6-417a-a61a-0f3ea0927574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29901
21747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2990121747
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3090033948
Short name T1181
Test name
Test status
Simulation time 8363536766 ps
CPU time 13.08 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:09 PM PDT 24
Peak memory 204704 kb
Host smart-3e0fdc1d-122e-4f5e-aa3a-69c797a67b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
33948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3090033948
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2412863135
Short name T615
Test name
Test status
Simulation time 8391398431 ps
CPU time 10.91 seconds
Started May 19 02:03:51 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204840 kb
Host smart-fc40716b-d3b1-4d2f-b8e2-0c0ad8614d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
63135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2412863135
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3496873480
Short name T574
Test name
Test status
Simulation time 9208911820 ps
CPU time 13.22 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:05 PM PDT 24
Peak memory 204644 kb
Host smart-fb237700-d015-4105-8baf-25ea46196e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34968
73480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3496873480
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1729948311
Short name T1592
Test name
Test status
Simulation time 8421198140 ps
CPU time 12.95 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204752 kb
Host smart-cc56784b-0574-4d55-9c87-07699b0a1d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17299
48311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1729948311
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4162479941
Short name T1659
Test name
Test status
Simulation time 8465886299 ps
CPU time 10.79 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204832 kb
Host smart-c6e45cb1-2ede-4a15-ac70-5379e9ace587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
79941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4162479941
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1748373988
Short name T1293
Test name
Test status
Simulation time 8374303453 ps
CPU time 11.74 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204840 kb
Host smart-5047ab95-a398-422e-ac96-f21df7ad50c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
73988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1748373988
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1680345709
Short name T1591
Test name
Test status
Simulation time 8405085428 ps
CPU time 11.87 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:05 PM PDT 24
Peak memory 204820 kb
Host smart-9824cbd1-e0ae-4334-bbb8-80a3ae29b60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16803
45709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1680345709
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1325405477
Short name T1730
Test name
Test status
Simulation time 8426633691 ps
CPU time 11.2 seconds
Started May 19 02:03:39 PM PDT 24
Finished May 19 02:03:51 PM PDT 24
Peak memory 204892 kb
Host smart-41c2f014-88d9-4161-8e1e-a1bee38a3181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13254
05477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1325405477
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2449748402
Short name T1077
Test name
Test status
Simulation time 11556824952 ps
CPU time 13.83 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204736 kb
Host smart-2f782782-fc13-49af-8868-bee4f45ca199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
48402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2449748402
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.513864041
Short name T877
Test name
Test status
Simulation time 8437014019 ps
CPU time 11.55 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204824 kb
Host smart-0b0ab914-4495-402e-8c41-1173b49a93cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51386
4041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.513864041
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3950337206
Short name T638
Test name
Test status
Simulation time 8373799442 ps
CPU time 12.31 seconds
Started May 19 02:04:02 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204780 kb
Host smart-6ebf0c47-251b-49de-924a-ee8492b0db51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39503
37206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3950337206
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1238601883
Short name T129
Test name
Test status
Simulation time 8408251216 ps
CPU time 12.47 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204888 kb
Host smart-cb0076b3-5704-4879-a4ec-c4e759fc5273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12386
01883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1238601883
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2701956647
Short name T1223
Test name
Test status
Simulation time 8426652050 ps
CPU time 11.36 seconds
Started May 19 02:03:46 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204816 kb
Host smart-0bff328b-76fc-4ff3-a724-9b4705c2e9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019
56647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2701956647
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.4075419074
Short name T449
Test name
Test status
Simulation time 8413629917 ps
CPU time 10.85 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204844 kb
Host smart-904cfb2e-f7fb-43ca-98ff-aa23c3680c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40754
19074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.4075419074
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1933140372
Short name T84
Test name
Test status
Simulation time 8377799151 ps
CPU time 10.65 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204808 kb
Host smart-cdbdc7eb-3a4f-471b-b78e-ca915a48109f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19331
40372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1933140372
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2550309578
Short name T186
Test name
Test status
Simulation time 8401172262 ps
CPU time 11.32 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204848 kb
Host smart-95448717-464a-41dc-8b60-6f63a49e588d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503
09578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2550309578
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.3654855906
Short name T1285
Test name
Test status
Simulation time 8410598820 ps
CPU time 11.94 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204820 kb
Host smart-addeee56-52c6-4d4f-a249-5f2a8aa1caeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36548
55906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.3654855906
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2001013268
Short name T1623
Test name
Test status
Simulation time 8363936507 ps
CPU time 11.29 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204784 kb
Host smart-1628aa83-8e35-4867-a461-319feed74eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20010
13268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2001013268
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.72457770
Short name T459
Test name
Test status
Simulation time 8365766013 ps
CPU time 11.37 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204788 kb
Host smart-ab5c5d2e-4c87-4d1d-b1af-5ed2d8ecb03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72457
770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.72457770
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2226200454
Short name T1677
Test name
Test status
Simulation time 14652356981 ps
CPU time 24.87 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204808 kb
Host smart-aa82a2da-e219-42b7-9e9a-e53a9adb41e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22262
00454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2226200454
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3052027050
Short name T790
Test name
Test status
Simulation time 8409321973 ps
CPU time 10.7 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204836 kb
Host smart-bb363eb9-05ca-4ded-86c7-beb8b42d4ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30520
27050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3052027050
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.574397524
Short name T17
Test name
Test status
Simulation time 8391527687 ps
CPU time 10.27 seconds
Started May 19 02:03:42 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204760 kb
Host smart-3fc40c0e-8067-44a8-9b2f-e3da400055a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57439
7524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.574397524
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3113698435
Short name T841
Test name
Test status
Simulation time 8408102405 ps
CPU time 13.31 seconds
Started May 19 02:03:40 PM PDT 24
Finished May 19 02:03:55 PM PDT 24
Peak memory 204832 kb
Host smart-8028fdc2-aa2d-44e3-83ee-78d6d7170b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31136
98435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3113698435
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2065070039
Short name T689
Test name
Test status
Simulation time 8370938339 ps
CPU time 10.44 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204780 kb
Host smart-097d2518-ef19-4166-9978-624e1daf1b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20650
70039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2065070039
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.703785716
Short name T343
Test name
Test status
Simulation time 8367961476 ps
CPU time 10.82 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204784 kb
Host smart-1889f30c-1281-4ee6-ac3f-8338b5f0a48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70378
5716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.703785716
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1149731509
Short name T605
Test name
Test status
Simulation time 8369547230 ps
CPU time 11.57 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204768 kb
Host smart-47beaede-7ca9-479d-b7fc-6050e79c7238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
31509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1149731509
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2336800715
Short name T632
Test name
Test status
Simulation time 8440458624 ps
CPU time 10.62 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 204732 kb
Host smart-3f68a4e5-77e0-4b7f-bcc7-bfafd1408a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23368
00715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2336800715
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1721874353
Short name T1332
Test name
Test status
Simulation time 8401327983 ps
CPU time 11.93 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:55 PM PDT 24
Peak memory 204848 kb
Host smart-1a68168e-050a-49fc-b798-ad435e38d85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
74353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1721874353
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.675700289
Short name T1674
Test name
Test status
Simulation time 8415156518 ps
CPU time 11.66 seconds
Started May 19 02:03:41 PM PDT 24
Finished May 19 02:03:55 PM PDT 24
Peak memory 204828 kb
Host smart-83520aee-6e75-411d-83f9-d44cdb8fac1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67570
0289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.675700289
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3322887773
Short name T543
Test name
Test status
Simulation time 8464399973 ps
CPU time 11.28 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204788 kb
Host smart-6eb77ba7-687a-4a0c-9fa3-689e724d40cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3322887773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3322887773
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.2156413281
Short name T1258
Test name
Test status
Simulation time 8389847696 ps
CPU time 11.73 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204844 kb
Host smart-ed42b052-327d-495d-9b68-7c14024c35f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2156413281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.2156413281
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.1621758858
Short name T1378
Test name
Test status
Simulation time 8418194561 ps
CPU time 10.73 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204860 kb
Host smart-caff0865-ae49-40cd-b029-03b1d7275693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16217
58858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.1621758858
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.877947028
Short name T1141
Test name
Test status
Simulation time 8395782431 ps
CPU time 13.73 seconds
Started May 19 02:03:53 PM PDT 24
Finished May 19 02:04:10 PM PDT 24
Peak memory 204844 kb
Host smart-ece42484-15b9-4f13-9e61-04f7353bed9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87794
7028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.877947028
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2648616429
Short name T182
Test name
Test status
Simulation time 9374812294 ps
CPU time 15.19 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 205080 kb
Host smart-3b093667-0ef6-4c59-ae23-5b964389c7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26486
16429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2648616429
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2937093814
Short name T1063
Test name
Test status
Simulation time 8389963003 ps
CPU time 10.94 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204780 kb
Host smart-1e07af3b-8849-4746-924f-ff067724b5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29370
93814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2937093814
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.4255321343
Short name T680
Test name
Test status
Simulation time 8384885073 ps
CPU time 10.89 seconds
Started May 19 02:03:53 PM PDT 24
Finished May 19 02:04:06 PM PDT 24
Peak memory 204832 kb
Host smart-588150e0-9684-4c7f-bb59-d43991c318b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42553
21343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.4255321343
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2246986335
Short name T1516
Test name
Test status
Simulation time 9066663879 ps
CPU time 14.76 seconds
Started May 19 02:03:55 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204748 kb
Host smart-3f2c5303-fe15-4e2b-9851-95440ae690df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
86335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2246986335
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2426793339
Short name T1272
Test name
Test status
Simulation time 8442614900 ps
CPU time 13.39 seconds
Started May 19 02:03:42 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204792 kb
Host smart-652cf187-8737-46da-8e68-73b082a6c7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267
93339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2426793339
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.12077115
Short name T832
Test name
Test status
Simulation time 8438032669 ps
CPU time 11.6 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204820 kb
Host smart-7c325c21-d148-4c7f-9615-23710fa29b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.12077115
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1831591148
Short name T1430
Test name
Test status
Simulation time 8367763663 ps
CPU time 13.15 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:05 PM PDT 24
Peak memory 204756 kb
Host smart-2ec40429-b6c2-4ad2-b2f4-29e619680241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18315
91148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1831591148
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3423201881
Short name T1127
Test name
Test status
Simulation time 8430240787 ps
CPU time 12.77 seconds
Started May 19 02:03:43 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204744 kb
Host smart-81bf8407-ace1-4e6e-9da5-a6459de0001c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232
01881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3423201881
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2987132444
Short name T379
Test name
Test status
Simulation time 8420493881 ps
CPU time 10.53 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204756 kb
Host smart-bfeab6d0-e8ae-42f7-bdca-05e178b38ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29871
32444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2987132444
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2284741607
Short name T1149
Test name
Test status
Simulation time 11572961709 ps
CPU time 14.88 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204788 kb
Host smart-3846bfe9-6f95-4d89-b1ac-e3ef82a02693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
41607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2284741607
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2013734087
Short name T1539
Test name
Test status
Simulation time 8453241691 ps
CPU time 13.05 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:19 PM PDT 24
Peak memory 204816 kb
Host smart-dbe23511-f5c3-4be0-83c1-62a1cfd6a2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137
34087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2013734087
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3312530397
Short name T581
Test name
Test status
Simulation time 8366758900 ps
CPU time 12.81 seconds
Started May 19 02:04:02 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204804 kb
Host smart-c30d4727-0048-4932-aae7-b3bc7c72c2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
30397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3312530397
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.986072795
Short name T1234
Test name
Test status
Simulation time 8386880118 ps
CPU time 10.92 seconds
Started May 19 02:04:09 PM PDT 24
Finished May 19 02:04:21 PM PDT 24
Peak memory 204828 kb
Host smart-d6dd8563-78d9-4b15-8420-67546f40d747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98607
2795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.986072795
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1131774597
Short name T626
Test name
Test status
Simulation time 8420199102 ps
CPU time 11.47 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204848 kb
Host smart-9609b442-5a9d-487f-ab74-2109ff510649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11317
74597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1131774597
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1168524310
Short name T738
Test name
Test status
Simulation time 8403462847 ps
CPU time 11.27 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204868 kb
Host smart-8c5b2270-2fe8-4798-a1cb-29a73273d1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11685
24310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1168524310
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.4229089296
Short name T1121
Test name
Test status
Simulation time 8398557242 ps
CPU time 10.95 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204788 kb
Host smart-9f808634-2e1e-43b0-b643-99d9a67575bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42290
89296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.4229089296
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2270552958
Short name T748
Test name
Test status
Simulation time 8377695713 ps
CPU time 12.95 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204796 kb
Host smart-70f522e6-7b9b-41fa-810b-139dc1f0db80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22705
52958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2270552958
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.1312781908
Short name T698
Test name
Test status
Simulation time 8409859794 ps
CPU time 11.29 seconds
Started May 19 02:03:46 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204792 kb
Host smart-13c59ac5-4e71-4d6a-9899-157e2e627325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13127
81908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.1312781908
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1161057133
Short name T1743
Test name
Test status
Simulation time 8386145320 ps
CPU time 10.91 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204792 kb
Host smart-a69fdc78-dd91-479a-8d84-f46c90dc5d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11610
57133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1161057133
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1252883615
Short name T1241
Test name
Test status
Simulation time 8365387126 ps
CPU time 11.48 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204824 kb
Host smart-c7878a21-5521-4b5e-96fa-3ae025655f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12528
83615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1252883615
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1652003572
Short name T1629
Test name
Test status
Simulation time 29187837703 ps
CPU time 58.44 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204804 kb
Host smart-710cc004-3028-41c1-a0b8-c3da34add9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520
03572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1652003572
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3662785190
Short name T1273
Test name
Test status
Simulation time 8399573740 ps
CPU time 10.82 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204728 kb
Host smart-d2f1d271-afb1-448b-a1ea-0baeb1091f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36627
85190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3662785190
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1283834554
Short name T1473
Test name
Test status
Simulation time 8416276110 ps
CPU time 11.2 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204820 kb
Host smart-e1392342-5d41-487a-a4e3-0549b85f7918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
34554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1283834554
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1656526651
Short name T1749
Test name
Test status
Simulation time 8423732391 ps
CPU time 13.21 seconds
Started May 19 02:03:53 PM PDT 24
Finished May 19 02:04:09 PM PDT 24
Peak memory 204764 kb
Host smart-8e15007e-fa20-4273-9fb8-cafa2783357d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16565
26651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1656526651
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.640000969
Short name T670
Test name
Test status
Simulation time 8365795219 ps
CPU time 10.58 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204804 kb
Host smart-5738f4da-f704-41f3-a4db-e98460c8c254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64000
0969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.640000969
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1390646492
Short name T570
Test name
Test status
Simulation time 8387840491 ps
CPU time 12.96 seconds
Started May 19 02:03:55 PM PDT 24
Finished May 19 02:04:10 PM PDT 24
Peak memory 204836 kb
Host smart-be461b69-34c6-4ffb-bafc-16c42d1c224e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
46492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1390646492
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1213517317
Short name T485
Test name
Test status
Simulation time 8400760102 ps
CPU time 12.87 seconds
Started May 19 02:03:46 PM PDT 24
Finished May 19 02:04:02 PM PDT 24
Peak memory 204832 kb
Host smart-ba15a723-7380-41b2-af97-62ed093139ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12135
17317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1213517317
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1558087407
Short name T1538
Test name
Test status
Simulation time 8444992461 ps
CPU time 10.88 seconds
Started May 19 02:03:56 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204780 kb
Host smart-92b0f951-d0c3-4285-ae47-bf66dbb45245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
87407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1558087407
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3592951564
Short name T807
Test name
Test status
Simulation time 8387742660 ps
CPU time 10.91 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204752 kb
Host smart-7a537a1c-25fe-4fcc-935d-0b1a9e300a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
51564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3592951564
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.106302678
Short name T1739
Test name
Test status
Simulation time 8414570962 ps
CPU time 11.42 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204800 kb
Host smart-0ea7d734-85e9-40c8-af11-f696f806d892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
2678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.106302678
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.1713907407
Short name T1246
Test name
Test status
Simulation time 8461330052 ps
CPU time 10.98 seconds
Started May 19 02:03:55 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204780 kb
Host smart-426c4088-9bb7-4dd5-8012-28e5d06b7dd3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1713907407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.1713907407
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.851436790
Short name T1412
Test name
Test status
Simulation time 8383988233 ps
CPU time 11.18 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204872 kb
Host smart-87580388-dcc8-480e-896e-9fb716a4c952
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=851436790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.851436790
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.4235651694
Short name T1732
Test name
Test status
Simulation time 8433053156 ps
CPU time 11.67 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204732 kb
Host smart-446b29da-4822-4a65-9c0d-659a43f3d1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42356
51694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.4235651694
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.4087382830
Short name T889
Test name
Test status
Simulation time 8401341172 ps
CPU time 11.37 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204804 kb
Host smart-48a366bf-bbbb-4df1-9a5d-edcb75071666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873
82830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.4087382830
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2943434155
Short name T48
Test name
Test status
Simulation time 9497320250 ps
CPU time 12.48 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204856 kb
Host smart-e9169de5-5780-4172-8052-c0932eed3f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
34155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2943434155
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.944715277
Short name T737
Test name
Test status
Simulation time 8372091543 ps
CPU time 11.12 seconds
Started May 19 02:04:14 PM PDT 24
Finished May 19 02:04:25 PM PDT 24
Peak memory 204760 kb
Host smart-a410503a-ee20-4c92-a9ab-4ace3da527ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94471
5277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.944715277
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3009818294
Short name T277
Test name
Test status
Simulation time 8392715513 ps
CPU time 11.17 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:05 PM PDT 24
Peak memory 204756 kb
Host smart-32bc70cf-fec5-4951-a73b-2cb82a045fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30098
18294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3009818294
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3726962937
Short name T766
Test name
Test status
Simulation time 9080762215 ps
CPU time 13.68 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:05 PM PDT 24
Peak memory 204824 kb
Host smart-9e2a14b0-59ff-4f63-827b-d296523317a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37269
62937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3726962937
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2040499492
Short name T1162
Test name
Test status
Simulation time 8618233645 ps
CPU time 14.9 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204816 kb
Host smart-974bbf2f-cf48-4567-80cb-6a96373ef1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404
99492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2040499492
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2420275591
Short name T1210
Test name
Test status
Simulation time 8418931321 ps
CPU time 11.53 seconds
Started May 19 02:04:19 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204824 kb
Host smart-a1345d33-2c51-40cc-ae1b-e80d2da773c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
75591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2420275591
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2484186515
Short name T410
Test name
Test status
Simulation time 8366125438 ps
CPU time 11.58 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204652 kb
Host smart-ecd050be-fb94-4aa6-af74-aad474e8bc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24841
86515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2484186515
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2601092599
Short name T1169
Test name
Test status
Simulation time 8413583570 ps
CPU time 11 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204664 kb
Host smart-335673aa-9e99-4d89-9c5e-6de84183af17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26010
92599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2601092599
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3607297122
Short name T861
Test name
Test status
Simulation time 8433376286 ps
CPU time 11.08 seconds
Started May 19 02:03:53 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 204720 kb
Host smart-47dd7a7e-44d2-4556-844f-21ff3ccc0a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
97122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3607297122
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.262225076
Short name T1570
Test name
Test status
Simulation time 11625016717 ps
CPU time 13.91 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204832 kb
Host smart-8afb06b8-e641-452c-96af-5f6e8dc6eda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
5076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.262225076
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2416523603
Short name T1487
Test name
Test status
Simulation time 8433543112 ps
CPU time 11.84 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204804 kb
Host smart-de1e60bc-aefc-47cf-8cda-890264b4a9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24165
23603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2416523603
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3471777267
Short name T759
Test name
Test status
Simulation time 8374840687 ps
CPU time 10.64 seconds
Started May 19 02:04:03 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204772 kb
Host smart-4087a71d-c090-4774-968a-76814bc9c929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
77267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3471777267
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3723153109
Short name T1651
Test name
Test status
Simulation time 8438979720 ps
CPU time 11.29 seconds
Started May 19 02:04:02 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204684 kb
Host smart-b28c45d3-2ec9-4398-902a-ce9534ca6b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37231
53109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3723153109
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2791332334
Short name T770
Test name
Test status
Simulation time 8423424169 ps
CPU time 11.41 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204876 kb
Host smart-2b2fd1c1-9084-4886-a86d-f209bc47a209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27913
32334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2791332334
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.657840945
Short name T604
Test name
Test status
Simulation time 8399798046 ps
CPU time 11.05 seconds
Started May 19 02:04:08 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204760 kb
Host smart-db78d975-1f9f-4348-9d64-dd4fed3816c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65784
0945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.657840945
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3573730207
Short name T1043
Test name
Test status
Simulation time 8460118776 ps
CPU time 11.25 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204824 kb
Host smart-7d6f90bf-9915-495e-9ff2-d1ae0976d1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35737
30207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3573730207
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.2734946012
Short name T823
Test name
Test status
Simulation time 8394852849 ps
CPU time 12.73 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:09 PM PDT 24
Peak memory 205032 kb
Host smart-89062fc5-06fe-4458-9278-3f0a8e189ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27349
46012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.2734946012
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.80898672
Short name T1307
Test name
Test status
Simulation time 8371303014 ps
CPU time 11.86 seconds
Started May 19 02:04:02 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 205008 kb
Host smart-ce1184b9-2c08-44f6-b148-0da36951bce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80898
672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.80898672
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.975551813
Short name T883
Test name
Test status
Simulation time 8364208005 ps
CPU time 10.81 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204744 kb
Host smart-69d2035a-c830-438c-9748-e0e550a89f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97555
1813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.975551813
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1392113659
Short name T78
Test name
Test status
Simulation time 16703659686 ps
CPU time 33.49 seconds
Started May 19 02:04:11 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204788 kb
Host smart-435dd2a0-8d86-4240-91da-ae52c1c7cf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
13659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1392113659
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3081673686
Short name T616
Test name
Test status
Simulation time 8416669556 ps
CPU time 10.5 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204700 kb
Host smart-111ab802-bb9b-4c3f-8965-05245a806d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30816
73686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3081673686
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.135975887
Short name T950
Test name
Test status
Simulation time 8451072309 ps
CPU time 11.45 seconds
Started May 19 02:03:52 PM PDT 24
Finished May 19 02:04:06 PM PDT 24
Peak memory 204832 kb
Host smart-cafe8354-a219-46f7-a0ed-94f2648b3f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13597
5887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.135975887
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2053983847
Short name T372
Test name
Test status
Simulation time 8405024226 ps
CPU time 10.61 seconds
Started May 19 02:03:55 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204792 kb
Host smart-74c76abf-46ae-46de-8ba3-f900fa2f45a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539
83847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2053983847
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.4270590714
Short name T1562
Test name
Test status
Simulation time 8382712576 ps
CPU time 12.33 seconds
Started May 19 02:03:56 PM PDT 24
Finished May 19 02:04:10 PM PDT 24
Peak memory 204784 kb
Host smart-542ec838-9c19-442c-8670-b81dce7ed1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
90714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.4270590714
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2867498391
Short name T718
Test name
Test status
Simulation time 8379370916 ps
CPU time 11.58 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204764 kb
Host smart-154535ca-071f-4ad8-a6a7-9d0d9ad1ce17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28674
98391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2867498391
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2528398286
Short name T1320
Test name
Test status
Simulation time 8367093176 ps
CPU time 11.93 seconds
Started May 19 02:03:58 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204760 kb
Host smart-6b54507e-a5c3-44d8-8eb2-ce2b2e663363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25283
98286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2528398286
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1523335051
Short name T1590
Test name
Test status
Simulation time 8455101044 ps
CPU time 11.31 seconds
Started May 19 02:03:52 PM PDT 24
Finished May 19 02:04:06 PM PDT 24
Peak memory 204720 kb
Host smart-7a2e3bcf-a650-4c0f-a832-4ff703c66a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
35051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1523335051
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3502822507
Short name T941
Test name
Test status
Simulation time 8385441861 ps
CPU time 10.86 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:58 PM PDT 24
Peak memory 204796 kb
Host smart-4782ba99-7ac9-4e4d-8c56-eb71d08f2ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35028
22507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3502822507
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1740095574
Short name T1402
Test name
Test status
Simulation time 8458891943 ps
CPU time 10.46 seconds
Started May 19 02:04:09 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204816 kb
Host smart-3cf96db5-66a2-40ca-bf16-24b08f64ce24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17400
95574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1740095574
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.4282764281
Short name T525
Test name
Test status
Simulation time 8471251236 ps
CPU time 10.95 seconds
Started May 19 02:04:15 PM PDT 24
Finished May 19 02:04:27 PM PDT 24
Peak memory 204860 kb
Host smart-02467cb9-9fe5-4ecd-96b6-f61ff763fe48
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4282764281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.4282764281
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2347402033
Short name T1527
Test name
Test status
Simulation time 8392724487 ps
CPU time 11.31 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204844 kb
Host smart-2e46f91a-23c2-460c-9155-f07ef845df45
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2347402033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2347402033
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3605114192
Short name T344
Test name
Test status
Simulation time 8396942020 ps
CPU time 10.96 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204816 kb
Host smart-2e8d22c6-0b7b-4dd7-8536-a964c08b302a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
14192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3605114192
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1794532956
Short name T1541
Test name
Test status
Simulation time 8395397401 ps
CPU time 11.16 seconds
Started May 19 02:04:14 PM PDT 24
Finished May 19 02:04:26 PM PDT 24
Peak memory 204832 kb
Host smart-70787733-32f7-45bb-9215-36ee99228713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
32956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1794532956
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1285422652
Short name T195
Test name
Test status
Simulation time 9356166127 ps
CPU time 15.32 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:22 PM PDT 24
Peak memory 204816 kb
Host smart-be88d4cb-bf1c-4714-9075-3e1d00d431d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12854
22652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1285422652
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.954755287
Short name T936
Test name
Test status
Simulation time 8376046239 ps
CPU time 10.58 seconds
Started May 19 02:03:53 PM PDT 24
Finished May 19 02:04:06 PM PDT 24
Peak memory 204744 kb
Host smart-3024ddc3-2c0e-46e1-a54a-c3396a1856aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95475
5287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.954755287
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.822033828
Short name T956
Test name
Test status
Simulation time 8376110308 ps
CPU time 11.23 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204792 kb
Host smart-e747aa4c-3e11-4f71-92b7-2eb988841df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82203
3828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.822033828
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3109588610
Short name T1440
Test name
Test status
Simulation time 9053578908 ps
CPU time 14.42 seconds
Started May 19 02:03:44 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204752 kb
Host smart-e2c67d7b-8d21-4e5a-acae-492df09aa917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31095
88610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3109588610
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.515241770
Short name T1664
Test name
Test status
Simulation time 8452691562 ps
CPU time 13.57 seconds
Started May 19 02:03:51 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 204768 kb
Host smart-570a9c5e-4bf1-4348-9644-83670e9470a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51524
1770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.515241770
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2109815401
Short name T1224
Test name
Test status
Simulation time 8397564169 ps
CPU time 11.29 seconds
Started May 19 02:04:08 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204860 kb
Host smart-09271a57-0815-4d92-a276-779af8888951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21098
15401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2109815401
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2427836788
Short name T723
Test name
Test status
Simulation time 8384119146 ps
CPU time 10.76 seconds
Started May 19 02:04:12 PM PDT 24
Finished May 19 02:04:23 PM PDT 24
Peak memory 204708 kb
Host smart-26147955-2f58-4e02-9733-047022f3e123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
36788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2427836788
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2176272366
Short name T1469
Test name
Test status
Simulation time 8428240263 ps
CPU time 11.06 seconds
Started May 19 02:04:03 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204848 kb
Host smart-41897c90-a70a-4f5b-b7e1-ed2315b8b994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
72366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2176272366
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3178217529
Short name T1706
Test name
Test status
Simulation time 8442792658 ps
CPU time 11.96 seconds
Started May 19 02:03:51 PM PDT 24
Finished May 19 02:04:06 PM PDT 24
Peak memory 204800 kb
Host smart-4d566d33-29db-4e71-b63e-09dc2e82dc06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31782
17529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3178217529
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3975314322
Short name T878
Test name
Test status
Simulation time 11536437057 ps
CPU time 15.07 seconds
Started May 19 02:03:54 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204776 kb
Host smart-8b5ef32f-ec46-498e-9c26-7e4e01c78716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39753
14322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3975314322
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3177087035
Short name T793
Test name
Test status
Simulation time 8456798922 ps
CPU time 11.27 seconds
Started May 19 02:03:45 PM PDT 24
Finished May 19 02:03:59 PM PDT 24
Peak memory 204752 kb
Host smart-41db7e22-6ddc-4d0c-a884-9495b255be2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31770
87035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3177087035
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1185530938
Short name T692
Test name
Test status
Simulation time 8374953632 ps
CPU time 10.99 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204664 kb
Host smart-3362aa00-babb-488f-bcdc-0e0d3bbae2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11855
30938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1185530938
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1879724498
Short name T147
Test name
Test status
Simulation time 8432738920 ps
CPU time 11.03 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204836 kb
Host smart-1efb94c7-399b-49bd-bef9-020e7f9d7c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
24498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1879724498
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3831924078
Short name T722
Test name
Test status
Simulation time 8419334909 ps
CPU time 10.61 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:29 PM PDT 24
Peak memory 204852 kb
Host smart-86995473-6b94-4d4d-99cf-ce7aa28e4f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
24078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3831924078
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.872151652
Short name T1025
Test name
Test status
Simulation time 8394833729 ps
CPU time 12.15 seconds
Started May 19 02:04:18 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204776 kb
Host smart-0dced996-7b86-4a34-9085-5137abff1b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87215
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.872151652
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2318774872
Short name T1093
Test name
Test status
Simulation time 8407035229 ps
CPU time 11.63 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204848 kb
Host smart-ea19edba-f259-474d-8f9c-8fc29c5fbc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23187
74872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2318774872
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1141884162
Short name T1504
Test name
Test status
Simulation time 8391977005 ps
CPU time 12.06 seconds
Started May 19 02:03:49 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204904 kb
Host smart-f4125786-90ba-4ea2-978b-4dbe87ac5a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11418
84162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1141884162
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.262553584
Short name T1462
Test name
Test status
Simulation time 8396671387 ps
CPU time 10.72 seconds
Started May 19 02:04:18 PM PDT 24
Finished May 19 02:04:32 PM PDT 24
Peak memory 204780 kb
Host smart-0086e30e-14d4-4b11-85c4-4c099579a4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.262553584
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3852845565
Short name T631
Test name
Test status
Simulation time 8366858066 ps
CPU time 10.67 seconds
Started May 19 02:03:58 PM PDT 24
Finished May 19 02:04:10 PM PDT 24
Peak memory 204760 kb
Host smart-c9fcb7dd-db87-4841-a287-6b4ee494279e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38528
45565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3852845565
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1158555865
Short name T1278
Test name
Test status
Simulation time 8425045497 ps
CPU time 11.9 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204772 kb
Host smart-a0367268-a0f5-473d-ae9c-477e1c312f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11585
55865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1158555865
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2514404779
Short name T1018
Test name
Test status
Simulation time 16057967109 ps
CPU time 28.94 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:46 PM PDT 24
Peak memory 204788 kb
Host smart-533652fa-7fa7-4fa3-b05d-1964dbae1c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25144
04779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2514404779
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4117866746
Short name T382
Test name
Test status
Simulation time 8384305467 ps
CPU time 13.02 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204832 kb
Host smart-614bcdb5-2f89-4e18-b3ac-08a2e2391239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41178
66746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4117866746
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1943263898
Short name T867
Test name
Test status
Simulation time 8446882849 ps
CPU time 11.45 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:15 PM PDT 24
Peak memory 204856 kb
Host smart-8f3b4d9b-4f7f-4b3a-9345-eccbf5212f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19432
63898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1943263898
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2424032659
Short name T1682
Test name
Test status
Simulation time 8425010468 ps
CPU time 11.47 seconds
Started May 19 02:04:09 PM PDT 24
Finished May 19 02:04:22 PM PDT 24
Peak memory 204752 kb
Host smart-de0d9b3b-2ec9-40df-bbe2-84574bf21755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24240
32659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2424032659
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.964801007
Short name T505
Test name
Test status
Simulation time 8369773240 ps
CPU time 10.67 seconds
Started May 19 02:04:03 PM PDT 24
Finished May 19 02:04:15 PM PDT 24
Peak memory 204792 kb
Host smart-97fd65aa-d682-4f51-9d2d-ee38632e6ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96480
1007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.964801007
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2047980310
Short name T1290
Test name
Test status
Simulation time 8392749073 ps
CPU time 11.09 seconds
Started May 19 02:03:57 PM PDT 24
Finished May 19 02:04:09 PM PDT 24
Peak memory 204688 kb
Host smart-5a90eed8-1215-4bde-b06f-3330a2d2eaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479
80310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2047980310
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1903041199
Short name T1303
Test name
Test status
Simulation time 8367786112 ps
CPU time 11.77 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204836 kb
Host smart-724559ea-2ee7-4a6e-a23f-e9f0e3d64aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19030
41199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1903041199
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3594614885
Short name T1480
Test name
Test status
Simulation time 8404527376 ps
CPU time 11.2 seconds
Started May 19 02:03:46 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 204840 kb
Host smart-2fdff9da-133a-4f27-8ddf-e4560f6062a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
14885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3594614885
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3654223026
Short name T417
Test name
Test status
Simulation time 8407244087 ps
CPU time 11.67 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204836 kb
Host smart-acbc3909-b720-4199-96ca-bb5f6393e5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
23026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3654223026
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3665797477
Short name T1397
Test name
Test status
Simulation time 8405025778 ps
CPU time 10.59 seconds
Started May 19 02:04:12 PM PDT 24
Finished May 19 02:04:23 PM PDT 24
Peak memory 204780 kb
Host smart-895ed133-09ec-4aaf-ac4e-6351bcbcca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36657
97477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3665797477
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.212027756
Short name T308
Test name
Test status
Simulation time 8469031822 ps
CPU time 10.98 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204900 kb
Host smart-2c04f3cf-0a21-45a3-982e-1e0697b0d3ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=212027756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.212027756
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.1309886187
Short name T1463
Test name
Test status
Simulation time 8388115956 ps
CPU time 10.89 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204800 kb
Host smart-88e4f831-4d0e-4ccd-b44b-c6e98edaad3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1309886187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.1309886187
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.184566961
Short name T1595
Test name
Test status
Simulation time 8403766819 ps
CPU time 10.92 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204776 kb
Host smart-b6759caf-1451-47e4-8516-2e0b49c84c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18456
6961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.184566961
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.568757524
Short name T777
Test name
Test status
Simulation time 8379150902 ps
CPU time 12.79 seconds
Started May 19 02:04:09 PM PDT 24
Finished May 19 02:04:22 PM PDT 24
Peak memory 204832 kb
Host smart-7134f6ac-5173-4b70-8b64-780c920daf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56875
7524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.568757524
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1571588576
Short name T98
Test name
Test status
Simulation time 8412899934 ps
CPU time 11.62 seconds
Started May 19 02:03:53 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 204760 kb
Host smart-536862b4-73e4-43ae-9a0a-b90794fe5bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715
88576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1571588576
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1899010834
Short name T1366
Test name
Test status
Simulation time 8660963633 ps
CPU time 11.57 seconds
Started May 19 02:04:03 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204816 kb
Host smart-8f3e3d09-0620-4c96-bbb6-361e006ce658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
10834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1899010834
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3775711815
Short name T419
Test name
Test status
Simulation time 8427632799 ps
CPU time 13.04 seconds
Started May 19 02:04:07 PM PDT 24
Finished May 19 02:04:21 PM PDT 24
Peak memory 204716 kb
Host smart-68321c71-4ea3-4c6f-a150-6f2ec17d3316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
11815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3775711815
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3143227045
Short name T892
Test name
Test status
Simulation time 8387110503 ps
CPU time 10.84 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:39 PM PDT 24
Peak memory 204836 kb
Host smart-3d94f132-a07e-43fb-a37f-f3be4f4c9269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
27045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3143227045
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2157308807
Short name T376
Test name
Test status
Simulation time 9140457979 ps
CPU time 12.16 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 204836 kb
Host smart-f5cbcca9-d3cc-4751-87f1-8fd7a7b912f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21573
08807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2157308807
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2135381723
Short name T1191
Test name
Test status
Simulation time 8527209051 ps
CPU time 12.73 seconds
Started May 19 02:04:07 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204852 kb
Host smart-4f60b3aa-7fb6-43cc-b9c7-1aa14d121e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21353
81723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2135381723
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3203973838
Short name T1615
Test name
Test status
Simulation time 8442806875 ps
CPU time 11.4 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204876 kb
Host smart-20e3b33c-1caa-44c6-bc6e-1ef0cd16a823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32039
73838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3203973838
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3468501256
Short name T1647
Test name
Test status
Simulation time 8390390598 ps
CPU time 11.27 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204836 kb
Host smart-9c387707-ccea-408e-aa9e-43f1c94909b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34685
01256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3468501256
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1327505690
Short name T602
Test name
Test status
Simulation time 8440671608 ps
CPU time 11.33 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204832 kb
Host smart-0ee2fab8-c49a-426c-87f7-033d94688c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13275
05690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1327505690
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.586074859
Short name T690
Test name
Test status
Simulation time 11498788619 ps
CPU time 12.97 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204780 kb
Host smart-13583dd1-6bc9-4172-a908-d96149e76635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58607
4859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.586074859
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2052106577
Short name T679
Test name
Test status
Simulation time 8470511589 ps
CPU time 10.72 seconds
Started May 19 02:03:56 PM PDT 24
Finished May 19 02:04:09 PM PDT 24
Peak memory 204792 kb
Host smart-3fc443f6-1e59-4446-bfb8-7af088e5d2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20521
06577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2052106577
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2566950673
Short name T586
Test name
Test status
Simulation time 8373835476 ps
CPU time 10.7 seconds
Started May 19 02:04:17 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 204764 kb
Host smart-923e8754-031f-4b0a-8d37-12b4785aeff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25669
50673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2566950673
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.4173331612
Short name T131
Test name
Test status
Simulation time 8419154620 ps
CPU time 11.81 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:39 PM PDT 24
Peak memory 204780 kb
Host smart-c220dacd-5fb2-4097-b92c-64da486ba275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
31612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.4173331612
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3967599522
Short name T1731
Test name
Test status
Simulation time 8417442006 ps
CPU time 12.32 seconds
Started May 19 02:04:00 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 205036 kb
Host smart-b15b3fd3-f490-4910-a173-b95ae4a8394e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
99522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3967599522
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2893543383
Short name T1338
Test name
Test status
Simulation time 8406084142 ps
CPU time 11.48 seconds
Started May 19 02:03:47 PM PDT 24
Finished May 19 02:04:01 PM PDT 24
Peak memory 204856 kb
Host smart-3fd37e10-1d22-4e1a-9080-ca087fe0cfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28935
43383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2893543383
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.493964940
Short name T357
Test name
Test status
Simulation time 8394796018 ps
CPU time 11.71 seconds
Started May 19 02:04:08 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204816 kb
Host smart-65fd85a3-2eaa-4d23-9de8-1014b6d7c8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49396
4940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.493964940
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1342924601
Short name T176
Test name
Test status
Simulation time 8386250559 ps
CPU time 12.61 seconds
Started May 19 02:03:55 PM PDT 24
Finished May 19 02:04:10 PM PDT 24
Peak memory 205036 kb
Host smart-f1d1eeb7-284e-4211-9e40-e53ee33578c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429
24601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1342924601
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.4083738104
Short name T52
Test name
Test status
Simulation time 8407891982 ps
CPU time 10.92 seconds
Started May 19 02:03:51 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204792 kb
Host smart-05f0710c-67cf-4c21-b4ad-e30ccafde1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40837
38104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.4083738104
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1579367719
Short name T1680
Test name
Test status
Simulation time 8403657305 ps
CPU time 10.18 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:28 PM PDT 24
Peak memory 204744 kb
Host smart-77f860d4-3aa8-4d1d-a7bb-8a8bfe53e28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15793
67719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1579367719
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.842890524
Short name T815
Test name
Test status
Simulation time 8370295576 ps
CPU time 14.15 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:21 PM PDT 24
Peak memory 204808 kb
Host smart-cd99ff79-7988-4266-b144-1982090ee64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84289
0524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.842890524
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2274084189
Short name T568
Test name
Test status
Simulation time 26396528503 ps
CPU time 55.2 seconds
Started May 19 02:04:00 PM PDT 24
Finished May 19 02:04:57 PM PDT 24
Peak memory 204752 kb
Host smart-8edc9f3e-4ba4-440c-9038-2d308f03900f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22740
84189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2274084189
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1922057257
Short name T1735
Test name
Test status
Simulation time 8392646846 ps
CPU time 12 seconds
Started May 19 02:03:57 PM PDT 24
Finished May 19 02:04:10 PM PDT 24
Peak memory 204728 kb
Host smart-d9e46c84-bfff-4fc9-8287-0de3e7909492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
57257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1922057257
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1853016789
Short name T989
Test name
Test status
Simulation time 8437234625 ps
CPU time 11.69 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204740 kb
Host smart-bca01e44-6b0d-4856-a02a-aabc2c4314e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18530
16789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1853016789
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2158575352
Short name T753
Test name
Test status
Simulation time 8413317523 ps
CPU time 11.43 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:14 PM PDT 24
Peak memory 204800 kb
Host smart-49f2af0d-0e32-494d-bff5-b6af6abf73d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
75352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2158575352
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.4189177797
Short name T1299
Test name
Test status
Simulation time 8381556420 ps
CPU time 11 seconds
Started May 19 02:03:55 PM PDT 24
Finished May 19 02:04:08 PM PDT 24
Peak memory 204976 kb
Host smart-65b474e2-4d54-4897-b2b4-f4e02c7aecd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41891
77797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.4189177797
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1474504131
Short name T691
Test name
Test status
Simulation time 8376692003 ps
CPU time 11.47 seconds
Started May 19 02:03:50 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 204824 kb
Host smart-33cf6723-d2c2-4ecf-b367-8f4d92733796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
04131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1474504131
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1175708723
Short name T814
Test name
Test status
Simulation time 8364148988 ps
CPU time 12.35 seconds
Started May 19 02:03:48 PM PDT 24
Finished May 19 02:04:03 PM PDT 24
Peak memory 204784 kb
Host smart-338a9fcf-1d6a-415e-a250-c0e34468c99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11757
08723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1175708723
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1316655140
Short name T1372
Test name
Test status
Simulation time 8397762476 ps
CPU time 10.64 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:11 PM PDT 24
Peak memory 204808 kb
Host smart-423ef56a-2839-4ea3-9fe3-43a90f459577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13166
55140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1316655140
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.61958560
Short name T971
Test name
Test status
Simulation time 8386157746 ps
CPU time 10.84 seconds
Started May 19 02:04:12 PM PDT 24
Finished May 19 02:04:24 PM PDT 24
Peak memory 204760 kb
Host smart-e8377fdf-6efd-434d-b4c8-a972355b723f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61958
560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.61958560
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2541039937
Short name T726
Test name
Test status
Simulation time 8410453181 ps
CPU time 11.84 seconds
Started May 19 02:04:08 PM PDT 24
Finished May 19 02:04:21 PM PDT 24
Peak memory 204796 kb
Host smart-768cae58-1641-402c-91d6-b8244fd37c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
39937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2541039937
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3362386470
Short name T628
Test name
Test status
Simulation time 8465810699 ps
CPU time 11.09 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204744 kb
Host smart-19b226fb-145c-4d8b-ba64-bff37d7b95b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3362386470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3362386470
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.1227008158
Short name T154
Test name
Test status
Simulation time 8382167528 ps
CPU time 11.58 seconds
Started May 19 02:04:10 PM PDT 24
Finished May 19 02:04:22 PM PDT 24
Peak memory 204864 kb
Host smart-48fa257f-e133-4420-bd4f-f73eb68d7768
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1227008158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.1227008158
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.4029064924
Short name T820
Test name
Test status
Simulation time 8399234144 ps
CPU time 11.2 seconds
Started May 19 02:04:10 PM PDT 24
Finished May 19 02:04:22 PM PDT 24
Peak memory 204816 kb
Host smart-dcc8a72b-4a44-4131-98ab-7bc21631117d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40290
64924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.4029064924
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3189001363
Short name T1375
Test name
Test status
Simulation time 8417962887 ps
CPU time 10.91 seconds
Started May 19 02:04:00 PM PDT 24
Finished May 19 02:04:13 PM PDT 24
Peak memory 204744 kb
Host smart-a36a95cf-4fb9-4d9d-93c8-1546f25a9ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890
01363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3189001363
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.2555182011
Short name T974
Test name
Test status
Simulation time 8434986867 ps
CPU time 11.31 seconds
Started May 19 02:04:00 PM PDT 24
Finished May 19 02:04:13 PM PDT 24
Peak memory 204824 kb
Host smart-9247e4f9-fac0-44cc-b2b5-c9125d0d2724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25551
82011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.2555182011
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.612063623
Short name T183
Test name
Test status
Simulation time 9711661075 ps
CPU time 14.12 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204868 kb
Host smart-b2b25a98-c9e0-4891-b848-5da878cc4db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61206
3623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.612063623
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2942236459
Short name T1381
Test name
Test status
Simulation time 8421219263 ps
CPU time 11.54 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:17 PM PDT 24
Peak memory 204812 kb
Host smart-bc4bf373-72d1-47fe-9100-cad7391b5a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29422
36459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2942236459
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.771878295
Short name T988
Test name
Test status
Simulation time 8383377568 ps
CPU time 11.24 seconds
Started May 19 02:04:13 PM PDT 24
Finished May 19 02:04:25 PM PDT 24
Peak memory 204804 kb
Host smart-e1e65715-55d6-44eb-9c56-c29dc5fedbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77187
8295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.771878295
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1021869205
Short name T32
Test name
Test status
Simulation time 9047641432 ps
CPU time 11.94 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204800 kb
Host smart-5c418370-c090-4407-9dfa-12b591828a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10218
69205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1021869205
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3822523978
Short name T1700
Test name
Test status
Simulation time 8592790973 ps
CPU time 12.05 seconds
Started May 19 02:04:12 PM PDT 24
Finished May 19 02:04:25 PM PDT 24
Peak memory 204812 kb
Host smart-9cef7ae9-e213-4214-9b7a-c2e7b344cfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38225
23978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3822523978
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.4044140739
Short name T905
Test name
Test status
Simulation time 8447511942 ps
CPU time 10.98 seconds
Started May 19 02:04:01 PM PDT 24
Finished May 19 02:04:15 PM PDT 24
Peak memory 204788 kb
Host smart-88a2fa3b-0944-4533-8802-46d629021668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441
40739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.4044140739
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2581178553
Short name T1010
Test name
Test status
Simulation time 8373408558 ps
CPU time 11.35 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204796 kb
Host smart-d52da11e-5185-4539-a1a8-8c2114e6a4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
78553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2581178553
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.336442254
Short name T622
Test name
Test status
Simulation time 8474603469 ps
CPU time 12.22 seconds
Started May 19 02:03:59 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204772 kb
Host smart-44658404-7569-480f-9dd4-e033de7dab66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33644
2254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.336442254
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2433402954
Short name T319
Test name
Test status
Simulation time 8452690773 ps
CPU time 11.8 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 204884 kb
Host smart-ab965e83-3c18-4eaf-89f4-be2c3df7fd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
02954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2433402954
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1373904578
Short name T655
Test name
Test status
Simulation time 11524233844 ps
CPU time 14.2 seconds
Started May 19 02:03:56 PM PDT 24
Finished May 19 02:04:12 PM PDT 24
Peak memory 204868 kb
Host smart-851f8dbc-93fc-4579-ad2a-639c2cc974c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13739
04578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1373904578
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3132855544
Short name T1408
Test name
Test status
Simulation time 8413395509 ps
CPU time 12.21 seconds
Started May 19 02:04:15 PM PDT 24
Finished May 19 02:04:28 PM PDT 24
Peak memory 204728 kb
Host smart-19224e61-2d79-4145-932c-89ad54331e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31328
55544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3132855544
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2135417990
Short name T1746
Test name
Test status
Simulation time 8369323378 ps
CPU time 11.93 seconds
Started May 19 02:04:02 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204832 kb
Host smart-133ceabf-c59c-409a-97e0-94348f4f9621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21354
17990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2135417990
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3767546545
Short name T125
Test name
Test status
Simulation time 8463498063 ps
CPU time 13.12 seconds
Started May 19 02:04:11 PM PDT 24
Finished May 19 02:04:25 PM PDT 24
Peak memory 204864 kb
Host smart-77f25f85-09ba-48e9-8441-c2463d14f532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37675
46545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3767546545
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.4123006159
Short name T578
Test name
Test status
Simulation time 8420560595 ps
CPU time 10.71 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204776 kb
Host smart-d4ef01f5-0cb7-4079-b701-50c9373b5c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41230
06159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.4123006159
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1280104793
Short name T1281
Test name
Test status
Simulation time 8385707720 ps
CPU time 10.49 seconds
Started May 19 02:04:15 PM PDT 24
Finished May 19 02:04:26 PM PDT 24
Peak memory 204828 kb
Host smart-05910637-367a-4afd-8416-08e55375e29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
04793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1280104793
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1919131493
Short name T696
Test name
Test status
Simulation time 8419260153 ps
CPU time 12.09 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204788 kb
Host smart-07327e25-fb73-4e03-8b7d-7766d7bea231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19191
31493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1919131493
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.2267776518
Short name T1164
Test name
Test status
Simulation time 8412147579 ps
CPU time 11.79 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204820 kb
Host smart-f72c3309-e208-4689-9eb0-6c1624c2044c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22677
76518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.2267776518
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2119163026
Short name T447
Test name
Test status
Simulation time 8369673811 ps
CPU time 11.4 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204796 kb
Host smart-951373e3-81c1-4740-8040-c06192719278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
63026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2119163026
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1195032028
Short name T1767
Test name
Test status
Simulation time 8394739356 ps
CPU time 11.56 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204856 kb
Host smart-0cc7fc6b-652b-4295-a08d-e70d5b85e96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11950
32028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1195032028
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1332046497
Short name T992
Test name
Test status
Simulation time 19743503899 ps
CPU time 33.42 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204812 kb
Host smart-82a08435-d381-4088-a912-ce82e6ca5345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
46497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1332046497
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3007528582
Short name T1724
Test name
Test status
Simulation time 8429613880 ps
CPU time 10.6 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204780 kb
Host smart-80c4706e-0676-4d47-8ad2-f41c1a64d0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30075
28582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3007528582
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3694235162
Short name T758
Test name
Test status
Simulation time 8413348271 ps
CPU time 12.22 seconds
Started May 19 02:04:07 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 205052 kb
Host smart-9db9332a-46b5-4dfb-8aa9-1e4db14bd2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
35162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3694235162
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1881424732
Short name T1220
Test name
Test status
Simulation time 8394187074 ps
CPU time 12.11 seconds
Started May 19 02:04:07 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204760 kb
Host smart-30bb249e-e202-4b65-89d8-3267e45545db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18814
24732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1881424732
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.169375516
Short name T1707
Test name
Test status
Simulation time 8368608951 ps
CPU time 11.25 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204748 kb
Host smart-069ac90e-6b6e-4bbb-95c2-a8dcaefbc731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16937
5516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.169375516
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2199695453
Short name T1008
Test name
Test status
Simulation time 8382410599 ps
CPU time 11.56 seconds
Started May 19 02:04:19 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204792 kb
Host smart-dded31b1-4d31-4ddf-be77-db73aea9092b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21996
95453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2199695453
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3969996217
Short name T492
Test name
Test status
Simulation time 8401994533 ps
CPU time 11.03 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204836 kb
Host smart-804f34cf-07bd-415e-bc43-7891f6c5a4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
96217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3969996217
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.4293935064
Short name T1650
Test name
Test status
Simulation time 8454828634 ps
CPU time 11.3 seconds
Started May 19 02:04:02 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 204872 kb
Host smart-55dd920d-749d-4d05-9fbd-79bd9765d610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42939
35064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4293935064
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2657867066
Short name T792
Test name
Test status
Simulation time 8387421077 ps
CPU time 10.61 seconds
Started May 19 02:04:17 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 204636 kb
Host smart-ba812810-791c-480a-8e37-6c2d998cf220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26578
67066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2657867066
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1367855392
Short name T1204
Test name
Test status
Simulation time 8389220181 ps
CPU time 11.17 seconds
Started May 19 02:04:20 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204888 kb
Host smart-e8863cd0-eec9-41a8-b04f-443203d94ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
55392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1367855392
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.504922828
Short name T1600
Test name
Test status
Simulation time 8469953430 ps
CPU time 11.58 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204756 kb
Host smart-542ca695-2c94-4d9c-a249-dc39c4d8d051
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=504922828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.504922828
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.4147038424
Short name T310
Test name
Test status
Simulation time 8382523912 ps
CPU time 11.65 seconds
Started May 19 02:04:18 PM PDT 24
Finished May 19 02:04:33 PM PDT 24
Peak memory 204796 kb
Host smart-9b2ce744-1f7a-4bba-8d3d-6463cf1c502c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4147038424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.4147038424
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.679695520
Short name T1095
Test name
Test status
Simulation time 8413878379 ps
CPU time 11.87 seconds
Started May 19 02:04:14 PM PDT 24
Finished May 19 02:04:27 PM PDT 24
Peak memory 204788 kb
Host smart-8cf54f97-a955-43d9-bb2a-8f925c1b5173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67969
5520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.679695520
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2342484266
Short name T1193
Test name
Test status
Simulation time 8380503822 ps
CPU time 12.73 seconds
Started May 19 02:04:17 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204788 kb
Host smart-48b60b3f-358c-4f9a-a1e3-401eefd561c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
84266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2342484266
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1719227369
Short name T507
Test name
Test status
Simulation time 8390810931 ps
CPU time 11.11 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204812 kb
Host smart-f0f55128-4ca4-49ca-b1b3-57d7a59b173a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17192
27369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1719227369
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2017437664
Short name T188
Test name
Test status
Simulation time 9252778812 ps
CPU time 12.12 seconds
Started May 19 02:04:06 PM PDT 24
Finished May 19 02:04:19 PM PDT 24
Peak memory 204848 kb
Host smart-a5845801-7b95-42d1-870e-950978b7f32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20174
37664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2017437664
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.422520358
Short name T341
Test name
Test status
Simulation time 8377127533 ps
CPU time 10.91 seconds
Started May 19 02:04:10 PM PDT 24
Finished May 19 02:04:21 PM PDT 24
Peak memory 204716 kb
Host smart-a095bdef-947c-49f6-8a98-849ef395209b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42252
0358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.422520358
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.4230511336
Short name T1517
Test name
Test status
Simulation time 8384733862 ps
CPU time 10.74 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204872 kb
Host smart-a8826c7a-d270-49d4-b2c8-3610ea1c8810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
11336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4230511336
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1277895692
Short name T1653
Test name
Test status
Simulation time 9125393326 ps
CPU time 13.09 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204776 kb
Host smart-f0de50e2-4a66-4645-a704-1a2d45734be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12778
95692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1277895692
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2990973509
Short name T1576
Test name
Test status
Simulation time 8412538419 ps
CPU time 11.49 seconds
Started May 19 02:04:10 PM PDT 24
Finished May 19 02:04:23 PM PDT 24
Peak memory 204760 kb
Host smart-e596d17d-bda6-4cab-8457-06b1e9e2005f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29909
73509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2990973509
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2277732339
Short name T393
Test name
Test status
Simulation time 8455539343 ps
CPU time 10.92 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:29 PM PDT 24
Peak memory 204816 kb
Host smart-c48477e5-57bf-4040-953b-b51a6fec32ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
32339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2277732339
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2072442156
Short name T529
Test name
Test status
Simulation time 8373439756 ps
CPU time 11.08 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204820 kb
Host smart-c5ac3cb3-cae9-4a80-84f3-cf3b162b6b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
42156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2072442156
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3452871018
Short name T649
Test name
Test status
Simulation time 8437472625 ps
CPU time 11.3 seconds
Started May 19 02:04:11 PM PDT 24
Finished May 19 02:04:23 PM PDT 24
Peak memory 204844 kb
Host smart-7d1acced-89ac-44ab-9d66-c9018fc60b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34528
71018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3452871018
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3143344629
Short name T337
Test name
Test status
Simulation time 8422153815 ps
CPU time 10.98 seconds
Started May 19 02:04:18 PM PDT 24
Finished May 19 02:04:32 PM PDT 24
Peak memory 204864 kb
Host smart-68a081f3-545b-499d-8bc1-019f4b7f4ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
44629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3143344629
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1653646231
Short name T904
Test name
Test status
Simulation time 11536778354 ps
CPU time 14.26 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204836 kb
Host smart-5fe84d88-f94b-4826-9c8a-a6bc913ffdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536
46231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1653646231
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3822205436
Short name T107
Test name
Test status
Simulation time 8413141058 ps
CPU time 12.5 seconds
Started May 19 02:04:10 PM PDT 24
Finished May 19 02:04:23 PM PDT 24
Peak memory 204792 kb
Host smart-06aded48-9066-4a00-b500-fc097f163e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
05436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3822205436
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3738754738
Short name T1337
Test name
Test status
Simulation time 8396596999 ps
CPU time 10.49 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204756 kb
Host smart-25ad4a7c-5d2b-4de9-89d5-1d319a21a63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
54738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3738754738
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.232792506
Short name T1530
Test name
Test status
Simulation time 8422068183 ps
CPU time 12.1 seconds
Started May 19 02:04:11 PM PDT 24
Finished May 19 02:04:24 PM PDT 24
Peak memory 204828 kb
Host smart-68d637aa-2501-43dd-ad26-ddc4c26cb02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23279
2506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.232792506
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1360341747
Short name T1642
Test name
Test status
Simulation time 8415669072 ps
CPU time 11 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204816 kb
Host smart-b44d227c-73db-4a9a-9785-8b57b19c7889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
41747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1360341747
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2037072931
Short name T736
Test name
Test status
Simulation time 8394923928 ps
CPU time 10.33 seconds
Started May 19 02:04:13 PM PDT 24
Finished May 19 02:04:24 PM PDT 24
Peak memory 205020 kb
Host smart-11b88201-fdea-4daf-a50a-ddf80b942199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20370
72931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2037072931
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3364180815
Short name T1428
Test name
Test status
Simulation time 8415090389 ps
CPU time 11.4 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204868 kb
Host smart-5884b6f8-5862-40a1-b87c-239b3e2c9fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
80815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3364180815
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2555946944
Short name T194
Test name
Test status
Simulation time 8389314399 ps
CPU time 10.77 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204832 kb
Host smart-7c5cf2e5-a16c-4d10-8f91-fb557f127cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
46944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2555946944
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.308506513
Short name T970
Test name
Test status
Simulation time 8401711940 ps
CPU time 10.94 seconds
Started May 19 02:04:06 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204768 kb
Host smart-d8e8803a-3af7-4000-ac32-22b669952846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30850
6513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.308506513
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3640707351
Short name T857
Test name
Test status
Simulation time 8370202612 ps
CPU time 10.84 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204760 kb
Host smart-96d4c469-8ece-4049-a123-5043e9aee2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36407
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3640707351
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.957280469
Short name T1161
Test name
Test status
Simulation time 8399280007 ps
CPU time 10.42 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204812 kb
Host smart-a0fd8cb6-2455-48df-8b89-ba772ef48620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95728
0469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.957280469
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1911478306
Short name T1432
Test name
Test status
Simulation time 18246417184 ps
CPU time 37.99 seconds
Started May 19 02:04:00 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204800 kb
Host smart-d0f98628-a8f3-47f3-9a99-7eed5ebfadcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19114
78306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1911478306
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2138500504
Short name T930
Test name
Test status
Simulation time 8374757890 ps
CPU time 12.18 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204792 kb
Host smart-8932be5d-4f97-4e27-865b-e67025140c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21385
00504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2138500504
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.462361781
Short name T728
Test name
Test status
Simulation time 8454460647 ps
CPU time 10.76 seconds
Started May 19 02:04:14 PM PDT 24
Finished May 19 02:04:25 PM PDT 24
Peak memory 204992 kb
Host smart-926afd3b-f80b-43b9-960b-07da11514e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46236
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.462361781
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3109047409
Short name T729
Test name
Test status
Simulation time 8397700240 ps
CPU time 11.82 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204796 kb
Host smart-50c00d0a-77c6-4e44-ae86-40ab83621206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31090
47409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3109047409
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.34822243
Short name T524
Test name
Test status
Simulation time 8374510693 ps
CPU time 12.73 seconds
Started May 19 02:04:08 PM PDT 24
Finished May 19 02:04:21 PM PDT 24
Peak memory 204820 kb
Host smart-acf6ff71-e955-44d3-8e11-7ebbbc679187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34822
243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.34822243
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2918112731
Short name T395
Test name
Test status
Simulation time 8378346752 ps
CPU time 11.67 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204816 kb
Host smart-3098f232-d65e-4293-84c0-243bb3c2e17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29181
12731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2918112731
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.162444595
Short name T556
Test name
Test status
Simulation time 8408641400 ps
CPU time 12.07 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204824 kb
Host smart-c62dc7eb-c17e-4877-8e86-4a201aac402f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16244
4595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.162444595
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3265486545
Short name T730
Test name
Test status
Simulation time 8417730580 ps
CPU time 12.27 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204832 kb
Host smart-628447f6-05d2-4c1a-a8f7-289eb48c67f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32654
86545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3265486545
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2563447284
Short name T816
Test name
Test status
Simulation time 8407991655 ps
CPU time 14.07 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204872 kb
Host smart-fa279068-b5df-44db-9e34-cdf6f8f33641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25634
47284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2563447284
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.437978053
Short name T523
Test name
Test status
Simulation time 8450210495 ps
CPU time 10.79 seconds
Started May 19 02:04:06 PM PDT 24
Finished May 19 02:04:23 PM PDT 24
Peak memory 204848 kb
Host smart-08551cf1-978b-4e45-ab22-750953f60358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43797
8053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.437978053
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.3561935415
Short name T1387
Test name
Test status
Simulation time 8471737167 ps
CPU time 10.46 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204780 kb
Host smart-eaaedc9b-8842-4b57-bda6-a2566729ada3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3561935415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.3561935415
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1991445567
Short name T668
Test name
Test status
Simulation time 8381176321 ps
CPU time 10.95 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204868 kb
Host smart-e84524e4-a605-4609-91b6-84adb5d27fa5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1991445567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1991445567
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.3940411333
Short name T975
Test name
Test status
Simulation time 8381104826 ps
CPU time 13.02 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:50 PM PDT 24
Peak memory 204840 kb
Host smart-a3f0f66b-64d2-427f-8f4e-2b812bd1cb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39404
11333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.3940411333
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2817053111
Short name T565
Test name
Test status
Simulation time 8386163734 ps
CPU time 10.72 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204776 kb
Host smart-e7a498dd-ba18-40b5-85ad-c6bff343c3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28170
53111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2817053111
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.14353654
Short name T1266
Test name
Test status
Simulation time 8416251504 ps
CPU time 12.19 seconds
Started May 19 02:04:20 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204828 kb
Host smart-6f0e2e1a-d912-4068-a824-0386108e008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.14353654
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1899124426
Short name T88
Test name
Test status
Simulation time 8365824279 ps
CPU time 10.34 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204740 kb
Host smart-6c244b9a-4e51-425d-81a7-c2d11f099b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
24426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1899124426
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3525133043
Short name T1314
Test name
Test status
Simulation time 8382469412 ps
CPU time 10.55 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204836 kb
Host smart-4e357d96-395e-484b-990c-b730b9bf5afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35251
33043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3525133043
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.348364072
Short name T1766
Test name
Test status
Simulation time 9217776466 ps
CPU time 12.49 seconds
Started May 19 02:04:04 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 204848 kb
Host smart-60a0c953-7df3-40b9-bfa7-755417c4ac96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
4072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.348364072
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1552625954
Short name T1021
Test name
Test status
Simulation time 8407727268 ps
CPU time 11.94 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204752 kb
Host smart-5fd54525-ac90-41a8-a74a-21f415c1cade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15526
25954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1552625954
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2655784106
Short name T1227
Test name
Test status
Simulation time 8390745114 ps
CPU time 11.76 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204672 kb
Host smart-442df8bf-1a9f-4d12-a401-50cda142838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
84106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2655784106
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2250485159
Short name T749
Test name
Test status
Simulation time 8378192522 ps
CPU time 10.74 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204992 kb
Host smart-16cb5de1-bc37-4e27-adc8-045ebd376478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
85159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2250485159
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.210399041
Short name T1567
Test name
Test status
Simulation time 8494782233 ps
CPU time 12.46 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204824 kb
Host smart-6a0b54e1-aafa-4e31-86e6-fd6b12dde749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
9041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.210399041
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.109346595
Short name T919
Test name
Test status
Simulation time 8415407113 ps
CPU time 13.63 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204864 kb
Host smart-3675d63e-409e-4080-82d5-7efc9a25a8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934
6595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.109346595
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3092943426
Short name T651
Test name
Test status
Simulation time 11543745475 ps
CPU time 15.04 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204960 kb
Host smart-e163315b-0bd4-4199-971b-8f37d9c8a9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
43426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3092943426
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3336649340
Short name T851
Test name
Test status
Simulation time 8425992133 ps
CPU time 10.98 seconds
Started May 19 02:04:20 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204824 kb
Host smart-1c25fd02-d618-4615-bf4e-ee0e2494d30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33366
49340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3336649340
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.516878500
Short name T312
Test name
Test status
Simulation time 8377715208 ps
CPU time 12.88 seconds
Started May 19 02:04:19 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204832 kb
Host smart-d8ad439d-6b3c-40e0-80d0-5199bf53b117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51687
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.516878500
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.4207898399
Short name T1648
Test name
Test status
Simulation time 8444624009 ps
CPU time 10.62 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204808 kb
Host smart-0ebeec4f-f215-4dd5-aa91-32aafe68adb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42078
98399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.4207898399
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2541988997
Short name T1502
Test name
Test status
Simulation time 8433320022 ps
CPU time 10.83 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204732 kb
Host smart-d73be427-3736-494b-b0aa-08419e6052a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419
88997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2541988997
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2257001056
Short name T374
Test name
Test status
Simulation time 8409077660 ps
CPU time 12.03 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204836 kb
Host smart-af889579-29a6-47fa-b45b-bd117ae35804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
01056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2257001056
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1443325136
Short name T202
Test name
Test status
Simulation time 8406872286 ps
CPU time 12.17 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:39 PM PDT 24
Peak memory 204748 kb
Host smart-40f41d5c-9296-42f3-a7cc-90ba845ebba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14433
25136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1443325136
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.2267819506
Short name T1759
Test name
Test status
Simulation time 8510996625 ps
CPU time 11.85 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 204788 kb
Host smart-390158f0-dfe5-4f03-b1ad-0bf9a18b7f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22678
19506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.2267819506
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1672783208
Short name T1710
Test name
Test status
Simulation time 8368742663 ps
CPU time 11.11 seconds
Started May 19 02:04:20 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204788 kb
Host smart-08dc0db9-46b5-4234-9a37-6a819a62c402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16727
83208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1672783208
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.400405967
Short name T1153
Test name
Test status
Simulation time 8361947598 ps
CPU time 10.82 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204760 kb
Host smart-b9333c43-fa5d-4d63-b2a7-17403fd6c67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40040
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.400405967
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2241942713
Short name T1733
Test name
Test status
Simulation time 18482712659 ps
CPU time 33.17 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204844 kb
Host smart-f6502ca5-ae4d-46f3-8d2f-9ffa7b184e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
42713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2241942713
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.503244787
Short name T435
Test name
Test status
Simulation time 8395336408 ps
CPU time 10.8 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204816 kb
Host smart-afff7933-dab7-437a-aa25-71b343af54f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50324
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.503244787
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.153735487
Short name T700
Test name
Test status
Simulation time 8440094675 ps
CPU time 10.31 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204756 kb
Host smart-6a8b0962-c5cc-4599-a3b7-a69814d206c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15373
5487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.153735487
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2147895056
Short name T1665
Test name
Test status
Simulation time 8400858721 ps
CPU time 13.73 seconds
Started May 19 02:04:05 PM PDT 24
Finished May 19 02:04:20 PM PDT 24
Peak memory 204812 kb
Host smart-5c827ea7-5fcf-426d-a8d9-3b3d02f92313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21478
95056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2147895056
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1613383315
Short name T493
Test name
Test status
Simulation time 8368711187 ps
CPU time 11.31 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204828 kb
Host smart-842d5673-b019-4e68-a6fe-9d74973c5904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16133
83315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1613383315
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2493170419
Short name T433
Test name
Test status
Simulation time 8384580873 ps
CPU time 11.43 seconds
Started May 19 02:04:13 PM PDT 24
Finished May 19 02:04:25 PM PDT 24
Peak memory 204828 kb
Host smart-4e99f8f8-fb81-40c8-86e0-44ba3a23d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24931
70419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2493170419
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2456506747
Short name T498
Test name
Test status
Simulation time 8365810738 ps
CPU time 11.18 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204756 kb
Host smart-ba700cdf-16fb-43dc-8f12-0eee445ec640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24565
06747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2456506747
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2917334760
Short name T672
Test name
Test status
Simulation time 8489168188 ps
CPU time 11.26 seconds
Started May 19 02:04:20 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204844 kb
Host smart-5538a848-d391-443b-9acd-40b8d331ca7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173
34760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2917334760
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3241501743
Short name T712
Test name
Test status
Simulation time 8410534600 ps
CPU time 12.74 seconds
Started May 19 02:04:17 PM PDT 24
Finished May 19 02:04:32 PM PDT 24
Peak memory 204848 kb
Host smart-4c9a00c9-b015-412e-a883-a555a9a4e807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
01743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3241501743
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3283614645
Short name T1064
Test name
Test status
Simulation time 8417733101 ps
CPU time 10.34 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204792 kb
Host smart-fbeea7c5-6a56-44c3-b17a-995ceb8bce48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32836
14645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3283614645
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1338795682
Short name T399
Test name
Test status
Simulation time 8478383727 ps
CPU time 13.09 seconds
Started May 19 02:01:34 PM PDT 24
Finished May 19 02:01:49 PM PDT 24
Peak memory 204872 kb
Host smart-a327afe3-67db-4174-941b-d6efb0e58cbd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1338795682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1338795682
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.3593674054
Short name T1703
Test name
Test status
Simulation time 8393403999 ps
CPU time 10.84 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:29 PM PDT 24
Peak memory 204852 kb
Host smart-6e46d2de-fe4d-4c75-ac37-3008bc9e3744
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3593674054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.3593674054
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.1003699176
Short name T969
Test name
Test status
Simulation time 8404385716 ps
CPU time 13.09 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 204980 kb
Host smart-1efa1f11-cc37-44ba-bb71-e7249b5a495b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
99176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.1003699176
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3843530098
Short name T402
Test name
Test status
Simulation time 8383965183 ps
CPU time 11.9 seconds
Started May 19 02:01:16 PM PDT 24
Finished May 19 02:01:29 PM PDT 24
Peak memory 204752 kb
Host smart-e67d4310-5252-448d-bad7-04c952d68d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38435
30098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3843530098
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.369489463
Short name T197
Test name
Test status
Simulation time 8748986525 ps
CPU time 11.37 seconds
Started May 19 02:01:21 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204856 kb
Host smart-a4f8e86d-f8e5-4e86-84b6-fd558cfb59c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
9463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.369489463
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2855723250
Short name T89
Test name
Test status
Simulation time 8369490622 ps
CPU time 13.8 seconds
Started May 19 02:01:13 PM PDT 24
Finished May 19 02:01:28 PM PDT 24
Peak memory 204764 kb
Host smart-13060254-a530-410f-b81e-d3c931631299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28557
23250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2855723250
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2703016352
Short name T719
Test name
Test status
Simulation time 8377107935 ps
CPU time 10.89 seconds
Started May 19 02:01:13 PM PDT 24
Finished May 19 02:01:25 PM PDT 24
Peak memory 204848 kb
Host smart-c5094671-4cb3-4729-9695-5be341fbb572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27030
16352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2703016352
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.1801347446
Short name T420
Test name
Test status
Simulation time 9364499362 ps
CPU time 15.37 seconds
Started May 19 02:01:13 PM PDT 24
Finished May 19 02:01:30 PM PDT 24
Peak memory 204828 kb
Host smart-98ff9472-3759-4879-b697-89311d81db20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18013
47446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1801347446
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1196767311
Short name T932
Test name
Test status
Simulation time 8438121151 ps
CPU time 11.51 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204768 kb
Host smart-440df473-e4ae-4c76-a48c-a7e2f451e3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11967
67311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1196767311
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1920326027
Short name T531
Test name
Test status
Simulation time 8380264574 ps
CPU time 10.86 seconds
Started May 19 02:01:25 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204796 kb
Host smart-6e0ba478-f85e-4b6f-80b6-52d95368fab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
26027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1920326027
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1580919824
Short name T1742
Test name
Test status
Simulation time 8398391689 ps
CPU time 12.26 seconds
Started May 19 02:01:14 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204780 kb
Host smart-f067f9c8-0042-467f-ba43-0ac28f2d561f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
19824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1580919824
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.117800134
Short name T1450
Test name
Test status
Simulation time 8375883954 ps
CPU time 11.41 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204788 kb
Host smart-fc70f188-63f0-430f-af5d-c91d50dd9452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11780
0134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.117800134
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2864310341
Short name T559
Test name
Test status
Simulation time 11584698761 ps
CPU time 15.48 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:36 PM PDT 24
Peak memory 204864 kb
Host smart-8a89f9f4-a3fb-45bd-82cc-151c79409067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28643
10341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2864310341
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3879477594
Short name T1725
Test name
Test status
Simulation time 8423296869 ps
CPU time 11.81 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:30 PM PDT 24
Peak memory 204832 kb
Host smart-f6e8e15b-5a8d-4883-a462-1afa4ab9c23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38794
77594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3879477594
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1532827894
Short name T384
Test name
Test status
Simulation time 8378061963 ps
CPU time 10.52 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 204732 kb
Host smart-28ef0013-b284-409c-a166-b8de744f959c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328
27894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1532827894
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2673385009
Short name T1702
Test name
Test status
Simulation time 8419307044 ps
CPU time 10.73 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204828 kb
Host smart-e6e070b6-ca05-4f52-973d-b0c92f49bfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26733
85009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2673385009
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1500426218
Short name T1613
Test name
Test status
Simulation time 8411257627 ps
CPU time 10.67 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204836 kb
Host smart-bb77c622-fccf-4368-8ba4-c206eb48cd58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15004
26218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1500426218
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1860663481
Short name T469
Test name
Test status
Simulation time 8393995727 ps
CPU time 12.48 seconds
Started May 19 02:01:12 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 204760 kb
Host smart-31ef35ee-206d-40fd-8e1f-ee9155ce8e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
63481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1860663481
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.270208113
Short name T1120
Test name
Test status
Simulation time 8414442013 ps
CPU time 11.3 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204756 kb
Host smart-c627c8b9-3468-4ec4-b448-e2d9cff7c940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
8113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.270208113
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.717365511
Short name T809
Test name
Test status
Simulation time 8376034304 ps
CPU time 11.34 seconds
Started May 19 02:01:13 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 204772 kb
Host smart-bb4e7a49-f399-4c56-96d9-65ad2162916e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71736
5511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.717365511
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3382942207
Short name T34
Test name
Test status
Simulation time 8356071167 ps
CPU time 11.02 seconds
Started May 19 02:01:41 PM PDT 24
Finished May 19 02:01:53 PM PDT 24
Peak memory 204764 kb
Host smart-9b6eb0b5-4f22-483c-809a-1bb6bd45776a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33829
42207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3382942207
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.119362354
Short name T1304
Test name
Test status
Simulation time 25642569318 ps
CPU time 47.07 seconds
Started May 19 02:01:21 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 204776 kb
Host smart-e5cc2216-e01a-4643-b55d-7c21c49d2bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.119362354
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2290645514
Short name T1237
Test name
Test status
Simulation time 8388479484 ps
CPU time 11.22 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:30 PM PDT 24
Peak memory 204728 kb
Host smart-bd0f8517-cbad-4988-9353-ef6bcb683fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22906
45514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2290645514
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.593947309
Short name T900
Test name
Test status
Simulation time 8399588197 ps
CPU time 12.25 seconds
Started May 19 02:01:15 PM PDT 24
Finished May 19 02:01:28 PM PDT 24
Peak memory 204864 kb
Host smart-d059dbcc-8134-466e-9468-1bd0a064a27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59394
7309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.593947309
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.615411277
Short name T443
Test name
Test status
Simulation time 8391056921 ps
CPU time 12.67 seconds
Started May 19 02:01:14 PM PDT 24
Finished May 19 02:01:28 PM PDT 24
Peak memory 204788 kb
Host smart-b9c4764f-76a0-461f-96db-73bc2338e8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61541
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.615411277
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1119765148
Short name T1009
Test name
Test status
Simulation time 8398143952 ps
CPU time 11.88 seconds
Started May 19 02:01:14 PM PDT 24
Finished May 19 02:01:27 PM PDT 24
Peak memory 204756 kb
Host smart-3d76c954-9585-4a4d-9da7-84349f2a4b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197
65148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1119765148
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.290296969
Short name T56
Test name
Test status
Simulation time 176204498 ps
CPU time 0.97 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 220352 kb
Host smart-d3f09b4d-2c35-448c-b340-50dd550520d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=290296969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.290296969
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3755228848
Short name T1003
Test name
Test status
Simulation time 8373657585 ps
CPU time 11.6 seconds
Started May 19 02:01:18 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 204812 kb
Host smart-dbcd699e-f056-4fc8-acae-d602a0568b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37552
28848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3755228848
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3196119601
Short name T751
Test name
Test status
Simulation time 8450919068 ps
CPU time 13.24 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 204876 kb
Host smart-29a6ed69-e6b4-4202-8b1f-6d9e076c3952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
19601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3196119601
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2109789428
Short name T685
Test name
Test status
Simulation time 8382236083 ps
CPU time 11.94 seconds
Started May 19 02:01:16 PM PDT 24
Finished May 19 02:01:29 PM PDT 24
Peak memory 204788 kb
Host smart-5974c948-5ed3-4a94-965d-83590720d970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21097
89428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2109789428
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2986936980
Short name T517
Test name
Test status
Simulation time 8412227296 ps
CPU time 12.05 seconds
Started May 19 02:01:15 PM PDT 24
Finished May 19 02:01:28 PM PDT 24
Peak memory 205020 kb
Host smart-12f33ba3-c52f-484e-ae95-51e6e87090a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869
36980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2986936980
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.2341404197
Short name T369
Test name
Test status
Simulation time 8463057770 ps
CPU time 11.7 seconds
Started May 19 02:04:47 PM PDT 24
Finished May 19 02:05:00 PM PDT 24
Peak memory 204900 kb
Host smart-a31ae683-3fbf-4846-a3d1-890bc1a2294b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2341404197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.2341404197
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3948670508
Short name T27
Test name
Test status
Simulation time 8400245907 ps
CPU time 11.07 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204844 kb
Host smart-f649ed9e-1669-4ec2-ace8-a20789142513
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3948670508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3948670508
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.2204480279
Short name T1701
Test name
Test status
Simulation time 8405057476 ps
CPU time 13.55 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204824 kb
Host smart-04b2b6fc-dedd-4191-9b5d-0ae336fd69b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
80279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.2204480279
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.937920236
Short name T1728
Test name
Test status
Simulation time 8381247267 ps
CPU time 12.72 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204788 kb
Host smart-34c687b9-7580-4a97-ac2f-cc0526f27996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93792
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.937920236
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2919930993
Short name T931
Test name
Test status
Simulation time 8371672494 ps
CPU time 11.34 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204760 kb
Host smart-8c740cef-f45f-4712-9934-76979ce63746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
30993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2919930993
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.388439761
Short name T943
Test name
Test status
Simulation time 8391300876 ps
CPU time 12.8 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204836 kb
Host smart-61921c3b-9603-485a-892a-5937ff866e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.388439761
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.928031675
Short name T1072
Test name
Test status
Simulation time 9146701601 ps
CPU time 11.52 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204856 kb
Host smart-45b7154f-3dd6-440c-98ea-4f5713d5755f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92803
1675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.928031675
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2239117407
Short name T1177
Test name
Test status
Simulation time 8412979381 ps
CPU time 12.4 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204772 kb
Host smart-25805362-7ff1-4b4b-ae22-99a437d492ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22391
17407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2239117407
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3093831739
Short name T1394
Test name
Test status
Simulation time 8414748945 ps
CPU time 11.36 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:39 PM PDT 24
Peak memory 204848 kb
Host smart-021c55c1-25bd-4b33-bdc3-0e32e49b0a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30938
31739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3093831739
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2730219937
Short name T1484
Test name
Test status
Simulation time 8382126567 ps
CPU time 11.01 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204816 kb
Host smart-7fc510b7-2b3c-4aae-be6f-6aad43e1c702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27302
19937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2730219937
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3560242996
Short name T821
Test name
Test status
Simulation time 8449174697 ps
CPU time 10.61 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204832 kb
Host smart-fbedc6db-f4b7-430e-82c8-ed2bc41e962e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35602
42996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3560242996
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3001410529
Short name T771
Test name
Test status
Simulation time 8404231513 ps
CPU time 12.55 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204800 kb
Host smart-58805a06-26c4-4167-b768-01cfb071dd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30014
10529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3001410529
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4020293844
Short name T1392
Test name
Test status
Simulation time 11536548940 ps
CPU time 15.2 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:50 PM PDT 24
Peak memory 204692 kb
Host smart-6780c22e-4a55-4b99-9742-44fb8b2b37dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40202
93844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4020293844
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2131510730
Short name T1363
Test name
Test status
Simulation time 8415795345 ps
CPU time 11.35 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204808 kb
Host smart-da7ffedc-e4f7-47bc-a06c-e7a417736207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
10730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2131510730
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1426553711
Short name T1503
Test name
Test status
Simulation time 8370810618 ps
CPU time 10.65 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204744 kb
Host smart-c23695e1-f2b8-40af-a248-87fb474a7390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14265
53711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1426553711
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3425236385
Short name T1514
Test name
Test status
Simulation time 8461657464 ps
CPU time 11.08 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204840 kb
Host smart-29f74ae2-80c3-4f9b-bb97-eeb0ae0bdbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
36385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3425236385
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.445148534
Short name T619
Test name
Test status
Simulation time 8414260376 ps
CPU time 10.62 seconds
Started May 19 02:04:22 PM PDT 24
Finished May 19 02:04:36 PM PDT 24
Peak memory 204764 kb
Host smart-ed4c9c37-0a33-4d80-b02b-17f648c13dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44514
8534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.445148534
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2509795951
Short name T1154
Test name
Test status
Simulation time 8369124358 ps
CPU time 12.15 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204768 kb
Host smart-9c383939-33df-4b66-98e0-49385ed52fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25097
95951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2509795951
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2817197655
Short name T1136
Test name
Test status
Simulation time 8393276757 ps
CPU time 10.94 seconds
Started May 19 02:04:33 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204816 kb
Host smart-4a9fa8c0-1ba8-4346-9dd6-82dba032e58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
97655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2817197655
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2405516745
Short name T207
Test name
Test status
Simulation time 8407817801 ps
CPU time 12.84 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:46 PM PDT 24
Peak memory 204868 kb
Host smart-670a79e4-219e-4b7e-a7c9-21f5016b2f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24055
16745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2405516745
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.3644641649
Short name T334
Test name
Test status
Simulation time 8390915725 ps
CPU time 12 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204800 kb
Host smart-34f088ac-d413-4148-b986-40f90f0d1aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
41649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.3644641649
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.902590007
Short name T448
Test name
Test status
Simulation time 8372754354 ps
CPU time 10.92 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204784 kb
Host smart-e90b3cd0-90d9-4db9-99e2-b9e2408217ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90259
0007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.902590007
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3061571119
Short name T383
Test name
Test status
Simulation time 8358658046 ps
CPU time 11.5 seconds
Started May 19 02:04:20 PM PDT 24
Finished May 19 02:04:35 PM PDT 24
Peak memory 204732 kb
Host smart-f593bb6a-2d66-405f-8404-011bee04d059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
71119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3061571119
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2697327535
Short name T233
Test name
Test status
Simulation time 16470024186 ps
CPU time 30.5 seconds
Started May 19 02:04:21 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204744 kb
Host smart-61660d7b-05e1-40da-94f9-e8ae0161800f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26973
27535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2697327535
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3067960052
Short name T1086
Test name
Test status
Simulation time 8411759221 ps
CPU time 11.01 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:46 PM PDT 24
Peak memory 204772 kb
Host smart-9b5dfdf8-836b-4648-a7b9-52f1d54ff163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30679
60052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3067960052
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2470520693
Short name T388
Test name
Test status
Simulation time 8442306288 ps
CPU time 12.12 seconds
Started May 19 02:04:19 PM PDT 24
Finished May 19 02:04:34 PM PDT 24
Peak memory 204852 kb
Host smart-b682993f-eabf-4108-b48f-51044858d589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24705
20693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2470520693
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.4148744982
Short name T929
Test name
Test status
Simulation time 8414460989 ps
CPU time 10.94 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:46 PM PDT 24
Peak memory 204816 kb
Host smart-c55b24f9-d79e-4fa1-9927-32aafb5c03a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
44982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.4148744982
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.743949954
Short name T1034
Test name
Test status
Simulation time 8365789722 ps
CPU time 10.86 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204848 kb
Host smart-1b2c4a04-e224-4d9e-86eb-c3e14473a6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74394
9954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.743949954
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1171841019
Short name T163
Test name
Test status
Simulation time 8377695361 ps
CPU time 10.5 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204784 kb
Host smart-3106ad36-d117-4b50-94b3-d965864fc04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11718
41019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1171841019
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.858463859
Short name T1548
Test name
Test status
Simulation time 8366753409 ps
CPU time 10.95 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204824 kb
Host smart-a0fd4a4f-56fd-41f8-9753-d301dee1859d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85846
3859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.858463859
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3491534530
Short name T339
Test name
Test status
Simulation time 8424014113 ps
CPU time 10.96 seconds
Started May 19 02:04:18 PM PDT 24
Finished May 19 02:04:32 PM PDT 24
Peak memory 204900 kb
Host smart-d9304cfb-eea6-46ca-bfe3-e730e03e5a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34915
34530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3491534530
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3032752528
Short name T398
Test name
Test status
Simulation time 8463884140 ps
CPU time 11.51 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204756 kb
Host smart-b46f81fe-0ff3-4fb6-a275-c22e6c957588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327
52528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3032752528
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3409004810
Short name T677
Test name
Test status
Simulation time 8475193809 ps
CPU time 11.41 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:57 PM PDT 24
Peak memory 204872 kb
Host smart-577170b6-d37a-4150-b387-d388a3fb2076
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3409004810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3409004810
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.2678095935
Short name T1254
Test name
Test status
Simulation time 8382577403 ps
CPU time 10.84 seconds
Started May 19 02:04:41 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204856 kb
Host smart-4d32c65c-8a91-45ec-af3f-9228496329e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2678095935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.2678095935
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1102038592
Short name T502
Test name
Test status
Simulation time 8421678912 ps
CPU time 10.67 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204888 kb
Host smart-d12fbda7-a340-437c-84e5-76adceea9b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11020
38592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1102038592
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4116854825
Short name T1189
Test name
Test status
Simulation time 8395129323 ps
CPU time 10.85 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204772 kb
Host smart-4397fede-12f2-4cca-874d-1b44d94e46f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41168
54825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4116854825
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.779777744
Short name T1087
Test name
Test status
Simulation time 9068617283 ps
CPU time 12.4 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204868 kb
Host smart-076c9ab2-b712-4d3b-9017-3fe49e7d69ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77977
7744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.779777744
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2025814163
Short name T318
Test name
Test status
Simulation time 8363867152 ps
CPU time 11.67 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204800 kb
Host smart-7431b301-0135-4a7f-b253-8c525707772a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
14163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2025814163
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2137317678
Short name T995
Test name
Test status
Simulation time 8383179487 ps
CPU time 10.95 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204872 kb
Host smart-02a74411-5c26-423d-bdc5-06f04601823a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
17678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2137317678
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1884520128
Short name T155
Test name
Test status
Simulation time 9120938456 ps
CPU time 11.91 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204808 kb
Host smart-adada7ae-b53b-4c92-89dc-b229335e94f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
20128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1884520128
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.858858575
Short name T828
Test name
Test status
Simulation time 8445215418 ps
CPU time 12.5 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204808 kb
Host smart-057532d7-6591-409e-b02c-673ce92d62d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85885
8575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.858858575
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1204080122
Short name T348
Test name
Test status
Simulation time 8416692214 ps
CPU time 10.59 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204844 kb
Host smart-8a7f4324-3e9b-4705-a94c-1d1793f0acb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12040
80122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1204080122
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2618289683
Short name T467
Test name
Test status
Simulation time 8373197739 ps
CPU time 11.9 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:57 PM PDT 24
Peak memory 204664 kb
Host smart-24c0bc00-a8b5-47e5-a759-a42fbbb1d6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26182
89683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2618289683
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3317842934
Short name T609
Test name
Test status
Simulation time 8404135801 ps
CPU time 10.78 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204884 kb
Host smart-c0c0b8a4-6480-4da5-8802-9a0dbcf06b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33178
42934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3317842934
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2474718503
Short name T477
Test name
Test status
Simulation time 8476546960 ps
CPU time 11.66 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204848 kb
Host smart-6ac0902f-3d18-4a4b-ac90-7c39ee132737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24747
18503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2474718503
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3015764510
Short name T833
Test name
Test status
Simulation time 11571317067 ps
CPU time 15.32 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204876 kb
Host smart-bb8ecd1d-94be-470b-902f-1a1e20611d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30157
64510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3015764510
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2375700523
Short name T405
Test name
Test status
Simulation time 8429358446 ps
CPU time 13.55 seconds
Started May 19 02:04:41 PM PDT 24
Finished May 19 02:04:58 PM PDT 24
Peak memory 204728 kb
Host smart-3d5f08f0-f94e-4628-87dd-7c227f02fc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
00523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2375700523
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.274537035
Short name T1451
Test name
Test status
Simulation time 8393077313 ps
CPU time 11.49 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204824 kb
Host smart-e5abc831-bfa3-4cc4-8304-94e5eb8727a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.274537035
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.932587542
Short name T1247
Test name
Test status
Simulation time 8456443342 ps
CPU time 11.63 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204868 kb
Host smart-3a8856c3-f0fd-4712-a7d6-d8201b070298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93258
7542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.932587542
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.4131941790
Short name T654
Test name
Test status
Simulation time 8432074582 ps
CPU time 11.24 seconds
Started May 19 02:04:33 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204868 kb
Host smart-bc43a63f-9100-42ad-90a5-03c372bc4892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41319
41790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.4131941790
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.4048934620
Short name T1569
Test name
Test status
Simulation time 8370013308 ps
CPU time 11.35 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204804 kb
Host smart-72c1412f-a1ce-4201-9c83-9cfa07b1da19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40489
34620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.4048934620
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3850859133
Short name T797
Test name
Test status
Simulation time 8387361624 ps
CPU time 12.15 seconds
Started May 19 02:04:16 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 204848 kb
Host smart-23054990-7b05-4e73-aafe-34d1c8e5693f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
59133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3850859133
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3322869840
Short name T156
Test name
Test status
Simulation time 8439520916 ps
CPU time 11.75 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204860 kb
Host smart-b9013a09-dd47-4f1a-91db-a9c8ad7ee742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
69840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3322869840
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.2500149580
Short name T1573
Test name
Test status
Simulation time 8389653575 ps
CPU time 10.79 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204808 kb
Host smart-1ec5fd6f-4bc8-4946-b1b7-8418f0a2a62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25001
49580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.2500149580
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.386543445
Short name T1168
Test name
Test status
Simulation time 8369135552 ps
CPU time 10.5 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204780 kb
Host smart-f68cf549-b9d1-4d9c-a6c2-9cb7a5a098e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654
3445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.386543445
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.890019106
Short name T1065
Test name
Test status
Simulation time 8367493823 ps
CPU time 11.32 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:39 PM PDT 24
Peak memory 204816 kb
Host smart-f07bc1c5-8c4f-4cc4-9138-4dc3e33a55d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89001
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.890019106
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1170661609
Short name T239
Test name
Test status
Simulation time 14617337895 ps
CPU time 22.87 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204796 kb
Host smart-d22c19d6-03af-456c-beca-33111a3ed9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11706
61609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1170661609
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2690547580
Short name T1580
Test name
Test status
Simulation time 8452833215 ps
CPU time 11.18 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204820 kb
Host smart-43404f0d-77b0-4388-a265-da6eba8c8bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26905
47580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2690547580
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3366153242
Short name T345
Test name
Test status
Simulation time 8462508214 ps
CPU time 11.17 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204784 kb
Host smart-29be7b68-2fdd-4173-9505-bff9031e3e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
53242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3366153242
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.3291862469
Short name T1775
Test name
Test status
Simulation time 8427774658 ps
CPU time 11.58 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204776 kb
Host smart-867b6c5a-cebf-4fef-a447-49ecf9fe0b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
62469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.3291862469
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2912800892
Short name T1529
Test name
Test status
Simulation time 8407436751 ps
CPU time 11.21 seconds
Started May 19 02:04:23 PM PDT 24
Finished May 19 02:04:38 PM PDT 24
Peak memory 204728 kb
Host smart-997c33dd-20ab-4486-a770-575f8063aeda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29128
00892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2912800892
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.886424410
Short name T160
Test name
Test status
Simulation time 8376158237 ps
CPU time 10.27 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204772 kb
Host smart-097f2b1e-216f-41c9-8772-0accebc866b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88642
4410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.886424410
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2061464950
Short name T940
Test name
Test status
Simulation time 8376391467 ps
CPU time 10.81 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204712 kb
Host smart-702608f8-0b92-4ec9-8e9b-2aca89592174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
64950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2061464950
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1716137237
Short name T756
Test name
Test status
Simulation time 8469484166 ps
CPU time 13.21 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204868 kb
Host smart-db70cf76-8643-4322-804b-2b11470d6d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
37237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1716137237
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3383065392
Short name T693
Test name
Test status
Simulation time 8445391501 ps
CPU time 11.68 seconds
Started May 19 02:04:26 PM PDT 24
Finished May 19 02:04:41 PM PDT 24
Peak memory 204832 kb
Host smart-5595df27-cb4f-465b-aa11-5a57a5d8ac84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
65392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3383065392
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1127142843
Short name T1492
Test name
Test status
Simulation time 8381143065 ps
CPU time 10.92 seconds
Started May 19 02:04:19 PM PDT 24
Finished May 19 02:04:33 PM PDT 24
Peak memory 204796 kb
Host smart-007c9d7c-fc96-468e-8f09-697ace992761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11271
42843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1127142843
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.252715273
Short name T482
Test name
Test status
Simulation time 8474160915 ps
CPU time 11.77 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204660 kb
Host smart-62d7ae07-204e-4c3c-8269-880e2c716ff7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=252715273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.252715273
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3666149200
Short name T780
Test name
Test status
Simulation time 8377362278 ps
CPU time 10.83 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204852 kb
Host smart-e94e4edd-3160-402d-a8b0-39026b31f775
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3666149200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3666149200
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.1471037277
Short name T873
Test name
Test status
Simulation time 8431965018 ps
CPU time 10.71 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204840 kb
Host smart-e912d612-ac2b-4c69-af7c-079c5564501e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14710
37277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.1471037277
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1941128649
Short name T1083
Test name
Test status
Simulation time 8381671702 ps
CPU time 10.51 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204764 kb
Host smart-82296e76-e8d0-48c0-9139-e5ffe79cdd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19411
28649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1941128649
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2650516990
Short name T85
Test name
Test status
Simulation time 8405005691 ps
CPU time 11.12 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 205012 kb
Host smart-db4ed02b-3a5a-43ad-857b-52d21420b6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
16990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2650516990
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1357682315
Short name T1302
Test name
Test status
Simulation time 9047620641 ps
CPU time 14.53 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204856 kb
Host smart-c77c0927-8e8a-40e7-9f79-c7ad9b55f2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13576
82315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1357682315
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1722303256
Short name T849
Test name
Test status
Simulation time 8420508136 ps
CPU time 11.01 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 204836 kb
Host smart-c22d1424-569d-4b69-a8fe-d6fa26e7cd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17223
03256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1722303256
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.4267622195
Short name T1330
Test name
Test status
Simulation time 8430810150 ps
CPU time 12.41 seconds
Started May 19 02:04:33 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204728 kb
Host smart-844b7de4-dac7-46d8-9c5c-09e03009574c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
22195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.4267622195
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.4258767351
Short name T1178
Test name
Test status
Simulation time 9069725726 ps
CPU time 11.37 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204796 kb
Host smart-a2fd49ab-32cf-4cc3-881b-52601b9ba271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42587
67351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.4258767351
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.188286008
Short name T375
Test name
Test status
Simulation time 8538991539 ps
CPU time 12.13 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204760 kb
Host smart-c65d9326-6a05-4a9b-a722-51d7a75505e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18828
6008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.188286008
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3511809129
Short name T1411
Test name
Test status
Simulation time 8521145431 ps
CPU time 10.7 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204872 kb
Host smart-5dc15b53-13d8-406c-a543-9d7c2050817b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35118
09129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3511809129
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.148654266
Short name T1501
Test name
Test status
Simulation time 8363823528 ps
CPU time 11.78 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:46 PM PDT 24
Peak memory 205012 kb
Host smart-9faa91cf-8083-41a5-8663-5489270d3345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14865
4266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.148654266
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1816635649
Short name T757
Test name
Test status
Simulation time 8422913889 ps
CPU time 13.51 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204872 kb
Host smart-08a39af4-2a84-4d89-ba36-abf1ef15d743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18166
35649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1816635649
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2745745129
Short name T656
Test name
Test status
Simulation time 8424432562 ps
CPU time 10.67 seconds
Started May 19 02:04:25 PM PDT 24
Finished May 19 02:04:39 PM PDT 24
Peak memory 204828 kb
Host smart-a9704822-b7f0-4e16-907a-f9bedbb91299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
45129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2745745129
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1912075745
Short name T333
Test name
Test status
Simulation time 11567728403 ps
CPU time 13.96 seconds
Started May 19 02:04:31 PM PDT 24
Finished May 19 02:04:48 PM PDT 24
Peak memory 204868 kb
Host smart-376d1362-2019-4a3d-b0d1-b81710df899a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
75745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1912075745
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.356112437
Short name T1449
Test name
Test status
Simulation time 8412958313 ps
CPU time 11.95 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204828 kb
Host smart-3025eb72-0aba-4db5-831e-f049aaf240bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35611
2437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.356112437
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1994227339
Short name T1367
Test name
Test status
Simulation time 8402428359 ps
CPU time 13.26 seconds
Started May 19 02:04:24 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204748 kb
Host smart-72c1b9be-29b5-4bc7-98c1-dbd777b51cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19942
27339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1994227339
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1977741664
Short name T133
Test name
Test status
Simulation time 8411844792 ps
CPU time 11.74 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:44 PM PDT 24
Peak memory 205072 kb
Host smart-98a3856a-71a2-4dc4-a9b8-8a01c22b7973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19777
41664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1977741664
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4180654972
Short name T1133
Test name
Test status
Simulation time 8416639453 ps
CPU time 11.51 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204788 kb
Host smart-4cd97012-3308-4611-817d-f17911d0eca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
54972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4180654972
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1685353465
Short name T813
Test name
Test status
Simulation time 8378541016 ps
CPU time 11.62 seconds
Started May 19 02:04:56 PM PDT 24
Finished May 19 02:05:09 PM PDT 24
Peak memory 204744 kb
Host smart-5fbf46d7-d6b2-43e3-90f2-9b80b2859338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
53465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1685353465
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4264414504
Short name T717
Test name
Test status
Simulation time 8417847780 ps
CPU time 11.33 seconds
Started May 19 02:04:33 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204868 kb
Host smart-c7340850-5694-4c7b-b2c8-997c64f9e2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644
14504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4264414504
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2625872515
Short name T162
Test name
Test status
Simulation time 8426166966 ps
CPU time 10.64 seconds
Started May 19 02:04:29 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204736 kb
Host smart-2dec87dd-4272-45e9-b5f5-902959c33cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26258
72515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2625872515
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.3903346681
Short name T938
Test name
Test status
Simulation time 8427303514 ps
CPU time 11.08 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204748 kb
Host smart-02a147fc-03a1-4e14-9206-4271682ad8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39033
46681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.3903346681
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1027026925
Short name T1723
Test name
Test status
Simulation time 8367434280 ps
CPU time 11 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204732 kb
Host smart-ab19994a-ee95-432e-a58f-9066e20d8dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
26925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1027026925
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2701754051
Short name T427
Test name
Test status
Simulation time 8364734335 ps
CPU time 12.43 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 205008 kb
Host smart-71000272-4e3e-4d08-b64e-de2afdfb7660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27017
54051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2701754051
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.376679204
Short name T1711
Test name
Test status
Simulation time 15918402076 ps
CPU time 29.48 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204820 kb
Host smart-ac10a389-a86a-423a-9bc8-bb16343f13ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37667
9204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.376679204
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1704100438
Short name T1357
Test name
Test status
Simulation time 8436501193 ps
CPU time 11.61 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 205048 kb
Host smart-1badcc8c-5c0f-401a-89e9-5211892afa5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17041
00438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1704100438
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.224163873
Short name T1148
Test name
Test status
Simulation time 8440903740 ps
CPU time 13.35 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204816 kb
Host smart-b6ccffc7-ae55-4bfd-a978-14a2d570edaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22416
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.224163873
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.2073350943
Short name T775
Test name
Test status
Simulation time 8395785753 ps
CPU time 11.9 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:57 PM PDT 24
Peak memory 204816 kb
Host smart-0b2dd152-65cb-4653-b6d1-020a3084cc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20733
50943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.2073350943
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3459194217
Short name T1176
Test name
Test status
Simulation time 8381684128 ps
CPU time 10.65 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:50 PM PDT 24
Peak memory 204760 kb
Host smart-9cb2d67f-89cd-4dff-8ef3-7c1f417c75bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34591
94217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3459194217
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1785325166
Short name T1639
Test name
Test status
Simulation time 8380330233 ps
CPU time 10.6 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:40 PM PDT 24
Peak memory 204852 kb
Host smart-ca4a51ad-51f5-4493-b5a1-6454ca551d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
25166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1785325166
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1344912552
Short name T648
Test name
Test status
Simulation time 8375013617 ps
CPU time 11.1 seconds
Started May 19 02:04:30 PM PDT 24
Finished May 19 02:04:43 PM PDT 24
Peak memory 204772 kb
Host smart-0cee9dfc-13da-40e7-bc11-af4ed2e06e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
12552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1344912552
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2202037861
Short name T1670
Test name
Test status
Simulation time 8448974378 ps
CPU time 12.75 seconds
Started May 19 02:04:33 PM PDT 24
Finished May 19 02:04:48 PM PDT 24
Peak memory 204884 kb
Host smart-380a4e5a-8143-4116-a860-3fa70566b436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
37861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2202037861
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1519198996
Short name T305
Test name
Test status
Simulation time 8425169623 ps
CPU time 12.05 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204844 kb
Host smart-0a02e73a-9ec9-4479-be00-a57c24ab2a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191
98996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1519198996
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.624171048
Short name T999
Test name
Test status
Simulation time 8404489844 ps
CPU time 12.39 seconds
Started May 19 02:04:27 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204860 kb
Host smart-1e5e6dd7-ca0e-433c-a06f-3c35ac3cb978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62417
1048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.624171048
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3552080608
Short name T1572
Test name
Test status
Simulation time 8463446807 ps
CPU time 11.45 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204852 kb
Host smart-3eddd118-ff48-45b7-a939-839203f2b635
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3552080608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3552080608
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.187404161
Short name T1762
Test name
Test status
Simulation time 8379960782 ps
CPU time 13.6 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204776 kb
Host smart-174e54a2-195e-41b6-843b-d4f97f344595
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=187404161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.187404161
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.1008758741
Short name T1203
Test name
Test status
Simulation time 8464544964 ps
CPU time 11.08 seconds
Started May 19 02:04:47 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204780 kb
Host smart-6106d6b8-9fa8-4b8a-83ba-25d35a965616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
58741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.1008758741
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2895925541
Short name T1345
Test name
Test status
Simulation time 8404668429 ps
CPU time 12.05 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:50 PM PDT 24
Peak memory 204852 kb
Host smart-d21dce6f-b0e9-43ae-ae3a-759dee81f969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28959
25541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2895925541
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.348776469
Short name T37
Test name
Test status
Simulation time 8379453692 ps
CPU time 11.29 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:50 PM PDT 24
Peak memory 204784 kb
Host smart-4eae55c3-e063-4f0e-8e95-bf9f6130e8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
6469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.348776469
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1140751587
Short name T676
Test name
Test status
Simulation time 8707316181 ps
CPU time 11.4 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204868 kb
Host smart-d8218182-bf47-4ac8-8ebd-97ecb2e0d4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11407
51587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1140751587
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.4120929578
Short name T1679
Test name
Test status
Simulation time 8401167096 ps
CPU time 11.22 seconds
Started May 19 02:04:33 PM PDT 24
Finished May 19 02:04:48 PM PDT 24
Peak memory 204780 kb
Host smart-fefd75d4-e5ac-4906-bcbb-b6b5ef33ae25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
29578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4120929578
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1617988086
Short name T1721
Test name
Test status
Simulation time 8402763682 ps
CPU time 11.41 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204708 kb
Host smart-a940f1d8-5ea3-47d7-9c37-d6de42dab09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
88086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1617988086
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.867583170
Short name T587
Test name
Test status
Simulation time 8389013870 ps
CPU time 11.87 seconds
Started May 19 02:04:40 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204772 kb
Host smart-f68071e3-8817-494e-a5bd-de3f267098f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86758
3170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.867583170
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3058225102
Short name T778
Test name
Test status
Simulation time 8388073980 ps
CPU time 10.44 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204760 kb
Host smart-f98d73df-11e0-43bf-8dc6-4d63954ba7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
25102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3058225102
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1020857856
Short name T336
Test name
Test status
Simulation time 8405444087 ps
CPU time 10.39 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204852 kb
Host smart-43b54d4a-2e29-4358-b630-bcebbab3be97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10208
57856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1020857856
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3678795726
Short name T772
Test name
Test status
Simulation time 8430569402 ps
CPU time 10.79 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204740 kb
Host smart-a3fa0739-1339-444b-ad87-dfa49fb8ffc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
95726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3678795726
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3973537604
Short name T715
Test name
Test status
Simulation time 11580812096 ps
CPU time 14.04 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 205016 kb
Host smart-707b3222-2d2f-45ba-87e7-ff97fe818177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39735
37604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3973537604
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2285162078
Short name T110
Test name
Test status
Simulation time 8453828783 ps
CPU time 11.63 seconds
Started May 19 02:04:40 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204992 kb
Host smart-85b92817-a675-401f-ad55-8347e27ed8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22851
62078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2285162078
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.889680070
Short name T1505
Test name
Test status
Simulation time 8378995297 ps
CPU time 11.34 seconds
Started May 19 02:04:28 PM PDT 24
Finished May 19 02:04:42 PM PDT 24
Peak memory 204828 kb
Host smart-4df14355-457f-45c2-85dc-6dc6312dea6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88968
0070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.889680070
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.477862293
Short name T142
Test name
Test status
Simulation time 8449174537 ps
CPU time 11.07 seconds
Started May 19 02:04:41 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204764 kb
Host smart-f4bd7465-3d04-4221-ac11-64639c701937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47786
2293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.477862293
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2191517619
Short name T645
Test name
Test status
Simulation time 8427917657 ps
CPU time 10.31 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:48 PM PDT 24
Peak memory 205072 kb
Host smart-b7c81dab-2f94-4bd5-8112-a1398eceb397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
17619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2191517619
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.883921225
Short name T843
Test name
Test status
Simulation time 8446383537 ps
CPU time 11.06 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:48 PM PDT 24
Peak memory 204872 kb
Host smart-047a437b-35eb-46b0-8448-8f59be3e5c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88392
1225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.883921225
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3607413122
Short name T491
Test name
Test status
Simulation time 8401984774 ps
CPU time 10.79 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 205024 kb
Host smart-f598aa2a-114e-4915-bc91-64167f8cc1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
13122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3607413122
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.4151403579
Short name T1466
Test name
Test status
Simulation time 8371111455 ps
CPU time 10.9 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:01 PM PDT 24
Peak memory 204812 kb
Host smart-485c82c3-cc52-4e69-a2ce-ebd86cc1127c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41514
03579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.4151403579
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.2593007515
Short name T785
Test name
Test status
Simulation time 8382034713 ps
CPU time 11.56 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204768 kb
Host smart-59554f5f-85d9-40d7-8112-d8e52e258e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25930
07515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.2593007515
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2372648686
Short name T1012
Test name
Test status
Simulation time 8409572813 ps
CPU time 13.29 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204764 kb
Host smart-fae61a5a-edfe-48e1-b2e0-8ecfabf10d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23726
48686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2372648686
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.791741451
Short name T26
Test name
Test status
Simulation time 8364219188 ps
CPU time 10.59 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204752 kb
Host smart-11e632fa-f4a1-42a7-b9ea-717050a4f873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79174
1451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.791741451
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2167611273
Short name T1400
Test name
Test status
Simulation time 20589313904 ps
CPU time 38.89 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204744 kb
Host smart-22b5b884-9f56-4445-92df-2749c3c23fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21676
11273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2167611273
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2934040476
Short name T725
Test name
Test status
Simulation time 8415237271 ps
CPU time 10.49 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:48 PM PDT 24
Peak memory 204784 kb
Host smart-e92a64fa-4649-477d-b31e-2ca72cde29b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
40476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2934040476
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.990644305
Short name T1094
Test name
Test status
Simulation time 8435720996 ps
CPU time 10.7 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204740 kb
Host smart-eaa69b5d-6a17-4240-83fa-97d4559cb859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99064
4305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.990644305
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1878148688
Short name T1232
Test name
Test status
Simulation time 8387370242 ps
CPU time 10.85 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204816 kb
Host smart-47b52df0-2ad8-4057-a07d-46bef3f496af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
48688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1878148688
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.962987855
Short name T1207
Test name
Test status
Simulation time 8370622645 ps
CPU time 12.37 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:57 PM PDT 24
Peak memory 204772 kb
Host smart-df0b70d7-3f7b-495d-a3c4-2d70e12932e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96298
7855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.962987855
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1923957630
Short name T159
Test name
Test status
Simulation time 8375843333 ps
CPU time 11.04 seconds
Started May 19 02:04:53 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204776 kb
Host smart-0986f3dd-8bc4-42e4-89d0-0d6d102cc226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
57630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1923957630
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3670039710
Short name T994
Test name
Test status
Simulation time 8377424097 ps
CPU time 11.13 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204836 kb
Host smart-2e15f86d-fc6c-47b9-915f-5ecee94d3b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36700
39710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3670039710
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1395479359
Short name T170
Test name
Test status
Simulation time 8423645780 ps
CPU time 12.39 seconds
Started May 19 02:04:40 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204812 kb
Host smart-29cc9623-ca15-4cad-a7a1-6faba7229fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
79359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1395479359
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.488971624
Short name T1089
Test name
Test status
Simulation time 8415678180 ps
CPU time 12.29 seconds
Started May 19 02:04:58 PM PDT 24
Finished May 19 02:05:11 PM PDT 24
Peak memory 204848 kb
Host smart-e8fdcdbc-7c7e-441b-a3ad-256967860ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48897
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.488971624
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3440488097
Short name T1295
Test name
Test status
Simulation time 8407124680 ps
CPU time 10.57 seconds
Started May 19 02:04:46 PM PDT 24
Finished May 19 02:05:03 PM PDT 24
Peak memory 204844 kb
Host smart-c151d2b5-efe1-43ce-aa0a-8ba33b30fa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34404
88097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3440488097
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.2822928229
Short name T1649
Test name
Test status
Simulation time 8478716548 ps
CPU time 11.55 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:49 PM PDT 24
Peak memory 204828 kb
Host smart-97609bb2-38ce-436c-a5a2-154a227b59e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2822928229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.2822928229
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.3453052114
Short name T916
Test name
Test status
Simulation time 8383249301 ps
CPU time 10.67 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204852 kb
Host smart-f4dd6072-6d66-418f-b2b8-c47d4f675ba3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3453052114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.3453052114
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.3566603112
Short name T442
Test name
Test status
Simulation time 8419522981 ps
CPU time 11.34 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204800 kb
Host smart-7e998112-5822-4d2a-aae7-0884a6805acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35666
03112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.3566603112
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3806178893
Short name T1415
Test name
Test status
Simulation time 8398609118 ps
CPU time 11.54 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:11 PM PDT 24
Peak memory 204780 kb
Host smart-ddbab8b5-90d2-4818-a6e6-3b0e7c47a026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38061
78893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3806178893
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3024402600
Short name T1456
Test name
Test status
Simulation time 8373955135 ps
CPU time 11.62 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204780 kb
Host smart-0a38152c-1f0d-448a-89b9-92e13fa9acff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
02600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3024402600
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.3044942552
Short name T503
Test name
Test status
Simulation time 8569509446 ps
CPU time 12.75 seconds
Started May 19 02:04:40 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204828 kb
Host smart-3b0cde2a-5102-4285-b240-a76d99bb7b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30449
42552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.3044942552
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3234093865
Short name T686
Test name
Test status
Simulation time 8363164464 ps
CPU time 11.47 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204616 kb
Host smart-be463ecb-f5b6-4d7b-a158-326cbd0feec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32340
93865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3234093865
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3060953204
Short name T1269
Test name
Test status
Simulation time 8388009623 ps
CPU time 10.59 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 204836 kb
Host smart-64ce4ee1-efe7-4de2-ab62-32446b7282d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
53204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3060953204
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.4281346072
Short name T432
Test name
Test status
Simulation time 9156359881 ps
CPU time 12.11 seconds
Started May 19 02:04:56 PM PDT 24
Finished May 19 02:05:09 PM PDT 24
Peak memory 205052 kb
Host smart-528dae5e-ec9b-403c-8d40-caa389f5cfcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813
46072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.4281346072
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.391593683
Short name T957
Test name
Test status
Simulation time 8412441588 ps
CPU time 14.32 seconds
Started May 19 02:04:34 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204776 kb
Host smart-72ac7e2c-5cb2-4266-919a-174c4caddbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159
3683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.391593683
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1320662321
Short name T1213
Test name
Test status
Simulation time 8442308423 ps
CPU time 10.82 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204824 kb
Host smart-f1a5ca0b-a834-4ba7-8a74-dd25489d5f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
62321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1320662321
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2890121305
Short name T1571
Test name
Test status
Simulation time 8377638101 ps
CPU time 13.22 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204840 kb
Host smart-c3a89f16-a3ee-4dc1-82be-84032f456948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
21305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2890121305
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3113956403
Short name T674
Test name
Test status
Simulation time 8445502088 ps
CPU time 11.57 seconds
Started May 19 02:04:32 PM PDT 24
Finished May 19 02:04:47 PM PDT 24
Peak memory 204788 kb
Host smart-8dd3e8cd-c3e4-4471-ab5c-566dabf4b022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31139
56403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3113956403
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.4015195374
Short name T400
Test name
Test status
Simulation time 8415672693 ps
CPU time 11.01 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204828 kb
Host smart-bc29b78b-fce2-4ad7-9cca-b87871256df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
95374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.4015195374
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1805708952
Short name T1313
Test name
Test status
Simulation time 11537582167 ps
CPU time 14.35 seconds
Started May 19 02:05:05 PM PDT 24
Finished May 19 02:05:20 PM PDT 24
Peak memory 204788 kb
Host smart-f5352ef9-f3a7-4f77-99a9-04abfadf4942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18057
08952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1805708952
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1790547202
Short name T1155
Test name
Test status
Simulation time 8437874944 ps
CPU time 11.42 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204808 kb
Host smart-3f6eb994-e2f8-4fd7-aed4-3309fda07fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17905
47202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1790547202
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2454590576
Short name T1333
Test name
Test status
Simulation time 8394776918 ps
CPU time 10.5 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204808 kb
Host smart-eb5017a0-771d-406b-a19b-15cce42a13d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545
90576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2454590576
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.792946297
Short name T123
Test name
Test status
Simulation time 8415309092 ps
CPU time 12.12 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204776 kb
Host smart-5d431966-a907-4736-a3a1-4e0f04ae1e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79294
6297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.792946297
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1284567154
Short name T429
Test name
Test status
Simulation time 8436586180 ps
CPU time 12.24 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 205004 kb
Host smart-56ceadfb-53b2-45fa-ab47-1f5a77e8b7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12845
67154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1284567154
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1875319431
Short name T1736
Test name
Test status
Simulation time 8386325703 ps
CPU time 10.98 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204856 kb
Host smart-597869de-ce20-459b-875e-03c32b15ae2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
19431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1875319431
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2271054335
Short name T826
Test name
Test status
Simulation time 8411498521 ps
CPU time 12.98 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204780 kb
Host smart-69db7aee-9775-4067-8e2a-4bd704442e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22710
54335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2271054335
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3844200621
Short name T158
Test name
Test status
Simulation time 8399188224 ps
CPU time 11.02 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204860 kb
Host smart-5b3ed98e-1d10-46a6-8f4c-07ceee8eebfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38442
00621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3844200621
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.2355770109
Short name T1525
Test name
Test status
Simulation time 8402893094 ps
CPU time 11.3 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204788 kb
Host smart-b0ed4c71-cf8f-4b21-9fef-ab4aabc8f78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
70109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.2355770109
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3672870196
Short name T1200
Test name
Test status
Simulation time 8371382508 ps
CPU time 11.83 seconds
Started May 19 02:04:46 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204780 kb
Host smart-2901ba3b-2f1b-4873-92ab-3effafca213d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728
70196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3672870196
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.718617365
Short name T11
Test name
Test status
Simulation time 8370778795 ps
CPU time 10.5 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:17 PM PDT 24
Peak memory 204692 kb
Host smart-dee3cce9-2c7a-41f9-a92d-0e9ac49f0614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71861
7365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.718617365
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.738064773
Short name T1137
Test name
Test status
Simulation time 8396112903 ps
CPU time 10.82 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204844 kb
Host smart-7b6230c8-61c7-4bf3-b4c3-7af9a4a4f4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73806
4773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.738064773
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1807861419
Short name T79
Test name
Test status
Simulation time 8440529883 ps
CPU time 10.76 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204812 kb
Host smart-22fbc5be-50cf-4780-81c2-f268ad3d5109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078
61419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1807861419
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.23506160
Short name T1551
Test name
Test status
Simulation time 8448980489 ps
CPU time 11.49 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204788 kb
Host smart-7a7b0be6-1ee0-49fc-b69f-d0058010a0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.23506160
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1493013168
Short name T907
Test name
Test status
Simulation time 8433591511 ps
CPU time 11.46 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204708 kb
Host smart-218cc09f-0838-4466-8abd-0b24a1da0a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14930
13168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1493013168
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3932281966
Short name T1681
Test name
Test status
Simulation time 8391548041 ps
CPU time 10.45 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204912 kb
Host smart-e318cd0b-9461-40a2-b3ec-a3f187252d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39322
81966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3932281966
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2623195442
Short name T1217
Test name
Test status
Simulation time 8362732052 ps
CPU time 11.08 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 204768 kb
Host smart-f6f4d0db-158b-4d26-ba47-ff184bd415a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26231
95442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2623195442
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.346085780
Short name T175
Test name
Test status
Simulation time 8453252817 ps
CPU time 12.02 seconds
Started May 19 02:04:52 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204856 kb
Host smart-051ea85a-a3de-4232-8189-171372108122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
5780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.346085780
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1882278972
Short name T1326
Test name
Test status
Simulation time 8398083452 ps
CPU time 10.94 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 204736 kb
Host smart-ea6f837a-f814-4b99-b260-fe9393c8295b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822
78972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1882278972
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1891453696
Short name T1358
Test name
Test status
Simulation time 8373519559 ps
CPU time 11.51 seconds
Started May 19 02:04:41 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204720 kb
Host smart-92aab81c-f711-4d58-9405-f4d62d0c6d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18914
53696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1891453696
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.29409824
Short name T1557
Test name
Test status
Simulation time 8472000262 ps
CPU time 10.6 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204860 kb
Host smart-081e0898-e1f4-40f9-bf53-bb55ba3b27d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=29409824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.29409824
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.581686454
Short name T612
Test name
Test status
Simulation time 8379030910 ps
CPU time 12.35 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:17 PM PDT 24
Peak memory 204756 kb
Host smart-f717a2ee-8ef0-4ba2-aa17-0b757f28ab50
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=581686454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.581686454
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.3809390293
Short name T299
Test name
Test status
Simulation time 8391858788 ps
CPU time 10.74 seconds
Started May 19 02:04:47 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204844 kb
Host smart-80fc8b56-2aba-4916-8d24-7d7b47838acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38093
90293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3809390293
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2216590593
Short name T1401
Test name
Test status
Simulation time 8376716575 ps
CPU time 10.96 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 204736 kb
Host smart-e26bc173-518b-4dd3-9704-5b69788fd18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22165
90593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2216590593
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3309872248
Short name T1689
Test name
Test status
Simulation time 9701845055 ps
CPU time 12.71 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204756 kb
Host smart-1a36b9db-cff3-4b76-8576-a2ae2304b23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33098
72248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3309872248
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.175956275
Short name T1015
Test name
Test status
Simulation time 8396643940 ps
CPU time 10.84 seconds
Started May 19 02:04:38 PM PDT 24
Finished May 19 02:04:52 PM PDT 24
Peak memory 204716 kb
Host smart-0c95507f-8c4e-43f2-9bc5-8f19dd1e3a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17595
6275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.175956275
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2165447295
Short name T403
Test name
Test status
Simulation time 8387953275 ps
CPU time 11.25 seconds
Started May 19 02:04:46 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204848 kb
Host smart-55901ec8-4cbc-44b8-aae7-955713584776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21654
47295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2165447295
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1464784018
Short name T328
Test name
Test status
Simulation time 8438219768 ps
CPU time 12.38 seconds
Started May 19 02:04:35 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204788 kb
Host smart-fcb251e7-6c16-4a2f-8a28-e0e41e46577d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647
84018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1464784018
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2044458295
Short name T1298
Test name
Test status
Simulation time 8463970925 ps
CPU time 12.43 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204800 kb
Host smart-970274bb-3383-4ad8-b032-640ddfb917a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
58295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2044458295
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3745278481
Short name T1070
Test name
Test status
Simulation time 8373200516 ps
CPU time 11.38 seconds
Started May 19 02:05:07 PM PDT 24
Finished May 19 02:05:20 PM PDT 24
Peak memory 204720 kb
Host smart-76123df8-7956-4caa-9be7-2dbb58720f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
78481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3745278481
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.336131750
Short name T560
Test name
Test status
Simulation time 8433239318 ps
CPU time 11.15 seconds
Started May 19 02:04:57 PM PDT 24
Finished May 19 02:05:09 PM PDT 24
Peak memory 204800 kb
Host smart-8d86f73c-2331-466d-a99a-b7e2fbb779d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613
1750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.336131750
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2468061179
Short name T397
Test name
Test status
Simulation time 8417429541 ps
CPU time 12.05 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:03 PM PDT 24
Peak memory 204800 kb
Host smart-3b09ab2d-8216-498e-b815-d2ca2b1cec1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
61179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2468061179
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.422711613
Short name T108
Test name
Test status
Simulation time 8423680302 ps
CPU time 13.11 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204816 kb
Host smart-4abbda05-c4f3-40ae-9427-ce20555f6091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
1613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.422711613
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.68821386
Short name T422
Test name
Test status
Simulation time 8394221743 ps
CPU time 11.19 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:57 PM PDT 24
Peak memory 204836 kb
Host smart-a76230ad-97d4-40bf-8e73-5d5be6f95233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68821
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.68821386
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1384071761
Short name T136
Test name
Test status
Simulation time 8442157655 ps
CPU time 10.96 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:01 PM PDT 24
Peak memory 204844 kb
Host smart-c98d86c5-35ff-4789-be6f-a395d554f087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
71761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1384071761
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3106787826
Short name T732
Test name
Test status
Simulation time 8415750729 ps
CPU time 10.96 seconds
Started May 19 02:04:56 PM PDT 24
Finished May 19 02:05:08 PM PDT 24
Peak memory 204884 kb
Host smart-bcbe3458-bfe9-4c88-8283-c800fe363dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
87826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3106787826
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2375438978
Short name T1654
Test name
Test status
Simulation time 8445466454 ps
CPU time 10.46 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:00 PM PDT 24
Peak memory 204736 kb
Host smart-87a223f7-72a9-4087-a1d4-5fed169033f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
38978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2375438978
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2374359112
Short name T1151
Test name
Test status
Simulation time 8392227544 ps
CPU time 11.86 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204844 kb
Host smart-953199c4-4aa0-4386-be8a-19a27da734e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
59112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2374359112
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.223642869
Short name T209
Test name
Test status
Simulation time 8409279937 ps
CPU time 10.45 seconds
Started May 19 02:04:39 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204656 kb
Host smart-6c9b953b-1d4b-432d-bf02-46f0325f3bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22364
2869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.223642869
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.1955868125
Short name T111
Test name
Test status
Simulation time 8426782260 ps
CPU time 10.76 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204780 kb
Host smart-931dbeda-cb9e-4eff-b214-01e8cf418bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19558
68125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.1955868125
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2780933366
Short name T1001
Test name
Test status
Simulation time 8372831607 ps
CPU time 12.76 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:04 PM PDT 24
Peak memory 204800 kb
Host smart-0c2c7e3a-2582-4ada-83f9-e7dcf8ab631e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27809
33366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2780933366
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3990712232
Short name T1215
Test name
Test status
Simulation time 8360110362 ps
CPU time 10.94 seconds
Started May 19 02:04:48 PM PDT 24
Finished May 19 02:05:00 PM PDT 24
Peak memory 204836 kb
Host smart-2f71bf44-48f3-4717-bd1d-3ebb43797dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39907
12232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3990712232
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.4172564000
Short name T115
Test name
Test status
Simulation time 17365619622 ps
CPU time 31.05 seconds
Started May 19 02:04:49 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204780 kb
Host smart-662b15c8-5ec5-4a2f-b4f3-8e4eda9d7c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41725
64000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.4172564000
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4004249895
Short name T437
Test name
Test status
Simulation time 8399264242 ps
CPU time 12.68 seconds
Started May 19 02:04:51 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204852 kb
Host smart-8e8da495-c26b-47ab-8f83-262a288a862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
49895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4004249895
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1867682135
Short name T392
Test name
Test status
Simulation time 8424488755 ps
CPU time 13.67 seconds
Started May 19 02:04:43 PM PDT 24
Finished May 19 02:04:58 PM PDT 24
Peak memory 204744 kb
Host smart-aa0eeae1-6211-4f52-9ab9-123151defd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18676
82135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1867682135
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3990605288
Short name T1761
Test name
Test status
Simulation time 8389489528 ps
CPU time 10.65 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204748 kb
Host smart-0d2e3290-33d9-4316-8357-9a2350eb05c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39906
05288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3990605288
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4142092214
Short name T457
Test name
Test status
Simulation time 8408299668 ps
CPU time 11.9 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204756 kb
Host smart-9414bd34-392b-4590-95e0-3fbf680ac1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41420
92214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4142092214
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.432900073
Short name T1753
Test name
Test status
Simulation time 8373979114 ps
CPU time 11.87 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:13 PM PDT 24
Peak memory 204792 kb
Host smart-0604ad0c-26d4-4bbc-99e8-cbd335e2eef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43290
0073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.432900073
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3702055496
Short name T101
Test name
Test status
Simulation time 8380983308 ps
CPU time 11.08 seconds
Started May 19 02:04:58 PM PDT 24
Finished May 19 02:05:10 PM PDT 24
Peak memory 204760 kb
Host smart-737f8be0-a6b8-46d2-86e3-e3264326afe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37020
55496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3702055496
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3179084180
Short name T161
Test name
Test status
Simulation time 8452469109 ps
CPU time 11.69 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 204840 kb
Host smart-df11eb67-b5f9-423f-934a-6073d5f1ba41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31790
84180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3179084180
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.361042680
Short name T589
Test name
Test status
Simulation time 8418734570 ps
CPU time 13.05 seconds
Started May 19 02:04:40 PM PDT 24
Finished May 19 02:05:00 PM PDT 24
Peak memory 204852 kb
Host smart-2f862438-9c5b-4bb0-912e-19d913388de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36104
2680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.361042680
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4146977843
Short name T1519
Test name
Test status
Simulation time 8386168166 ps
CPU time 10.77 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:14 PM PDT 24
Peak memory 204784 kb
Host smart-da06f6eb-0ece-40da-890e-ea813bfd3b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41469
77843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4146977843
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.84379389
Short name T741
Test name
Test status
Simulation time 8490763416 ps
CPU time 12.38 seconds
Started May 19 02:05:22 PM PDT 24
Finished May 19 02:05:35 PM PDT 24
Peak memory 204816 kb
Host smart-b73352d5-a1c1-490d-8e01-36f09136065a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=84379389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.84379389
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.4002714328
Short name T1667
Test name
Test status
Simulation time 8389420046 ps
CPU time 11.62 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204844 kb
Host smart-4d695bc1-80d4-4b95-a966-fc2adb5fc539
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4002714328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.4002714328
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.2196507829
Short name T551
Test name
Test status
Simulation time 8502920319 ps
CPU time 10.9 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204784 kb
Host smart-7f8abc86-f100-4f78-8f73-ba881f23b51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21965
07829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.2196507829
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3443912770
Short name T513
Test name
Test status
Simulation time 8391004404 ps
CPU time 10.79 seconds
Started May 19 02:04:36 PM PDT 24
Finished May 19 02:04:51 PM PDT 24
Peak memory 204876 kb
Host smart-0c7338d8-1a30-4f75-86de-21df91b4ddee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439
12770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3443912770
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2624687341
Short name T1206
Test name
Test status
Simulation time 8399216473 ps
CPU time 11.86 seconds
Started May 19 02:05:10 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 204992 kb
Host smart-0852d302-607f-4a2c-a238-c3b537d4bcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
87341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2624687341
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2975340995
Short name T1778
Test name
Test status
Simulation time 8451961475 ps
CPU time 10.97 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204884 kb
Host smart-83b2566f-d52f-4561-8469-e7e624c07b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29753
40995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2975340995
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1384143330
Short name T1334
Test name
Test status
Simulation time 8405521095 ps
CPU time 11.48 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 204780 kb
Host smart-38b40023-116b-45ab-ad7c-7f540782de38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13841
43330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1384143330
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3998959512
Short name T1235
Test name
Test status
Simulation time 8385871182 ps
CPU time 10.59 seconds
Started May 19 02:05:01 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204816 kb
Host smart-2ca363b5-0b28-4c8b-9ce9-34c2c19fe139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39989
59512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3998959512
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.16876582
Short name T1146
Test name
Test status
Simulation time 9285943490 ps
CPU time 15.5 seconds
Started May 19 02:04:40 PM PDT 24
Finished May 19 02:04:59 PM PDT 24
Peak memory 204848 kb
Host smart-d7ab7c05-4b36-4271-9079-8a31c6484553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16876
582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.16876582
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2144050122
Short name T1318
Test name
Test status
Simulation time 8409607226 ps
CPU time 11.87 seconds
Started May 19 02:04:53 PM PDT 24
Finished May 19 02:05:07 PM PDT 24
Peak memory 204736 kb
Host smart-6a0b4df8-404a-42e2-b924-0c1676f77c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21440
50122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2144050122
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2287441394
Short name T1636
Test name
Test status
Simulation time 8452951141 ps
CPU time 10.64 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 204828 kb
Host smart-059781c9-eaba-4dba-9452-e0d27ae1b96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874
41394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2287441394
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1081467040
Short name T77
Test name
Test status
Simulation time 8450711076 ps
CPU time 11.35 seconds
Started May 19 02:05:06 PM PDT 24
Finished May 19 02:05:19 PM PDT 24
Peak memory 204784 kb
Host smart-81e4e477-45eb-46be-9013-0dab47358f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10814
67040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1081467040
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2170726290
Short name T1704
Test name
Test status
Simulation time 8392207136 ps
CPU time 10.62 seconds
Started May 19 02:04:42 PM PDT 24
Finished May 19 02:04:55 PM PDT 24
Peak memory 204796 kb
Host smart-d8fd5382-1993-4185-ae65-845fc953be73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21707
26290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2170726290
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1466721762
Short name T490
Test name
Test status
Simulation time 8399477080 ps
CPU time 11.25 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204828 kb
Host smart-65c3c18a-4d76-4491-be90-d5f04d410296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
21762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1466721762
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2640657580
Short name T1036
Test name
Test status
Simulation time 11566106297 ps
CPU time 13.29 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204756 kb
Host smart-6c0774ea-d62a-4d38-8275-7a766297a951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
57580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2640657580
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3756538114
Short name T1712
Test name
Test status
Simulation time 8439785815 ps
CPU time 12.11 seconds
Started May 19 02:04:48 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204772 kb
Host smart-fe069970-a1d0-4379-af65-e48918ea49ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
38114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3756538114
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2152783914
Short name T642
Test name
Test status
Simulation time 8429742648 ps
CPU time 11.13 seconds
Started May 19 02:05:06 PM PDT 24
Finished May 19 02:05:19 PM PDT 24
Peak memory 204796 kb
Host smart-9da4cc0c-445a-4ee1-80cb-dd35c04e2a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21527
83914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2152783914
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2818602667
Short name T106
Test name
Test status
Simulation time 8421951991 ps
CPU time 10.6 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:10 PM PDT 24
Peak memory 204740 kb
Host smart-f97f7d6e-63ad-4a01-a57a-99c10f2ba3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
02667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2818602667
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1970102999
Short name T377
Test name
Test status
Simulation time 8416213420 ps
CPU time 11.47 seconds
Started May 19 02:04:51 PM PDT 24
Finished May 19 02:05:04 PM PDT 24
Peak memory 204856 kb
Host smart-9b88f6a5-66e2-4af2-836c-5aa570decc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
02999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1970102999
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.4060873124
Short name T1672
Test name
Test status
Simulation time 8484282677 ps
CPU time 12.3 seconds
Started May 19 02:04:37 PM PDT 24
Finished May 19 02:04:53 PM PDT 24
Peak memory 205084 kb
Host smart-a5323e5f-7dce-4512-868a-e360b5f7b9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40608
73124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.4060873124
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2800508635
Short name T659
Test name
Test status
Simulation time 8395811405 ps
CPU time 10.83 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204796 kb
Host smart-de62a1b2-b07b-45af-976d-11a0d194edbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
08635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2800508635
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3540324467
Short name T897
Test name
Test status
Simulation time 8401333095 ps
CPU time 11.89 seconds
Started May 19 02:05:13 PM PDT 24
Finished May 19 02:05:26 PM PDT 24
Peak memory 204884 kb
Host smart-77683ca7-47cb-4eb8-9baf-8fed7bbde903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35403
24467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3540324467
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.3957296174
Short name T1474
Test name
Test status
Simulation time 8441273737 ps
CPU time 12.28 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:17 PM PDT 24
Peak memory 204752 kb
Host smart-a20e9241-9bb3-452e-92e5-da49c39a1751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39572
96174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.3957296174
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3380962853
Short name T1566
Test name
Test status
Simulation time 8377133779 ps
CPU time 10.54 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:14 PM PDT 24
Peak memory 204728 kb
Host smart-4f02068e-a399-48d5-83c0-d79224440580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809
62853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3380962853
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1058259697
Short name T979
Test name
Test status
Simulation time 24960228133 ps
CPU time 45.35 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:46 PM PDT 24
Peak memory 204772 kb
Host smart-41711889-9e10-4091-b882-9d95c7124dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10582
59697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1058259697
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3578175096
Short name T1773
Test name
Test status
Simulation time 8416658297 ps
CPU time 10.83 seconds
Started May 19 02:04:45 PM PDT 24
Finished May 19 02:04:58 PM PDT 24
Peak memory 204768 kb
Host smart-6222a8fc-47d1-4063-8344-06be5d2999a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35781
75096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3578175096
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1921089626
Short name T921
Test name
Test status
Simulation time 8451138714 ps
CPU time 10.92 seconds
Started May 19 02:05:01 PM PDT 24
Finished May 19 02:05:13 PM PDT 24
Peak memory 204860 kb
Host smart-29e231a1-57fe-45cb-9bf2-ff0bd6ec5d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210
89626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1921089626
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.885998168
Short name T1251
Test name
Test status
Simulation time 8380803598 ps
CPU time 12.89 seconds
Started May 19 02:05:06 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204724 kb
Host smart-0ea7caae-30cd-4251-902a-60a2f2c69f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88599
8168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.885998168
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3303426148
Short name T41
Test name
Test status
Simulation time 8377556848 ps
CPU time 13.15 seconds
Started May 19 02:04:46 PM PDT 24
Finished May 19 02:05:00 PM PDT 24
Peak memory 204784 kb
Host smart-26e7ed7e-8dc5-47bb-b9d5-dd1d8122a7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034
26148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3303426148
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1852793439
Short name T1114
Test name
Test status
Simulation time 8385591046 ps
CPU time 11.1 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204740 kb
Host smart-f2051416-742c-4bc0-a720-a08fdc965fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18527
93439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1852793439
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.943489551
Short name T1078
Test name
Test status
Simulation time 8362673912 ps
CPU time 13.87 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:28 PM PDT 24
Peak memory 204524 kb
Host smart-00159237-a74b-41ec-8560-1d1c346f27cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94348
9551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.943489551
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4214569664
Short name T1022
Test name
Test status
Simulation time 8525790388 ps
CPU time 11.03 seconds
Started May 19 02:05:10 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204808 kb
Host smart-06ce3970-f6d2-42fa-85dc-52c4016d6192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
69664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4214569664
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.4160269807
Short name T378
Test name
Test status
Simulation time 8409450701 ps
CPU time 12.3 seconds
Started May 19 02:04:51 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204804 kb
Host smart-3aa0412a-c890-49eb-820e-de8d6c1bbe40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
69807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.4160269807
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2148538391
Short name T1542
Test name
Test status
Simulation time 8400934758 ps
CPU time 11.02 seconds
Started May 19 02:04:52 PM PDT 24
Finished May 19 02:05:04 PM PDT 24
Peak memory 204796 kb
Host smart-b33bfc16-22bd-4a93-a8d4-67bef5822b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485
38391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2148538391
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.340170490
Short name T347
Test name
Test status
Simulation time 8465404796 ps
CPU time 12.33 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204880 kb
Host smart-6d7ac80e-4276-408c-8aec-e77977d8aeef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=340170490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.340170490
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.3526822463
Short name T408
Test name
Test status
Simulation time 8385572762 ps
CPU time 11.07 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204784 kb
Host smart-a88c7dbb-c072-4347-b15a-b872b1e9eb30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3526822463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.3526822463
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.2783300575
Short name T1048
Test name
Test status
Simulation time 8419053629 ps
CPU time 11.32 seconds
Started May 19 02:04:46 PM PDT 24
Finished May 19 02:04:58 PM PDT 24
Peak memory 204776 kb
Host smart-0055eff7-cf49-4dc2-858f-1ec6a2697123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27833
00575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.2783300575
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.672086823
Short name T584
Test name
Test status
Simulation time 8379806768 ps
CPU time 11.95 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:04 PM PDT 24
Peak memory 204780 kb
Host smart-f8f40673-c3c8-43e4-9356-00bc16f2ed33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67208
6823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.672086823
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.765699194
Short name T745
Test name
Test status
Simulation time 8594497713 ps
CPU time 11.69 seconds
Started May 19 02:05:20 PM PDT 24
Finished May 19 02:05:33 PM PDT 24
Peak memory 204852 kb
Host smart-676f02ba-1e28-4cbf-a6e3-dc3f13fda07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76569
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.765699194
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_enable.3672549437
Short name T998
Test name
Test status
Simulation time 8386733295 ps
CPU time 11.4 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204708 kb
Host smart-9cdf58e9-daf6-436f-a160-ded842bb0145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36725
49437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3672549437
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.249255282
Short name T1309
Test name
Test status
Simulation time 9040702670 ps
CPU time 11.93 seconds
Started May 19 02:05:07 PM PDT 24
Finished May 19 02:05:20 PM PDT 24
Peak memory 204776 kb
Host smart-a20c1aca-4c45-4ab0-9779-d1f06757324b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24925
5282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.249255282
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3657701159
Short name T765
Test name
Test status
Simulation time 8578436807 ps
CPU time 11.92 seconds
Started May 19 02:04:55 PM PDT 24
Finished May 19 02:05:08 PM PDT 24
Peak memory 204836 kb
Host smart-5a850327-610d-488d-9858-68bf7e9f93fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
01159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3657701159
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3865328513
Short name T855
Test name
Test status
Simulation time 8443292301 ps
CPU time 11.2 seconds
Started May 19 02:04:54 PM PDT 24
Finished May 19 02:05:06 PM PDT 24
Peak memory 204856 kb
Host smart-fcad9125-984b-4381-9deb-44bf616863de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38653
28513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3865328513
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1249755325
Short name T1426
Test name
Test status
Simulation time 8382656011 ps
CPU time 11.68 seconds
Started May 19 02:05:05 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 204856 kb
Host smart-90b42c04-ab25-44a3-9305-777d612ecfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12497
55325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1249755325
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1476293103
Short name T800
Test name
Test status
Simulation time 8457972835 ps
CPU time 12.32 seconds
Started May 19 02:04:52 PM PDT 24
Finished May 19 02:05:06 PM PDT 24
Peak memory 204824 kb
Host smart-cce7838d-2529-4f5b-8d18-6b4ca0c9f05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14762
93103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1476293103
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1266941858
Short name T1228
Test name
Test status
Simulation time 8416506974 ps
CPU time 11.92 seconds
Started May 19 02:05:17 PM PDT 24
Finished May 19 02:05:30 PM PDT 24
Peak memory 204816 kb
Host smart-8a41371f-f3cf-4047-98fd-8f0d9dc1047d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12669
41858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1266941858
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.873199495
Short name T537
Test name
Test status
Simulation time 11522341068 ps
CPU time 16.02 seconds
Started May 19 02:04:58 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204836 kb
Host smart-5daffbfb-2190-4c8c-a6ae-38bb07dddb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87319
9495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.873199495
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.126057237
Short name T933
Test name
Test status
Simulation time 8430363712 ps
CPU time 11.47 seconds
Started May 19 02:05:05 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 204760 kb
Host smart-56da98d1-c420-4210-be61-27ac4fbff428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12605
7237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.126057237
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3725202156
Short name T137
Test name
Test status
Simulation time 8443995401 ps
CPU time 11.82 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204744 kb
Host smart-e2de1528-deeb-4dab-9687-a34073ba27f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37252
02156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3725202156
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1772032862
Short name T773
Test name
Test status
Simulation time 8412985045 ps
CPU time 10.41 seconds
Started May 19 02:04:51 PM PDT 24
Finished May 19 02:05:03 PM PDT 24
Peak memory 204808 kb
Host smart-8c9b2985-ed3a-406a-bb65-84bbe9d75efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17720
32862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1772032862
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2825339456
Short name T1236
Test name
Test status
Simulation time 8481989742 ps
CPU time 11.34 seconds
Started May 19 02:04:52 PM PDT 24
Finished May 19 02:05:05 PM PDT 24
Peak memory 204840 kb
Host smart-b6c039bb-b91c-4b61-82a7-e73c1a68fb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28253
39456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2825339456
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3092058003
Short name T231
Test name
Test status
Simulation time 8383121308 ps
CPU time 11.02 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204824 kb
Host smart-2734157a-5999-424b-9778-672db735e18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30920
58003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3092058003
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.403663553
Short name T917
Test name
Test status
Simulation time 8383147957 ps
CPU time 10.85 seconds
Started May 19 02:04:44 PM PDT 24
Finished May 19 02:04:56 PM PDT 24
Peak memory 204856 kb
Host smart-7efce000-b003-4f9d-88bb-9c6773b3ac41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
3553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.403663553
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.2428290632
Short name T1027
Test name
Test status
Simulation time 8391697418 ps
CPU time 11.73 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 204820 kb
Host smart-6b8a826f-222b-4405-a464-c359d74f3193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24282
90632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.2428290632
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3592836862
Short name T1317
Test name
Test status
Simulation time 8373831726 ps
CPU time 10.81 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 204764 kb
Host smart-83d1f0ff-7687-4d1b-88dd-a88bbdffb0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35928
36862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3592836862
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1519468117
Short name T238
Test name
Test status
Simulation time 20316084021 ps
CPU time 39.72 seconds
Started May 19 02:04:47 PM PDT 24
Finished May 19 02:05:28 PM PDT 24
Peak memory 204804 kb
Host smart-33971922-c42a-45ce-87ff-89cd7af2ab57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
68117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1519468117
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2813287983
Short name T1427
Test name
Test status
Simulation time 8393744724 ps
CPU time 11.95 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204848 kb
Host smart-28acf7b4-2754-4694-9207-eb4097b551d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
87983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2813287983
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3320626596
Short name T458
Test name
Test status
Simulation time 8448913973 ps
CPU time 11.11 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204796 kb
Host smart-b6c02956-8fc3-4ef3-985d-6b74f06c9e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33206
26596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3320626596
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3752281526
Short name T920
Test name
Test status
Simulation time 8394706984 ps
CPU time 11.63 seconds
Started May 19 02:04:58 PM PDT 24
Finished May 19 02:05:11 PM PDT 24
Peak memory 204764 kb
Host smart-936ecb3e-3a65-45ba-bb91-515030e270e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37522
81526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3752281526
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.674600480
Short name T1488
Test name
Test status
Simulation time 8371735041 ps
CPU time 11.81 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 204712 kb
Host smart-5b1c968a-6802-4f4c-bffe-0fe55b38c55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67460
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.674600480
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.579290924
Short name T1475
Test name
Test status
Simulation time 8388564755 ps
CPU time 12.92 seconds
Started May 19 02:04:57 PM PDT 24
Finished May 19 02:05:11 PM PDT 24
Peak memory 204852 kb
Host smart-d544fcf0-13de-45bd-832b-fdcc3c050cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57929
0924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.579290924
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.380015360
Short name T494
Test name
Test status
Simulation time 8365449529 ps
CPU time 10.8 seconds
Started May 19 02:04:48 PM PDT 24
Finished May 19 02:05:00 PM PDT 24
Peak memory 204636 kb
Host smart-f677acb4-e9fc-49ed-9603-a4a0af8172b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
5360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.380015360
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.798539597
Short name T1552
Test name
Test status
Simulation time 8460324979 ps
CPU time 11.41 seconds
Started May 19 02:05:17 PM PDT 24
Finished May 19 02:05:30 PM PDT 24
Peak memory 204800 kb
Host smart-09da130a-ef7d-4878-9848-499f6a6de36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79853
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.798539597
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.800742624
Short name T782
Test name
Test status
Simulation time 8394822712 ps
CPU time 13.19 seconds
Started May 19 02:04:46 PM PDT 24
Finished May 19 02:05:01 PM PDT 24
Peak memory 204856 kb
Host smart-5d14f1f9-0655-48ce-81ad-c09cfd8282c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80074
2624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.800742624
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3742095294
Short name T1165
Test name
Test status
Simulation time 8380202855 ps
CPU time 11.4 seconds
Started May 19 02:04:54 PM PDT 24
Finished May 19 02:05:07 PM PDT 24
Peak memory 204884 kb
Host smart-bedebb1c-cc46-4a06-939e-98b7f4b78ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
95294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3742095294
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.3998066615
Short name T554
Test name
Test status
Simulation time 8466038731 ps
CPU time 11.27 seconds
Started May 19 02:05:16 PM PDT 24
Finished May 19 02:05:28 PM PDT 24
Peak memory 204808 kb
Host smart-154578e8-bccf-440a-880f-cae52b289894
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3998066615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.3998066615
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.749462549
Short name T1032
Test name
Test status
Simulation time 8382429671 ps
CPU time 11.58 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204848 kb
Host smart-8f2ced07-3622-481d-8edf-e2724a893e13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=749462549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.749462549
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.589144777
Short name T1139
Test name
Test status
Simulation time 8489054610 ps
CPU time 14.15 seconds
Started May 19 02:04:54 PM PDT 24
Finished May 19 02:05:10 PM PDT 24
Peak memory 204848 kb
Host smart-dc7cd893-9419-4868-a2d5-a215a30eadb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58914
4777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.589144777
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3460874212
Short name T673
Test name
Test status
Simulation time 8376835064 ps
CPU time 11.53 seconds
Started May 19 02:04:54 PM PDT 24
Finished May 19 02:05:07 PM PDT 24
Peak memory 204716 kb
Host smart-6b81b34a-81b1-4ba7-bd93-e99b00774bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
74212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3460874212
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.529070357
Short name T1020
Test name
Test status
Simulation time 8376974039 ps
CPU time 10.77 seconds
Started May 19 02:05:06 PM PDT 24
Finished May 19 02:05:19 PM PDT 24
Peak memory 204768 kb
Host smart-dfeaa8c1-9bcd-4fb8-a2ac-4943fcf408f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52907
0357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.529070357
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3634440500
Short name T1708
Test name
Test status
Simulation time 9586478057 ps
CPU time 14.67 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:06 PM PDT 24
Peak memory 204868 kb
Host smart-932eda63-bfb2-4ec1-b628-84b8b8b67bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344
40500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3634440500
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.275712583
Short name T1420
Test name
Test status
Simulation time 8369246646 ps
CPU time 12.03 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204788 kb
Host smart-556fcacd-136f-4c7e-9e60-5343f5835eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27571
2583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.275712583
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1128005301
Short name T1393
Test name
Test status
Simulation time 8381461592 ps
CPU time 10.44 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204708 kb
Host smart-f1d96d47-9596-43f0-9fc2-1be5a84f3e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11280
05301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1128005301
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1512990326
Short name T1528
Test name
Test status
Simulation time 9074383742 ps
CPU time 11.83 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204712 kb
Host smart-bbfe5242-b3d4-412c-8686-aaf87645f9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
90326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1512990326
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1319399675
Short name T627
Test name
Test status
Simulation time 8545935215 ps
CPU time 14.98 seconds
Started May 19 02:05:01 PM PDT 24
Finished May 19 02:05:17 PM PDT 24
Peak memory 204820 kb
Host smart-d14dc56d-25f3-4507-981b-3159d88a8aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193
99675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1319399675
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3883232329
Short name T1107
Test name
Test status
Simulation time 8406727252 ps
CPU time 13.57 seconds
Started May 19 02:05:01 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204832 kb
Host smart-ca541992-ced6-4baf-9fa9-4ce8d42cae26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38832
32329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3883232329
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.755129823
Short name T640
Test name
Test status
Simulation time 8396606399 ps
CPU time 12.82 seconds
Started May 19 02:04:56 PM PDT 24
Finished May 19 02:05:10 PM PDT 24
Peak memory 204752 kb
Host smart-f49e5035-eeeb-4da7-a8b9-9f0854fe827c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75512
9823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.755129823
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3892583067
Short name T1668
Test name
Test status
Simulation time 8406043271 ps
CPU time 11.21 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204816 kb
Host smart-9b6f7930-cf48-460c-ba22-bb575f4d7293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
83067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3892583067
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1940259897
Short name T786
Test name
Test status
Simulation time 8417544121 ps
CPU time 10.63 seconds
Started May 19 02:05:01 PM PDT 24
Finished May 19 02:05:13 PM PDT 24
Peak memory 204816 kb
Host smart-f06083f5-a0d0-47b5-9fb0-93e1555ac1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19402
59897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1940259897
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1547175783
Short name T912
Test name
Test status
Simulation time 11490276991 ps
CPU time 13.49 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 204868 kb
Host smart-ff4260bb-5fcc-4b47-ab0d-792e6777e15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
75783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1547175783
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2888842811
Short name T1671
Test name
Test status
Simulation time 8442768853 ps
CPU time 11.33 seconds
Started May 19 02:04:56 PM PDT 24
Finished May 19 02:05:08 PM PDT 24
Peak memory 204796 kb
Host smart-c787c680-f2b7-496a-9270-161e8b967edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28888
42811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2888842811
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2208469909
Short name T1180
Test name
Test status
Simulation time 8386318065 ps
CPU time 13.24 seconds
Started May 19 02:05:04 PM PDT 24
Finished May 19 02:05:19 PM PDT 24
Peak memory 204788 kb
Host smart-9e8ee240-6b9a-4548-8d1a-0f65ecb96ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22084
69909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2208469909
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.77037672
Short name T146
Test name
Test status
Simulation time 8474329209 ps
CPU time 11.34 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204856 kb
Host smart-1c29f72e-6659-4837-8f01-ac416d6f1968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77037
672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.77037672
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2763159510
Short name T660
Test name
Test status
Simulation time 8415384578 ps
CPU time 10.74 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204800 kb
Host smart-d9aa4171-6f38-4f78-ac41-f462bc708fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
59510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2763159510
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3224249222
Short name T409
Test name
Test status
Simulation time 8407534802 ps
CPU time 11.99 seconds
Started May 19 02:04:50 PM PDT 24
Finished May 19 02:05:04 PM PDT 24
Peak memory 204760 kb
Host smart-0fd16ad6-6971-4c25-84b1-924f0946c196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32242
49222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3224249222
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1159813950
Short name T1565
Test name
Test status
Simulation time 8407920833 ps
CPU time 10.95 seconds
Started May 19 02:05:06 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 204884 kb
Host smart-d83913f4-6ad1-4989-ad21-6b5672ed2333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11598
13950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1159813950
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.203560154
Short name T1245
Test name
Test status
Simulation time 8392280112 ps
CPU time 12.63 seconds
Started May 19 02:05:02 PM PDT 24
Finished May 19 02:05:15 PM PDT 24
Peak memory 204808 kb
Host smart-c492ad2b-1b03-447d-88cd-e8dc5219cd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20356
0154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.203560154
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3445709562
Short name T1244
Test name
Test status
Simulation time 8412845726 ps
CPU time 11.36 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204752 kb
Host smart-176d88b0-52f1-4800-b59f-97ed6df79c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34457
09562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3445709562
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2295637963
Short name T1170
Test name
Test status
Simulation time 8378119418 ps
CPU time 11.26 seconds
Started May 19 02:05:19 PM PDT 24
Finished May 19 02:05:32 PM PDT 24
Peak memory 204772 kb
Host smart-7a95aba1-c924-4388-aa98-726d95babfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
37963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2295637963
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.132383309
Short name T24
Test name
Test status
Simulation time 8364789892 ps
CPU time 10.81 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 204696 kb
Host smart-8d1150fe-cc20-4dd5-b949-c7edfeee3e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
3309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.132383309
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3470869864
Short name T1356
Test name
Test status
Simulation time 27032811601 ps
CPU time 49.73 seconds
Started May 19 02:05:19 PM PDT 24
Finished May 19 02:06:10 PM PDT 24
Peak memory 204832 kb
Host smart-e66bd785-e252-4172-9760-562b668a84c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
69864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3470869864
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4063497565
Short name T630
Test name
Test status
Simulation time 8382314232 ps
CPU time 10.86 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204636 kb
Host smart-0928b8c1-e792-4b15-86b3-4642ee5b59dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40634
97565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4063497565
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3060977677
Short name T541
Test name
Test status
Simulation time 8429323006 ps
CPU time 10.88 seconds
Started May 19 02:04:59 PM PDT 24
Finished May 19 02:05:11 PM PDT 24
Peak memory 204808 kb
Host smart-0da5330e-8035-4cf3-9b21-b6ff2436c2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
77677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3060977677
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2985540951
Short name T595
Test name
Test status
Simulation time 8402877307 ps
CPU time 11.11 seconds
Started May 19 02:04:56 PM PDT 24
Finished May 19 02:05:08 PM PDT 24
Peak memory 204816 kb
Host smart-c625fa89-9449-4719-bf4c-f9a380af9862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29855
40951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2985540951
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2491526261
Short name T607
Test name
Test status
Simulation time 8379634785 ps
CPU time 11.55 seconds
Started May 19 02:05:01 PM PDT 24
Finished May 19 02:05:13 PM PDT 24
Peak memory 204776 kb
Host smart-6124f56a-0af0-4735-84c0-a0aa9bd3a90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24915
26261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2491526261
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1592618413
Short name T744
Test name
Test status
Simulation time 8378476498 ps
CPU time 10.85 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204820 kb
Host smart-289ffdf5-5355-400c-883f-4c88e4974168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926
18413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1592618413
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.6858525
Short name T1442
Test name
Test status
Simulation time 8388453728 ps
CPU time 11.23 seconds
Started May 19 02:04:55 PM PDT 24
Finished May 19 02:05:07 PM PDT 24
Peak memory 204836 kb
Host smart-051f7b72-beb6-40fe-937b-2fb178ea0ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68585
25 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.6858525
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2397475735
Short name T863
Test name
Test status
Simulation time 8469788543 ps
CPU time 11.99 seconds
Started May 19 02:05:04 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 205120 kb
Host smart-2e67a4da-1351-40ae-b8ea-8c6250530ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974
75735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2397475735
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1840883138
Short name T349
Test name
Test status
Simulation time 8394503184 ps
CPU time 13.81 seconds
Started May 19 02:04:53 PM PDT 24
Finished May 19 02:05:09 PM PDT 24
Peak memory 204700 kb
Host smart-8ba8518f-7578-4071-8556-d3dc76623aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18408
83138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1840883138
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3818551117
Short name T1007
Test name
Test status
Simulation time 8423368687 ps
CPU time 11.16 seconds
Started May 19 02:05:06 PM PDT 24
Finished May 19 02:05:19 PM PDT 24
Peak memory 204760 kb
Host smart-886cfdee-16ca-453f-b7fc-60430eac8b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38185
51117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3818551117
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3099450779
Short name T1212
Test name
Test status
Simulation time 8480915468 ps
CPU time 10.79 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204744 kb
Host smart-3bff375a-0842-42ff-95b8-dd45fbe7679e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3099450779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3099450779
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.763944384
Short name T360
Test name
Test status
Simulation time 8391282154 ps
CPU time 12.53 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204876 kb
Host smart-561c0c38-f9bc-4872-9cdf-8dd6902dac7d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=763944384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.763944384
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.556703920
Short name T937
Test name
Test status
Simulation time 8388455366 ps
CPU time 11.1 seconds
Started May 19 02:05:22 PM PDT 24
Finished May 19 02:05:35 PM PDT 24
Peak memory 204808 kb
Host smart-8be6890d-8883-4ec3-8237-f7a7565b1e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55670
3920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.556703920
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.962759475
Short name T942
Test name
Test status
Simulation time 8392174831 ps
CPU time 11.43 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:26 PM PDT 24
Peak memory 204884 kb
Host smart-cb7961bd-9f46-40d9-986e-02c17c315a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96275
9475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.962759475
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3735863134
Short name T1053
Test name
Test status
Simulation time 9089411324 ps
CPU time 12.79 seconds
Started May 19 02:05:19 PM PDT 24
Finished May 19 02:05:33 PM PDT 24
Peak memory 204820 kb
Host smart-8cebc723-58c8-4f43-803e-dabacec04aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
63134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3735863134
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1341163164
Short name T972
Test name
Test status
Simulation time 8403769129 ps
CPU time 11.28 seconds
Started May 19 02:05:10 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204804 kb
Host smart-04eb9b74-aab9-4dd3-a73c-47a482aa6af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
63164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1341163164
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3385369102
Short name T533
Test name
Test status
Simulation time 8391093580 ps
CPU time 10.71 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 204844 kb
Host smart-5051d770-29c0-4055-9776-3c7fe625a17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
69102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3385369102
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1875987415
Short name T28
Test name
Test status
Simulation time 9242284721 ps
CPU time 13.6 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 204836 kb
Host smart-1aede3a0-c66e-406a-be64-2de1439484ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18759
87415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1875987415
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3497773772
Short name T454
Test name
Test status
Simulation time 8413131225 ps
CPU time 12.44 seconds
Started May 19 02:05:22 PM PDT 24
Finished May 19 02:05:36 PM PDT 24
Peak memory 204740 kb
Host smart-522ecb35-22db-49de-9bed-97e25200ac2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34977
73772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3497773772
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3004330353
Short name T614
Test name
Test status
Simulation time 8418661993 ps
CPU time 10.59 seconds
Started May 19 02:05:04 PM PDT 24
Finished May 19 02:05:21 PM PDT 24
Peak memory 204812 kb
Host smart-1f82e155-3b68-466a-ab89-c2290fda51a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043
30353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3004330353
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1770036162
Short name T1616
Test name
Test status
Simulation time 8400056903 ps
CPU time 11.06 seconds
Started May 19 02:05:09 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 205048 kb
Host smart-27063c0d-cb68-4056-9b7a-67a70ef74f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
36162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1770036162
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2860226228
Short name T962
Test name
Test status
Simulation time 8469533479 ps
CPU time 13.07 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204832 kb
Host smart-c06ca990-714e-4623-88e3-e5b6d00416d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28602
26228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2860226228
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1379572162
Short name T573
Test name
Test status
Simulation time 8467808195 ps
CPU time 12.24 seconds
Started May 19 02:05:14 PM PDT 24
Finished May 19 02:05:27 PM PDT 24
Peak memory 204864 kb
Host smart-d0e91320-2378-40c7-90d7-86e9c3740163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13795
72162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1379572162
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.4223189199
Short name T423
Test name
Test status
Simulation time 11546128880 ps
CPU time 16.47 seconds
Started May 19 02:05:19 PM PDT 24
Finished May 19 02:05:37 PM PDT 24
Peak memory 204796 kb
Host smart-e6cb98bc-b101-41fa-9031-81bef8b5b677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42231
89199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.4223189199
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3121479311
Short name T1448
Test name
Test status
Simulation time 8441014490 ps
CPU time 11.5 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204976 kb
Host smart-af60ebe6-4416-4b4e-a286-018b0df3bce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31214
79311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3121479311
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2149448050
Short name T1379
Test name
Test status
Simulation time 8384707417 ps
CPU time 11.98 seconds
Started May 19 02:05:11 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204816 kb
Host smart-6218d42a-2584-4468-bfda-a9e0248b0108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21494
48050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2149448050
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2564193621
Short name T31
Test name
Test status
Simulation time 8428873857 ps
CPU time 11.26 seconds
Started May 19 02:05:10 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204872 kb
Host smart-be2def79-b016-4eeb-9276-0ddca374cc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25641
93621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2564193621
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1213455085
Short name T666
Test name
Test status
Simulation time 8439526822 ps
CPU time 10.73 seconds
Started May 19 02:05:10 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204776 kb
Host smart-2c0293ac-2213-42ab-a9b6-70a76b516f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12134
55085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1213455085
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2403524766
Short name T798
Test name
Test status
Simulation time 8388395098 ps
CPU time 13.21 seconds
Started May 19 02:05:07 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 204820 kb
Host smart-29d5d07d-2725-4ad3-a57c-d22d4d572af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
24766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2403524766
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1809114810
Short name T1693
Test name
Test status
Simulation time 8372834796 ps
CPU time 10.4 seconds
Started May 19 02:05:08 PM PDT 24
Finished May 19 02:05:20 PM PDT 24
Peak memory 204772 kb
Host smart-a97d94e9-d145-4260-aa6a-9d9b0dfac025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18091
14810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1809114810
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1239127296
Short name T177
Test name
Test status
Simulation time 8389535445 ps
CPU time 11.23 seconds
Started May 19 02:05:07 PM PDT 24
Finished May 19 02:05:20 PM PDT 24
Peak memory 204872 kb
Host smart-ab39f16e-28ab-4cd4-9553-fd7bf3a75eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12391
27296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1239127296
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.3725797765
Short name T1431
Test name
Test status
Simulation time 8428204686 ps
CPU time 11.77 seconds
Started May 19 02:05:03 PM PDT 24
Finished May 19 02:05:17 PM PDT 24
Peak memory 204760 kb
Host smart-16aba7d8-490c-451f-86f4-3560bc0ec6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37257
97765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.3725797765
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.394768215
Short name T590
Test name
Test status
Simulation time 8370928713 ps
CPU time 12.03 seconds
Started May 19 02:05:18 PM PDT 24
Finished May 19 02:05:32 PM PDT 24
Peak memory 204792 kb
Host smart-64a06788-8cea-48c3-bf33-884ca80ac1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39476
8215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.394768215
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2926384389
Short name T13
Test name
Test status
Simulation time 8377163048 ps
CPU time 11.45 seconds
Started May 19 02:05:05 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 204768 kb
Host smart-aa8aeaf7-2883-4d86-80ee-dccc523125ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29263
84389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2926384389
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3002551743
Short name T1205
Test name
Test status
Simulation time 22556537796 ps
CPU time 39.6 seconds
Started May 19 02:05:07 PM PDT 24
Finished May 19 02:05:48 PM PDT 24
Peak memory 204828 kb
Host smart-b08b7b06-53b4-4cf1-ae28-b8e48e69699a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30025
51743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3002551743
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1628403342
Short name T582
Test name
Test status
Simulation time 8419845228 ps
CPU time 11.89 seconds
Started May 19 02:05:13 PM PDT 24
Finished May 19 02:05:26 PM PDT 24
Peak memory 204876 kb
Host smart-3981277a-faad-4047-a4f2-8d622e99279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
03342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1628403342
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.313970249
Short name T1195
Test name
Test status
Simulation time 8494243180 ps
CPU time 11.64 seconds
Started May 19 02:05:10 PM PDT 24
Finished May 19 02:05:23 PM PDT 24
Peak memory 204756 kb
Host smart-b1ebae89-efd5-41c7-b727-1deb8281cd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31397
0249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.313970249
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.260193531
Short name T658
Test name
Test status
Simulation time 8425988081 ps
CPU time 11.4 seconds
Started May 19 02:05:05 PM PDT 24
Finished May 19 02:05:18 PM PDT 24
Peak memory 204804 kb
Host smart-eb5fc47b-8dc5-433e-a8f1-4252eddea96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
3531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.260193531
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3261698205
Short name T1339
Test name
Test status
Simulation time 8371761220 ps
CPU time 13.25 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:27 PM PDT 24
Peak memory 204836 kb
Host smart-707301be-bdf6-4dee-bccd-097d5fe4ca1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32616
98205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3261698205
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2431982340
Short name T1446
Test name
Test status
Simulation time 8404705314 ps
CPU time 11.6 seconds
Started May 19 02:05:00 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 204840 kb
Host smart-d20ae199-31d6-4556-a3e4-bb774055c34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24319
82340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2431982340
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1257077358
Short name T617
Test name
Test status
Simulation time 8364152430 ps
CPU time 12.02 seconds
Started May 19 02:05:18 PM PDT 24
Finished May 19 02:05:32 PM PDT 24
Peak memory 204672 kb
Host smart-4752af3e-9431-4fd5-be43-945d12b0ced5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12570
77358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1257077358
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3686105703
Short name T1756
Test name
Test status
Simulation time 8440609915 ps
CPU time 13.01 seconds
Started May 19 02:05:25 PM PDT 24
Finished May 19 02:05:41 PM PDT 24
Peak memory 204764 kb
Host smart-4cb749c7-9181-4e62-a6ba-268968f27105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
05703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3686105703
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.980355246
Short name T1512
Test name
Test status
Simulation time 8407826822 ps
CPU time 10.86 seconds
Started May 19 02:05:12 PM PDT 24
Finished May 19 02:05:25 PM PDT 24
Peak memory 204864 kb
Host smart-fca42822-c233-4352-b5cc-e8933134de54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98035
5246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.980355246
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.4128488887
Short name T484
Test name
Test status
Simulation time 8472265221 ps
CPU time 12.43 seconds
Started May 19 02:01:40 PM PDT 24
Finished May 19 02:01:58 PM PDT 24
Peak memory 204864 kb
Host smart-a11848a1-4fbc-4899-94c3-f3357f8c3b42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4128488887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.4128488887
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.4067281528
Short name T752
Test name
Test status
Simulation time 8414289002 ps
CPU time 10.81 seconds
Started May 19 02:01:45 PM PDT 24
Finished May 19 02:01:56 PM PDT 24
Peak memory 204788 kb
Host smart-5cbec7b5-80ea-494d-85ea-a303fd2f6c9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4067281528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.4067281528
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.3443723748
Short name T1467
Test name
Test status
Simulation time 8441795855 ps
CPU time 11.1 seconds
Started May 19 02:01:24 PM PDT 24
Finished May 19 02:01:36 PM PDT 24
Peak memory 204720 kb
Host smart-0a143c23-2653-43ea-9548-46f1a4ddebc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34437
23748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.3443723748
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2945407301
Short name T391
Test name
Test status
Simulation time 8386975691 ps
CPU time 11.88 seconds
Started May 19 02:01:24 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204840 kb
Host smart-63be6aa4-8fda-4060-9bfc-da2548525314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454
07301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2945407301
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3494319947
Short name T1395
Test name
Test status
Simulation time 8375978152 ps
CPU time 12.04 seconds
Started May 19 02:01:18 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204736 kb
Host smart-3efeb355-ced5-4229-aed3-c950338f41be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
19947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3494319947
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4042767290
Short name T185
Test name
Test status
Simulation time 9722954483 ps
CPU time 14.73 seconds
Started May 19 02:01:18 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204820 kb
Host smart-3f7b2ab0-9fb0-4576-bda5-af5b3764092e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40427
67290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4042767290
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3643669164
Short name T1042
Test name
Test status
Simulation time 8378872748 ps
CPU time 12.57 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204828 kb
Host smart-a75d9bf0-5e6b-4793-9b85-04913e402746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
69164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3643669164
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1173747776
Short name T944
Test name
Test status
Simulation time 8424344021 ps
CPU time 11.83 seconds
Started May 19 02:01:16 PM PDT 24
Finished May 19 02:01:29 PM PDT 24
Peak memory 204872 kb
Host smart-04957df5-3aee-483b-a4e6-0d3a50ac4025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11737
47776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1173747776
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2861806654
Short name T465
Test name
Test status
Simulation time 8985604638 ps
CPU time 11.77 seconds
Started May 19 02:01:18 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 204848 kb
Host smart-8fbe16ad-ea74-427c-ae81-6aa50056b3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
06654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2861806654
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2516512189
Short name T1406
Test name
Test status
Simulation time 8479315020 ps
CPU time 13.71 seconds
Started May 19 02:01:16 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 204684 kb
Host smart-cd3159ae-0ef0-4430-aad2-77a08421baf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25165
12189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2516512189
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.573378640
Short name T316
Test name
Test status
Simulation time 8470218452 ps
CPU time 10.88 seconds
Started May 19 02:01:41 PM PDT 24
Finished May 19 02:01:53 PM PDT 24
Peak memory 204836 kb
Host smart-cf5f87b4-4f65-4d25-9edd-e9f088f4f11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57337
8640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.573378640
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1320698518
Short name T1368
Test name
Test status
Simulation time 8369584571 ps
CPU time 10.52 seconds
Started May 19 02:01:22 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204860 kb
Host smart-db5b4ba2-3520-41b9-a4e9-5c051fab44d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
98518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1320698518
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.251392723
Short name T1183
Test name
Test status
Simulation time 8435025577 ps
CPU time 10.63 seconds
Started May 19 02:01:24 PM PDT 24
Finished May 19 02:01:36 PM PDT 24
Peak memory 204840 kb
Host smart-75238869-d5ee-433a-bfe8-66667dc1941d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25139
2723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.251392723
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1436589016
Short name T1533
Test name
Test status
Simulation time 8432396447 ps
CPU time 10.75 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204748 kb
Host smart-9bd01d31-df25-4844-a584-ff2811793502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14365
89016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1436589016
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1181334002
Short name T1386
Test name
Test status
Simulation time 11535783098 ps
CPU time 13.9 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204820 kb
Host smart-8ff5a1f0-9122-4c8a-bf5f-acce147314f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11813
34002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1181334002
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.211720898
Short name T1633
Test name
Test status
Simulation time 8419316992 ps
CPU time 12.15 seconds
Started May 19 02:01:23 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204764 kb
Host smart-9e51710b-2c4b-43ca-a56a-336050815ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21172
0898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.211720898
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.498353309
Short name T1777
Test name
Test status
Simulation time 8372655910 ps
CPU time 11.12 seconds
Started May 19 02:01:21 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 205020 kb
Host smart-01e46e66-b533-49db-91ef-04bff117868f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49835
3309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.498353309
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2928992803
Short name T983
Test name
Test status
Simulation time 8430486157 ps
CPU time 10.77 seconds
Started May 19 02:01:16 PM PDT 24
Finished May 19 02:01:28 PM PDT 24
Peak memory 204860 kb
Host smart-a59a0512-0176-4aa9-986a-f43e6374a2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29289
92803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2928992803
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3665307934
Short name T1306
Test name
Test status
Simulation time 8423218715 ps
CPU time 11.53 seconds
Started May 19 02:01:19 PM PDT 24
Finished May 19 02:01:32 PM PDT 24
Peak memory 204708 kb
Host smart-d70dfb23-76d5-4e94-8260-e83c9ade323b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36653
07934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3665307934
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1196511952
Short name T1019
Test name
Test status
Simulation time 8418526654 ps
CPU time 11.22 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204844 kb
Host smart-1cbcbcfa-1e2a-4c5a-989e-8cb7c9679942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11965
11952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1196511952
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1844835641
Short name T799
Test name
Test status
Simulation time 8377462995 ps
CPU time 11.77 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204868 kb
Host smart-8abb8751-70eb-40d1-b32c-d4cf858239c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448
35641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1844835641
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3536078530
Short name T83
Test name
Test status
Simulation time 8403509911 ps
CPU time 11.45 seconds
Started May 19 02:01:29 PM PDT 24
Finished May 19 02:01:41 PM PDT 24
Peak memory 204876 kb
Host smart-68372a05-8d8f-4ff3-aa3f-13d9ede36a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35360
78530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3536078530
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1443629119
Short name T1620
Test name
Test status
Simulation time 8404587403 ps
CPU time 11.28 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:01 PM PDT 24
Peak memory 204756 kb
Host smart-efe82246-b105-4260-9559-683fdf63da82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14436
29119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1443629119
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2409395491
Short name T473
Test name
Test status
Simulation time 8370601936 ps
CPU time 10.51 seconds
Started May 19 02:01:22 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204772 kb
Host smart-4a8e7500-fdae-45e8-8240-fa6018d27d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24093
95491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2409395491
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2049857863
Short name T1175
Test name
Test status
Simulation time 8384642250 ps
CPU time 11.81 seconds
Started May 19 02:01:37 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204828 kb
Host smart-232e891e-40a8-4f29-b303-dad547878022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20498
57863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2049857863
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4130865684
Short name T1498
Test name
Test status
Simulation time 30494643694 ps
CPU time 60.64 seconds
Started May 19 02:01:22 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204756 kb
Host smart-1e0a84d8-6371-4a49-8d3e-016cd2acbcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41308
65684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4130865684
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1587392389
Short name T669
Test name
Test status
Simulation time 8440434695 ps
CPU time 10.87 seconds
Started May 19 02:01:22 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 204756 kb
Host smart-a019ed35-0e72-4b63-b601-43381cb3ca63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
92389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1587392389
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4206710402
Short name T599
Test name
Test status
Simulation time 8425702033 ps
CPU time 11.4 seconds
Started May 19 02:01:24 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204868 kb
Host smart-f854617b-c53b-487b-8dfb-a7cf9625e0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
10402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4206710402
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1104483916
Short name T854
Test name
Test status
Simulation time 8411309269 ps
CPU time 12.97 seconds
Started May 19 02:01:29 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204800 kb
Host smart-aaafa6e7-f7f0-4402-b732-80079b7c736d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
83916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1104483916
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3704846191
Short name T40
Test name
Test status
Simulation time 8363723995 ps
CPU time 11.42 seconds
Started May 19 02:01:20 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204788 kb
Host smart-811165f0-9c0f-4c9d-bf7e-5e727c143716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37048
46191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3704846191
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.464568012
Short name T639
Test name
Test status
Simulation time 8379878044 ps
CPU time 11.1 seconds
Started May 19 02:01:27 PM PDT 24
Finished May 19 02:01:39 PM PDT 24
Peak memory 204840 kb
Host smart-a96d1138-dc03-4718-95fd-da973d5ed182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46456
8012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.464568012
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.145341551
Short name T418
Test name
Test status
Simulation time 8411586581 ps
CPU time 10.8 seconds
Started May 19 02:01:23 PM PDT 24
Finished May 19 02:01:36 PM PDT 24
Peak memory 204820 kb
Host smart-dc7ce79e-4fdb-4bfc-93f7-60f6e600bcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14534
1551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.145341551
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2895167303
Short name T166
Test name
Test status
Simulation time 8485137871 ps
CPU time 10.51 seconds
Started May 19 02:01:17 PM PDT 24
Finished May 19 02:01:29 PM PDT 24
Peak memory 204892 kb
Host smart-a3476384-5f2a-4cad-adcc-558bcf99f9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28951
67303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2895167303
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.384747716
Short name T401
Test name
Test status
Simulation time 8405808714 ps
CPU time 10.91 seconds
Started May 19 02:01:21 PM PDT 24
Finished May 19 02:01:33 PM PDT 24
Peak memory 204704 kb
Host smart-e9b98b7c-ce44-4ed0-bec4-5364fafb0db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38474
7716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.384747716
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.85926036
Short name T1354
Test name
Test status
Simulation time 8396111458 ps
CPU time 10.82 seconds
Started May 19 02:01:27 PM PDT 24
Finished May 19 02:01:39 PM PDT 24
Peak memory 204840 kb
Host smart-720b5381-f1c4-499a-bc0f-0efb608979ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85926
036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.85926036
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.418855464
Short name T982
Test name
Test status
Simulation time 8472055494 ps
CPU time 10.73 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:44 PM PDT 24
Peak memory 204752 kb
Host smart-003cb52a-7f8b-487e-8fdb-d95842879715
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=418855464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.418855464
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.2762686555
Short name T1199
Test name
Test status
Simulation time 8420186011 ps
CPU time 10.9 seconds
Started May 19 02:01:47 PM PDT 24
Finished May 19 02:01:59 PM PDT 24
Peak memory 205000 kb
Host smart-3d16d185-1239-46f9-88c5-b124db6f713a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2762686555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.2762686555
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.2338342244
Short name T1291
Test name
Test status
Simulation time 8444995997 ps
CPU time 11.84 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 204860 kb
Host smart-d0f51659-8ab3-4be9-aa84-71d4b342b4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23383
42244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.2338342244
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2010749906
Short name T1597
Test name
Test status
Simulation time 8385044792 ps
CPU time 10.37 seconds
Started May 19 02:01:26 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204764 kb
Host smart-246b7c44-d228-49f2-bee6-e61b0bbe4233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
49906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2010749906
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.300083272
Short name T519
Test name
Test status
Simulation time 8381703503 ps
CPU time 11.24 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 204852 kb
Host smart-96fa5e32-47b1-4a63-998e-afc5b6f37bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
3272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.300083272
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.101746890
Short name T1041
Test name
Test status
Simulation time 8969480035 ps
CPU time 12.81 seconds
Started May 19 02:01:23 PM PDT 24
Finished May 19 02:01:38 PM PDT 24
Peak memory 204852 kb
Host smart-2f037c23-7d5d-4dc0-9360-86c204e07ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
6890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.101746890
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.628672527
Short name T901
Test name
Test status
Simulation time 8367026536 ps
CPU time 12.63 seconds
Started May 19 02:01:26 PM PDT 24
Finished May 19 02:01:45 PM PDT 24
Peak memory 204768 kb
Host smart-9edf00a2-7dda-4d2f-8229-91d577664b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62867
2527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.628672527
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.4209270325
Short name T1422
Test name
Test status
Simulation time 8376245947 ps
CPU time 11.57 seconds
Started May 19 02:01:26 PM PDT 24
Finished May 19 02:01:38 PM PDT 24
Peak memory 204788 kb
Host smart-46b6fb46-eae4-40fc-88a3-ca7a73bef314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42092
70325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.4209270325
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1073220443
Short name T338
Test name
Test status
Simulation time 9219642632 ps
CPU time 12.32 seconds
Started May 19 02:01:31 PM PDT 24
Finished May 19 02:01:44 PM PDT 24
Peak memory 204704 kb
Host smart-21fa4810-64d5-4f7e-bdef-e28bc837e991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10732
20443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1073220443
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1172477781
Short name T1287
Test name
Test status
Simulation time 8463376880 ps
CPU time 11.88 seconds
Started May 19 02:01:26 PM PDT 24
Finished May 19 02:01:39 PM PDT 24
Peak memory 204764 kb
Host smart-ca30753d-ed60-45bd-ba90-6c16299bf9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11724
77781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1172477781
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3711088961
Short name T1255
Test name
Test status
Simulation time 8384327924 ps
CPU time 10.78 seconds
Started May 19 02:01:28 PM PDT 24
Finished May 19 02:01:39 PM PDT 24
Peak memory 204880 kb
Host smart-5a197382-bad7-4acc-bbd9-bad6147d2a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110
88961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3711088961
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3504588727
Short name T464
Test name
Test status
Simulation time 8371498609 ps
CPU time 11.13 seconds
Started May 19 02:01:28 PM PDT 24
Finished May 19 02:01:40 PM PDT 24
Peak memory 204836 kb
Host smart-e9221300-7398-460d-af6e-3bb8091bcb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
88727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3504588727
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2589742460
Short name T1425
Test name
Test status
Simulation time 8466282789 ps
CPU time 11.19 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204748 kb
Host smart-39a5c8ba-d8d3-4a72-8847-3c41122ee658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
42460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2589742460
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3248284211
Short name T580
Test name
Test status
Simulation time 8404561171 ps
CPU time 10.99 seconds
Started May 19 02:01:37 PM PDT 24
Finished May 19 02:01:49 PM PDT 24
Peak memory 204792 kb
Host smart-5214f0c0-1323-48b9-a092-f50181ccf7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32482
84211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3248284211
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.4095769693
Short name T652
Test name
Test status
Simulation time 8448211187 ps
CPU time 10.6 seconds
Started May 19 02:01:34 PM PDT 24
Finished May 19 02:01:45 PM PDT 24
Peak memory 204804 kb
Host smart-1cae198f-4a73-4e3b-ab06-2f4bba2a39fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40957
69693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.4095769693
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2200193957
Short name T1508
Test name
Test status
Simulation time 8377175898 ps
CPU time 11.43 seconds
Started May 19 02:01:24 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 205052 kb
Host smart-5532878d-023b-4f6f-b666-1cb6aa7cd201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22001
93957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2200193957
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1946252789
Short name T130
Test name
Test status
Simulation time 8438291442 ps
CPU time 13.57 seconds
Started May 19 02:01:25 PM PDT 24
Finished May 19 02:01:40 PM PDT 24
Peak memory 204876 kb
Host smart-eb18eabb-80d4-4dfc-aa80-a9f521145566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462
52789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1946252789
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3501576030
Short name T1081
Test name
Test status
Simulation time 8410233053 ps
CPU time 11.08 seconds
Started May 19 02:01:25 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204800 kb
Host smart-deb2b300-c7a3-496c-96c2-ccaf7df4f226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
76030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3501576030
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3993684595
Short name T842
Test name
Test status
Simulation time 8400322172 ps
CPU time 11.33 seconds
Started May 19 02:01:34 PM PDT 24
Finished May 19 02:01:47 PM PDT 24
Peak memory 204872 kb
Host smart-798167dc-144e-4103-85ab-709d4d2fa496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
84595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3993684595
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1697960034
Short name T928
Test name
Test status
Simulation time 8391256151 ps
CPU time 11.55 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:43 PM PDT 24
Peak memory 205016 kb
Host smart-2d358f68-15de-4557-b495-fa8beb839625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16979
60034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1697960034
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2004352188
Short name T1628
Test name
Test status
Simulation time 8405396480 ps
CPU time 13.37 seconds
Started May 19 02:01:40 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204816 kb
Host smart-e8ffa45f-f151-448f-81fa-af698ec4b732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
52188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2004352188
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.368968926
Short name T993
Test name
Test status
Simulation time 8366710440 ps
CPU time 12.64 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:47 PM PDT 24
Peak memory 204800 kb
Host smart-be5b1041-2673-4b9a-9202-fb83b204d5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36896
8926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.368968926
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1757432698
Short name T1074
Test name
Test status
Simulation time 8409422103 ps
CPU time 12.3 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204784 kb
Host smart-a1241c5f-01da-43ef-b390-f242af3f0fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17574
32698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1757432698
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.430300811
Short name T750
Test name
Test status
Simulation time 25863093342 ps
CPU time 44.58 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 204736 kb
Host smart-c0831d4b-a576-455c-b979-b3640dce7534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43030
0811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.430300811
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2679786943
Short name T610
Test name
Test status
Simulation time 8406742884 ps
CPU time 12.22 seconds
Started May 19 02:01:38 PM PDT 24
Finished May 19 02:01:51 PM PDT 24
Peak memory 204820 kb
Host smart-4b533d03-d492-4003-a8aa-cfb8fd25e78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797
86943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2679786943
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3632599646
Short name T1049
Test name
Test status
Simulation time 8414004433 ps
CPU time 11.02 seconds
Started May 19 02:01:25 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 204828 kb
Host smart-872653f2-a1a7-4a31-b12e-f603e6dbd153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36325
99646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3632599646
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3932168440
Short name T945
Test name
Test status
Simulation time 8444795744 ps
CPU time 10.83 seconds
Started May 19 02:01:25 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 205032 kb
Host smart-1b3df634-d4dc-444d-9d93-7775458b71d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39321
68440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3932168440
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.4269246731
Short name T1734
Test name
Test status
Simulation time 8393949794 ps
CPU time 10.64 seconds
Started May 19 02:01:27 PM PDT 24
Finished May 19 02:01:38 PM PDT 24
Peak memory 204764 kb
Host smart-c0aec181-63c6-4030-a2a4-57a9ae19fdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692
46731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.4269246731
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2980043145
Short name T168
Test name
Test status
Simulation time 8379485883 ps
CPU time 12.6 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204832 kb
Host smart-12dfe053-58f1-4602-9bb3-cceda5097a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29800
43145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2980043145
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3467515252
Short name T1090
Test name
Test status
Simulation time 8410892291 ps
CPU time 10.89 seconds
Started May 19 02:01:27 PM PDT 24
Finished May 19 02:01:39 PM PDT 24
Peak memory 204804 kb
Host smart-0822c735-4f73-4b12-84b4-8f2abd1364db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675
15252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3467515252
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3948374214
Short name T890
Test name
Test status
Simulation time 8433518489 ps
CPU time 11 seconds
Started May 19 02:01:24 PM PDT 24
Finished May 19 02:01:36 PM PDT 24
Peak memory 204872 kb
Host smart-48c2989c-705c-41db-958d-40ac2e5d8a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
74214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3948374214
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3188596548
Short name T1382
Test name
Test status
Simulation time 8379121658 ps
CPU time 11.02 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:01:47 PM PDT 24
Peak memory 204852 kb
Host smart-7598bf03-0ccc-4e48-be12-fd3932eea52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31885
96548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3188596548
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.180060642
Short name T601
Test name
Test status
Simulation time 8389728673 ps
CPU time 11.23 seconds
Started May 19 02:01:28 PM PDT 24
Finished May 19 02:01:40 PM PDT 24
Peak memory 204804 kb
Host smart-ab90e7d0-5fc7-4d33-84e8-34acc3b68628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
0642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.180060642
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.3245696859
Short name T862
Test name
Test status
Simulation time 8478682792 ps
CPU time 12.01 seconds
Started May 19 02:01:29 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204860 kb
Host smart-3f0e3619-43d7-4b9d-863e-a0fa76b3634e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3245696859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.3245696859
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2547341909
Short name T596
Test name
Test status
Simulation time 8471360668 ps
CPU time 10.86 seconds
Started May 19 02:01:40 PM PDT 24
Finished May 19 02:01:52 PM PDT 24
Peak memory 204780 kb
Host smart-2a1a777d-581e-4e99-8569-10d1ab6869d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2547341909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2547341909
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.831101029
Short name T1369
Test name
Test status
Simulation time 8458766028 ps
CPU time 11.59 seconds
Started May 19 02:01:31 PM PDT 24
Finished May 19 02:01:44 PM PDT 24
Peak memory 204812 kb
Host smart-c29a0d87-a305-4f8b-9679-546797af2c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83110
1029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.831101029
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.960528627
Short name T1610
Test name
Test status
Simulation time 8380580326 ps
CPU time 10.61 seconds
Started May 19 02:01:40 PM PDT 24
Finished May 19 02:01:52 PM PDT 24
Peak memory 204868 kb
Host smart-1353a970-ae9c-429c-aa32-d8ff2ad854c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96052
8627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.960528627
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3575004757
Short name T1717
Test name
Test status
Simulation time 8792771890 ps
CPU time 12.42 seconds
Started May 19 02:01:32 PM PDT 24
Finished May 19 02:01:45 PM PDT 24
Peak memory 204872 kb
Host smart-51eb8002-8252-4a70-9f89-342ae9da161c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35750
04757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3575004757
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1551571931
Short name T363
Test name
Test status
Simulation time 8387936837 ps
CPU time 11.13 seconds
Started May 19 02:01:40 PM PDT 24
Finished May 19 02:01:52 PM PDT 24
Peak memory 204764 kb
Host smart-e5588573-7a70-41b9-9586-eb1cc380048b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15515
71931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1551571931
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.616437215
Short name T1145
Test name
Test status
Simulation time 8378134943 ps
CPU time 12.51 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204880 kb
Host smart-b89245be-94b1-46b1-a00e-610e2d072c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61643
7215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.616437215
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1890566918
Short name T885
Test name
Test status
Simulation time 9136724362 ps
CPU time 11.93 seconds
Started May 19 02:01:34 PM PDT 24
Finished May 19 02:01:47 PM PDT 24
Peak memory 204848 kb
Host smart-deb025d9-840a-41eb-a7f4-c72a8b2a851a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18905
66918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1890566918
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2101971308
Short name T327
Test name
Test status
Simulation time 8528796503 ps
CPU time 11.71 seconds
Started May 19 02:01:37 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204832 kb
Host smart-231e1bc1-00fa-4ee4-977f-8375db387c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21019
71308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2101971308
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2731859491
Short name T1534
Test name
Test status
Simulation time 8423685546 ps
CPU time 10.93 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:01:47 PM PDT 24
Peak memory 204876 kb
Host smart-7b3d2130-f02e-4cb0-a893-3cdbfa521573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318
59491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2731859491
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1840460070
Short name T1160
Test name
Test status
Simulation time 8368888157 ps
CPU time 12 seconds
Started May 19 02:01:28 PM PDT 24
Finished May 19 02:01:41 PM PDT 24
Peak memory 204800 kb
Host smart-3499ca9e-0fc3-4acd-bf07-aa372496c1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18404
60070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1840460070
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.716400115
Short name T1609
Test name
Test status
Simulation time 8479263485 ps
CPU time 11.69 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204840 kb
Host smart-d67efd4a-1749-4cad-a48c-7ea16ec16fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71640
0115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.716400115
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1038992812
Short name T1537
Test name
Test status
Simulation time 8422249706 ps
CPU time 11.81 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204836 kb
Host smart-c735a0c0-d87c-4328-a993-aa4b0ea6ff75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10389
92812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1038992812
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3139547701
Short name T1261
Test name
Test status
Simulation time 11556222250 ps
CPU time 14.63 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 204800 kb
Host smart-9fb29d94-3803-4d3f-9ae9-c0028d5679e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31395
47701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3139547701
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3935422137
Short name T436
Test name
Test status
Simulation time 8422975184 ps
CPU time 10.88 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:45 PM PDT 24
Peak memory 204780 kb
Host smart-208dc647-e6ea-41da-9c4f-ddeab7ea3e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354
22137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3935422137
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.705427567
Short name T735
Test name
Test status
Simulation time 8375278192 ps
CPU time 11.09 seconds
Started May 19 02:01:27 PM PDT 24
Finished May 19 02:01:39 PM PDT 24
Peak memory 204820 kb
Host smart-1d786f09-adcd-499d-9861-df5d6f7586ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70542
7567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.705427567
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.246760801
Short name T1344
Test name
Test status
Simulation time 8481167232 ps
CPU time 12.76 seconds
Started May 19 02:01:34 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 204888 kb
Host smart-b3b6cad6-1e9a-4d79-972c-26c7a46e86da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
0801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.246760801
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2289349394
Short name T1197
Test name
Test status
Simulation time 8418364308 ps
CPU time 14.22 seconds
Started May 19 02:01:45 PM PDT 24
Finished May 19 02:02:00 PM PDT 24
Peak memory 204820 kb
Host smart-832dccf3-ff89-4c4e-b2a9-877c2c576a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22893
49394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2289349394
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3291908744
Short name T903
Test name
Test status
Simulation time 8414944767 ps
CPU time 10.85 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 204828 kb
Host smart-98b55e7f-e5ec-4b28-a1ac-98cfa30e73ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32919
08744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3291908744
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3431631759
Short name T1308
Test name
Test status
Simulation time 8406391776 ps
CPU time 11.34 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204816 kb
Host smart-5fdd562b-27d7-490c-a239-dcd7e53ef268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34316
31759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3431631759
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3769224969
Short name T204
Test name
Test status
Simulation time 8413916786 ps
CPU time 11.01 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 204768 kb
Host smart-659057e4-94b9-49b8-8257-ff0e13f39545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37692
24969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3769224969
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.840112858
Short name T1198
Test name
Test status
Simulation time 8422249634 ps
CPU time 13.67 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:57 PM PDT 24
Peak memory 204704 kb
Host smart-6a54b422-d412-4ed8-9a59-ef502351f69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84011
2858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.840112858
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2289221807
Short name T1329
Test name
Test status
Simulation time 8371552339 ps
CPU time 12.7 seconds
Started May 19 02:01:44 PM PDT 24
Finished May 19 02:01:58 PM PDT 24
Peak memory 204800 kb
Host smart-dbec043d-8e42-4344-99d8-1376747c1cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
21807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2289221807
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3269034574
Short name T1692
Test name
Test status
Simulation time 8365453619 ps
CPU time 11.33 seconds
Started May 19 02:01:28 PM PDT 24
Finished May 19 02:01:40 PM PDT 24
Peak memory 204840 kb
Host smart-413dfa6f-bf39-4295-b107-4350edc61bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690
34574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3269034574
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1806237901
Short name T234
Test name
Test status
Simulation time 18603186031 ps
CPU time 31.86 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 205028 kb
Host smart-53aabb12-bce2-44ae-bef2-117f4d489151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062
37901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1806237901
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2818678256
Short name T515
Test name
Test status
Simulation time 8411191059 ps
CPU time 10.95 seconds
Started May 19 02:01:30 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204752 kb
Host smart-a641481c-81c9-41fe-8758-1843ba617915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
78256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2818678256
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3365165688
Short name T472
Test name
Test status
Simulation time 8456179664 ps
CPU time 12.81 seconds
Started May 19 02:01:29 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204880 kb
Host smart-d4347ab1-604a-447c-ad98-1b6d543884d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33651
65688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3365165688
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.3612832154
Short name T1635
Test name
Test status
Simulation time 8391617344 ps
CPU time 11.27 seconds
Started May 19 02:01:48 PM PDT 24
Finished May 19 02:02:00 PM PDT 24
Peak memory 204812 kb
Host smart-cdf6af89-7f53-437c-9aab-6d787974e627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36128
32154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.3612832154
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3452557669
Short name T1764
Test name
Test status
Simulation time 8364563091 ps
CPU time 11.75 seconds
Started May 19 02:01:29 PM PDT 24
Finished May 19 02:01:42 PM PDT 24
Peak memory 204816 kb
Host smart-93c2cfa6-4a8f-4794-8af3-902597681eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
57669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3452557669
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2728783850
Short name T1614
Test name
Test status
Simulation time 8384715480 ps
CPU time 11.1 seconds
Started May 19 02:01:31 PM PDT 24
Finished May 19 02:01:43 PM PDT 24
Peak memory 204772 kb
Host smart-2050ced1-ae53-476d-a39a-a7fe62d98365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27287
83850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2728783850
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.4112512250
Short name T620
Test name
Test status
Simulation time 8372817191 ps
CPU time 10.98 seconds
Started May 19 02:01:37 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204772 kb
Host smart-0a2f6f03-cc74-44e7-93e0-5e8747c6aeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125
12250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.4112512250
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1171983495
Short name T180
Test name
Test status
Simulation time 8525192566 ps
CPU time 11.68 seconds
Started May 19 02:01:39 PM PDT 24
Finished May 19 02:01:51 PM PDT 24
Peak memory 205016 kb
Host smart-f496cdaf-4508-4f79-86d4-050693e4f4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
83495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1171983495
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.954758599
Short name T1441
Test name
Test status
Simulation time 8405356636 ps
CPU time 11.37 seconds
Started May 19 02:01:29 PM PDT 24
Finished May 19 02:01:46 PM PDT 24
Peak memory 204832 kb
Host smart-f421fa59-77ce-4195-bb30-010fba872adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95475
8599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.954758599
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.3702365870
Short name T1108
Test name
Test status
Simulation time 8465440109 ps
CPU time 12.97 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204752 kb
Host smart-f5c6957b-ca0c-473b-b9d9-edae3e149b59
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3702365870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.3702365870
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1077598028
Short name T1068
Test name
Test status
Simulation time 8380597027 ps
CPU time 10.74 seconds
Started May 19 02:01:48 PM PDT 24
Finished May 19 02:01:59 PM PDT 24
Peak memory 204772 kb
Host smart-9bd3b93b-19a9-4ec0-b92f-ac7e438da0da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1077598028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1077598028
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.443972205
Short name T1598
Test name
Test status
Simulation time 8435256502 ps
CPU time 12.2 seconds
Started May 19 02:01:46 PM PDT 24
Finished May 19 02:01:59 PM PDT 24
Peak memory 204852 kb
Host smart-16c081e3-6c20-4678-871f-ad30162f9052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44397
2205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.443972205
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1737145116
Short name T743
Test name
Test status
Simulation time 8456871516 ps
CPU time 12.82 seconds
Started May 19 02:01:35 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204792 kb
Host smart-dbd6633b-9bb6-4f0d-9ae4-aaba307cbe5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17371
45116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1737145116
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3395253401
Short name T1263
Test name
Test status
Simulation time 8517985891 ps
CPU time 11.46 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:01 PM PDT 24
Peak memory 204824 kb
Host smart-fcad8e8c-d36a-4b6b-a0fc-095ae2138511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
53401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3395253401
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2134513307
Short name T1607
Test name
Test status
Simulation time 8363128703 ps
CPU time 10.84 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:50 PM PDT 24
Peak memory 204832 kb
Host smart-60be21ec-0572-4b01-8723-d28a4dfef3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
13307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2134513307
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3893651563
Short name T1587
Test name
Test status
Simulation time 8370032301 ps
CPU time 11 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204812 kb
Host smart-f3a3f3ed-f918-48e5-9ef5-b68d68a363df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38936
51563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3893651563
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2876915419
Short name T1004
Test name
Test status
Simulation time 8512069043 ps
CPU time 12.16 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 204812 kb
Host smart-bb8180dd-4d69-4d9f-a0a6-a76c167b74f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769
15419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2876915419
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1726473174
Short name T95
Test name
Test status
Simulation time 8431251146 ps
CPU time 11.5 seconds
Started May 19 02:01:44 PM PDT 24
Finished May 19 02:01:56 PM PDT 24
Peak memory 204764 kb
Host smart-cfdd5e0d-b171-41e3-9626-9eb3408ab16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17264
73174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1726473174
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.4237810306
Short name T1407
Test name
Test status
Simulation time 8429278841 ps
CPU time 10.62 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:54 PM PDT 24
Peak memory 204796 kb
Host smart-a808a5d8-e908-4caf-b249-5ba226755f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
10306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.4237810306
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2284808020
Short name T1226
Test name
Test status
Simulation time 8468551416 ps
CPU time 11.92 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:47 PM PDT 24
Peak memory 204844 kb
Host smart-5249ed7d-19c5-4d01-a71c-fa40590937d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22848
08020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2284808020
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.854118161
Short name T342
Test name
Test status
Simulation time 8438450138 ps
CPU time 10.74 seconds
Started May 19 02:01:41 PM PDT 24
Finished May 19 02:01:53 PM PDT 24
Peak memory 204820 kb
Host smart-f533c290-652e-47f3-ae0c-d65d973efec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85411
8161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.854118161
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1953122143
Short name T539
Test name
Test status
Simulation time 11508525013 ps
CPU time 13.43 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:51 PM PDT 24
Peak memory 204872 kb
Host smart-d9a8240f-28f5-44ff-b3a6-87aa94331133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19531
22143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1953122143
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1526964467
Short name T1159
Test name
Test status
Simulation time 8486973952 ps
CPU time 11.88 seconds
Started May 19 02:01:38 PM PDT 24
Finished May 19 02:01:51 PM PDT 24
Peak memory 204812 kb
Host smart-e4b20ce7-fb9e-4c21-b2eb-c2990bd58838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15269
64467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1526964467
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1113597952
Short name T1596
Test name
Test status
Simulation time 8385431028 ps
CPU time 11.4 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204848 kb
Host smart-d5ad7057-1218-43f4-9cc9-e028ee122896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
97952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1113597952
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2169539048
Short name T1621
Test name
Test status
Simulation time 8459542056 ps
CPU time 10.51 seconds
Started May 19 02:01:44 PM PDT 24
Finished May 19 02:01:56 PM PDT 24
Peak memory 204832 kb
Host smart-d4e282fe-cc59-472f-9769-825d94dd4dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21695
39048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2169539048
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.496945720
Short name T1419
Test name
Test status
Simulation time 8413706765 ps
CPU time 10.48 seconds
Started May 19 02:01:47 PM PDT 24
Finished May 19 02:01:58 PM PDT 24
Peak memory 204784 kb
Host smart-51273ff4-a69c-4e5f-8f96-7a3a5e0f9bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49694
5720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.496945720
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1692635003
Short name T1037
Test name
Test status
Simulation time 8389588271 ps
CPU time 11.91 seconds
Started May 19 02:01:44 PM PDT 24
Finished May 19 02:01:57 PM PDT 24
Peak memory 204868 kb
Host smart-27b5add7-4630-4f93-a7b3-9159d7e93585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16926
35003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1692635003
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1427265492
Short name T1253
Test name
Test status
Simulation time 8402030859 ps
CPU time 10.63 seconds
Started May 19 02:01:56 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204744 kb
Host smart-6f6c5b26-77d1-4b3e-ace8-1474d5bc1dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
65492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1427265492
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2991160085
Short name T1399
Test name
Test status
Simulation time 8409573558 ps
CPU time 11.15 seconds
Started May 19 02:01:43 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204876 kb
Host smart-8635b613-7eb1-4543-a135-fc1b0524e080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29911
60085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2991160085
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.792182855
Short name T1315
Test name
Test status
Simulation time 8391194178 ps
CPU time 11.08 seconds
Started May 19 02:01:41 PM PDT 24
Finished May 19 02:01:54 PM PDT 24
Peak memory 204780 kb
Host smart-cd6bf4f7-b763-4959-ac44-66d87f7eaaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79218
2855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.792182855
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1488972999
Short name T588
Test name
Test status
Simulation time 8367111123 ps
CPU time 12.95 seconds
Started May 19 02:01:47 PM PDT 24
Finished May 19 02:02:01 PM PDT 24
Peak memory 204604 kb
Host smart-f0c0ba1a-666b-49ae-a477-3535a2348b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14889
72999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1488972999
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.151979711
Short name T1091
Test name
Test status
Simulation time 8411165496 ps
CPU time 11.91 seconds
Started May 19 02:01:44 PM PDT 24
Finished May 19 02:01:57 PM PDT 24
Peak memory 204836 kb
Host smart-2ea9ace9-4d03-4a60-b124-fe1982b66fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15197
9711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.151979711
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3801131789
Short name T1323
Test name
Test status
Simulation time 21078207151 ps
CPU time 41.3 seconds
Started May 19 02:01:47 PM PDT 24
Finished May 19 02:02:29 PM PDT 24
Peak memory 204800 kb
Host smart-e640e5fc-3713-4893-8350-4dbb25bd387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011
31789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3801131789
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2520869009
Short name T1014
Test name
Test status
Simulation time 8406433027 ps
CPU time 12.3 seconds
Started May 19 02:01:39 PM PDT 24
Finished May 19 02:01:52 PM PDT 24
Peak memory 204832 kb
Host smart-1952b174-1472-47ac-a503-74c435c00edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25208
69009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2520869009
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3649819383
Short name T1172
Test name
Test status
Simulation time 8469082260 ps
CPU time 11.47 seconds
Started May 19 02:01:39 PM PDT 24
Finished May 19 02:01:52 PM PDT 24
Peak memory 204796 kb
Host smart-10c223f8-52bd-4987-87ba-fc9e48e0b30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
19383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3649819383
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3124987010
Short name T1364
Test name
Test status
Simulation time 8403244850 ps
CPU time 11.14 seconds
Started May 19 02:01:47 PM PDT 24
Finished May 19 02:01:59 PM PDT 24
Peak memory 204764 kb
Host smart-b0f8b187-abcf-43a3-b38f-633bdc63973f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31249
87010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3124987010
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2557457593
Short name T887
Test name
Test status
Simulation time 8366795957 ps
CPU time 11.43 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204768 kb
Host smart-fc4e21e4-fbc2-43ea-9343-e9f8cc299e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25574
57593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2557457593
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.516629630
Short name T470
Test name
Test status
Simulation time 8381111156 ps
CPU time 12.16 seconds
Started May 19 02:01:33 PM PDT 24
Finished May 19 02:01:46 PM PDT 24
Peak memory 204760 kb
Host smart-de49be26-6bdb-4c01-8c30-d81c7534343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51662
9630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.516629630
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.331482902
Short name T440
Test name
Test status
Simulation time 8368049663 ps
CPU time 13.68 seconds
Started May 19 02:01:37 PM PDT 24
Finished May 19 02:01:52 PM PDT 24
Peak memory 204840 kb
Host smart-7e0208f7-0d83-4b45-b32a-dd7f820223e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33148
2902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.331482902
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2559084021
Short name T1758
Test name
Test status
Simulation time 8539648620 ps
CPU time 11.48 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:55 PM PDT 24
Peak memory 204872 kb
Host smart-e23a7743-31aa-443a-a300-bfea04c236cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25590
84021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2559084021
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1792336486
Short name T462
Test name
Test status
Simulation time 8389168365 ps
CPU time 11.83 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204848 kb
Host smart-ed6cf535-496c-4592-ae58-fac42a027901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17923
36486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1792336486
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.4180558166
Short name T434
Test name
Test status
Simulation time 8367699155 ps
CPU time 11.41 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204720 kb
Host smart-1acb3d38-c49f-4c91-ac22-c3576a1343ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
58166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.4180558166
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.735839324
Short name T990
Test name
Test status
Simulation time 8377934559 ps
CPU time 11.5 seconds
Started May 19 02:01:50 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 204856 kb
Host smart-9fb282ef-6f0e-4ee6-9766-f5b9617e0348
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=735839324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.735839324
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.3624910076
Short name T1359
Test name
Test status
Simulation time 8429521477 ps
CPU time 11.27 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204804 kb
Host smart-8b5a79a4-dc31-46e9-822f-adc0cf4adb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
10076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3624910076
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2289996621
Short name T1601
Test name
Test status
Simulation time 8378054834 ps
CPU time 11.08 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:10 PM PDT 24
Peak memory 204832 kb
Host smart-44a7af9e-37ef-4275-9c2a-6058df387f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22899
96621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2289996621
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3203006963
Short name T739
Test name
Test status
Simulation time 8920584820 ps
CPU time 12.33 seconds
Started May 19 02:01:52 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204820 kb
Host smart-384dd1af-3829-4f4c-b214-d2c5346827e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32030
06963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3203006963
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3148411503
Short name T229
Test name
Test status
Simulation time 8367632401 ps
CPU time 11.73 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 204760 kb
Host smart-8f6b2a15-097a-4bf1-b318-9172619441ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31484
11503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3148411503
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.4135691068
Short name T509
Test name
Test status
Simulation time 8377632743 ps
CPU time 11.6 seconds
Started May 19 02:01:50 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 204880 kb
Host smart-945936ae-5b60-416b-9e42-4a47e61d4c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41356
91068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4135691068
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1043187885
Short name T350
Test name
Test status
Simulation time 9067844804 ps
CPU time 15.42 seconds
Started May 19 02:01:52 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 205076 kb
Host smart-594705dc-2ae9-453a-bb69-a9051e9b0358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
87885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1043187885
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.109357268
Short name T1447
Test name
Test status
Simulation time 8578493268 ps
CPU time 12.23 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204792 kb
Host smart-23b91f8c-f955-44d3-8bcd-c542bfcd2618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10935
7268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.109357268
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1300955680
Short name T846
Test name
Test status
Simulation time 8499771421 ps
CPU time 11.77 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204856 kb
Host smart-3ad7d1eb-e13e-4f12-a714-060f22c700c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13009
55680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1300955680
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3951608609
Short name T569
Test name
Test status
Simulation time 8368091585 ps
CPU time 10.98 seconds
Started May 19 02:01:52 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 204828 kb
Host smart-0fdce3f5-815b-4ac4-9e54-5ba9f1e5b7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
08609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3951608609
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2805960967
Short name T817
Test name
Test status
Simulation time 8440112702 ps
CPU time 11.47 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:01 PM PDT 24
Peak memory 204852 kb
Host smart-2b92410e-2a69-442b-8dd9-871857867754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28059
60967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2805960967
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3282902594
Short name T1391
Test name
Test status
Simulation time 8395650600 ps
CPU time 11.74 seconds
Started May 19 02:01:51 PM PDT 24
Finished May 19 02:02:04 PM PDT 24
Peak memory 204884 kb
Host smart-dd6112d0-ba53-4680-9a04-36752fd4915f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
02594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3282902594
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1304523308
Short name T1292
Test name
Test status
Simulation time 11501078966 ps
CPU time 14.32 seconds
Started May 19 02:01:52 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204872 kb
Host smart-64fcff53-ebd0-4925-9ecc-55b468131247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045
23308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1304523308
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.398635490
Short name T1506
Test name
Test status
Simulation time 8411535550 ps
CPU time 10.39 seconds
Started May 19 02:01:51 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 204668 kb
Host smart-804becd1-a97a-4574-af89-f8916591bd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39863
5490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.398635490
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.368258351
Short name T724
Test name
Test status
Simulation time 8373582609 ps
CPU time 10.73 seconds
Started May 19 02:01:36 PM PDT 24
Finished May 19 02:01:49 PM PDT 24
Peak memory 204812 kb
Host smart-6d4daadd-b543-4dce-a19b-ea37dab59063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825
8351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.368258351
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3453027910
Short name T150
Test name
Test status
Simulation time 8478359237 ps
CPU time 11.45 seconds
Started May 19 02:01:46 PM PDT 24
Finished May 19 02:01:58 PM PDT 24
Peak memory 204868 kb
Host smart-efba9c8b-e163-4f0a-b345-48bc5c923b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34530
27910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3453027910
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2443189598
Short name T407
Test name
Test status
Simulation time 8422355697 ps
CPU time 11.98 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 204868 kb
Host smart-0b943558-8161-4bc2-94d2-3ac76c7df5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24431
89598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2443189598
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.18377399
Short name T731
Test name
Test status
Simulation time 8407434018 ps
CPU time 11.47 seconds
Started May 19 02:01:48 PM PDT 24
Finished May 19 02:02:00 PM PDT 24
Peak memory 204844 kb
Host smart-064943a5-2e03-4fc9-ab0d-f435a9559d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18377
399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.18377399
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2003968800
Short name T1270
Test name
Test status
Simulation time 8402355510 ps
CPU time 11.58 seconds
Started May 19 02:01:48 PM PDT 24
Finished May 19 02:02:01 PM PDT 24
Peak memory 204844 kb
Host smart-251de88c-842e-4c99-97e3-660401706ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20039
68800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2003968800
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.3127780085
Short name T1757
Test name
Test status
Simulation time 8412919155 ps
CPU time 11.16 seconds
Started May 19 02:02:00 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 204828 kb
Host smart-0d5f8c57-f839-412a-8870-07fdea39b294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31277
80085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.3127780085
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2938618364
Short name T1134
Test name
Test status
Simulation time 8370977423 ps
CPU time 13.33 seconds
Started May 19 02:01:54 PM PDT 24
Finished May 19 02:02:09 PM PDT 24
Peak memory 204760 kb
Host smart-b6fc71cc-2c72-499c-8047-b0bd80b2873d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386
18364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2938618364
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2551855165
Short name T1603
Test name
Test status
Simulation time 8429154432 ps
CPU time 10.98 seconds
Started May 19 02:01:58 PM PDT 24
Finished May 19 02:02:10 PM PDT 24
Peak memory 204824 kb
Host smart-13dd4f0b-9601-4bd4-9fa8-777d2097344f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25518
55165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2551855165
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.534556724
Short name T260
Test name
Test status
Simulation time 14280724316 ps
CPU time 21.93 seconds
Started May 19 02:01:46 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204832 kb
Host smart-2cb53963-32c2-4a5a-8801-e89083b20433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53455
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.534556724
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1066553616
Short name T544
Test name
Test status
Simulation time 8377981633 ps
CPU time 11.14 seconds
Started May 19 02:01:59 PM PDT 24
Finished May 19 02:02:13 PM PDT 24
Peak memory 204748 kb
Host smart-3ca50957-04b7-4a5d-ae40-34f2aad28aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
53616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1066553616
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2073362957
Short name T598
Test name
Test status
Simulation time 8398853929 ps
CPU time 11.33 seconds
Started May 19 02:01:57 PM PDT 24
Finished May 19 02:02:10 PM PDT 24
Peak memory 204684 kb
Host smart-4d012e42-6850-4114-8e39-e7596c8c5c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20733
62957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2073362957
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.470785602
Short name T426
Test name
Test status
Simulation time 8415664047 ps
CPU time 11.47 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 204764 kb
Host smart-dd4fd303-0745-417f-92be-e593d2a7e310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47078
5602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.470785602
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1677892714
Short name T1073
Test name
Test status
Simulation time 8361150449 ps
CPU time 11.65 seconds
Started May 19 02:01:49 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 204768 kb
Host smart-bfbf15f5-b7e5-40f6-b5cc-980c26b89e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
92714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1677892714
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2140029858
Short name T621
Test name
Test status
Simulation time 8384936470 ps
CPU time 11.04 seconds
Started May 19 02:02:08 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 204768 kb
Host smart-581038c4-747b-4f3e-bb79-0d34eba9c28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21400
29858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2140029858
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2425272372
Short name T1696
Test name
Test status
Simulation time 8384918985 ps
CPU time 11.15 seconds
Started May 19 02:01:53 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 204780 kb
Host smart-5d632081-3129-4fa3-ae0d-afd0a5d7c3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24252
72372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2425272372
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2931858143
Short name T1325
Test name
Test status
Simulation time 8401208483 ps
CPU time 11.14 seconds
Started May 19 02:01:47 PM PDT 24
Finished May 19 02:01:59 PM PDT 24
Peak memory 204576 kb
Host smart-a0756358-efb5-41cf-a77d-b29a6e7ce7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
58143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2931858143
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2244029591
Short name T1585
Test name
Test status
Simulation time 8461252812 ps
CPU time 10.5 seconds
Started May 19 02:01:55 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 204816 kb
Host smart-6bcec431-d587-4ebf-ba2d-d5174a0124c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
29591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2244029591
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3030361138
Short name T802
Test name
Test status
Simulation time 8381788430 ps
CPU time 11 seconds
Started May 19 02:01:42 PM PDT 24
Finished May 19 02:01:54 PM PDT 24
Peak memory 204868 kb
Host smart-0e1be031-e57f-4b8e-8f7f-1f2291bcfbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303
61138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3030361138
Directory /workspace/9.usbdev_stall_trans/latest
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