Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	27550	1		T1	17		T2	4		T3	2
all_values[1]	27550	1		T1	17		T2	4		T3	2
all_values[2]	27550	1		T1	17		T2	4		T3	2
all_values[3]	27550	1		T1	17		T2	4		T3	2
all_values[4]	27550	1		T1	17		T2	4		T3	2
all_values[5]	27550	1		T1	17		T2	4		T3	2
all_values[6]	27550	1		T1	17		T2	4		T3	2
all_values[7]	27550	1		T1	17		T2	4		T3	2
all_values[8]	27550	1		T1	17		T2	4		T3	2
all_values[9]	27550	1		T1	17		T2	4		T3	2
all_values[10]	27550	1		T1	17		T2	4		T3	2
all_values[11]	27550	1		T1	17		T2	4		T3	2
all_values[12]	27550	1		T1	17		T2	4		T3	2
all_values[13]	27550	1		T1	17		T2	4		T3	2
all_values[14]	27550	1		T1	17		T2	4		T3	2
all_values[15]	27550	1		T1	17		T2	4		T3	2
all_values[16]	27550	1		T1	17		T2	4		T3	2
all_values[17]	27550	1		T1	17		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	490479	1		T1	289		T2	72		T3	34
auto[1]	5421	1		T1	17		T3	2		T9	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	490793	1		T1	306		T2	72		T3	36
auto[1]	5107	1		T83	128		T86	74		T84	125

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	26540	1		T1	17		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	133	1		T83	2		T86	1		T84	5
all_values[0]	auto[1]	auto[0]	739	1		T9	4		T36	3		T37	3
all_values[0]	auto[1]	auto[1]	138	1		T83	6		T86	4		T84	1
all_values[1]	auto[0]	auto[0]	25734	1		T2	4		T3	2		T9	4
all_values[1]	auto[0]	auto[1]	135	1		T83	5		T84	4		T85	1
all_values[1]	auto[1]	auto[0]	1523	1		T1	17		T21	19		T26	5
all_values[1]	auto[1]	auto[1]	158	1		T83	2		T86	4		T84	4
all_values[2]	auto[0]	auto[0]	27132	1		T1	17		T2	4		T9	4
all_values[2]	auto[0]	auto[1]	155	1		T83	4		T86	5		T84	3
all_values[2]	auto[1]	auto[0]	123	1		T3	2		T7	2		T8	2
all_values[2]	auto[1]	auto[1]	140	1		T83	3		T84	5		T85	4
all_values[3]	auto[0]	auto[0]	27239	1		T1	17		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	153	1		T83	2		T86	5		T85	3
all_values[3]	auto[1]	auto[0]	19	1		T83	1		T84	1		T88	1
all_values[3]	auto[1]	auto[1]	139	1		T83	5		T84	6		T85	1
all_values[4]	auto[0]	auto[0]	27239	1		T1	17		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	141	1		T83	2		T86	3		T84	5
all_values[4]	auto[1]	auto[0]	23	1		T84	1		T88	1		T87	1
all_values[4]	auto[1]	auto[1]	147	1		T83	6		T86	1		T84	2
all_values[5]	auto[0]	auto[0]	27233	1		T1	17		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	159	1		T83	6		T86	4		T84	6
all_values[5]	auto[1]	auto[0]	22	1		T86	1		T85	2		T250	2
all_values[5]	auto[1]	auto[1]	136	1		T83	2		T84	2		T88	3
all_values[6]	auto[0]	auto[0]	27238	1		T1	17		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	152	1		T83	2		T84	5		T88	6
all_values[6]	auto[1]	auto[0]	23	1		T86	2		T88	1		T251	1
all_values[6]	auto[1]	auto[1]	137	1		T83	5		T84	3		T85	5
all_values[7]	auto[0]	auto[0]	27239	1		T1	17		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	137	1		T83	2		T86	2		T84	5
all_values[7]	auto[1]	auto[0]	34	1		T83	1		T85	1		T250	1
all_values[7]	auto[1]	auto[1]	140	1		T83	5		T86	3		T84	2
all_values[8]	auto[0]	auto[0]	27251	1		T1	17		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	136	1		T83	3		T86	4		T84	3
all_values[8]	auto[1]	auto[0]	25	1		T84	1		T251	1		T252	2
all_values[8]	auto[1]	auto[1]	138	1		T83	5		T86	1		T84	3
all_values[9]	auto[0]	auto[0]	27237	1		T1	17		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	145	1		T83	6		T86	4		T84	2
all_values[9]	auto[1]	auto[0]	27	1		T84	1		T87	1		T251	5
all_values[9]	auto[1]	auto[1]	141	1		T83	2		T86	1		T84	5
all_values[10]	auto[0]	auto[0]	27235	1		T1	17		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	128	1		T83	6		T86	2		T84	3
all_values[10]	auto[1]	auto[0]	41	1		T84	4		T250	2		T251	1
all_values[10]	auto[1]	auto[1]	146	1		T83	2		T86	3		T84	1
all_values[11]	auto[0]	auto[0]	27136	1		T1	17		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	166	1		T83	6		T86	5		T84	7
all_values[11]	auto[1]	auto[0]	128	1		T20	2		T34	2		T35	2
all_values[11]	auto[1]	auto[1]	120	1		T83	1		T84	1		T88	5
all_values[12]	auto[0]	auto[0]	27236	1		T1	17		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	153	1		T83	6		T86	1		T84	2
all_values[12]	auto[1]	auto[0]	17	1		T248	2		T87	1		T253	1
all_values[12]	auto[1]	auto[1]	144	1		T83	2		T86	3		T84	6
all_values[13]	auto[0]	auto[0]	27246	1		T1	17		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	112	1		T83	1		T86	5		T84	1
all_values[13]	auto[1]	auto[0]	32	1		T83	2		T251	1		T252	1
all_values[13]	auto[1]	auto[1]	160	1		T83	5		T84	7		T85	5
all_values[14]	auto[0]	auto[0]	27237	1		T1	17		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	134	1		T83	1		T84	2		T88	3
all_values[14]	auto[1]	auto[0]	29	1		T83	2		T86	4		T249	1
all_values[14]	auto[1]	auto[1]	150	1		T83	4		T84	6		T85	4
all_values[15]	auto[0]	auto[0]	27246	1		T1	17		T2	4		T3	2
all_values[15]	auto[0]	auto[1]	150	1		T83	6		T86	5		T84	1
all_values[15]	auto[1]	auto[0]	23	1		T83	1		T84	1		T85	1
all_values[15]	auto[1]	auto[1]	131	1		T83	1		T84	4		T85	1
all_values[16]	auto[0]	auto[0]	27245	1		T1	17		T2	4		T3	2
all_values[16]	auto[0]	auto[1]	162	1		T83	1		T86	4		T84	6
all_values[16]	auto[1]	auto[0]	28	1		T83	2		T84	1		T85	1
all_values[16]	auto[1]	auto[1]	115	1		T83	3		T86	1		T88	3
all_values[17]	auto[0]	auto[0]	27246	1		T1	17		T2	4		T3	2
all_values[17]	auto[0]	auto[1]	119	1		T83	6		T84	2		T88	7
all_values[17]	auto[1]	auto[0]	28	1		T84	1		T85	1		T248	1
all_values[17]	auto[1]	auto[1]	157	1		T83	2		T86	3		T84	5