Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	27550	1		T1	17		T2	4		T3	2
all_pins[1]	27550	1		T1	17		T2	4		T3	2
all_pins[2]	27550	1		T1	17		T2	4		T3	2
all_pins[3]	27550	1		T1	17		T2	4		T3	2
all_pins[4]	27550	1		T1	17		T2	4		T3	2
all_pins[5]	27550	1		T1	17		T2	4		T3	2
all_pins[6]	27550	1		T1	17		T2	4		T3	2
all_pins[7]	27550	1		T1	17		T2	4		T3	2
all_pins[8]	27550	1		T1	17		T2	4		T3	2
all_pins[9]	27550	1		T1	17		T2	4		T3	2
all_pins[10]	27550	1		T1	17		T2	4		T3	2
all_pins[11]	27550	1		T1	17		T2	4		T3	2
all_pins[12]	27550	1		T1	17		T2	4		T3	2
all_pins[13]	27550	1		T1	17		T2	4		T3	2
all_pins[14]	27550	1		T1	17		T2	4		T3	2
all_pins[15]	27550	1		T1	17		T2	4		T3	2
all_pins[16]	27550	1		T1	17		T2	4		T3	2
all_pins[17]	27550	1		T1	17		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	493639	1		T1	291		T2	72		T3	35
values[0x1]	2261	1		T1	15		T3	1		T9	1
transitions[0x0=>0x1]	1948	1		T1	15		T3	1		T9	1
transitions[0x1=>0x0]	1960	1		T1	15		T3	1		T9	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	27395	1		T1	17		T2	4		T3	2
all_pins[0]	values[0x1]	155	1		T9	1		T58	1		T59	1
all_pins[0]	transitions[0x0=>0x1]	140	1		T9	1		T58	1		T59	1
all_pins[0]	transitions[0x1=>0x0]	931	1		T1	15		T21	15		T26	2
all_pins[1]	values[0x0]	26604	1		T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	946	1		T1	15		T21	15		T26	2
all_pins[1]	transitions[0x0=>0x1]	929	1		T1	15		T21	15		T26	2
all_pins[1]	transitions[0x1=>0x0]	107	1		T3	1		T7	1		T8	1
all_pins[2]	values[0x0]	27426	1		T1	17		T2	4		T3	1
all_pins[2]	values[0x1]	124	1		T3	1		T7	1		T8	1
all_pins[2]	transitions[0x0=>0x1]	108	1		T3	1		T7	1		T8	1
all_pins[2]	transitions[0x1=>0x0]	49	1		T83	3		T84	2		T85	1
all_pins[3]	values[0x0]	27485	1		T1	17		T2	4		T3	2
all_pins[3]	values[0x1]	65	1		T83	3		T84	2		T85	1
all_pins[3]	transitions[0x0=>0x1]	52	1		T83	2		T84	2		T248	1
all_pins[3]	transitions[0x1=>0x0]	62	1		T83	2		T86	1		T84	1
all_pins[4]	values[0x0]	27475	1		T1	17		T2	4		T3	2
all_pins[4]	values[0x1]	75	1		T83	3		T86	1		T84	1
all_pins[4]	transitions[0x0=>0x1]	66	1		T83	1		T86	1		T84	1
all_pins[4]	transitions[0x1=>0x0]	46	1		T84	2		T87	1		T251	2
all_pins[5]	values[0x0]	27495	1		T1	17		T2	4		T3	2
all_pins[5]	values[0x1]	55	1		T83	2		T84	2		T87	1
all_pins[5]	transitions[0x0=>0x1]	41	1		T83	1		T84	1		T87	1
all_pins[5]	transitions[0x1=>0x0]	57	1		T83	3		T84	1		T85	4
all_pins[6]	values[0x0]	27479	1		T1	17		T2	4		T3	2
all_pins[6]	values[0x1]	71	1		T83	4		T84	2		T85	4
all_pins[6]	transitions[0x0=>0x1]	56	1		T83	4		T84	2		T85	3
all_pins[6]	transitions[0x1=>0x0]	36	1		T86	1		T88	2		T248	2
all_pins[7]	values[0x0]	27499	1		T1	17		T2	4		T3	2
all_pins[7]	values[0x1]	51	1		T86	1		T85	1		T88	2
all_pins[7]	transitions[0x0=>0x1]	39	1		T86	1		T85	1		T248	1
all_pins[7]	transitions[0x1=>0x0]	47	1		T83	3		T86	1		T88	1
all_pins[8]	values[0x0]	27491	1		T1	17		T2	4		T3	2
all_pins[8]	values[0x1]	59	1		T83	3		T86	1		T88	3
all_pins[8]	transitions[0x0=>0x1]	45	1		T83	2		T86	1		T88	3
all_pins[8]	transitions[0x1=>0x0]	51	1		T84	2		T85	2		T248	2
all_pins[9]	values[0x0]	27485	1		T1	17		T2	4		T3	2
all_pins[9]	values[0x1]	65	1		T83	1		T84	2		T85	2
all_pins[9]	transitions[0x0=>0x1]	42	1		T83	1		T84	2		T85	2
all_pins[9]	transitions[0x1=>0x0]	57	1		T83	2		T86	2		T88	2
all_pins[10]	values[0x0]	27470	1		T1	17		T2	4		T3	2
all_pins[10]	values[0x1]	80	1		T83	2		T86	2		T88	2
all_pins[10]	transitions[0x0=>0x1]	63	1		T83	2		T86	2		T88	2
all_pins[10]	transitions[0x1=>0x0]	90	1		T20	1		T34	1		T35	1
all_pins[11]	values[0x0]	27443	1		T1	17		T2	4		T3	2
all_pins[11]	values[0x1]	107	1		T20	1		T34	1		T35	1
all_pins[11]	transitions[0x0=>0x1]	83	1		T20	1		T34	1		T35	1
all_pins[11]	transitions[0x1=>0x0]	39	1		T83	2		T84	4		T88	2
all_pins[12]	values[0x0]	27487	1		T1	17		T2	4		T3	2
all_pins[12]	values[0x1]	63	1		T83	2		T84	5		T88	2
all_pins[12]	transitions[0x0=>0x1]	43	1		T83	1		T84	2		T88	1
all_pins[12]	transitions[0x1=>0x0]	62	1		T83	3		T84	1		T85	3
all_pins[13]	values[0x0]	27468	1		T1	17		T2	4		T3	2
all_pins[13]	values[0x1]	82	1		T83	4		T84	4		T85	3
all_pins[13]	transitions[0x0=>0x1]	58	1		T83	4		T84	3		T85	1
all_pins[13]	transitions[0x1=>0x0]	53	1		T84	2		T85	1		T88	2
all_pins[14]	values[0x0]	27473	1		T1	17		T2	4		T3	2
all_pins[14]	values[0x1]	77	1		T84	3		T85	3		T88	2
all_pins[14]	transitions[0x0=>0x1]	57	1		T84	3		T85	2		T88	2
all_pins[14]	transitions[0x1=>0x0]	43	1		T83	1		T248	1		T250	1
all_pins[15]	values[0x0]	27487	1		T1	17		T2	4		T3	2
all_pins[15]	values[0x1]	63	1		T83	1		T85	1		T248	1
all_pins[15]	transitions[0x0=>0x1]	47	1		T83	1		T85	1		T250	2
all_pins[15]	transitions[0x1=>0x0]	48	1		T83	2		T86	1		T88	3
all_pins[16]	values[0x0]	27486	1		T1	17		T2	4		T3	2
all_pins[16]	values[0x1]	64	1		T83	2		T86	1		T88	3
all_pins[16]	transitions[0x0=>0x1]	44	1		T83	2		T86	1		T88	2
all_pins[16]	transitions[0x1=>0x0]	39	1		T86	1		T87	1		T251	1
all_pins[17]	values[0x0]	27491	1		T1	17		T2	4		T3	2
all_pins[17]	values[0x1]	59	1		T86	1		T88	1		T87	1
all_pins[17]	transitions[0x0=>0x1]	35	1		T86	1		T88	1		T251	1
all_pins[17]	transitions[0x1=>0x0]	143	1		T9	1		T58	1		T59	1