Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1		T83	7		T86	4		T84	7
all_values[1]	287	1		T83	7		T86	4		T84	7
all_values[2]	287	1		T83	7		T86	4		T84	7
all_values[3]	287	1		T83	7		T86	4		T84	7
all_values[4]	287	1		T83	7		T86	4		T84	7
all_values[5]	287	1		T83	7		T86	4		T84	7
all_values[6]	287	1		T83	7		T86	4		T84	7
all_values[7]	287	1		T83	7		T86	4		T84	7
all_values[8]	287	1		T83	7		T86	4		T84	7
all_values[9]	287	1		T83	7		T86	4		T84	7
all_values[10]	287	1		T83	7		T86	4		T84	7
all_values[11]	287	1		T83	7		T86	4		T84	7
all_values[12]	287	1		T83	7		T86	4		T84	7
all_values[13]	287	1		T83	7		T86	4		T84	7
all_values[14]	287	1		T83	7		T86	4		T84	7
all_values[15]	287	1		T83	7		T86	4		T84	7
all_values[16]	287	1		T83	7		T86	4		T84	7
all_values[17]	287	1		T83	7		T86	4		T84	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2864	1		T83	60		T86	49		T84	58
auto[1]	2302	1		T83	66		T86	23		T84	68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	902	1		T83	16		T86	14		T84	19
auto[1]	4264	1		T83	110		T86	58		T84	107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3019	1		T83	69		T86	40		T84	74
auto[1]	2147	1		T83	57		T86	32		T84	52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	32	1		T84	2		T88	1		T248	1
all_values[0]	auto[0]	auto[0]	auto[1]	54	1		T86	1		T84	3		T85	1
all_values[0]	auto[0]	auto[1]	auto[0]	32	1		T85	1		T88	4		T248	3
all_values[0]	auto[0]	auto[1]	auto[1]	57	1		T83	2		T86	1		T84	1
all_values[0]	auto[1]	auto[0]	auto[1]	62	1		T83	2		T86	1		T84	1
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T83	3		T86	1		T85	1
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T248	1		T249	2		T254	2
all_values[1]	auto[0]	auto[0]	auto[1]	58	1		T83	3		T84	1		T85	1
all_values[1]	auto[0]	auto[1]	auto[0]	11	1		T83	1		T86	1		T248	3
all_values[1]	auto[0]	auto[1]	auto[1]	65	1		T83	1		T86	2		T84	4
all_values[1]	auto[1]	auto[0]	auto[1]	74	1		T83	1		T84	2		T85	1
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T83	1		T86	1		T88	1
all_values[2]	auto[0]	auto[0]	auto[0]	21	1		T248	1		T249	1		T255	1
all_values[2]	auto[0]	auto[0]	auto[1]	64	1		T83	2		T86	3		T85	1
all_values[2]	auto[0]	auto[1]	auto[0]	18	1		T83	1		T250	3		T249	1
all_values[2]	auto[0]	auto[1]	auto[1]	57	1		T84	3		T85	2		T250	2
all_values[2]	auto[1]	auto[0]	auto[1]	77	1		T83	2		T86	1		T84	3
all_values[2]	auto[1]	auto[1]	auto[1]	50	1		T83	2		T84	1		T88	3
all_values[3]	auto[0]	auto[0]	auto[0]	31	1		T84	2		T85	1		T250	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1		T86	2		T85	1		T88	1
all_values[3]	auto[0]	auto[1]	auto[0]	12	1		T83	1		T88	2		T250	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1		T83	2		T84	2		T248	1
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T83	2		T86	2		T85	2
all_values[3]	auto[1]	auto[1]	auto[1]	59	1		T83	2		T84	3		T88	3
all_values[4]	auto[0]	auto[0]	auto[0]	34	1		T86	1		T88	2		T250	1
all_values[4]	auto[0]	auto[0]	auto[1]	53	1		T86	1		T84	3		T88	1
all_values[4]	auto[0]	auto[1]	auto[0]	12	1		T84	1		T254	1		T256	2
all_values[4]	auto[0]	auto[1]	auto[1]	57	1		T83	4		T85	1		T250	2
all_values[4]	auto[1]	auto[0]	auto[1]	77	1		T84	1		T248	2		T250	2
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T83	3		T86	2		T84	2
all_values[5]	auto[0]	auto[0]	auto[0]	24	1		T250	2		T254	2		T257	1
all_values[5]	auto[0]	auto[0]	auto[1]	70	1		T83	2		T86	1		T84	2
all_values[5]	auto[0]	auto[1]	auto[0]	15	1		T86	1		T85	2		T250	3
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T83	1		T88	1		T248	1
all_values[5]	auto[1]	auto[0]	auto[1]	68	1		T83	2		T86	2		T84	2
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T83	2		T84	3		T87	1
all_values[6]	auto[0]	auto[0]	auto[0]	30	1		T83	1		T86	1		T251	1
all_values[6]	auto[0]	auto[0]	auto[1]	58	1		T84	2		T88	3		T248	1
all_values[6]	auto[0]	auto[1]	auto[0]	15	1		T86	3		T88	1		T258	4
all_values[6]	auto[0]	auto[1]	auto[1]	56	1		T83	2		T84	1		T85	2
all_values[6]	auto[1]	auto[0]	auto[1]	73	1		T83	2		T84	1		T248	3
all_values[6]	auto[1]	auto[1]	auto[1]	55	1		T83	2		T84	3		T85	2
all_values[7]	auto[0]	auto[0]	auto[0]	34	1		T84	1		T250	1		T87	1
all_values[7]	auto[0]	auto[0]	auto[1]	60	1		T83	3		T84	3		T88	3
all_values[7]	auto[0]	auto[1]	auto[0]	23	1		T83	1		T85	1		T250	1
all_values[7]	auto[0]	auto[1]	auto[1]	69	1		T83	2		T86	1		T84	1
all_values[7]	auto[1]	auto[0]	auto[1]	62	1		T83	1		T86	3		T84	2
all_values[7]	auto[1]	auto[1]	auto[1]	39	1		T85	1		T88	2		T248	1
all_values[8]	auto[0]	auto[0]	auto[0]	39	1		T85	4		T250	1		T251	1
all_values[8]	auto[0]	auto[0]	auto[1]	52	1		T86	1		T88	1		T248	2
all_values[8]	auto[0]	auto[1]	auto[0]	20	1		T84	2		T251	1		T252	1
all_values[8]	auto[0]	auto[1]	auto[1]	61	1		T83	1		T84	2		T88	3
all_values[8]	auto[1]	auto[0]	auto[1]	67	1		T83	2		T86	2		T84	3
all_values[8]	auto[1]	auto[1]	auto[1]	48	1		T83	4		T86	1		T88	3
all_values[9]	auto[0]	auto[0]	auto[0]	30	1		T88	1		T87	1		T251	1
all_values[9]	auto[0]	auto[0]	auto[1]	56	1		T83	6		T86	1		T85	2
all_values[9]	auto[0]	auto[1]	auto[0]	19	1		T84	1		T251	3		T252	2
all_values[9]	auto[0]	auto[1]	auto[1]	59	1		T86	2		T84	2		T88	3
all_values[9]	auto[1]	auto[0]	auto[1]	59	1		T86	1		T84	1		T88	1
all_values[9]	auto[1]	auto[1]	auto[1]	64	1		T83	1		T84	3		T85	2
all_values[10]	auto[0]	auto[0]	auto[0]	30	1		T85	2		T88	1		T248	2
all_values[10]	auto[0]	auto[0]	auto[1]	55	1		T83	4		T84	1		T85	1
all_values[10]	auto[0]	auto[1]	auto[0]	28	1		T84	4		T250	2		T252	2
all_values[10]	auto[0]	auto[1]	auto[1]	58	1		T86	1		T88	1		T248	1
all_values[10]	auto[1]	auto[0]	auto[1]	64	1		T83	1		T86	3		T84	1
all_values[10]	auto[1]	auto[1]	auto[1]	52	1		T83	2		T84	1		T248	1
all_values[11]	auto[0]	auto[0]	auto[0]	27	1		T250	1		T87	4		T252	1
all_values[11]	auto[0]	auto[0]	auto[1]	64	1		T83	2		T86	2		T84	2
all_values[11]	auto[0]	auto[1]	auto[0]	22	1		T83	1		T250	1		T87	3
all_values[11]	auto[0]	auto[1]	auto[1]	54	1		T84	1		T88	2		T248	2
all_values[11]	auto[1]	auto[0]	auto[1]	79	1		T83	4		T86	2		T84	3
all_values[11]	auto[1]	auto[1]	auto[1]	41	1		T84	1		T88	1		T249	1
all_values[12]	auto[0]	auto[0]	auto[0]	29	1		T86	1		T85	2		T248	1
all_values[12]	auto[0]	auto[0]	auto[1]	63	1		T83	2		T85	1		T88	4
all_values[12]	auto[0]	auto[1]	auto[0]	11	1		T248	1		T259	2		T260	1
all_values[12]	auto[0]	auto[1]	auto[1]	63	1		T83	2		T86	1		T84	4
all_values[12]	auto[1]	auto[0]	auto[1]	82	1		T83	3		T86	2		T84	1
all_values[12]	auto[1]	auto[1]	auto[1]	39	1		T84	2		T88	1		T249	1
all_values[13]	auto[0]	auto[0]	auto[0]	43	1		T251	4		T249	1		T252	2
all_values[13]	auto[0]	auto[0]	auto[1]	43	1		T83	1		T86	2		T88	4
all_values[13]	auto[0]	auto[1]	auto[0]	19	1		T83	2		T255	1		T261	3
all_values[13]	auto[0]	auto[1]	auto[1]	63	1		T83	1		T84	2		T85	1
all_values[13]	auto[1]	auto[0]	auto[1]	57	1		T83	1		T86	2		T84	2
all_values[13]	auto[1]	auto[1]	auto[1]	62	1		T83	2		T84	3		T85	3
all_values[14]	auto[0]	auto[0]	auto[0]	34	1		T83	1		T86	2		T85	1
all_values[14]	auto[0]	auto[0]	auto[1]	61	1		T88	1		T250	1		T87	2
all_values[14]	auto[0]	auto[1]	auto[0]	16	1		T83	2		T86	2		T262	1
all_values[14]	auto[0]	auto[1]	auto[1]	67	1		T83	2		T84	5		T85	2
all_values[14]	auto[1]	auto[0]	auto[1]	64	1		T83	2		T85	1		T88	3
all_values[14]	auto[1]	auto[1]	auto[1]	45	1		T84	2		T248	2		T250	2
all_values[15]	auto[0]	auto[0]	auto[0]	37	1		T84	3		T249	4		T255	6
all_values[15]	auto[0]	auto[0]	auto[1]	55	1		T83	2		T86	1		T84	1
all_values[15]	auto[0]	auto[1]	auto[0]	14	1		T83	1		T85	1		T255	1
all_values[15]	auto[0]	auto[1]	auto[1]	56	1		T83	1		T84	1		T88	3
all_values[15]	auto[1]	auto[0]	auto[1]	72	1		T83	2		T86	3		T84	1
all_values[15]	auto[1]	auto[1]	auto[1]	53	1		T83	1		T84	1		T85	1
all_values[16]	auto[0]	auto[0]	auto[0]	40	1		T83	1		T84	2		T85	2
all_values[16]	auto[0]	auto[0]	auto[1]	70	1		T86	1		T84	3		T88	2
all_values[16]	auto[0]	auto[1]	auto[0]	15	1		T83	3		T85	2		T252	1
all_values[16]	auto[0]	auto[1]	auto[1]	45	1		T83	1		T86	1		T88	1
all_values[16]	auto[1]	auto[0]	auto[1]	67	1		T86	1		T84	2		T88	2
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T83	2		T86	1		T88	2
all_values[17]	auto[0]	auto[0]	auto[0]	39	1		T86	2		T85	4		T248	4
all_values[17]	auto[0]	auto[0]	auto[1]	47	1		T83	2		T84	1		T88	3
all_values[17]	auto[0]	auto[1]	auto[0]	16	1		T84	1		T252	1		T254	1
all_values[17]	auto[0]	auto[1]	auto[1]	69	1		T83	2		T86	1		T84	4
all_values[17]	auto[1]	auto[0]	auto[1]	67	1		T83	1		T86	1		T88	3
all_values[17]	auto[1]	auto[1]	auto[1]	49	1		T83	2		T84	1		T252	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal